275 rader
13 KiB
C
275 rader
13 KiB
C
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////////////////////////////////////////////////////////////////////////////////
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//
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// The University of Illinois/NCSA
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// Open Source License (NCSA)
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//
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// Copyright (c) 2014-2015, Advanced Micro Devices, Inc. All rights reserved.
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//
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// Developed by:
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//
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// AMD Research and AMD HSA Software Development
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//
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// Advanced Micro Devices, Inc.
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//
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// www.amd.com
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to
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// deal with the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimers.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimers in
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// the documentation and/or other materials provided with the distribution.
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// - Neither the names of Advanced Micro Devices, Inc,
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// nor the names of its contributors may be used to endorse or promote
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// products derived from this Software without specific prior written
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// permission.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS WITH THE SOFTWARE.
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//
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////////////////////////////////////////////////////////////////////////////////
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#ifndef AMD_HSA_KERNEL_CODE_H
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#define AMD_HSA_KERNEL_CODE_H
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#include "amd_hsa_common.h"
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#include "hsa.h"
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// AMD Kernel Code Version Enumeration Values.
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typedef uint32_t amd_kernel_code_version32_t;
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enum amd_kernel_code_version_t {
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AMD_KERNEL_CODE_VERSION_MAJOR = 1,
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AMD_KERNEL_CODE_VERSION_MINOR = 1
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};
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// AMD Machine Kind Enumeration Values.
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typedef uint16_t amd_machine_kind16_t;
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enum amd_machine_kind_t {
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AMD_MACHINE_KIND_UNDEFINED = 0,
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AMD_MACHINE_KIND_AMDGPU = 1
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};
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// AMD Machine Version.
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typedef uint16_t amd_machine_version16_t;
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// AMD Float Round Mode Enumeration Values.
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enum amd_float_round_mode_t {
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AMD_FLOAT_ROUND_MODE_NEAREST_EVEN = 0,
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AMD_FLOAT_ROUND_MODE_PLUS_INFINITY = 1,
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AMD_FLOAT_ROUND_MODE_MINUS_INFINITY = 2,
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AMD_FLOAT_ROUND_MODE_ZERO = 3
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};
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// AMD Float Denorm Mode Enumeration Values.
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enum amd_float_denorm_mode_t {
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AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE_OUTPUT = 0,
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AMD_FLOAT_DENORM_MODE_FLUSH_OUTPUT = 1,
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AMD_FLOAT_DENORM_MODE_FLUSH_SOURCE = 2,
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AMD_FLOAT_DENORM_MODE_NO_FLUSH = 3
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};
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// AMD Compute Program Resource Register One.
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typedef uint32_t amd_compute_pgm_rsrc_one32_t;
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enum amd_compute_pgm_rsrc_one_t {
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_GRANULATED_WAVEFRONT_SGPR_COUNT, 6, 4),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_PRIORITY, 10, 2),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_32, 12, 2),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_ROUND_MODE_16_64, 14, 2),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32, 16, 2),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64, 18, 2),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_PRIV, 20, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP, 21, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_DEBUG_MODE, 22, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE, 23, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_BULKY, 24, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_CDBG_USER, 25, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_FP16_OVFL, 26, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_RESERVED0, 27, 2),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_WGP_MODE, 29, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_MEM_ORDERED, 30, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_ONE_FWD_PROGRESS, 31, 1),
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};
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// AMD System VGPR Workitem ID Enumeration Values.
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enum amd_system_vgpr_workitem_id_t {
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AMD_SYSTEM_VGPR_WORKITEM_ID_X = 0,
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AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y = 1,
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AMD_SYSTEM_VGPR_WORKITEM_ID_X_Y_Z = 2,
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AMD_SYSTEM_VGPR_WORKITEM_ID_UNDEFINED = 3
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};
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// AMD Compute Program Resource Register Two.
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typedef uint32_t amd_compute_pgm_rsrc_two32_t;
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enum amd_compute_pgm_rsrc_two_t {
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_BYTE_OFFSET, 0, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT, 1, 5),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_TRAP_HANDLER, 6, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X, 7, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y, 8, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z, 9, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_INFO, 10, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_VGPR_WORKITEM_ID, 11, 2),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_ADDRESS_WATCH, 13, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_MEMORY_VIOLATION, 14, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE, 15, 9),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION, 24, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE, 25, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO, 26, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW, 27, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW, 28, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT, 29, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_EXCEPTION_INT_DIVISION_BY_ZERO, 30, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_COMPUTE_PGM_RSRC_TWO_RESERVED1, 31, 1)
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};
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// AMD Element Byte Size Enumeration Values.
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enum amd_element_byte_size_t {
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AMD_ELEMENT_BYTE_SIZE_2 = 0,
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AMD_ELEMENT_BYTE_SIZE_4 = 1,
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AMD_ELEMENT_BYTE_SIZE_8 = 2,
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AMD_ELEMENT_BYTE_SIZE_16 = 3
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};
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// AMD Kernel Code Properties.
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typedef uint32_t amd_kernel_code_properties32_t;
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enum amd_kernel_code_properties_t {
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR, 1, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_QUEUE_PTR, 2, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR, 3, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_ID, 4, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_FLAT_SCRATCH_INIT, 5, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE, 6, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X, 7, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y, 8, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z, 9, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_WAVEFRONT_SIZE32, 10, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_RESERVED1, 11, 5),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_ENABLE_ORDERED_APPEND_GDS, 16, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_PRIVATE_ELEMENT_SIZE, 17, 2),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_IS_PTR64, 19, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_IS_DYNAMIC_CALLSTACK, 20, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_IS_DEBUG_ENABLED, 21, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_IS_XNACK_ENABLED, 22, 1),
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AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_KERNEL_CODE_PROPERTIES_RESERVED2, 23, 9)
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};
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// AMD Power Of Two Enumeration Values.
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typedef uint8_t amd_powertwo8_t;
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enum amd_powertwo_t {
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AMD_POWERTWO_1 = 0,
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AMD_POWERTWO_2 = 1,
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AMD_POWERTWO_4 = 2,
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AMD_POWERTWO_8 = 3,
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AMD_POWERTWO_16 = 4,
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AMD_POWERTWO_32 = 5,
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AMD_POWERTWO_64 = 6,
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AMD_POWERTWO_128 = 7,
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AMD_POWERTWO_256 = 8
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};
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// AMD Enabled Control Directive Enumeration Values.
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typedef uint64_t amd_enabled_control_directive64_t;
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enum amd_enabled_control_directive_t {
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AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_BREAK_EXCEPTIONS = 1,
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AMD_ENABLED_CONTROL_DIRECTIVE_ENABLE_DETECT_EXCEPTIONS = 2,
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AMD_ENABLED_CONTROL_DIRECTIVE_MAX_DYNAMIC_GROUP_SIZE = 4,
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AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_GRID_SIZE = 8,
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AMD_ENABLED_CONTROL_DIRECTIVE_MAX_FLAT_WORKGROUP_SIZE = 16,
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AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_DIM = 32,
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AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_GRID_SIZE = 64,
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AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRED_WORKGROUP_SIZE = 128,
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AMD_ENABLED_CONTROL_DIRECTIVE_REQUIRE_NO_PARTIAL_WORKGROUPS = 256
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};
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// AMD Exception Kind Enumeration Values.
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typedef uint16_t amd_exception_kind16_t;
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enum amd_exception_kind_t {
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AMD_EXCEPTION_KIND_INVALID_OPERATION = 1,
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AMD_EXCEPTION_KIND_DIVISION_BY_ZERO = 2,
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AMD_EXCEPTION_KIND_OVERFLOW = 4,
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AMD_EXCEPTION_KIND_UNDERFLOW = 8,
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AMD_EXCEPTION_KIND_INEXACT = 16
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};
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// AMD Control Directives.
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#define AMD_CONTROL_DIRECTIVES_ALIGN_BYTES 64
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#define AMD_CONTROL_DIRECTIVES_ALIGN __ALIGNED__(AMD_CONTROL_DIRECTIVES_ALIGN_BYTES)
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typedef AMD_CONTROL_DIRECTIVES_ALIGN struct amd_control_directives_s {
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amd_enabled_control_directive64_t enabled_control_directives;
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uint16_t enable_break_exceptions;
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uint16_t enable_detect_exceptions;
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uint32_t max_dynamic_group_size;
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uint64_t max_flat_grid_size;
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uint32_t max_flat_workgroup_size;
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uint8_t required_dim;
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uint8_t reserved1[3];
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uint64_t required_grid_size[3];
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uint32_t required_workgroup_size[3];
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uint8_t reserved2[60];
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} amd_control_directives_t;
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// AMD Kernel Code.
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#define AMD_ISA_ALIGN_BYTES 256
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#define AMD_KERNEL_CODE_ALIGN_BYTES 64
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#define AMD_KERNEL_CODE_ALIGN __ALIGNED__(AMD_KERNEL_CODE_ALIGN_BYTES)
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typedef AMD_KERNEL_CODE_ALIGN struct amd_kernel_code_s {
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amd_kernel_code_version32_t amd_kernel_code_version_major;
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amd_kernel_code_version32_t amd_kernel_code_version_minor;
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amd_machine_kind16_t amd_machine_kind;
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amd_machine_version16_t amd_machine_version_major;
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amd_machine_version16_t amd_machine_version_minor;
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amd_machine_version16_t amd_machine_version_stepping;
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int64_t kernel_code_entry_byte_offset;
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int64_t kernel_code_prefetch_byte_offset;
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uint64_t kernel_code_prefetch_byte_size;
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uint64_t max_scratch_backing_memory_byte_size;
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amd_compute_pgm_rsrc_one32_t compute_pgm_rsrc1;
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amd_compute_pgm_rsrc_two32_t compute_pgm_rsrc2;
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amd_kernel_code_properties32_t kernel_code_properties;
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uint32_t workitem_private_segment_byte_size;
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uint32_t workgroup_group_segment_byte_size;
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uint32_t gds_segment_byte_size;
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uint64_t kernarg_segment_byte_size;
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uint32_t workgroup_fbarrier_count;
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uint16_t wavefront_sgpr_count;
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uint16_t workitem_vgpr_count;
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uint16_t reserved_vgpr_first;
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uint16_t reserved_vgpr_count;
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uint16_t reserved_sgpr_first;
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uint16_t reserved_sgpr_count;
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uint16_t debug_wavefront_private_segment_offset_sgpr;
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uint16_t debug_private_segment_buffer_sgpr;
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||
|
|
amd_powertwo8_t kernarg_segment_alignment;
|
||
|
|
amd_powertwo8_t group_segment_alignment;
|
||
|
|
amd_powertwo8_t private_segment_alignment;
|
||
|
|
amd_powertwo8_t wavefront_size;
|
||
|
|
int32_t call_convention;
|
||
|
|
uint8_t reserved1[12];
|
||
|
|
uint64_t runtime_loader_kernel_symbol;
|
||
|
|
amd_control_directives_t control_directives;
|
||
|
|
} amd_kernel_code_t;
|
||
|
|
|
||
|
|
// TODO: this struct should be completely gone once debugger designs/implements
|
||
|
|
// Debugger APIs.
|
||
|
|
typedef struct amd_runtime_loader_debug_info_s {
|
||
|
|
const void* elf_raw;
|
||
|
|
size_t elf_size;
|
||
|
|
const char *kernel_name;
|
||
|
|
const void *owning_segment;
|
||
|
|
} amd_runtime_loader_debug_info_t;
|
||
|
|
|
||
|
|
#endif // AMD_HSA_KERNEL_CODE_H
|