2019-03-14 19:39:20 -07:00
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/*************************************************************************
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2021-04-12 16:00:11 -07:00
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* Copyright (c) 2015-2021, NVIDIA CORPORATION. All rights reserved.
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2019-03-14 19:39:20 -07:00
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*
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* See LICENSE.txt for license information
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************************************************************************/
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#ifndef NCCL_DEVICE_H_
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#define NCCL_DEVICE_H_
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#include "nccl.h"
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#include "align.h"
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#include <stdint.h>
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#define NCCL_NUM_FUNCTIONS 5 // SendRecv not included for now
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typedef enum { ncclFuncBroadcast, ncclFuncReduce, ncclFuncAllGather, ncclFuncReduceScatter, ncclFuncAllReduce, ncclFuncSendRecv} ncclFunc_t;
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extern const char* ncclFuncStr[NCCL_NUM_FUNCTIONS];
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#define NCCL_NUM_ALGORITHMS 3 // Tree/Ring/CollNet
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#define NCCL_ALGO_TREE 0
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#define NCCL_ALGO_RING 1
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#define NCCL_ALGO_COLLNET 2
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extern const char* ncclAlgoStr[NCCL_NUM_ALGORITHMS];
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#define NCCL_NUM_PROTOCOLS 3 // Simple/LL/LL128
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#define NCCL_PROTO_LL 0
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#define NCCL_PROTO_LL128 1
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#define NCCL_PROTO_SIMPLE 2
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extern const char* ncclProtoStr[NCCL_NUM_PROTOCOLS];
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#define NCCL_MAX_OPS 2048
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#define NCCL_STEPS 8
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union ncclLLFifoLine {
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/* Flags have to be *after* data, because otherwise, an incomplete receive
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from the network may receive the flag but not the data.
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Note this is assuming that either we receive contiguous chunks of data
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(sockets) or data is written with an atomicity of 8 bytes (IB/RDMA). */
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struct {
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uint32_t data1;
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uint32_t flag1;
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uint32_t data2;
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uint32_t flag2;
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};
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uint64_t v[2];
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int4 i4;
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};
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2019-11-19 14:57:39 -08:00
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#define WARP_SIZE 32
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#define MAXCHANNELS 32
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#define NCCL_MAX_NTHREADS 640
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#define NCCL_SIMPLE_MAX_NTHREADS 512
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#define NCCL_LL_MAX_NTHREADS 512
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#define NCCL_LL_LINES_PER_THREAD 8
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#ifdef TEST_LL_CLEANUP
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#define NCCL_LL_CLEAN_MASK 0x078 // Set to 0x100 to disable cleanup
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#define NCCL_LL_FLAG_MAX 0x100
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#define NCCL_LL_FLAG(a) ((uint32_t)((a) % NCCL_LL_FLAG_MAX))
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#else
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#define NCCL_LL_CLEAN_MASK 0x7ffffff8
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#define NCCL_LL_FLAG(a) ((uint32_t)(a))
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#endif
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// Make sure the clean mask will last for at least NCCL_NSTEPS
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static_assert(NCCL_LL_CLEAN_MASK % NCCL_STEPS == 0, "Invalid NCCL_LL_CLEAN_MASK value");
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#define NCCL_LL128_LINESIZE 128
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#define NCCL_LL128_LINEELEMS (NCCL_LL128_LINESIZE/sizeof(uint64_t))
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#define NCCL_LL128_DATAELEMS (NCCL_LL128_LINEELEMS-1)
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#define NCCL_LL128_MAX_NTHREADS 640
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#define NCCL_LL128_ELEMS_PER_THREAD 120
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// Receiving from up to 3 sources is more compute intensive than sending
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// to 3 dests. Use 70% for reduce and 30% for bcast.
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#define NCCL_LL128_SPLIT(nt) ((nt*7/(10*32))*32)
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#define NCCL_LL128_SHMEM_ELEMS_PER_THREAD 8
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#define NCCL_LL128_SHMEM_SIZE (NCCL_LL128_SHMEM_ELEMS_PER_THREAD*NCCL_LL128_MAX_NTHREADS)
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#define NCCL_DIRECT_GPU 0x01
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#define NCCL_DIRECT_NIC 0x10
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struct ncclConnInfo {
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// Regular comm mechanism
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char *buffs[NCCL_NUM_PROTOCOLS]; // Local for recv, remote for send
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uint64_t *tail; // Local for recv, remote for send
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uint64_t *head; // Local for send, remote for recv
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int direct; // Direct communication
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int shared; // Buffers are shared
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void **ptrExchange; // Pointer exchange for direct communication
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int *sizesFifo; // Sizes fifo from GPU to proxy
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void* *ptrsFifo; // Buffer fifo from proxy to GPU
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uint64_t step; // Keep where we are
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uint64_t llLastCleaning;
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};
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struct ncclConnector {
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int connected;
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struct ncclProxyArgs *proxyAppend;
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struct ncclProxyArgs **proxyAppendPtr;
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struct ncclTransportComm* transportComm;
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void* transportResources;
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struct ncclConnInfo conn;
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struct ncclComm *comm;
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};
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struct ncclRing {
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// Shortcuts for userRanks[1] and userRanks[n-1]
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int prev;
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int next;
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// Maps an internal nccl index to user-specified rank order. This is necessary
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// since we need to know how the user expects data to be ordered across
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// devices. Ordered from current device.
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int* userRanks;
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int* devUserRanks;
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};
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#define NCCL_MAX_TREE_ARITY 3
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struct ncclTree {
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int depth;
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int up;
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int down[NCCL_MAX_TREE_ARITY];
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};
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#define NCCL_MAX_DIRECT_ARITY 7
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struct ncclDirect {
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int depth;
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int out;
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int nHeads;
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int headRank;
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int shift;
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int up[NCCL_MAX_DIRECT_ARITY];
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int down[NCCL_MAX_DIRECT_ARITY];
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};
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#define NCCL_MAX_CONNS 2
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struct ncclPeer {
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struct ncclConnector send[NCCL_MAX_CONNS];
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struct ncclConnector recv[NCCL_MAX_CONNS];
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};
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struct ncclDevComm;
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#define NCCL_MAX_WORK_ELEMENTS 8
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#define NCCL_MAX_GROUPS (NCCL_MAX_WORK_ELEMENTS*2)
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/* ncclWork is to be a power of two, currently 8x64 bytes, */
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/* to make sure reads to host from the CUDA kernel are aligned. */
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/* Make sure to adjust padding at the end of ncclWorkElem. */
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struct ncclWorkElem {
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// Header
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struct ncclDevComm* comm;
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uint16_t nThreads;
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uint16_t funcIndex;
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uint16_t index;
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uint16_t active;
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const void * sendbuff;
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void * recvbuff;
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// Op-specific fields.
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union {
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struct {
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size_t count;
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size_t lastChunkSize;
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uint32_t root;
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uint8_t bid;
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uint8_t nChannels;
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} coll;
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struct {
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size_t sendCount;
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size_t recvCount;
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int sendChunkSize;
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int recvChunkSize;
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int32_t delta;
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uint16_t nThreads;
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} p2p;
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uint64_t align[4];
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};
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};
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struct ncclWork {
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struct ncclWorkElem elems[NCCL_MAX_WORK_ELEMENTS];
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};
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static_assert(sizeof(struct ncclWorkElem) == (0x10*sizeof(int)), "ncclWorkElem must have a pow2 size");
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struct ncclChannel {
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union {
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struct {
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struct ncclRing ring;
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struct ncclTree tree;
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struct ncclDirect collTree;
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int id;
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// Communication structures
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struct ncclPeer* peers;
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struct ncclPeer* devPeers;
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// Operation list for aggregation
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struct ncclWork* workFifo;
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int workCount;
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uint64_t workFifoTail; // Only used by CPU
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uint16_t index; // Only used by GPU
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// GDRCOPY support
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struct ncclWork* workFifoGdr;
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struct ncclWork* workFifoDev;
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void* gdrMemDesc;
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};
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int data[0x80];
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};
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};
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static_assert(sizeof(struct ncclChannel) == 0x80*sizeof(int), "ncclChannel must have a pow2 size");
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struct ncclDevComm {
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int rank;
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int nRanks;
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int buffSizes[NCCL_NUM_PROTOCOLS];
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// Flag to ask NCCL kernels to abort
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volatile uint32_t *abortFlag;
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// Channels, device side
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struct ncclChannel* channels;
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};
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#endif
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