tests/workloads/kernel_substr/MI300A_A1/pmc_perf.csv

Dispatch_ID,GPU_ID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Correlation_ID,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_EA0_WRREQ_64B_sum,TCC_EA0_WRREQ_DRAM_sum,TCC_EA0_WRREQ_sum,TCC_EA0_WR_UNCACHED_32B_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_TRANSLATION_MISS_sum,Wave_Size_1,Correlation_ID_1,XCC_Index,TCC_EA0_WRREQ[0],TCC_EA0_WRREQ_64B[0],TCC_EA0_WRREQ_LEVEL[0],TCC_HIT[0],TCC_EA0_WRREQ[1],TCC_EA0_WRREQ_64B[1],TCC_EA0_WRREQ_LEVEL[1],TCC_HIT[1],TCC_EA0_WRREQ[2],TCC_EA0_WRREQ_64B[2],TCC_EA0_WRREQ_LEVEL[2],TCC_HIT[2],TCC_EA0_WRREQ[3],TCC_EA0_WRREQ_64B[3],TCC_EA0_WRREQ_LEVEL[3],TCC_HIT[3],TCC_EA0_WRREQ[4],TCC_EA0_WRREQ_64B[4],TCC_EA0_WRREQ_LEVEL[4],TCC_HIT[4],TCC_EA0_WRREQ[5],TCC_EA0_WRREQ_64B[5],TCC_EA0_WRREQ_LEVEL[5],TCC_HIT[5],TCC_EA0_WRREQ[6],TCC_EA0_WRREQ_64B[6],TCC_EA0_WRREQ_LEVEL[6],TCC_HIT[6],TCC_EA0_WRREQ[7],TCC_EA0_WRREQ_64B[7],TCC_EA0_WRREQ_LEVEL[7],TCC_HIT[7],TCC_EA0_WRREQ[8],TCC_EA0_WRREQ_64B[8],TCC_EA0_WRREQ_LEVEL[8],TCC_HIT[8],TCC_EA0_WRREQ[9],TCC_EA0_WRREQ_64B[9],TCC_EA0_WRREQ_LEVEL[9],TCC_HIT[9],TCC_EA0_WRREQ[10],TCC_EA0_WRREQ_64B[10],TCC_EA0_WRREQ_LEVEL[10],TCC_HIT[10],TCC_EA0_WRREQ[11],TCC_EA0_WRREQ_64B[11],TCC_EA0_WRREQ_LEVEL[11],TCC_HIT[11],TCC_EA0_WRREQ[12],TCC_EA0_WRREQ_64B[12],TCC_EA0_WRREQ_LEVEL[12],TCC_HIT[12],TCC_EA0_WRREQ[13],TCC_EA0_WRREQ_64B[13],TCC_EA0_WRREQ_LEVEL[13],TCC_HIT[13],TCC_EA0_WRREQ[14],TCC_EA0_WRREQ_64B[14],TCC_EA0_WRREQ_LEVEL[14],TCC_HIT[14],TCC_EA0_WRREQ[15],TCC_EA0_WRREQ_64B[15],TCC_EA0_WRREQ_LEVEL[15],TCC_HIT[15],TCC_EA0_WRREQ[16],TCC_EA0_WRREQ_64B[16],TCC_EA0_WRREQ_LEVEL[16],TCC_HIT[16],TCC_EA0_WRREQ[17],TCC_EA0_WRREQ_64B[17],TCC_EA0_WRREQ_LEVEL[17],TCC_HIT[17],TCC_EA0_WRREQ[18],TCC_EA0_WRREQ_64B[18],TCC_EA0_WRREQ_LEVEL[18],TCC_HIT[18],TCC_EA0_WRREQ[19],TCC_EA0_WRREQ_64B[19],TCC_EA0_WRREQ_LEVEL[19],TCC_HIT[19],TCC_EA0_WRREQ[20],TCC_EA0_WRREQ_64B[20],TCC_EA0_WRREQ_LEVEL[20],TCC_HIT[20],TCC_EA0_WRREQ[21],TCC_EA0_WRREQ_64B[21],TCC_EA0_WRREQ_LEVEL[21],TCC_HIT[21],TCC_EA0_WRREQ[22],TCC_EA0_WRREQ_64B[22],TCC_EA0_WRREQ_LEVEL[22],TCC_HIT[22],TCC_EA0_WRREQ[23],TCC_EA0_WRREQ_64B[23],TCC_EA0_WRREQ_LEVEL[23],TCC_HIT[23],TCC_EA0_WRREQ[24],TCC_EA0_WRREQ_64B[24],TCC_EA0_WRREQ_LEVEL[24],TCC_HIT[24],TCC_EA0_WRREQ[25],TCC_EA0_WRREQ_64B[25],TCC_EA0_WRREQ_LEVEL[25],TCC_HIT[25],TCC_EA0_WRREQ[26],TCC_EA0_WRREQ_64B[26],TCC_EA0_WRREQ_LEVEL[26],TCC_HIT[26],TCC_EA0_WRREQ[27],TCC_EA0_WRREQ_64B[27],TCC_EA0_WRREQ_LEVEL[27],TCC_HIT[27],TCC_EA0_WRREQ[28],TCC_EA0_WRREQ_64B[28],TCC_EA0_WRREQ_LEVEL[28],TCC_HIT[28],TCC_EA0_WRREQ[29],TCC_EA0_WRREQ_64B[29],TCC_EA0_WRREQ_LEVEL[29],TCC_HIT[29],TCC_EA0_WRREQ[30],TCC_EA0_WRREQ_64B[30],TCC_EA0_WRREQ_LEVEL[30],TCC_HIT[30],TCC_EA0_WRREQ[31],TCC_EA0_WRREQ_64B[31],TCC_EA0_WRREQ_LEVEL[31],TCC_HIT[31],TCC_EA0_WRREQ[32],TCC_EA0_WRREQ_64B[32],TCC_EA0_WRREQ_LEVEL[32],TCC_HIT[32],TCC_EA0_WRREQ[33],TCC_EA0_WRREQ_64B[33],TCC_EA0_WRREQ_LEVEL[33],TCC_HIT[33],TCC_EA0_WRREQ[34],TCC_EA0_WRREQ_64B[34],TCC_EA0_WRREQ_LEVEL[34],TCC_HIT[34],TCC_EA0_WRREQ[35],TCC_EA0_WRREQ_64B[35],TCC_EA0_WRREQ_LEVEL[35],TCC_HIT[35],TCC_EA0_WRREQ[36],TCC_EA0_WRREQ_64B[36],TCC_EA0_WRREQ_LEVEL[36],TCC_HIT[36],TCC_EA0_WRREQ[37],TCC_EA0_WRREQ_64B[37],TCC_EA0_WRREQ_LEVEL[37],TCC_HIT[37],TCC_EA0_WRREQ[38],TCC_EA0_WRREQ_64B[38],TCC_EA0_WRREQ_LEVEL[38],TCC_HIT[38],TCC_EA0_WRREQ[39],TCC_EA0_WRREQ_64B[39],TCC_EA0_WRREQ_LEVEL[39],TCC_HIT[39],TCC_EA0_WRREQ[40],TCC_EA0_WRREQ_64B[40],TCC_EA0_WRREQ_LEVEL[40],TCC_HIT[40],TCC_EA0_WRREQ[41],TCC_EA0_WRREQ_64B[41],TCC_EA0_WRREQ_LEVEL[41],TCC_HIT[41],TCC_EA0_WRREQ[42],TCC_EA0_WRREQ_64B[42],TCC_EA0_WRREQ_LEVEL[42],TCC_HIT[42],TCC_EA0_WRREQ[43],TCC_EA0_WRREQ_64B[43],TCC_EA0_WRREQ_LEVEL[43],TCC_HIT[43],TCC_EA0_WRREQ[44],TCC_EA0_WRREQ_64B[44],TCC_EA0_WRREQ_LEVEL[44],TCC_HIT[44],TCC_EA0_WRREQ[45],TCC_EA
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Add CI workloads for MI300A_A1 and MI300X_A1 2024-05-29 18:53:11 +00:00			Dispatch_ID,GPU_ID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Correlation_ID,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_EA0_WRREQ_64B_sum,TCC_EA0_WRREQ_DRAM_sum,TCC_EA0_WRREQ_sum,TCC_EA0_WR_UNCACHED_32B_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_TRANSLATION_MISS_sum,Wave_Size_1,Correlation_ID_1,XCC_Index,TCC_EA0_WRREQ[0],TCC_EA0_WRREQ_64B[0],TCC_EA0_WRREQ_LEVEL[0],TCC_HIT[0],TCC_EA0_WRREQ[1],TCC_EA0_WRREQ_64B[1],TCC_EA0_WRREQ_LEVEL[1],TCC_HIT[1],TCC_EA0_WRREQ[2],TCC_EA0_WRREQ_64B[2],TCC_EA0_WRREQ_LEVEL[2],TCC_HIT[2],TCC_EA0_WRREQ[3],TCC_EA0_WRREQ_64B[3],TCC_EA0_WRREQ_LEVEL[3],TCC_HIT[3],TCC_EA0_WRREQ[4],TCC_EA0_WRREQ_64B[4],TCC_EA0_WRREQ_LEVEL[4],TCC_HIT[4],TCC_EA0_WRREQ[5],TCC_EA0_WRREQ_64B[5],TCC_EA0_WRREQ_LEVEL[5],TCC_HIT[5],TCC_EA0_WRREQ[6],TCC_EA0_WRREQ_64B[6],TCC_EA0_WRREQ_LEVEL[6],TCC_HIT[6],TCC_EA0_WRREQ[7],TCC_EA0_WRREQ_64B[7],TCC_EA0_WRREQ_LEVEL[7],TCC_HIT[7],TCC_EA0_WRREQ[8],TCC_EA0_WRREQ_64B[8],TCC_EA0_WRREQ_LEVEL[8],TCC_HIT[8],TCC_EA0_WRREQ[9],TCC_EA0_WRREQ_64B[9],TCC_EA0_WRREQ_LEVEL[9],TCC_HIT[9],TCC_EA0_WRREQ[10],TCC_EA0_WRREQ_64B[10],TCC_EA0_WRREQ_LEVEL[10],TCC_HIT[10],TCC_EA0_WRREQ[11],TCC_EA0_WRREQ_64B[11],TCC_EA0_WRREQ_LEVEL[11],TCC_HIT[11],TCC_EA0_WRREQ[12],TCC_EA0_WRREQ_64B[12],TCC_EA0_WRREQ_LEVEL[12],TCC_HIT[12],TCC_EA0_WRREQ[13],TCC_EA0_WRREQ_64B[13],TCC_EA0_WRREQ_LEVEL[13],TCC_HIT[13],TCC_EA0_WRREQ[14],TCC_EA0_WRREQ_64B[14],TCC_EA0_WRREQ_LEVEL[14],TCC_HIT[14],TCC_EA0_WRREQ[15],TCC_EA0_WRREQ_64B[15],TCC_EA0_WRREQ_LEVEL[15],TCC_HIT[15],TCC_EA0_WRREQ[16],TCC_EA0_WRREQ_64B[16],TCC_EA0_WRREQ_LEVEL[16],TCC_HIT[16],TCC_EA0_WRREQ[17],TCC_EA0_WRREQ_64B[17],TCC_EA0_WRREQ_LEVEL[17],TCC_HIT[17],TCC_EA0_WRREQ[18],TCC_EA0_WRREQ_64B[18],TCC_EA0_WRREQ_LEVEL[18],TCC_HIT[18],TCC_EA0_WRREQ[19],TCC_EA0_WRREQ_64B[19],TCC_EA0_WRREQ_LEVEL[19],TCC_HIT[19],TCC_EA0_WRREQ[20],TCC_EA0_WRREQ_64B[20],TCC_EA0_WRREQ_LEVEL[20],TCC_HIT[20],TCC_EA0_WRREQ[21],TCC_EA0_WRREQ_64B[21],TCC_EA0_WRREQ_LEVEL[21],TCC_HIT[21],TCC_EA0_WRREQ[22],TCC_EA0_WRREQ_64B[22],TCC_EA0_WRREQ_LEVEL[22],TCC_HIT[22],TCC_EA0_WRREQ[23],TCC_EA0_WRREQ_64B[23],TCC_EA0_WRREQ_LEVEL[23],TCC_HIT[23],TCC_EA0_WRREQ[24],TCC_EA0_WRREQ_64B[24],TCC_EA0_WRREQ_LEVEL[24],TCC_HIT[24],TCC_EA0_WRREQ[25],TCC_EA0_WRREQ_64B[25],TCC_EA0_WRREQ_LEVEL[25],TCC_HIT[25],TCC_EA0_WRREQ[26],TCC_EA0_WRREQ_64B[26],TCC_EA0_WRREQ_LEVEL[26],TCC_HIT[26],TCC_EA0_WRREQ[27],TCC_EA0_WRREQ_64B[27],TCC_EA0_WRREQ_LEVEL[27],TCC_HIT[27],TCC_EA0_WRREQ[28],TCC_EA0_WRREQ_64B[28],TCC_EA0_WRREQ_LEVEL[28],TCC_HIT[28],TCC_EA0_WRREQ[29],TCC_EA0_WRREQ_64B[29],TCC_EA0_WRREQ_LEVEL[29],TCC_HIT[29],TCC_EA0_WRREQ[30],TCC_EA0_WRREQ_64B[30],TCC_EA0_WRREQ_LEVEL[30],TCC_HIT[30],TCC_EA0_WRREQ[31],TCC_EA0_WRREQ_64B[31],TCC_EA0_WRREQ_LEVEL[31],TCC_HIT[31],TCC_EA0_WRREQ[32],TCC_EA0_WRREQ_64B[32],TCC_EA0_WRREQ_LEVEL[32],TCC_HIT[32],TCC_EA0_WRREQ[33],TCC_EA0_WRREQ_64B[33],TCC_EA0_WRREQ_LEVEL[33],TCC_HIT[33],TCC_EA0_WRREQ[34],TCC_EA0_WRREQ_64B[34],TCC_EA0_WRREQ_LEVEL[34],TCC_HIT[34],TCC_EA0_WRREQ[35],TCC_EA0_WRREQ_64B[35],TCC_EA0_WRREQ_LEVEL[35],TCC_HIT[35],TCC_EA0_WRREQ[36],TCC_EA0_WRREQ_64B[36],TCC_EA0_WRREQ_LEVEL[36],TCC_HIT[36],TCC_EA0_WRREQ[37],TCC_EA0_WRREQ_64B[37],TCC_EA0_WRREQ_LEVEL[37],TCC_HIT[37],TCC_EA0_WRREQ[38],TCC_EA0_WRREQ_64B[38],TCC_EA0_WRREQ_LEVEL[38],TCC_HIT[38],TCC_EA0_WRREQ[39],TCC_EA0_WRREQ_64B[39],TCC_EA0_WRREQ_LEVEL[39],TCC_HIT[39],TCC_EA0_WRREQ[40],TCC_EA0_WRREQ_64B[40],TCC_EA0_WRREQ_LEVEL[40],TCC_HIT[40],TCC_EA0_WRREQ[41],TCC_EA0_WRREQ_64B[41],TCC_EA0_WRREQ_LEVEL[41],TCC_HIT[41],TCC_EA0_WRREQ[42],TCC_EA0_WRREQ_64B[42],TCC_EA0_WRREQ_LEVEL[42],TCC_HIT[42],TCC_EA0_WRREQ[43],TCC_EA0_WRREQ_64B[43],TCC_EA0_WRREQ_LEVEL[43],TCC_HIT[43],TCC_EA0_WRREQ[44],TCC_EA0_WRREQ_64B[44],TCC_EA0_WRREQ_LEVEL[44],TCC_HIT[44],TCC_EA0_WRREQ[45],TCC_EA
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