Files
rocm-systems/src/include/comm.h
T

171 lines
4.3 KiB
C
Raw Normal View History

2019-03-14 19:39:20 -07:00
/*************************************************************************
2020-01-16 16:02:42 -08:00
* Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
2020-01-15 17:54:27 -07:00
* Modifications Copyright (c) 2019-2020 Advanced Micro Devices, Inc. All rights reserved.
2019-03-14 19:39:20 -07:00
*
* See LICENSE.txt for license information
************************************************************************/
#ifndef NCCL_COMM_H_
#define NCCL_COMM_H_
2019-11-19 14:57:39 -08:00
#include "transport.h"
2020-05-12 14:40:18 -07:00
#include "p2p.h"
2021-01-28 09:45:01 -07:00
// [RCCL]
#include "clique/CliqueManager.h"
// [/RCCL]
2019-11-19 14:57:39 -08:00
#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
#else
2019-03-14 19:39:20 -07:00
#if CUDART_VERSION < 9000
struct cudaLaunchParams {
void *func;
dim3 gridDim;
dim3 blockDim;
void **args;
size_t sharedMem;
cudaStream_t stream;
};
#endif
#endif
2019-03-14 19:39:20 -07:00
2019-07-05 15:43:00 -07:00
#define CACHE_LINE_SIZE 64
2019-03-14 19:39:20 -07:00
#define MEM_ALIGN 4096
2019-07-12 08:30:05 -07:00
#define CUDA_IPC_MIN 2097152UL
2019-03-14 19:39:20 -07:00
2019-11-19 14:57:39 -08:00
// Channels / LL tuning
#define NCCL_LL_THREAD_THRESHOLD 8
#define NCCL_LL128_THREAD_THRESHOLD 8
#define NCCL_SIMPLE_THREAD_THRESHOLD 64
2019-03-14 19:39:20 -07:00
struct ncclSendMem {
union {
struct {
uint64_t head;
char pad1[CACHE_LINE_SIZE-sizeof(uint64_t)];
void* ptrExchange;
char pad2[CACHE_LINE_SIZE-sizeof(void*)];
};
char pad3[MEM_ALIGN];
};
2020-05-12 14:40:18 -07:00
char buff[1]; // Actually larger than that
2019-03-14 19:39:20 -07:00
};
struct ncclRecvMem {
union {
struct {
uint64_t tail;
char pad1[CACHE_LINE_SIZE-sizeof(uint64_t)];
int sizesFifo[NCCL_STEPS];
2020-09-04 14:35:05 -07:00
void* ptrsFifo[NCCL_STEPS];
2019-03-14 19:39:20 -07:00
};
char pad4[MEM_ALIGN];
};
char buff[1]; // Actually larger than that
};
struct ncclComm {
struct ncclChannel channels[MAXCHANNELS];
struct ncclPeerInfo* peerInfo;
2019-11-19 14:57:39 -08:00
struct ncclTopoSystem* topo;
2019-03-14 19:39:20 -07:00
void* bootstrap;
2020-09-04 14:35:05 -07:00
// Bitmasks for ncclTransportP2pSetup
int connect;
uint32_t* connectSend;
uint32_t* connectRecv;
2019-03-14 19:39:20 -07:00
int rank; // my rank in the communicator
int nRanks; // number of GPUs in communicator
int cudaDev; // my cuda device index
2019-11-19 14:57:39 -08:00
int64_t busId; // my PCI bus ID in int format
int node;
int nNodes;
int localRanks;
2019-03-14 19:39:20 -07:00
enum { GROUP, PARALLEL } launchMode;
2019-07-05 15:43:00 -07:00
hipStream_t userStream;
2019-03-14 19:39:20 -07:00
bool userStreamSet;
2019-07-05 15:43:00 -07:00
hipEvent_t doneEvent;
2019-03-14 19:39:20 -07:00
bool checkPointers;
// Counter to make sure collectives match (needed for bcast/reduce
// where syncs are not symmetric).
uint64_t opCount;
2019-11-19 14:57:39 -08:00
uint64_t lastOpCount;
2019-03-14 19:39:20 -07:00
// Channels for collectives
int nChannels;
2020-05-12 14:40:18 -07:00
// Channels (per peer) for p2p
int p2pnChannels;
int p2pnChannelsPerPeer;
int p2pChannels[MAXCHANNELS];
// Buffer sizes
int buffSizes[NCCL_NUM_PROTOCOLS];
2019-03-14 19:39:20 -07:00
2019-11-19 14:57:39 -08:00
// Algorithm/Protocols thresholds
ssize_t threadThresholds[NCCL_NUM_ALGORITHMS][NCCL_NUM_PROTOCOLS];
float latencies[NCCL_NUM_FUNCTIONS][NCCL_NUM_ALGORITHMS][NCCL_NUM_PROTOCOLS];
float bandwidths[NCCL_NUM_FUNCTIONS][NCCL_NUM_ALGORITHMS][NCCL_NUM_PROTOCOLS];
2020-01-16 16:02:42 -08:00
int maxThreads[NCCL_NUM_ALGORITHMS][NCCL_NUM_PROTOCOLS];
2019-03-14 19:39:20 -07:00
// An internal CUDA stream for NCCL kernel CGMD launches
int groupCudaStream;
2019-07-05 15:43:00 -07:00
hipStream_t groupStream;
2019-03-14 19:39:20 -07:00
// Whether there has been a fatal error in this communicator.
ncclResult_t fatalError;
// Flag to ask NCCL kernels to abort
volatile uint32_t *abortFlag;
// Device side of the communicator
struct ncclDevComm *devComm;
// Host copy of the devComm (to free CUDA allocs)
struct ncclDevComm hostDevComm;
// Intra-process sync
int intraRank;
int intraRanks;
int* intraBarrier;
int intraPhase;
// Storage for deferred intra-process launch
2019-07-05 15:43:00 -07:00
hipLaunchParams * intraParams;
hipLaunchParams *myParams;
2019-03-14 19:39:20 -07:00
int* intraCudaDevs;
int* intraCGMode; // Whether we can use CUDA9 CGMD or not
int* intraCC; // Only to check all have the same ComputeCap and disable CGMode if not
2020-09-04 14:35:05 -07:00
struct ncclWorkElem args;
2019-03-14 19:39:20 -07:00
void* argsptr;
// Global proxy thread
pthread_t proxyThread;
struct ncclProxyState proxyState;
2020-01-16 16:02:42 -08:00
// Whether this communicator uses collNet
int collNetSupport;
2020-09-04 14:35:05 -07:00
// Store info of async operations
struct ncclInfo* asyncOps;
int asyncOpCount;
size_t asyncTotalSize;
2020-05-12 14:40:18 -07:00
//list of async p2p operation queued in a group semantics
2020-09-04 14:35:05 -07:00
struct ncclP2Plist* p2pSends;
struct ncclP2Plist* p2pRecvs;
int p2pSendCount;
int p2pRecvCount;
2021-01-28 09:45:01 -07:00
// [RCCL]
bool alltoallDisable; // RCCL AllToAll/Scatter/Gather API
CliqueManager* cliqueManager; // CliqueManager handles pointer collection / distribution for clique-based kernels
int rootPid; // Process ID of root
// [/RCCL]
2019-03-14 19:39:20 -07:00
};
#endif