2018-09-24 16:06:59 -07:00
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/*************************************************************************
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2022-01-07 06:39:55 -08:00
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* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
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2018-09-24 16:06:59 -07:00
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*
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* See LICENSE.txt for license information
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************************************************************************/
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#ifndef NCCL_DEVICE_COMMON_H_
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#define NCCL_DEVICE_COMMON_H_
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2019-11-19 14:57:39 -08:00
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#include "collectives.h"
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#include "device.h"
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#include "op128.h"
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#include "network/unpack/unpack_defs.h"
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#define COLL_UNROLL (ncclCollUnroll())
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typedef void(*ncclDevFuncPtr_t)();
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extern __device__ ncclDevFuncPtr_t const ncclDevFuncTable[];
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struct ncclShmemGroup {
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ncclConnInfo *recvConns[NCCL_MAX_NVLS_ARITY];
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ncclConnInfo *sendConns[NCCL_MAX_NVLS_ARITY];
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void* srcs[NCCL_MAX_NVLS_ARITY+1];
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void* dsts[NCCL_MAX_NVLS_ARITY+1];
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union {
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unpackGroupShmem unpack;
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} devicePlugin;
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};
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struct ncclShmemData {
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struct ncclShmemGroup groups[NCCL_MAX_GROUPS];
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uint64_t redOpArgs[NCCL_MAX_NVLS_ARITY+1];
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int channelId;
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int aborted;
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alignas(16) struct ncclDevComm comm;
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alignas(16) struct ncclDevChannel channel;
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alignas(16) struct ncclWork work;
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alignas(16) union {
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unpackShmem unpack;
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} devicePlugin;
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};
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static_assert(offsetof(struct ncclShmemData, work)%16 == 0, "shmem.work needs to be 16B aligned");
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extern __shared__ ncclShmemData ncclShmem;
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#if __CUDA_ARCH__ >= 700
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extern __shared__ ulong2 ncclShmemPerWarp[/*ncclShmemDynamicSize()/sizeof(ulong2)*/];
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#else
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extern __shared__ ulong2 ncclShmemPerWarp[ncclShmemScratchWarpSize()*(NCCL_MAX_NTHREADS/WARP_SIZE)/sizeof(ulong2)];
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#endif
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__device__ inline void* ncclScratchForWarp(int warp) {
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return (char*)ncclShmemPerWarp + warp*ncclShmemScratchWarpSize();
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}
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__device__ inline bool barrierReduceAny(int bit) {
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uint32_t popc;
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asm ("{"
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".reg .pred barr_pred;"
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"setp.eq.u32 barr_pred, %1, 1;"
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"bar.red.popc.u32 %0, 2, barr_pred;"
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"}" : "=r"(popc) : "r"(bit));
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return popc != 0;
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}
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// Copy 16-byte aligned data. You must call with at least `(bytes+15)/16` threads.
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inline __device__ void copyToShmem16(int tid, void* dst, void const* src, int bytes) {
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int offset = 16*tid;
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if (offset < bytes) {
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uint64_t a=0, b=0;
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asm("ld.v2.u64 {%0,%1},[%2];" : "=l"(a),"=l"(b) : "l"((char const*)src + offset));
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asm volatile("st.v2.u64 [%0],{%1,%2};" :: "l"((char*)dst + offset), "l"(a), "l"(b));
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}
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}
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template<ncclFunc_t Fn, typename T, typename RedOp, int Algo, int Proto>
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struct RunWorkElement {
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__device__ void run(ncclWorkElem*) {
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// Put NOT IMPLEMENTED behavior here.
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}
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};
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template<ncclFunc_t Fn, typename T, typename RedOp, int Algo, int Proto>
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struct RunWork {
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// This __forceinline__ is necessary. The compiler was inserting a function call
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// here from the LL ncclKernel.
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__device__ __forceinline__ void run(ncclWork *w) {
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int wid = threadIdx.x / WARP_SIZE;
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ncclWorkElem* we = w->header.type == ncclWorkTypeRegColl ? &w->regElems[0].elem : &w->elems[0];
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int stride = w->header.type == ncclWorkTypeRegColl ? sizeof(ncclWorkElemReg) : sizeof(ncclWorkElem);
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#pragma unroll 1
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while ((char*)we + stride <= (char*)(w+1) && we->isUsed) {
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if (wid < we->nWarps) {
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RunWorkElement<Fn, T, RedOp, Algo, Proto>().run(we);
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}
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we = (ncclWorkElem*)((char*)we + stride);
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}
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}
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};
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static __device__ void ncclRedopPtrDeref(struct ncclWorkElem* we) {
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if (we->isUsed && we->redOpArgIsPtr) {
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/* redOpArg is a pointer to the scalar value, so we'll dereference it
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* here so that redOpArg holds the bits of the scalar going forward.
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* The tricky thing is we don't know its type T since that's encoded in
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* the funcIndex. Because it would be difficult to get sizeof(T) from
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* funcIndex, we'll cheat and just dereference the largest possible size
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* given the alignment of the pointer. We might be reading in more bytes
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* than we need but that's harmless.
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*/
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if (we->redOpArg%2 != 0)
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we->redOpArg = *reinterpret_cast<uint8_t*>(we->redOpArg);
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else if (we->redOpArg%4 != 0)
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we->redOpArg = *reinterpret_cast<uint16_t*>(we->redOpArg);
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else if (we->redOpArg%8 != 0)
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we->redOpArg = *reinterpret_cast<uint32_t*>(we->redOpArg);
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else
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we->redOpArg = *reinterpret_cast<uint64_t*>(we->redOpArg);
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}
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}
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template<int SpecializedFnId, typename SpecializedRunWork>
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__device__ void ncclKernelMain(struct ncclDevComm* comm, uint64_t channelMask, struct ncclWork* workHead) {
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int tid = threadIdx.x;
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// To map blockId to channelId, we need the n'th set bit of channelMask which
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// is the inverse of counting the number of set bits among the the first n.
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if (tid < WARP_SIZE) {
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int x = tid;
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if (channelMask & (1ull<<x)) {
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int y = __popcll(channelMask & ((1ull<<x)-1));
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if (blockIdx.x == y) ncclShmem.channelId = x;
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}
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if (32 < MAXCHANNELS) {
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x = 32 + tid;
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if (channelMask & (1ull<<x)) {
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int y = __popcll(channelMask & ((1ull<<x)-1));
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if (blockIdx.x == y) ncclShmem.channelId = x;
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}
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}
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}
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__syncthreads(); // publish ncclShmem.channelId
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int channelId = ncclShmem.channelId;
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/* set abort flag to 0 */
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if (tid == 0) ncclShmem.aborted = 0;
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if (true) {
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void *dst, *src;
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int bytes;
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// Use first 3 warps to load comm, channel, and work into ncclShmem
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switch (tid/WARP_SIZE) {
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case 0:
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dst = &ncclShmem.comm;
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src = comm;
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bytes = sizeof(ncclDevComm);
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static_assert(sizeof(ncclDevComm) <= 16*WARP_SIZE, "ncclDevComm cannot be loaded by a single warp in one insn.");
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break;
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case 1:
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// Get address of channel without incurring indirect load from ncclDevComm::channels
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dst = &ncclShmem.channel;
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src = &((ncclDevCommAndChannels*)comm)->channels[channelId];
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bytes = sizeof(ncclDevChannel);
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static_assert(sizeof(ncclDevChannel) <= 16*WARP_SIZE, "ncclDevChannel cannot be loaded by a single warp in one insn.");
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break;
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case 2:
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dst = &ncclShmem.work;
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src = workHead + blockIdx.x;
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bytes = sizeof(ncclWork);
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static_assert(sizeof(ncclWork) <= 16*WARP_SIZE, "ncclWork cannot be loaded by a single warp in one insn.");
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break;
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default:
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bytes = 0;
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break;
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}
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if (bytes) copyToShmem16(tid%WARP_SIZE, dst, src, bytes);
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}
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__syncthreads(); // publish ncclShmem
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while (true) {
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// Notify host that all fifo reads are complete.
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if (tid == 0 && ncclShmem.work.header.isLast && ncclShmem.work.header.inFifo) {
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*ncclShmem.channel.workFifoDone = ncclShmem.work.header.doneAcks;
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}
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__syncwarp();
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if (ncclShmem.work.header.type == ncclWorkTypeColl) {
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if (tid < NCCL_MAX_WORK_ELEMENTS) ncclRedopPtrDeref(&ncclShmem.work.elems[tid]);
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} else if (ncclShmem.work.header.type == ncclWorkTypeRegColl) {
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if (tid < NCCL_MAX_WORK_ELEMENTS_REG) ncclRedopPtrDeref(&ncclShmem.work.regElems[tid].elem);
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}
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__syncthreads();
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if (0 <= SpecializedFnId && ncclShmem.work.header.funcIndex == (unsigned)SpecializedFnId) {
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SpecializedRunWork().run(&ncclShmem.work);
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} else {
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ncclDevFuncTable[ncclShmem.work.header.funcIndex]();
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}
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int workIxNext = ncclShmem.work.header.workNext;
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__syncthreads();
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if (ncclShmem.work.header.isLast) break;
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copyToShmem16(tid, &ncclShmem.work, workHead + workIxNext, sizeof(ncclWork));
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{ // Check whether the last operation was aborted and make sure all threads exit
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int aborted = tid == 0 ? *comm->abortFlag : 0;
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if (barrierReduceAny(aborted)) // publish ncclShmem.work
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break;
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}
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2020-09-04 14:35:05 -07:00
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}
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2018-09-24 16:06:59 -07:00
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}
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2018-12-13 15:56:12 -08:00
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2023-09-26 05:47:28 -07:00
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__global__ void ncclDevKernel_Generic(struct ncclDevComm* comm, uint64_t channelMask, struct ncclWork* workHead);
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__device__ void ncclDevFunc_Nop();
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#define DEFINE_ncclDevKernel(suffix, coll, redop, ty, algo, proto, specializedFnId) \
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__global__ void ncclDevKernel_##suffix(struct ncclDevComm* comm, uint64_t channelMask, struct ncclWork* workHead) { \
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ncclKernelMain<specializedFnId, RunWork<coll, ty, redop<ty>, algo, proto>>(comm, channelMask, workHead); \
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}
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#define DEFINE_ncclDevFunc(suffix, coll, redop, ty, algo, proto) \
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__device__ void ncclDevFunc_##suffix() { \
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RunWork<coll, ty, redop<ty>, algo, proto>().run(&ncclShmem.work); \
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}
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2018-09-24 16:06:59 -07:00
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#endif
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