hsakmt: Enable graphics handle registration with a virtual address
Currently registering graphics memory without specifying a target node will return a memory handle that's not a virtual address. As a result, ROCr is forced to register with a target node for IPC usage. Mapping memory without specifying a target node afterwards will result in mapping to the target node that was imported because the previous import call flags this node targeting action to future mapping. For ROCr IPC usage, ROCr wants to map to all GPU nodes if the target node is not specified. Allow the caller to register graphics handles that returns a virtual address without having to specify the target node so that the caller can make a subsequent map call to all GPUs. Change-Id: I5a935092b885cc3568e4f3a5dd951c7ec6c84fca
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@@ -3586,7 +3586,8 @@ HSAKMT_STATUS hsakmt_fmm_register_memory(void *address, uint64_t size_in_bytes,
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HSAKMT_STATUS hsakmt_fmm_register_graphics_handle(HSAuint64 GraphicsResourceHandle,
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HsaGraphicsResourceInfo *GraphicsResourceInfo,
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uint32_t *gpu_id_array,
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uint32_t gpu_id_array_size)
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uint32_t gpu_id_array_size,
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HSA_REGISTER_MEM_FLAGS RegisterFlags)
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{
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struct kfd_ioctl_get_dmabuf_info_args infoArgs = {0};
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struct kfd_ioctl_import_dmabuf_args importArgs = {0};
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@@ -3630,7 +3631,7 @@ HSAKMT_STATUS hsakmt_fmm_register_graphics_handle(HSAuint64 GraphicsResourceHand
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goto error_free_metadata;
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/* import DMA buffer without VA assigned */
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if (!gpu_id_array && gpu_id_array_size == 0) {
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if (!gpu_id_array && gpu_id_array_size == 0 && !RegisterFlags.ui32.requiresVAddr) {
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aperture = &mem_handle_aperture;
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} else if (hsakmt_topology_is_svm_needed(gpu_mem[gpu_mem_id].EngineId)) {
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aperture = svm.dgpu_aperture;
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@@ -80,7 +80,8 @@ HSAKMT_STATUS hsakmt_fmm_register_memory(void *address, uint64_t size_in_bytes,
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HSAKMT_STATUS hsakmt_fmm_register_graphics_handle(HSAuint64 GraphicsResourceHandle,
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HsaGraphicsResourceInfo *GraphicsResourceInfo,
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uint32_t *gpu_id_array,
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uint32_t gpu_id_array_size);
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uint32_t gpu_id_array_size,
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HSA_REGISTER_MEM_FLAGS RegisterFlags);
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HSAKMT_STATUS hsakmt_fmm_deregister_memory(void *address);
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HSAKMT_STATUS hsakmt_fmm_export_dma_buf_fd(void *MemoryAddress,
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HSAuint64 MemorySizeInBytes,
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@@ -336,6 +336,23 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtRegisterGraphicsHandleToNodes(HSAuint64 GraphicsRe
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HsaGraphicsResourceInfo *GraphicsResourceInfo,
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HSAuint64 NumberOfNodes,
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HSAuint32 *NodeArray)
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{
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HSA_REGISTER_MEM_FLAGS regFlags;
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regFlags.Value = 0;
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return hsaKmtRegisterGraphicsHandleToNodesExt(GraphicsResourceHandle,
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GraphicsResourceInfo,
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NumberOfNodes,
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NodeArray,
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regFlags);
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}
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HSAKMT_STATUS HSAKMTAPI hsaKmtRegisterGraphicsHandleToNodesExt(HSAuint64 GraphicsResourceHandle,
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HsaGraphicsResourceInfo *GraphicsResourceInfo,
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HSAuint64 NumberOfNodes,
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HSAuint32 *NodeArray,
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HSA_REGISTER_MEM_FLAGS RegisterFlags)
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{
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CHECK_KFD_OPEN();
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uint32_t *gpu_id_array = NULL;
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@@ -351,7 +368,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtRegisterGraphicsHandleToNodes(HSAuint64 GraphicsRe
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if (ret == HSAKMT_STATUS_SUCCESS) {
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ret = hsakmt_fmm_register_graphics_handle(
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GraphicsResourceHandle, GraphicsResourceInfo,
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gpu_id_array, NumberOfNodes * sizeof(uint32_t));
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gpu_id_array, NumberOfNodes * sizeof(uint32_t), RegisterFlags);
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if (ret != HSAKMT_STATUS_SUCCESS)
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free(gpu_id_array);
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}
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