From 04ed74552f9bf1fd6cb42992d1ff69bd2327fcf2 Mon Sep 17 00:00:00 2001 From: kjayapra-amd Date: Sun, 6 Oct 2024 16:15:25 -0400 Subject: [PATCH] SWDEV-459254 - Overwrite cacheline size to 256 for gfx12, as it is used for kernarg alignment. Change-Id: Ia6acf312ee84f6dde1c830fc21f10d3a8a9de5ee [ROCm/clr commit: dd1dd86fd7acb6718546b3ccd26c0cd279726a4c] --- projects/clr/rocclr/device/rocm/rocdevice.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/projects/clr/rocclr/device/rocm/rocdevice.cpp b/projects/clr/rocclr/device/rocm/rocdevice.cpp index 757a113fe5..a2b77c8d0b 100644 --- a/projects/clr/rocclr/device/rocm/rocdevice.cpp +++ b/projects/clr/rocclr/device/rocm/rocdevice.cpp @@ -1208,6 +1208,11 @@ bool Device::populateOCLDeviceConstants() { } assert(info_.globalMemCacheLineSize_ > 0); + // override cache line size to 256 for gfx12, as it is used for kern arg alignment. + if ((isa().versionMajor() >= 12) && (info_.globalMemCacheLineSize_ < 256)) { + info_.globalMemCacheLineSize_ = 256; + } + uint32_t cachesize[4] = {0}; if (HSA_STATUS_SUCCESS != hsa_agent_get_info(bkendDevice_, HSA_AGENT_INFO_CACHE_SIZE, cachesize)) {