Adding timestamp marker into SQTT buffer for gfx9 GPUs (#200)
* Adding TS Marker
* Apply suggestions from code review
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
* Add option to enable/disable RT
---------
Co-authored-by: Giovanni Baraldi <gbaraldi@amd.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
[ROCm/aqlprofile commit: 926ec4a56f]
Этот коммит содержится в:
Baraldi, Giovanni
коммит произвёл
GitHub
GitHub
родитель
1157f97224
Коммит
0542860ef8
@@ -211,6 +211,13 @@ class CmdBuilder {
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/// @param cmdBuf command buffer to be appended with launch command
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virtual void BuildPrimeL2(CmdBuffer* cmdBuf, uint64_t addr) = 0;
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/// @brief Generates RT packets into thread trace buffer (gfx9 only)
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/// @param cmdBuf command buffer to be appended with launch command
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/// @param dst where gpu clock data is r/w. Must persist during packet dispatch
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/// @param reg userdata register address
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/// @param header SQTT packet header
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virtual void BuildGPUClockPacket(CmdBuffer* cmdBuf, uint64_t* dst, const Register& reg, uint32_t header) {};
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/// @brief Release resources used by CmdBuilder
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virtual ~CmdBuilder(){};
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@@ -446,6 +446,83 @@ class Gfx9CmdBuilder : public CmdBuilder {
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uint32_t size, bool wait) {
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BuildCopyRegDataPacket(cmd, get_addr(reg), dst_addr, size, wait);
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}
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std::array<uint32_t, 6> ClockRetrievePacket(uint64_t* dst)
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{
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auto addr = reinterpret_cast<uint64_t>(dst);
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uint32_t header = MakePacket3Header(PACKET3_COPY_DATA, 6 * sizeof(uint32_t));
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uint32_t dword2 =
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PACKET3_COPY_DATA__SRC_SEL(PACKET3_COPY_DATA__SRC_SEL__GPU_CLOCK_COUNT) |
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PACKET3_COPY_DATA__SRC_CACHE_POLICY(PACKET3_COPY_DATA__SRC_CACHE_POLICY__STREAM) |
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PACKET3_COPY_DATA__DST_SEL(PACKET3_COPY_DATA__DST_SEL__MEMORY) |
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PACKET3_COPY_DATA__DST_CACHE_POLICY(PACKET3_COPY_DATA__DST_CACHE_POLICY__STREAM) |
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PACKET3_COPY_DATA__WR_CONFIRM(PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION) |
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PACKET3_COPY_DATA__COUNT_SEL(PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA);
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uint32_t dword5 = PACKET3_COPY_DATA__DST_64B_ADDR_LO(addr >> 3);
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uint32_t dword6 = PACKET3_COPY_DATA__DST_ADDR_HI(High32(addr));
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return {header, dword2, 0, 0, dword5, dword6};
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}
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std::array<uint32_t, 6> UserdataLoPacket(uint32_t userdata_addr)
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{
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uint32_t header = MakePacket3Header(PACKET3_COPY_DATA, 6 * sizeof(uint32_t));
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uint32_t dword2 =
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PACKET3_COPY_DATA__SRC_SEL(PACKET3_COPY_DATA__SRC_SEL__GPU_CLOCK_COUNT) |
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PACKET3_COPY_DATA__SRC_CACHE_POLICY(PACKET3_COPY_DATA__SRC_CACHE_POLICY__STREAM) |
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PACKET3_COPY_DATA__DST_SEL(PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER) |
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PACKET3_COPY_DATA__DST_CACHE_POLICY(PACKET3_COPY_DATA__DST_CACHE_POLICY__STREAM) |
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PACKET3_COPY_DATA__WR_CONFIRM(PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION) |
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PACKET3_COPY_DATA__COUNT_SEL(PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA);
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return {header, dword2, 0, 0, userdata_addr, 0};
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}
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std::array<uint32_t, 6> TraceDataMem32Packet(uint32_t userdata_addr, uint32_t* addr)
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{
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uint32_t header = MakePacket3Header(PACKET3_COPY_DATA, 6 * sizeof(uint32_t));
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uint32_t dword2 = PACKET3_COPY_DATA__SRC_SEL(PACKET3_COPY_DATA__SRC_SEL__MEMORY) |
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PACKET3_COPY_DATA__SRC_CACHE_POLICY(PACKET3_COPY_DATA__SRC_CACHE_POLICY__STREAM) |
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PACKET3_COPY_DATA__DST_SEL(PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER) |
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PACKET3_COPY_DATA__DST_CACHE_POLICY(PACKET3_COPY_DATA__DST_CACHE_POLICY__STREAM) |
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PACKET3_COPY_DATA__WR_CONFIRM(PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION) |
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PACKET3_COPY_DATA__COUNT_SEL(PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA);
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uint32_t dword3 = PACKET3_COPY_DATA__SRC_32B_ADDR_LO(PtrLow32(addr) >> 2);
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uint32_t dword4 = PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI(PtrHigh32(addr));
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return {header, dword2, dword3, dword4, userdata_addr, 0};
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};
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void BuildGPUClockPacket(CmdBuffer* cmdBuf, uint64_t* dst, const Register& userdata_addr, uint32_t header) override
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{
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uint32_t addr = get_addr(userdata_addr);
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BuildWriteUConfigRegPacket(cmdBuf, addr, header);
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// Copy to dst
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{
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auto copy_data = ClockRetrievePacket(dst);
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APPEND_COMMAND_WRAPPER(cmdBuf, copy_data);
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}
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// Copy low-bits to userdata
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{
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auto copy_data = TraceDataMem32Packet(addr, (uint32_t*)dst);
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APPEND_COMMAND_WRAPPER(cmdBuf, copy_data);
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}
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// Copy hi-bits to userdata
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{
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auto copy_data = TraceDataMem32Packet(addr, (uint32_t*)dst + 1);
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APPEND_COMMAND_WRAPPER(cmdBuf, copy_data);
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}
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// Send instant clock
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{
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auto copy_data = UserdataLoPacket(addr);
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APPEND_COMMAND_WRAPPER(cmdBuf, copy_data);
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}
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}
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};
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} // namespace pm4_builder
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@@ -38,8 +38,9 @@ class CmdBuffer;
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class CmdBuilder;
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constexpr size_t ATT_CODEOBJ_OPCODE = 4;
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constexpr size_t ATT_TIMESTAMP_OPCODE = 5;
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union att_decoder_codeobj_header_t {
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union att_decoder_packet_header_t {
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struct {
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unsigned int opcode : 8;
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unsigned int type : 4;
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@@ -102,11 +103,14 @@ class XCC_Packet_Lock {
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// Thread traces status register indices to determine
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// status of thread trace run
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struct TraceControl {
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uint32_t status;
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uint32_t cntr;
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uint32_t wptr;
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uint32_t _reserved;
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struct TraceControl
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{
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uint32_t status{0};
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uint32_t cntr{0};
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uint32_t wptr{0};
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uint32_t _reserved{0};
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uint64_t gpu_clock_cnt_start{0};
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uint64_t gpu_clock_cnt_end{0};
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};
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// Encapsulates the various Api and structures that are used to enable
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@@ -126,7 +130,9 @@ class SqttBuilder {
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virtual void End(CmdBuffer* cmd_buffer, TraceConfig* config) = 0;
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// Builds Pm4 command stream to program hardware registers that
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// inserts "data" into the SQTT buffer as USERDATA_2 (data_lo) and USERDATA_3 (data_hi)
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virtual hsa_status_t InsertMarker(CmdBuffer* cmd_buffer, uint32_t data, unsigned channel) = 0;
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virtual hsa_status_t InsertCodeobjMarker(CmdBuffer* cmd_buffer, uint32_t data, unsigned channel) = 0;
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virtual void InsertTimestampMarker(CmdBuffer* cmd_buffer, uint64_t* addr) {};
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// Returns TT_CONTROL_UTC_ERR_MASK
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virtual size_t GetUTCErrorMask() const = 0;
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@@ -326,8 +332,6 @@ class GpuSqttBuilder : public SqttBuilder, protected Primitives {
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Primitives::sqtt_mode_on_value());
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base_addr += base_step;
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}
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// Reset the GRBM to broadcast mode
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SetGRBMToBroadcast(cmd_buffer);
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} else {
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SetGRBMToBroadcast(cmd_buffer);
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builder.BuildWritePConfigRegPacket(cmd_buffer, Primitives::SQ_THREAD_TRACE_STATUS_ADDR, 0);
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@@ -401,6 +405,20 @@ class GpuSqttBuilder : public SqttBuilder, protected Primitives {
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builder.BuildWriteUConfigRegPacket(cmd_buffer, userdata_channel, header.u32All);
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builder.BuildWriteUConfigRegPacket(cmd_buffer, userdata_channel, 524801);
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if (Primitives::GFXIP_LEVEL == 9 && config->enable_rt_timestamp)
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{
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for (size_t xcc = 0; xcc < GetXCCNumber(); xcc++)
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{
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bool some_se_enabled = false;
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for (int se = 0; se < se_number_xcc; se++) some_se_enabled |=config->target_cu_per_se.at(se + xcc*se_number_xcc) >= 0;
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if (!some_se_enabled) continue;
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XCC_Packet_Lock<Builder> lock(builder, cmd_buffer, GetXCCNumber(), xcc);
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auto& control = reinterpret_cast<TraceControl*>(config->control_buffer_ptr)[xcc];
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InsertTimestampMarker(cmd_buffer, &control.gpu_clock_cnt_start);
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}
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}
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}
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void End(CmdBuffer* cmd_buffer, TraceConfig* config) override {
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@@ -408,9 +426,25 @@ class GpuSqttBuilder : public SqttBuilder, protected Primitives {
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// Issue a CSPartialFlush cmd including cache flush
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builder.BuildWriteWaitIdlePacket(cmd_buffer);
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if (Primitives::GFXIP_LEVEL == 9) {
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if (Primitives::GFXIP_LEVEL == 9)
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{
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const uint32_t se_number_xcc = se_number_total / std::max(1u, GetXCCNumber());
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if (config->enable_rt_timestamp)
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{
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for (size_t xcc = 0; xcc < GetXCCNumber(); xcc++)
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{
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bool some_se_enabled = false;
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for (int se = 0; se < se_number_xcc; se++) some_se_enabled |=config->target_cu_per_se.at(se + xcc*se_number_xcc) >= 0;
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if (!some_se_enabled) continue;
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XCC_Packet_Lock<Builder> lock(builder, cmd_buffer, GetXCCNumber(), xcc);
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auto& control = reinterpret_cast<TraceControl*>(config->control_buffer_ptr)[xcc];
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InsertTimestampMarker(cmd_buffer, &control.gpu_clock_cnt_end);
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}
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builder.BuildWriteWaitIdlePacket(cmd_buffer);
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}
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// Program the thread trace mode register to disable thread trace
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builder.BuildWriteUConfigRegPacket(cmd_buffer, Primitives::SQ_THREAD_TRACE_MODE_ADDR,
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Primitives::sqtt_mode_off_value());
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@@ -527,9 +561,9 @@ class GpuSqttBuilder : public SqttBuilder, protected Primitives {
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return uint64_t(buffer_per_se) & ~((1 << Primitives::TT_BUFF_ALIGN_SHIFT) - 1);
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}
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virtual hsa_status_t InsertMarker(CmdBuffer* cmd_buffer, uint32_t data,
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virtual hsa_status_t InsertCodeobjMarker(CmdBuffer* cmd_buffer, uint32_t data,
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unsigned channel) override {
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att_decoder_codeobj_header_t header{};
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att_decoder_packet_header_t header{};
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header.opcode = ATT_CODEOBJ_OPCODE;
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header.type = channel;
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header.reserved = 0;
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@@ -540,6 +574,17 @@ class GpuSqttBuilder : public SqttBuilder, protected Primitives {
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builder.BuildWriteUConfigRegPacket(cmd_buffer, userdata_channel, data);
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return HSA_STATUS_SUCCESS;
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}
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virtual void InsertTimestampMarker(CmdBuffer* cmd_buffer, uint64_t* addr) override
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{
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att_decoder_packet_header_t header{};
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header.opcode = ATT_TIMESTAMP_OPCODE;
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header.type = 0;
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header.reserved = 0;
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SetGRBMToBroadcast(cmd_buffer);
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builder.BuildGPUClockPacket(cmd_buffer, addr, Primitives::SQ_THREAD_TRACE_USERDATA_3, header.u32All);
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}
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template <typename T>
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void WriteConfigPacket(CmdBuffer* cmdbuf, const T& reg, uint32_t value) {
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@@ -66,6 +66,8 @@ struct TraceConfig {
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std::unordered_map<int, int> target_cu_per_se{};
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std::unordered_map<int, uint64_t> se_base_addresses{};
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bool enable_rt_timestamp{false};
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int GetTargetCU(int SE) const { return target_cu_per_se.at(SE); };
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uint64_t GetSEmask() const { return se_mask; };
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uint64_t GetSEBaseAddr(int SE) const { return se_base_addresses.at(SE); }
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