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Allow passing zero bits into hsa_amd_queue_cu_set_mask.

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Passing 0 into num_cu_mask_count used to be an implicit error.
This has been repurposed as a short hand for enabling all CUs.
Enabling all CUs when HSA_CU_MASK is set will cause the CU mask to
reset to whatever was set by HSA_CU_MASK which may then be queried.

Change-Id: I1d6bb2034595a78ee48fa72aa05563e8ea6c0fff


[ROCm/ROCR-Runtime commit: 02666ec0f1]
This commit is contained in:
Sean Keely
2021-07-29 18:58:07 -05:00
parent dbba14f823
commit 07103a6b97
2 changed files with 6 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/rocr-runtime/runtime/hsa-runtime/core/runtime/hsa_ext_amd.cpp
+2 -3
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@@ -539,12 +539,11 @@ hsa_status_t hsa_amd_queue_cu_set_mask(const hsa_queue_t* queue, uint32_t num_cu
const uint32_t* cu_mask) {
TRY;
IS_OPEN();
IS_BAD_PTR(cu_mask);
core::Queue* cmd_queue = core::Queue::Convert(queue);
IS_VALID(cmd_queue);
if ((num_cu_mask_count == 0) || (num_cu_mask_count % 32 != 0))
return HSA_STATUS_ERROR_INVALID_ARGUMENT;
if (num_cu_mask_count != 0) IS_BAD_PTR(cu_mask);
if (num_cu_mask_count % 32 != 0) return HSA_STATUS_ERROR_INVALID_ARGUMENT;
return cmd_queue->SetCUMasking(num_cu_mask_count, cu_mask);
CATCH;
}