From 0d5a8a5b9d74c0943d4a5e8f9214cff1bbf13149 Mon Sep 17 00:00:00 2001
From: German Andryeyev <German.Andryeyev@amd.com>
Date: Thu, 24 Mar 2022 15:19:21 -0400
Subject: [PATCH] SWDEV-311271 - Add a key to control memory pool feature

Change-Id: Ibd929592b802e65d0e1a4fd9689050bce5059e98


[ROCm/clr commit: a02ae1b8512a274579abe0ecb5a52a6bb2d58b37]
---
 projects/clr/rocclr/utils/flags.hpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/projects/clr/rocclr/utils/flags.hpp b/projects/clr/rocclr/utils/flags.hpp
index 12487cb598..f22a3f5176 100644
--- a/projects/clr/rocclr/utils/flags.hpp
+++ b/projects/clr/rocclr/utils/flags.hpp
@@ -249,6 +249,8 @@ release(bool, ROC_ENABLE_PRE_VEGA, false,                                     \
         "Enable support of pre-vega ASICs in ROCm path")                      \
 release(bool, HIP_FORCE_QUEUE_PROFILING, false,                               \
         "Force command queue profiling by default")                           \
+release(bool, HIP_MEM_POOL_SUPPORT, false,                                    \
+        "Enables memory pool support in HIP")                                 \
 release(uint, PAL_FORCE_ASIC_REVISION, 0,                                     \
         "Force a specific asic revision for all devices")                     \
 release(bool, PAL_EMBED_KERNEL_MD, false,                                     \