P4 to Git Change 1410373 by gandryey@gera-w8 on 2017/05/16 17:16:52

SWDEV-120180 - [amdgpu-pro] OpenCL support for SSG
	- Add initial support of DGMA memory under ROCr backend.
	 - The implementation requires amdgpu-pro stack initialization and memory allocation.
	 - An interop with HSA device is created for ROCr access

Affected files ...

... //depot/stg/opencl/drivers/opencl/api/opencl/amdocl/Makefile#10 edit
... //depot/stg/opencl/drivers/opencl/api/opencl/amdocl/build/Makefile.api#153 edit
... //depot/stg/opencl/drivers/opencl/api/opencl/amdocl/cl_lqdflash_amd.cpp#18 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/device.hpp#285 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpusettings.cpp#351 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/build/Makefile.oclrocm#16 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/pro/lnxheaders.h#1 add
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/pro/prodevice.cpp#1 add
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/pro/prodevice.hpp#1 add
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/pro/prodriver.hpp#1 add
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocdevice.cpp#51 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocdevice.hpp#21 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocmemory.cpp#19 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocsettings.cpp#18 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocvirtual.cpp#38 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocvirtual.hpp#11 edit
... //depot/stg/opencl/drivers/opencl/runtime/platform/memory.hpp#101 edit
... //depot/stg/opencl/drivers/opencl/runtime/runtimedefs#41 edit

rocclr/runtime/device/rocm/rocvirtual.cpp

@@ -1757,4 +1757,56 @@ amd::Memory* VirtualGPU::findPinnedMem(void* addr, size_t size) {
 }
 
 void VirtualGPU::enableSyncBlit() const { blitMgr_->enableSynchronization(); }
+
+void VirtualGPU::submitTransferBufferFromFile(amd::TransferBufferFileCommand& cmd) {
+  size_t copySize = cmd.size()[0];
+  size_t fileOffset = cmd.fileOffset();
+  Memory* mem = dev().getRocMemory(&cmd.memory());
+  uint idx = 0;
+
+  assert((cmd.type() == CL_COMMAND_READ_SSG_FILE_AMD) ||
+         (cmd.type() == CL_COMMAND_WRITE_SSG_FILE_AMD));
+  const bool writeBuffer(cmd.type() == CL_COMMAND_READ_SSG_FILE_AMD);
+
+  if (writeBuffer) {
+    size_t dstOffset = cmd.origin()[0];
+    while (copySize > 0) {
+      Memory* staging = dev().getRocMemory(&cmd.staging(idx));
+      size_t dstSize = amd::TransferBufferFileCommand::StagingBufferSize;
+      dstSize = std::min(dstSize, copySize);
+      void* dstBuffer = staging->cpuMap(*this);
+      if (!cmd.file()->transferBlock(writeBuffer, dstBuffer, staging->size(), fileOffset, 0,
+                                     dstSize)) {
+        cmd.setStatus(CL_INVALID_OPERATION);
+        return;
+      }
+      staging->cpuUnmap(*this);
+
+      bool result = blitMgr().copyBuffer(*staging, *mem, 0, dstOffset, dstSize, false);
+      fileOffset += dstSize;
+      dstOffset += dstSize;
+      copySize -= dstSize;
+    }
+  } else {
+    size_t srcOffset = cmd.origin()[0];
+    while (copySize > 0) {
+      Memory* staging = dev().getRocMemory(&cmd.staging(idx));
+      size_t srcSize = amd::TransferBufferFileCommand::StagingBufferSize;
+      srcSize = std::min(srcSize, copySize);
+      bool result = blitMgr().copyBuffer(*mem, *staging, srcOffset, 0, srcSize, false);
+
+      void* srcBuffer = staging->cpuMap(*this);
+      if (!cmd.file()->transferBlock(writeBuffer, srcBuffer, staging->size(), fileOffset, 0,
+                                     srcSize)) {
+        cmd.setStatus(CL_INVALID_OPERATION);
+        return;
+      }
+      staging->cpuUnmap(*this);
+
+      fileOffset += srcSize;
+      srcOffset += srcSize;
+      copySize -= srcSize;
+    }
+  }
+}
 }  // End of roc namespace