Moved partition_id from static --asic-info to static --partition.
partition_id also removed from the `amdsmi_asic_info_t` struct and
supporting API has been added for querying partition information.
Signed-off-by: gabrpham <Gabriel.Pham@amd.com>
Change-Id: Id5a6291a77d11bb97a1c7a200fc465898e86e081
[ROCm/amdsmi commit: c9a489d437]
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@@ -87,6 +87,9 @@ typedef enum {
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#define AMDSMI_MAX_CONTAINER_TYPE 2
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#define AMDSMI_MAX_CACHE_TYPES 10
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#define AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK 64
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#define AMDSMI_MAX_ACCELERATOR_PROFILE 32
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#define AMDSMI_MAX_CP_PROFILE_RESOURCES 32
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#define AMDSMI_MAX_ACCELERATOR_PARTITIONS 8
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#define AMDSMI_GPU_UUID_SIZE 38
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@@ -275,6 +278,24 @@ typedef enum {
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AMDSMI_CLK_TYPE__MAX = AMDSMI_CLK_TYPE_DCLK1
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} amdsmi_clk_type_t;
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/**
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* @brief Accelerator Partition. This enum is used to identify
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* various accelerator partitioning settings.
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*/
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typedef enum {
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AMDSMI_ACCELERATOR_PARTITION_INVALID = 0,
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AMDSMI_ACCELERATOR_PARTITION_SPX, //!< Single GPU mode (SPX)- All XCCs work
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//!< together with shared memory
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AMDSMI_ACCELERATOR_PARTITION_DPX, //!< Dual GPU mode (DPX)- Half XCCs work
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//!< together with shared memory
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AMDSMI_ACCELERATOR_PARTITION_TPX, //!< Triple GPU mode (TPX)- One-third XCCs
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//!< work together with shared memory
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AMDSMI_ACCELERATOR_PARTITION_QPX, //!< Quad GPU mode (QPX)- Quarter XCCs
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//!< work together with shared memory
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AMDSMI_ACCELERATOR_PARTITION_CPX, //!< Core mode (CPX)- Per-chip XCC with
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//!< shared memory
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} amdsmi_accelerator_partition_type_t;
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/**
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* @brief Compute Partition. This enum is used to identify
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* various compute partitioning settings.
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@@ -590,8 +611,7 @@ typedef struct {
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uint32_t oam_id; //< 0xFFFF if not supported
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uint32_t num_of_compute_units; //< 0xFFFFFFFF if not supported
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uint64_t target_graphics_version; //< 0xFFFFFFFFFFFFFFFF if not supported
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uint32_t partition_id; //< 0xFFFFFFFF if not supported
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uint32_t reserved[14];
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uint32_t reserved[15];
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} amdsmi_asic_info_t;
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typedef struct {
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@@ -600,6 +620,15 @@ typedef struct {
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uint32_t reserved[13];
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} amdsmi_kfd_info_t;
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typedef struct {
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amdsmi_accelerator_partition_type_t profile_type; // SPX, DPX, QPX, CPX and so on
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uint32_t num_partitions; // On MI300X, SPX: 1, DPX: 2, QPX: 4, CPX: 8, the length of resources array
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uint32_t profile_index; // The index in the profiles array in amdsmi_accelerator_partition_profile_t
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uint32_t num_resources; // length of index_of_resources_profile
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uint32_t resources[AMDSMI_MAX_ACCELERATOR_PARTITIONS][AMDSMI_MAX_CP_PROFILE_RESOURCES];
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uint64_t reserved[6];
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} amdsmi_accelerator_partition_profile_t;
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typedef enum {
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AMDSMI_LINK_TYPE_PCIE,
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AMDSMI_LINK_TYPE_XGMI,
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@@ -4517,6 +4546,23 @@ amdsmi_status_t amdsmi_reset_gpu_memory_partition(amdsmi_processor_handle proces
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/** @} */ // end of memory_partition
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/*****************************************************************************/
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/** @defgroup accelerator_partition_profile Accelerator Partition Profile Functions
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* These functions are used to configure and query the device's
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* accelerator parition profile setting.
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* @{
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*/
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// TODO: declare rest of partition profile functions and complete doc commentary.
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/*
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Get the current accelerator partition profile. The function will return current profile.
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*/
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amdsmi_status_t
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amdsmi_get_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle,
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amdsmi_accelerator_partition_profile_t *profile,
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uint32_t *partition_id);
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/** @} */ // end of accelerator_partition_profile
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/*****************************************************************************/
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/** @defgroup EvntNotif Event Notification Functions
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* These functions are used to configure for and get asynchronous event
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