diff --git a/src/fmm.c b/src/fmm.c
index 411fc0ee32..d3f289761d 100644
--- a/src/fmm.c
+++ b/src/fmm.c
@@ -931,7 +931,7 @@ static vm_object_t *fmm_allocate_memory_object(uint32_t gpu_id, void *mem,
 	args.flags = flags |
 		KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE;
 	args.va_addr = (uint64_t)mem;
-	if (!topology_is_dgpu(get_device_id_by_gpu_id(gpu_id)) &&
+	if (!is_dgpu &&
 	    (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM))
 		args.va_addr = VOID_PTRS_SUB(mem, aperture->base);
 	if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)
@@ -1150,7 +1150,7 @@ static void fmm_release_scratch(uint32_t gpu_id)
 
 	size = VOID_PTRS_SUB(aperture->limit, aperture->base) + 1;
 
-	if (topology_is_dgpu(gpu_mem[gpu_mem_id].device_id)) {
+	if (is_dgpu) {
 		/* unmap and remove all remaining objects */
 		pthread_mutex_lock(&aperture->fmm_mutex);
 		while ((n = rbtree_node_any(&aperture->tree, MID))) {
@@ -1217,7 +1217,7 @@ void *fmm_allocate_scratch(uint32_t gpu_id, void *address, uint64_t MemorySizeIn
 		return NULL;
 
 	/* Allocate address space for scratch backing, 64KB aligned */
-	if (topology_is_dgpu(gpu_mem[gpu_mem_id].device_id)) {
+	if (is_dgpu) {
 		pthread_mutex_lock(&svm.dgpu_aperture->fmm_mutex);
 		mem = aperture_allocate_area_aligned(
 			svm.dgpu_aperture, address,
@@ -2173,12 +2173,17 @@ HSAKMT_STATUS fmm_init_process_apertures(unsigned int NumNodes)
 	 */
 
 	pacc = pci_ids_create();
+
+	is_dgpu = false;
+
 	for (i = 0; i < NumNodes; i++) {
 		memset(&props, 0, sizeof(props));
 		ret = topology_sysfs_get_node_props(i, &props, &gpu_id, pacc);
 		if (ret != HSAKMT_STATUS_SUCCESS)
 			goto sysfs_parse_failed;
 
+		topology_setup_is_dgpu_param(&props);
+
 		/* Skip non-GPU nodes */
 		if (gpu_id != 0) {
 			int fd = open_drm_render_device(props.DrmRenderMinor);
@@ -2209,6 +2214,7 @@ HSAKMT_STATUS fmm_init_process_apertures(unsigned int NumNodes)
 			gpu_mem_count++;
 		}
 	}
+
 	pci_ids_destroy(pacc);
 
 	/* The ioctl will also return Number of Nodes if
@@ -2617,7 +2623,7 @@ static int _fmm_map_to_gpu_scratch(uint32_t gpu_id, manageable_aperture_t *apert
 	if (gpu_mem_id < 0)
 		return -1;
 
-	if (!topology_is_dgpu(gpu_mem[gpu_mem_id].device_id))
+	if (!is_dgpu)
 		return 0; /* Nothing to do on APU */
 
 	/* sanity check the address */
@@ -2830,7 +2836,7 @@ static int _fmm_unmap_from_gpu_scratch(uint32_t gpu_id,
 	if (gpu_mem_id < 0)
 		return -1;
 
-	if (!topology_is_dgpu(gpu_mem[gpu_mem_id].device_id))
+	if (!is_dgpu)
 		return 0; /* Nothing to do on APU */
 
 	pthread_mutex_lock(&aperture->fmm_mutex);
diff --git a/src/libhsakmt.h b/src/libhsakmt.h
index 757ebeb0c6..e5e650bfe6 100644
--- a/src/libhsakmt.h
+++ b/src/libhsakmt.h
@@ -159,7 +159,7 @@ HSAKMT_STATUS validate_nodeid_array(uint32_t **gpu_id_array,
 HSAKMT_STATUS topology_sysfs_get_node_props(uint32_t node_id, HsaNodeProperties *props,
 		uint32_t *gpu_id, struct pci_ids pacc);
 HSAKMT_STATUS topology_sysfs_get_system_props(HsaSystemProperties *props);
-bool topology_is_dgpu(uint16_t device_id);
+void topology_setup_is_dgpu_param(HsaNodeProperties *props);
 bool topology_is_svm_needed(uint16_t device_id);
 HSAKMT_STATUS topology_get_asic_family(uint16_t device_id,
 					enum asic_family_type *asic);
diff --git a/src/queues.c b/src/queues.c
index 539b06b139..1ddf6805ee 100644
--- a/src/queues.c
+++ b/src/queues.c
@@ -272,7 +272,7 @@ static void get_doorbell_map_info(uint16_t dev_id,
 	 * GPUVM doorbell on Tonga requires a workaround for VM TLB ACTIVE bit
 	 * lookup bug. Remove ASIC check when this is implemented in amdgpu.
 	 */
-	doorbell->use_gpuvm = (topology_is_dgpu(dev_id) &&
+	doorbell->use_gpuvm = (is_dgpu &&
 			       dev_info->asic_family != CHIP_TONGA);
 	doorbell->size = DOORBELLS_PAGE_SIZE(dev_info->doorbell_size);
 }
diff --git a/src/topology.c b/src/topology.c
index b92342dd6e..3e6ca1e2d4 100644
--- a/src/topology.c
+++ b/src/topology.c
@@ -753,24 +753,19 @@ HSAKMT_STATUS topology_get_asic_family(uint16_t device_id,
 	return HSAKMT_STATUS_SUCCESS;
 }
 
-bool topology_is_dgpu(uint16_t device_id)
-{
-	const struct hsa_gfxip_table *hsa_gfxip =
-				find_hsa_gfxip_device(device_id);
 
-	if (hsa_gfxip && hsa_gfxip->is_dgpu) {
+void topology_setup_is_dgpu_param(HsaNodeProperties *props)
+{
+	/* if we found a dGPU node, then treat the whole system as dGPU */
+	if (!props->NumCPUCores && props->NumFComputeCores)
 		is_dgpu = true;
-		return true;
-	}
-	is_dgpu = false;
-	return false;
 }
 
 bool topology_is_svm_needed(uint16_t device_id)
 {
 	const struct hsa_gfxip_table *hsa_gfxip;
 
-	if (topology_is_dgpu(device_id))
+	if (is_dgpu)
 		return true;
 
 	hsa_gfxip = find_hsa_gfxip_device(device_id);
@@ -2004,7 +1999,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtGetNodeProperties(HSAuint32 NodeId,
 	/* For CPU only node don't add any additional GPU memory banks. */
 	if (gpu_id) {
 		uint64_t base, limit;
-		if (topology_is_dgpu(get_device_id_by_gpu_id(gpu_id)))
+		if (is_dgpu)
 			NodeProperties->NumMemoryBanks += NUM_OF_DGPU_HEAPS;
 		else
 			NodeProperties->NumMemoryBanks += NUM_OF_IGPU_HEAPS;