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Fixing SE numbering and cache invalidade parsing

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Change-Id: Ie63c68a0b2b07427586faaf69b68a19c315387e3


[ROCm/rocprofiler commit: 363abb238b]
This commit is contained in:
Giovanni LB
2024-01-31 13:11:19 -03:00
parent 3cca2ccb9f
commit 175f4e024e
2 changed files with 28 additions and 26 deletions
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projects/rocprofiler/plugin/att/stitch.py
+11 -10
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@@ -436,16 +436,17 @@ def stitch(insts, raw_code, jumps, gfxv, bIsAuto, codeservice):
if "flat_" in as_line[0]:
inc_ordering = True
if not bGFX9 and "store" in as_line[0]:
VSMEM_INST.append([reverse_map[line], num_inflight])
NUM_VSMEM += 1
if inc_ordering:
vsmem_ordering = 1
else:
VLMEM_INST.append([reverse_map[line], num_inflight])
NUM_VLMEM += 1
if inc_ordering:
vlmem_ordering = 1
if not "_inv" in as_line[0] and not "_wb" in as_line[0]:
if not bGFX9 and "store" in as_line[0]:
VSMEM_INST.append([reverse_map[line], num_inflight])
NUM_VSMEM += 1
if inc_ordering:
vsmem_ordering = 1
else:
VLMEM_INST.append([reverse_map[line], num_inflight])
NUM_VLMEM += 1
if inc_ordering:
vlmem_ordering = 1
elif inst.type == FLAT:
smem_ordering = 1
vlmem_ordering = 1