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fixes for titan platform

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[ROCm/hip commit: ff66ef0779]
This commit is contained in:
Ben Sander
2016-02-26 05:25:30 -06:00
parent b46a90852e
commit 1ac07d2b87
5 changed files with 4 additions and 12 deletions
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projects/hip/include/hip_runtime_api.h
+1 -5
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@@ -81,10 +81,8 @@ typedef struct hipDeviceProp_t {
int maxThreadsDim[3]; ///< Max number of threads in each dimension (XYZ) of a block.
int maxGridSize[3]; ///< Max grid dimensions (XYZ).
int clockRate; ///< Max clock frequency of the multiProcessors in khz.
#ifdef USE_ROCR_20
int memoryClockRate; ///< Max global memory clock frequency in khz.
int memoryBusWidth; ///< Global memory bus width in bits.
#endif
size_t totalConstMem; ///< Size of shared memory region (in bytes).
int major; ///< Major compute capability. On HCC, this is an approximation and features may differ from CUDA CC. See the arch feature flags for portable ways to query feature caps.
int minor; ///< Minor compute capability. On HCC, this is an approximation and features may differ from CUDA CC. See the arch feature flags for portable ways to query feature caps.
@@ -135,7 +133,7 @@ typedef struct hipPointerAttribute_t {
/*
* @brief hipError_t
asdasd* @brief hipError_t
* @enum
* @ingroup Enumerations
*/
@@ -175,10 +173,8 @@ typedef enum hipDeviceAttribute_t {
hipDeviceAttributeWarpSize, ///< Warp size in threads.
hipDeviceAttributeMaxRegistersPerBlock, ///< Maximum number of 32-bit registers available to a thread block. This number is shared by all thread blocks simultaneously resident on a multiprocessor.
hipDeviceAttributeClockRate, ///< Peak clock frequency in kilohertz.
#ifdef USE_ROCR_20
hipDeviceAttributeMemoryClockRate, ///< Peak memory clock frequency in kilohertz.
hipDeviceAttributeMemoryBusWidth, ///< Global memory bus width in bits.
#endif
hipDeviceAttributeMultiprocessorCount, ///< Number of multiprocessors on the device.
hipDeviceAttributeComputeMode, ///< Compute mode that device is currently in.
hipDeviceAttributeL2CacheSize, ///< Size of L2 cache in bytes. 0 if the device doesn't have L2 cache.