Initial Commit
Contributors: Ammar ELWazir <aelwazir@amd.com> AravindanC <aravindan.cheruvally@amd.com> Benjamin Welton <bewelton@amd.com> Ma, Bing <Bing.Ma@amd.com> Chun Yang <chun.yang@amd.com> Cole Nelson <cole.nelson@amd.com> Ethan Stewart <ethan.stewart@amd.com> Evgeny <evgeny.shcherbakov@amd.com> Freddy Paul <Freddy.paul@amd.com> Giovanni Baraldi <gbaraldi@amd.com> Gopesh Bhardwaj <Gopesh.Bhardwaj@amd.com> Icarus Sparry <icarus.sparry@amd.com> itrowbri <Ian.Trowbridge@amd.com> James Edwards <JamesAdrian.Edwards@amd.com> jatang <jatang@amd.com> Jeremy Newton <Jeremy.Newton@amd.com> Jonathan Kim <jonathan.kim@amd.com> Kent Russell <kent.russell@amd.com> Kiumars Sabeti <kiumars.sabeti@amd.com> Lang Yu <lang.yu@amd.com> Laurent Morichetti <laurent.morichetti@amd.com> Mallya, Ameya Keshava <AmeyaKeshava.Mallya@amd.com> Manjunath Jakaraddi <manjunath.jakaraddi@amd.com> Mark Laws <markdavid.laws@amd.com> Mohan Kumar Mithur <Mohan.KumarMithur@amd.com> Nicholas Curtis <nicurtis@amd.com> Nirmal Unnikrishnan <Nirmal.Unnikrishnan@amd.com> Parag Bhandari <parag.bhandari@amd.com> Ranjith Ramakrishnan <Ranjith.Ramakrishnan@amd.com> Robert Gregory <Robert.Gregory@amd.com> Saravanan Solaiyappan <saravanan.solaiyappan@amd.com> Saurabh Verma <saurabh.verma@amd.com> Srihari Uttanur <srihari.u@amd.com> Srinivasan Subramanian <srinivasan.subramanian@amd.com> Sriraksha Nagaraj <Sriraksha.Nagaraj@amd.com> Sushma Vaddireddy <svaddire@amd.com> Xianwei Zhang <Xianwei.Zhang@amd.com>
This commit is contained in:
Evgeny
Ammar ELWazir
+22764
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Load Diff
@@ -0,0 +1,678 @@
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef NVD_H
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#define NVD_H
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/**
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* Navi's PM4 definitions
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*/
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#define PACKET_TYPE0 0
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#define PACKET_TYPE1 1
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#define PACKET_TYPE2 2
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#define PACKET_TYPE3 3
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#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
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#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
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#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
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((reg) & 0xFFFF) | \
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((n) & 0x3FFF) << 16)
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#define CP_PACKET2 0x80000000
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#define PACKET2_PAD_SHIFT 0
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#define PACKET2_PAD_MASK (0x3fffffff << 0)
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#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
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(((op) & 0xFF) << 8) | \
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((n) & 0x3FFF) << 16)
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#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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/* Packet 3 types */
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#define PACKET3_NOP 0x10
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#define PACKET3_SET_BASE 0x11
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#define PACKET3_BASE_INDEX(x) ((x) << 0)
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#define CE_PARTITION_BASE 3
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#define PACKET3_CLEAR_STATE 0x12
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#define PACKET3_INDEX_BUFFER_SIZE 0x13
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#define PACKET3_DISPATCH_DIRECT 0x15
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#define PACKET3_DISPATCH_INDIRECT 0x16
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#define PACKET3_INDIRECT_BUFFER_END 0x17
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#define PACKET3_INDIRECT_BUFFER_CNST_END 0x19
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#define PACKET3_ATOMIC_GDS 0x1D
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#define PACKET3_ATOMIC_MEM 0x1E
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#define PACKET3_ATOMIC_MEM__ATOMIC(x) ((((unsigned)(x)) & 0x7F) << 0)
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#define PACKET3_ATOMIC_MEM__COMMAND(x) ((((unsigned)(x)) & 0xF) << 8)
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#define PACKET3_ATOMIC_MEM__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
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#define PACKET3_ATOMIC_MEM__ADDR_LO(x) (((unsigned)(x)))
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#define PACKET3_ATOMIC_MEM__ADDR_HI(x) (((unsigned)(x)))
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#define PACKET3_ATOMIC_MEM__SRC_DATA_LO(x) (((unsigned)(x)))
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#define PACKET3_ATOMIC_MEM__SRC_DATA_HI(x) (((unsigned)(x)))
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#define PACKET3_ATOMIC_MEM__CMP_DATA_LO(x) (((unsigned)(x)))
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#define PACKET3_ATOMIC_MEM__CMP_DATA_HI(x) (((unsigned)(x)))
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#define PACKET3_ATOMIC_MEM__LOOP_INTERVAL(x) ((((unsigned)(x)) & 0x1FFF) << 0)
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#define PACKET3_ATOMIC_MEM__COMMAND__SINGLE_PASS_ATOMIC 0
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#define PACKET3_ATOMIC_MEM__COMMAND__LOOP_UNTIL_COMPARE_SATISFIED 1
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#define PACKET3_ATOMIC_MEM__COMMAND__WAIT_FOR_WRITE_CONFIRMATION 2
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#define PACKET3_ATOMIC_MEM__COMMAND__SEND_AND_CONTINUE 3
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#define PACKET3_ATOMIC_MEM__CACHE_POLICY__LRU 0
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#define PACKET3_ATOMIC_MEM__CACHE_POLICY__STREAM 1
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#define PACKET3_ATOMIC_MEM__CACHE_POLICY__NOA 2
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#define PACKET3_ATOMIC_MEM__CACHE_POLICY__BYPASS 3
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#define PACKET3_OCCLUSION_QUERY 0x1F
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#define PACKET3_SET_PREDICATION 0x20
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#define PACKET3_REG_RMW 0x21
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#define PACKET3_COND_EXEC 0x22
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#define PACKET3_PRED_EXEC 0x23
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#define PACKET3_DRAW_INDIRECT 0x24
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#define PACKET3_DRAW_INDEX_INDIRECT 0x25
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#define PACKET3_INDEX_BASE 0x26
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#define PACKET3_DRAW_INDEX_2 0x27
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#define PACKET3_CONTEXT_CONTROL 0x28
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#define PACKET3_INDEX_TYPE 0x2A
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#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
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#define PACKET3_DRAW_INDEX_AUTO 0x2D
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#define PACKET3_NUM_INSTANCES 0x2F
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#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
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#define PACKET3_INDIRECT_BUFFER_PRIV 0x32
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#define PACKET3_INDIRECT_BUFFER_CNST 0x33
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#define PACKET3_COND_INDIRECT_BUFFER_CNST 0x33
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#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
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#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
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#define PACKET3_DRAW_PREAMBLE 0x36
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#define PACKET3_WRITE_DATA 0x37
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#define WRITE_DATA_DST_SEL(x) ((x) << 8)
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/* 0 - register
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* 1 - memory (sync - via GRBM)
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* 2 - gl2
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* 3 - gds
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* 4 - reserved
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* 5 - memory (async - direct)
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*/
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#define WR_ONE_ADDR (1 << 16)
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#define WR_CONFIRM (1 << 20)
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#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
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/* 0 - LRU
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* 1 - Stream
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*/
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#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
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/* 0 - me
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* 1 - pfp
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* 2 - ce
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*/
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#define PACKET3_WRITE_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8)
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#define PACKET3_WRITE_DATA__ADDR_INCR(x) ((((unsigned)(x)) & 0x1) << 16)
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#define PACKET3_WRITE_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20)
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#define PACKET3_WRITE_DATA__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
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#define PACKET3_WRITE_DATA__DST_MMREG_ADDR(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
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#define PACKET3_WRITE_DATA__DST_GDS_ADDR(x) ((((unsigned)(x)) & 0xFFFF) << 0)
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#define PACKET3_WRITE_DATA__DST_MEM_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
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#define PACKET3_WRITE_DATA__DST_MEM_ADDR_HI(x) ((unsigned)(x))
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#define PACKET3_WRITE_DATA__MODE(x) ((((unsigned)(x)) & 0x1) << 21)
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#define PACKET3_WRITE_DATA__AID_ID(x) ((((unsigned)(x)) & 0x3) << 22)
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#define PACKET3_WRITE_DATA__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 24)
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#define PACKET3_WRITE_DATA__DST_MMREG_ADDR_LO(x) ((unsigned)(x))
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#define PACKET3_WRITE_DATA__DST_MMREG_ADDR_HI(x) ((((unsigned)(x)) & 0xFF) << 0)
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#define PACKET3_WRITE_DATA__DST_SEL__MEM_MAPPED_REGISTER 0
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#define PACKET3_WRITE_DATA__DST_SEL__TC_L2 2
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#define PACKET3_WRITE_DATA__DST_SEL__GDS 3
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#define PACKET3_WRITE_DATA__DST_SEL__MEMORY 5
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#define PACKET3_WRITE_DATA__DST_SEL__MEMORY_MAPPED_ADC_PERSISTENT_STATE 6
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#define PACKET3_WRITE_DATA__ADDR_INCR__INCREMENT_ADDRESS 0
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#define PACKET3_WRITE_DATA__ADDR_INCR__DO_NOT_INCREMENT_ADDRESS 1
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#define PACKET3_WRITE_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_WRITE_CONFIRMATION 0
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#define PACKET3_WRITE_DATA__WR_CONFIRM__WAIT_FOR_WRITE_CONFIRMATION 1
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#define PACKET3_WRITE_DATA__MODE__PF_VF_DISABLED 0
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#define PACKET3_WRITE_DATA__MODE__PF_VF_ENABLED 1
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#define PACKET3_WRITE_DATA__TEMPORAL__RT 0
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#define PACKET3_WRITE_DATA__TEMPORAL__NT 1
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#define PACKET3_WRITE_DATA__TEMPORAL__HT 2
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#define PACKET3_WRITE_DATA__TEMPORAL__LU 3
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#define PACKET3_WRITE_DATA__CACHE_POLICY__LRU 0
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#define PACKET3_WRITE_DATA__CACHE_POLICY__STREAM 1
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#define PACKET3_WRITE_DATA__CACHE_POLICY__NOA 2
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#define PACKET3_WRITE_DATA__CACHE_POLICY__BYPASS 3
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#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
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#define PACKET3_MEM_SEMAPHORE 0x39
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# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
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# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
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# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
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# define PACKET3_SEM_SEL_WAIT (0x7 << 29)
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#define PACKET3_DRAW_INDEX_MULTI_INST 0x3A
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#define PACKET3_COPY_DW 0x3B
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#define PACKET3_WAIT_REG_MEM 0x3C
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#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
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/* 0 - always
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* 1 - <
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* 2 - <=
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* 3 - ==
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* 4 - !=
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* 5 - >=
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* 6 - >
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*/
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#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
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/* 0 - reg
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* 1 - mem
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*/
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#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
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/* 0 - wait_reg_mem
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* 1 - wr_wait_wr_reg
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*/
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#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
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/* 0 - me
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* 1 - pfp
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*/
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#define PACKET3_WAIT_REG_MEM__FUNCTION(x) ((((unsigned)(x)) & 0x7) << 0)
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#define PACKET3_WAIT_REG_MEM__MEM_SPACE(x) ((((unsigned)(x)) & 0x3) << 4)
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#define PACKET3_WAIT_REG_MEM__OPERATION(x) ((((unsigned)(x)) & 0x3) << 6)
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#define PACKET3_WAIT_REG_MEM__MES_INTR_PIPE(x) ((((unsigned)(x)) & 0x3) << 22)
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#define PACKET3_WAIT_REG_MEM__MES_ACTION(x) ((((unsigned)(x)) & 0x1) << 24)
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#define PACKET3_WAIT_REG_MEM__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
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#define PACKET3_WAIT_REG_MEM__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25)
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#define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
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#define PACKET3_WAIT_REG_MEM__REG_POLL_ADDR(x) ((((unsigned)(x)) & 0X3FFFF) << 0)
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#define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR1(x) ((((unsigned)(x)) & 0X3FFFF) << 0)
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#define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI(x) ((unsigned)(x))
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#define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR2(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
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#define PACKET3_WAIT_REG_MEM__REFERENCE(x) ((unsigned)(x))
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#define PACKET3_WAIT_REG_MEM__MASK(x) ((unsigned)(x))
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#define PACKET3_WAIT_REG_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0)
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#define PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE(x) ((((unsigned)(x)) & 0x1) << 31)
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#define PACKET3_WAIT_REG_MEM__FUNCTION__ALWAYS_PASS 0
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#define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_REF_VALUE 1
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#define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_EQUAL_TO_THE_REF_VALUE 2
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#define PACKET3_WAIT_REG_MEM__FUNCTION__EQUAL_TO_THE_REFERENCE_VALUE 3
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#define PACKET3_WAIT_REG_MEM__FUNCTION__NOT_EQUAL_REFERENCE_VALUE 4
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#define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_OR_EQUAL_REFERENCE_VALUE 5
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#define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_REFERENCE_VALUE 6
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#define PACKET3_WAIT_REG_MEM__MEM_SPACE__REGISTER_SPACE 0
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#define PACKET3_WAIT_REG_MEM__MEM_SPACE__MEMORY_SPACE 1
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#define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_REG_MEM 0
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#define PACKET3_WAIT_REG_MEM__OPERATION__WR_WAIT_WR_REG 1
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#define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_MEM_PREEMPTABLE 3
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#define PACKET3_WAIT_REG_MEM__CACHE_POLICY__LRU 0
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#define PACKET3_WAIT_REG_MEM__CACHE_POLICY__STREAM 1
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#define PACKET3_WAIT_REG_MEM__CACHE_POLICY__NOA 2
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#define PACKET3_WAIT_REG_MEM__CACHE_POLICY__BYPASS 3
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#define PACKET3_WAIT_REG_MEM__TEMPORAL__RT 0
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#define PACKET3_WAIT_REG_MEM__TEMPORAL__NT 1
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#define PACKET3_WAIT_REG_MEM__TEMPORAL__HT 2
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#define PACKET3_WAIT_REG_MEM__TEMPORAL__LU 3
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#define PACKET3_INDIRECT_BUFFER 0x3F
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#define INDIRECT_BUFFER_VALID (1 << 23)
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#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
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/* 0 - LRU
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* 1 - Stream
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* 2 - Bypass
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*/
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#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21)
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#define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30)
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#define PACKET3_INDIRECT_BUFFER__IB_BASE_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
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#define PACKET3_INDIRECT_BUFFER__IB_BASE_HI(x) ((unsigned)(x))
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#define PACKET3_INDIRECT_BUFFER__IB_SIZE(x) ((((unsigned)(x)) & 0xFFFFF) << 0)
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#define PACKET3_INDIRECT_BUFFER__CHAIN(x) ((((unsigned)(x)) & 0x1) << 20)
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#define PACKET3_INDIRECT_BUFFER__OFFLOAD_POLLING(x) ((((unsigned)(x)) & 0x1) << 21)
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#define PACKET3_INDIRECT_BUFFER__VALID(x) ((((unsigned)(x)) & 0x1) << 23)
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||||
#define PACKET3_INDIRECT_BUFFER__VMID(x) ((((unsigned)(x)) & 0xF) << 24)
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#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 28)
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#define PACKET3_INDIRECT_BUFFER__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 28)
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||||
#define PACKET3_INDIRECT_BUFFER__PRIV(x) ((((unsigned)(x)) & 0x1) << 31)
|
||||
#define PACKET3_INDIRECT_BUFFER__TEMPORAL__RT 0
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||||
#define PACKET3_INDIRECT_BUFFER__TEMPORAL__NT 1
|
||||
#define PACKET3_INDIRECT_BUFFER__TEMPORAL__HT 2
|
||||
#define PACKET3_INDIRECT_BUFFER__TEMPORAL__LU 3
|
||||
#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__LRU 0
|
||||
#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__STREAM 1
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||||
#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__NOA 2
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||||
#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__BYPASS 3
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||||
#define PACKET3_COND_INDIRECT_BUFFER 0x3F
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||||
#define PACKET3_COPY_DATA 0x40
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||||
#define PACKET3_COPY_DATA__SRC_SEL(x) ((((unsigned)(x)) & 0xF) << 0)
|
||||
#define PACKET3_COPY_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8)
|
||||
#define PACKET3_COPY_DATA__SRC_CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 13)
|
||||
#define PACKET3_COPY_DATA__SRC_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 13)
|
||||
#define PACKET3_COPY_DATA__COUNT_SEL(x) ((((unsigned)(x)) & 0x1) << 16)
|
||||
#define PACKET3_COPY_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20)
|
||||
#define PACKET3_COPY_DATA__DST_CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
|
||||
#define PACKET3_COPY_DATA__PQ_EXE_STATUS(x) ((((unsigned)(x)) & 0x1) << 29)
|
||||
#define PACKET3_COPY_DATA__SRC_REG_OFFSET(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
|
||||
#define PACKET3_COPY_DATA__SRC_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
|
||||
#define PACKET3_COPY_DATA__SRC_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
|
||||
#define PACKET3_COPY_DATA__SRC_GDS_ADDR_LO(x) ((((unsigned)(x)) & 0xFFFF) << 0)
|
||||
#define PACKET3_COPY_DATA__IMM_DATA(x) ((unsigned)(x))
|
||||
#define PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI(x) ((unsigned)(x))
|
||||
#define PACKET3_COPY_DATA__SRC_IMM_DATA(x) ((unsigned)(x))
|
||||
#define PACKET3_COPY_DATA__DST_REG_OFFSET(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
|
||||
#define PACKET3_COPY_DATA__DST_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
|
||||
#define PACKET3_COPY_DATA__DST_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
|
||||
#define PACKET3_COPY_DATA__DST_GDS_ADDR_LO(x) ((((unsigned)(x)) & 0xFFFF) << 0)
|
||||
#define PACKET3_COPY_DATA__DST_ADDR_HI(x) ((unsigned)(x))
|
||||
#define PACKET3_COPY_DATA__MODE(x) ((((unsigned)(x)) & 0x1) << 21)
|
||||
#define PACKET3_COPY_DATA__AID_ID(x) ((((unsigned)(x)) & 0x3) << 23)
|
||||
#define PACKET3_COPY_DATA__DST_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25)
|
||||
#define PACKET3_COPY_DATA__SRC_REG_OFFSET_LO(x) ((unsigned)(x))
|
||||
#define PACKET3_COPY_DATA__SRC_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0xFF) << 0)
|
||||
#define PACKET3_COPY_DATA__DST_REG_OFFSET_LO(x) ((unsigned)(x))
|
||||
#define PACKET3_COPY_DATA__DST_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0xFF) << 0)
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__MEM_MAPPED_REGISTER 0
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__TC_L2_OBSOLETE 1
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__TC_L2 2
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__GDS 3
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__PERFCOUNTERS 4
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__IMMEDIATE_DATA 5
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__ATOMIC_RETURN_DATA 6
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA0 7
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA1 8
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__GPU_CLOCK_COUNT 9
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__SYSTEM_CLOCK_COUNT 10
|
||||
#define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER 0
|
||||
#define PACKET3_COPY_DATA__DST_SEL__TC_L2 2
|
||||
#define PACKET3_COPY_DATA__DST_SEL__GDS 3
|
||||
#define PACKET3_COPY_DATA__DST_SEL__PERFCOUNTERS 4
|
||||
#define PACKET3_COPY_DATA__DST_SEL__TC_L2_OBSOLETE 5
|
||||
#define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REG_DC 6
|
||||
#define PACKET3_COPY_DATA__SRC_TEMPORAL__RT 0
|
||||
#define PACKET3_COPY_DATA__SRC_TEMPORAL__NT 1
|
||||
#define PACKET3_COPY_DATA__SRC_TEMPORAL__HT 2
|
||||
#define PACKET3_COPY_DATA__SRC_TEMPORAL__LU 3
|
||||
#define PACKET3_COPY_DATA__SRC_CACHE_POLICY__LRU 0
|
||||
#define PACKET3_COPY_DATA__SRC_CACHE_POLICY__STREAM 1
|
||||
#define PACKET3_COPY_DATA__SRC_CACHE_POLICY__NOA 2
|
||||
#define PACKET3_COPY_DATA__SRC_CACHE_POLICY__BYPASS 3
|
||||
#define PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA 0
|
||||
#define PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA 1
|
||||
#define PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION 0
|
||||
#define PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION 1
|
||||
#define PACKET3_COPY_DATA__MODE__PF_VF_DISABLED 0
|
||||
#define PACKET3_COPY_DATA__MODE__PF_VF_ENABLED 1
|
||||
#define PACKET3_COPY_DATA__DST_TEMPORAL__RT 0
|
||||
#define PACKET3_COPY_DATA__DST_TEMPORAL__NT 1
|
||||
#define PACKET3_COPY_DATA__DST_TEMPORAL__HT 2
|
||||
#define PACKET3_COPY_DATA__DST_TEMPORAL__LU 3
|
||||
#define PACKET3_COPY_DATA__DST_CACHE_POLICY__LRU 0
|
||||
#define PACKET3_COPY_DATA__DST_CACHE_POLICY__STREAM 1
|
||||
#define PACKET3_COPY_DATA__DST_CACHE_POLICY__NOA 2
|
||||
#define PACKET3_COPY_DATA__DST_CACHE_POLICY__BYPASS 3
|
||||
#define PACKET3_COPY_DATA__PQ_EXE_STATUS__DEFAULT 0
|
||||
#define PACKET3_COPY_DATA__PQ_EXE_STATUS__PHASE_UPDATE 1
|
||||
#define PACKET3_CP_DMA 0x41
|
||||
#define PACKET3_PFP_SYNC_ME 0x42
|
||||
#define PACKET3_SURFACE_SYNC 0x43
|
||||
#define PACKET3_ME_INITIALIZE 0x44
|
||||
#define PACKET3_COND_WRITE 0x45
|
||||
#define PACKET3_EVENT_WRITE 0x46
|
||||
#define EVENT_TYPE(x) ((x) << 0)
|
||||
#define EVENT_INDEX(x) ((x) << 8)
|
||||
/* 0 - any non-TS event
|
||||
* 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
|
||||
* 2 - SAMPLE_PIPELINESTAT
|
||||
* 3 - SAMPLE_STREAMOUTSTAT*
|
||||
* 4 - *S_PARTIAL_FLUSH
|
||||
*/
|
||||
#define PACKET3_EVENT_WRITE__EVENT_TYPE(x) ((((unsigned)(x)) & 0x3F) << 0)
|
||||
#define PACKET3_EVENT_WRITE__EVENT_INDEX(x) ((((unsigned)(x)) & 0xF) << 8)
|
||||
#define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE(x) ((((unsigned)(x)) & 0x3) << 29)
|
||||
#define PACKET3_EVENT_WRITE__OFFLOAD_ENABLE(x) ((((unsigned)(x)) & 0x1) << 0)
|
||||
#define PACKET3_EVENT_WRITE__ADDRESS_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
|
||||
#define PACKET3_EVENT_WRITE__ADDRESS_HI(x) ((unsigned)(x))
|
||||
#define PACKET3_EVENT_WRITE__EVENT_INDEX__OTHER 0
|
||||
#define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_PIPELINESTAT 2
|
||||
#define PACKET3_EVENT_WRITE__EVENT_INDEX__CS_PARTIAL_FLUSH 4
|
||||
#define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS 8
|
||||
#define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS1 9
|
||||
#define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS2 10
|
||||
#define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS3 11
|
||||
#define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__LEGACY_MODE 0
|
||||
#define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__MIXED_MODE1 1
|
||||
#define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__NEW_MODE 2
|
||||
#define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__MIXED_MODE3 3
|
||||
#define PACKET3_EVENT_WRITE_EOP 0x47
|
||||
#define PACKET3_EVENT_WRITE_EOS 0x48
|
||||
#define PACKET3_RELEASE_MEM 0x49
|
||||
#define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0)
|
||||
#define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8)
|
||||
#define PACKET3_RELEASE_MEM_GCR_GLM_WB (1 << 12)
|
||||
#define PACKET3_RELEASE_MEM_GCR_GLM_INV (1 << 13)
|
||||
#define PACKET3_RELEASE_MEM_GCR_GLV_INV (1 << 14)
|
||||
#define PACKET3_RELEASE_MEM_GCR_GL1_INV (1 << 15)
|
||||
#define PACKET3_RELEASE_MEM_GCR_GL2_US (1 << 16)
|
||||
#define PACKET3_RELEASE_MEM_GCR_GL2_RANGE (1 << 17)
|
||||
#define PACKET3_RELEASE_MEM_GCR_GL2_DISCARD (1 << 19)
|
||||
#define PACKET3_RELEASE_MEM_GCR_GL2_INV (1 << 20)
|
||||
#define PACKET3_RELEASE_MEM_GCR_GL2_WB (1 << 21)
|
||||
#define PACKET3_RELEASE_MEM_GCR_SEQ (1 << 22)
|
||||
#define PACKET3_RELEASE_MEM_CACHE_POLICY(x) ((x) << 25)
|
||||
/* 0 - cache_policy__me_release_mem__lru
|
||||
* 1 - cache_policy__me_release_mem__stream
|
||||
* 2 - cache_policy__me_release_mem__noa
|
||||
* 3 - cache_policy__me_release_mem__bypass
|
||||
*/
|
||||
#define PACKET3_RELEASE_MEM_EXECUTE (1 << 28)
|
||||
|
||||
#define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29)
|
||||
/* 0 - discard
|
||||
* 1 - send low 32bit data
|
||||
* 2 - send 64bit data
|
||||
* 3 - send 64bit GPU counter value
|
||||
* 4 - send 64bit sys counter value
|
||||
*/
|
||||
#define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24)
|
||||
/* 0 - none
|
||||
* 1 - interrupt only (DATA_SEL = 0)
|
||||
* 2 - interrupt when data write is confirmed
|
||||
*/
|
||||
#define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16)
|
||||
/* 0 - MC
|
||||
* 1 - TC/L2
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#define PACKET3_PREAMBLE_CNTL 0x4A
|
||||
# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
|
||||
# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
|
||||
#define PACKET3_DMA_DATA 0x50
|
||||
/* 1. header
|
||||
* 2. CONTROL
|
||||
* 3. SRC_ADDR_LO or DATA [31:0]
|
||||
* 4. SRC_ADDR_HI [31:0]
|
||||
* 5. DST_ADDR_LO [31:0]
|
||||
* 6. DST_ADDR_HI [7:0]
|
||||
* 7. COMMAND [31:26] | BYTE_COUNT [25:0]
|
||||
*/
|
||||
/* CONTROL */
|
||||
# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
|
||||
/* 0 - ME
|
||||
* 1 - PFP
|
||||
*/
|
||||
# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
|
||||
/* 0 - LRU
|
||||
* 1 - Stream
|
||||
*/
|
||||
# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
|
||||
/* 0 - DST_ADDR using DAS
|
||||
* 1 - GDS
|
||||
* 3 - DST_ADDR using L2
|
||||
*/
|
||||
# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
|
||||
/* 0 - LRU
|
||||
* 1 - Stream
|
||||
*/
|
||||
# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
|
||||
/* 0 - SRC_ADDR using SAS
|
||||
* 1 - GDS
|
||||
* 2 - DATA
|
||||
* 3 - SRC_ADDR using L2
|
||||
*/
|
||||
# define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
|
||||
/* COMMAND */
|
||||
# define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
|
||||
/* 0 - memory
|
||||
* 1 - register
|
||||
*/
|
||||
# define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
|
||||
/* 0 - memory
|
||||
* 1 - register
|
||||
*/
|
||||
# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
|
||||
# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
|
||||
# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
|
||||
#define PACKET3_CONTEXT_REG_RMW 0x51
|
||||
#define PACKET3_GFX_CNTX_UPDATE 0x52
|
||||
#define PACKET3_BLK_CNTX_UPDATE 0x53
|
||||
#define PACKET3_INCR_UPDT_STATE 0x55
|
||||
#define PACKET3_ACQUIRE_MEM 0x58
|
||||
/* 1. HEADER
|
||||
* 2. COHER_CNTL [30:0]
|
||||
* 2.1 ENGINE_SEL [31:31]
|
||||
* 2. COHER_SIZE [31:0]
|
||||
* 3. COHER_SIZE_HI [7:0]
|
||||
* 4. COHER_BASE_LO [31:0]
|
||||
* 5. COHER_BASE_HI [23:0]
|
||||
* 7. POLL_INTERVAL [15:0]
|
||||
* 8. GCR_CNTL [18:0]
|
||||
*/
|
||||
#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0)
|
||||
/*
|
||||
* 0:NOP
|
||||
* 1:ALL
|
||||
* 2:RANGE
|
||||
* 3:FIRST_LAST
|
||||
*/
|
||||
#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2)
|
||||
/*
|
||||
* 0:ALL
|
||||
* 1:reserved
|
||||
* 2:RANGE
|
||||
* 3:FIRST_LAST
|
||||
*/
|
||||
#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x) ((x) << 4)
|
||||
#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x) ((x) << 5)
|
||||
#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x) ((x) << 6)
|
||||
#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7)
|
||||
#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8)
|
||||
#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x) ((x) << 9)
|
||||
#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10)
|
||||
#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11)
|
||||
/*
|
||||
* 0:ALL
|
||||
* 1:VOL
|
||||
* 2:RANGE
|
||||
* 3:FIRST_LAST
|
||||
*/
|
||||
#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13)
|
||||
#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14)
|
||||
#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15)
|
||||
#define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16)
|
||||
/*
|
||||
* 0: PARALLEL
|
||||
* 1: FORWARD
|
||||
* 2: REVERSE
|
||||
*/
|
||||
#define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA (1 << 18)
|
||||
#define PACKET3_ACQUIRE_MEM__COHER_SIZE(x) ((unsigned)(x))
|
||||
#define PACKET3_ACQUIRE_MEM__COHER_SIZE_HI(x) ((((unsigned)(x)) & 0xFF) << 0)
|
||||
#define PACKET3_ACQUIRE_MEM__COHER_BASE_LO(x) ((unsigned)(x))
|
||||
#define PACKET3_ACQUIRE_MEM__COHER_BASE_HI(x) ((((unsigned)(x)) & 0xFFFFFF) << 0)
|
||||
#define PACKET3_ACQUIRE_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0)
|
||||
#define PACKET3_ACQUIRE_MEM__GCR_CNTL(x) ((((unsigned)(x)) & 0x7FFFF) << 0)
|
||||
#define PACKET3_REWIND 0x59
|
||||
#define PACKET3_INTERRUPT 0x5A
|
||||
#define PACKET3_GEN_PDEPTE 0x5B
|
||||
#define PACKET3_INDIRECT_BUFFER_PASID 0x5C
|
||||
#define PACKET3_PRIME_UTCL2 0x5D
|
||||
#define PACKET3_LOAD_UCONFIG_REG 0x5E
|
||||
#define PACKET3_LOAD_SH_REG 0x5F
|
||||
#define PACKET3_LOAD_CONFIG_REG 0x60
|
||||
#define PACKET3_LOAD_CONTEXT_REG 0x61
|
||||
#define PACKET3_LOAD_COMPUTE_STATE 0x62
|
||||
#define PACKET3_LOAD_SH_REG_INDEX 0x63
|
||||
#define PACKET3_SET_CONFIG_REG 0x68
|
||||
#define PACKET3_SET_CONFIG_REG_START 0x00002000
|
||||
#define PACKET3_SET_CONFIG_REG_END 0x00002c00
|
||||
#define PACKET3_SET_CONTEXT_REG 0x69
|
||||
#define PACKET3_SET_CONTEXT_REG_START 0x0000a000
|
||||
#define PACKET3_SET_CONTEXT_REG_END 0x0000a400
|
||||
#define PACKET3_SET_CONTEXT_REG_INDEX 0x6A
|
||||
#define PACKET3_SET_VGPR_REG_DI_MULTI 0x71
|
||||
#define PACKET3_SET_SH_REG_DI 0x72
|
||||
#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
|
||||
#define PACKET3_SET_SH_REG_DI_MULTI 0x74
|
||||
#define PACKET3_GFX_PIPE_LOCK 0x75
|
||||
#define PACKET3_SET_SH_REG 0x76
|
||||
#define PACKET3_SET_SH_REG_START 0x00002c00
|
||||
#define PACKET3_SET_SH_REG_END 0x00003000
|
||||
#define PACKET3_SET_SH_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0)
|
||||
#define PACKET3_SET_SH_REG__VMID_SHIFT(x) ((((unsigned)(x)) & 0x1F) << 23)
|
||||
#define PACKET3_SET_SH_REG__INDEX(x) ((((unsigned)(x)) & 0xF) << 28)
|
||||
#define PACKET3_SET_SH_REG__INDEX__DEFAULT 0
|
||||
#define PACKET3_SET_SH_REG__INDEX__INSERT_VMID 1
|
||||
#define PACKET3_SET_SH_REG_OFFSET 0x77
|
||||
#define PACKET3_SET_QUEUE_REG 0x78
|
||||
#define PACKET3_SET_UCONFIG_REG 0x79
|
||||
#define PACKET3_SET_UCONFIG_REG_START 0x0000c000
|
||||
#define PACKET3_SET_UCONFIG_REG_END 0x0000c400
|
||||
#define PACKET3_SET_UCONFIG_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0)
|
||||
#define PACKET3_SET_UCONFIG_REG_INDEX 0x7A
|
||||
#define PACKET3_FORWARD_HEADER 0x7C
|
||||
#define PACKET3_SCRATCH_RAM_WRITE 0x7D
|
||||
#define PACKET3_SCRATCH_RAM_READ 0x7E
|
||||
#define PACKET3_LOAD_CONST_RAM 0x80
|
||||
#define PACKET3_WRITE_CONST_RAM 0x81
|
||||
#define PACKET3_DUMP_CONST_RAM 0x83
|
||||
#define PACKET3_INCREMENT_CE_COUNTER 0x84
|
||||
#define PACKET3_INCREMENT_DE_COUNTER 0x85
|
||||
#define PACKET3_WAIT_ON_CE_COUNTER 0x86
|
||||
#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
|
||||
#define PACKET3_SWITCH_BUFFER 0x8B
|
||||
#define PACKET3_DISPATCH_DRAW_PREAMBLE 0x8C
|
||||
#define PACKET3_DISPATCH_DRAW_PREAMBLE_ACE 0x8C
|
||||
#define PACKET3_DISPATCH_DRAW 0x8D
|
||||
#define PACKET3_DISPATCH_DRAW_ACE 0x8D
|
||||
#define PACKET3_GET_LOD_STATS 0x8E
|
||||
#define PACKET3_DRAW_MULTI_PREAMBLE 0x8F
|
||||
#define PACKET3_FRAME_CONTROL 0x90
|
||||
# define FRAME_TMZ (1 << 0)
|
||||
# define FRAME_CMD(x) ((x) << 28)
|
||||
/*
|
||||
* x=0: tmz_begin
|
||||
* x=1: tmz_end
|
||||
*/
|
||||
#define PACKET3_INDEX_ATTRIBUTES_INDIRECT 0x91
|
||||
#define PACKET3_WAIT_REG_MEM64 0x93
|
||||
#define PACKET3_COND_PREEMPT 0x94
|
||||
#define PACKET3_HDP_FLUSH 0x95
|
||||
#define PACKET3_COPY_DATA_RB 0x96
|
||||
#define PACKET3_INVALIDATE_TLBS 0x98
|
||||
# define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0)
|
||||
# define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4)
|
||||
# define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5)
|
||||
# define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29)
|
||||
#define PACKET3_AQL_PACKET 0x99
|
||||
#define PACKET3_DMA_DATA_FILL_MULTI 0x9A
|
||||
#define PACKET3_SET_SH_REG_INDEX 0x9B
|
||||
#define PACKET3_DRAW_INDIRECT_COUNT_MULTI 0x9C
|
||||
#define PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI 0x9D
|
||||
#define PACKET3_DUMP_CONST_RAM_OFFSET 0x9E
|
||||
#define PACKET3_LOAD_CONTEXT_REG_INDEX 0x9F
|
||||
#define PACKET3_SET_RESOURCES 0xA0
|
||||
/* 1. header
|
||||
* 2. CONTROL
|
||||
* 3. QUEUE_MASK_LO [31:0]
|
||||
* 4. QUEUE_MASK_HI [31:0]
|
||||
* 5. GWS_MASK_LO [31:0]
|
||||
* 6. GWS_MASK_HI [31:0]
|
||||
* 7. OAC_MASK [15:0]
|
||||
* 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0]
|
||||
*/
|
||||
# define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0)
|
||||
# define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16)
|
||||
# define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29)
|
||||
#define PACKET3_MAP_PROCESS 0xA1
|
||||
#define PACKET3_MAP_QUEUES 0xA2
|
||||
/* 1. header
|
||||
* 2. CONTROL
|
||||
* 3. CONTROL2
|
||||
* 4. MQD_ADDR_LO [31:0]
|
||||
* 5. MQD_ADDR_HI [31:0]
|
||||
* 6. WPTR_ADDR_LO [31:0]
|
||||
* 7. WPTR_ADDR_HI [31:0]
|
||||
*/
|
||||
/* CONTROL */
|
||||
# define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
|
||||
# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8)
|
||||
# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13)
|
||||
# define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16)
|
||||
# define PACKET3_MAP_QUEUES_ME(x) ((x) << 18)
|
||||
# define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21)
|
||||
# define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24)
|
||||
# define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26)
|
||||
# define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29)
|
||||
/* CONTROL2 */
|
||||
# define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1)
|
||||
# define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2)
|
||||
#define PACKET3_UNMAP_QUEUES 0xA3
|
||||
/* 1. header
|
||||
* 2. CONTROL
|
||||
* 3. CONTROL2
|
||||
* 4. CONTROL3
|
||||
* 5. CONTROL4
|
||||
* 6. CONTROL5
|
||||
*/
|
||||
/* CONTROL */
|
||||
# define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0)
|
||||
/* 0 - PREEMPT_QUEUES
|
||||
* 1 - RESET_QUEUES
|
||||
* 2 - DISABLE_PROCESS_QUEUES
|
||||
* 3 - PREEMPT_QUEUES_NO_UNMAP
|
||||
*/
|
||||
# define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
|
||||
# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26)
|
||||
# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29)
|
||||
/* CONTROL2a */
|
||||
# define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0)
|
||||
/* CONTROL2b */
|
||||
# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2)
|
||||
/* CONTROL3a */
|
||||
# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2)
|
||||
/* CONTROL3b */
|
||||
# define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0)
|
||||
/* CONTROL4 */
|
||||
# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2)
|
||||
/* CONTROL5 */
|
||||
# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2)
|
||||
#define PACKET3_QUERY_STATUS 0xA4
|
||||
/* 1. header
|
||||
* 2. CONTROL
|
||||
* 3. CONTROL2
|
||||
* 4. ADDR_LO [31:0]
|
||||
* 5. ADDR_HI [31:0]
|
||||
* 6. DATA_LO [31:0]
|
||||
* 7. DATA_HI [31:0]
|
||||
*/
|
||||
/* CONTROL */
|
||||
# define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0)
|
||||
# define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28)
|
||||
# define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30)
|
||||
/* CONTROL2a */
|
||||
# define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0)
|
||||
/* CONTROL2b */
|
||||
# define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2)
|
||||
# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25)
|
||||
#define PACKET3_RUN_LIST 0xA5
|
||||
#define PACKET3_MAP_PROCESS_VM 0xA6
|
||||
|
||||
#define PACKET3_RUN_CLEANER_SHADER 0xD2
|
||||
/* 1. header
|
||||
* 2. RESERVED [31:0]
|
||||
*/
|
||||
|
||||
/* GFX11 */
|
||||
#define PACKET3_SET_Q_PREEMPTION_MODE 0xF0
|
||||
# define PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x) ((x) << 0)
|
||||
# define PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM (1 << 0)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,583 @@
|
||||
/*
|
||||
* Copyright 2014 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef SOC15_H
|
||||
#define SOC15_H
|
||||
|
||||
#define GFX9_NUM_GFX_RINGS 1
|
||||
#define GFX9_NUM_COMPUTE_RINGS 8
|
||||
|
||||
/*
|
||||
* PM4
|
||||
*/
|
||||
#define PACKET_TYPE0 0
|
||||
#define PACKET_TYPE1 1
|
||||
#define PACKET_TYPE2 2
|
||||
#define PACKET_TYPE3 3
|
||||
|
||||
#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
|
||||
#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
|
||||
#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
|
||||
#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
|
||||
#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
|
||||
((reg) & 0xFFFF) | \
|
||||
((n) & 0x3FFF) << 16)
|
||||
#define CP_PACKET2 0x80000000
|
||||
#define PACKET2_PAD_SHIFT 0
|
||||
#define PACKET2_PAD_MASK (0x3fffffff << 0)
|
||||
|
||||
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
|
||||
|
||||
#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
|
||||
(((op) & 0xFF) << 8) | \
|
||||
((n) & 0x3FFF) << 16)
|
||||
|
||||
#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
|
||||
|
||||
#define PACKETJ_CONDITION_CHECK0 0
|
||||
#define PACKETJ_CONDITION_CHECK1 1
|
||||
#define PACKETJ_CONDITION_CHECK2 2
|
||||
#define PACKETJ_CONDITION_CHECK3 3
|
||||
#define PACKETJ_CONDITION_CHECK4 4
|
||||
#define PACKETJ_CONDITION_CHECK5 5
|
||||
#define PACKETJ_CONDITION_CHECK6 6
|
||||
#define PACKETJ_CONDITION_CHECK7 7
|
||||
|
||||
#define PACKETJ_TYPE0 0
|
||||
#define PACKETJ_TYPE1 1
|
||||
#define PACKETJ_TYPE2 2
|
||||
#define PACKETJ_TYPE3 3
|
||||
#define PACKETJ_TYPE4 4
|
||||
#define PACKETJ_TYPE5 5
|
||||
#define PACKETJ_TYPE6 6
|
||||
#define PACKETJ_TYPE7 7
|
||||
|
||||
#define PACKETJ(reg, r, cond, type) ((reg & 0x3FFFF) | \
|
||||
((r & 0x3F) << 18) | \
|
||||
((cond & 0xF) << 24) | \
|
||||
((type & 0xF) << 28))
|
||||
|
||||
#define CP_PACKETJ_NOP 0x60000000
|
||||
#define CP_PACKETJ_GET_REG(x) ((x) & 0x3FFFF)
|
||||
#define CP_PACKETJ_GET_RES(x) (((x) >> 18) & 0x3F)
|
||||
#define CP_PACKETJ_GET_COND(x) (((x) >> 24) & 0xF)
|
||||
#define CP_PACKETJ_GET_TYPE(x) (((x) >> 28) & 0xF)
|
||||
|
||||
/* Packet 3 types */
|
||||
#define PACKET3_NOP 0x10
|
||||
#define PACKET3_SET_BASE 0x11
|
||||
#define PACKET3_BASE_INDEX(x) ((x) << 0)
|
||||
#define CE_PARTITION_BASE 3
|
||||
#define PACKET3_CLEAR_STATE 0x12
|
||||
#define PACKET3_INDEX_BUFFER_SIZE 0x13
|
||||
#define PACKET3_DISPATCH_DIRECT 0x15
|
||||
#define PACKET3_DISPATCH_INDIRECT 0x16
|
||||
#define PACKET3_ATOMIC_GDS 0x1D
|
||||
#define PACKET3_ATOMIC_MEM 0x1E
|
||||
#define PACKET3_ATOMIC_MEM__ATOMIC(x) ((((unsigned)(x)) & 0x3F) << 0)
|
||||
#define PACKET3_ATOMIC_MEM__COMMAND(x) ((((unsigned)(x)) & 0xF) << 8)
|
||||
#define PACKET3_ATOMIC_MEM__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
|
||||
#define PACKET3_ATOMIC_MEM__ADDR_LO(x) (((unsigned)(x)) << 0)
|
||||
#define PACKET3_ATOMIC_MEM__ADDR_HI(x) (((unsigned)(x)) << 0)
|
||||
#define PACKET3_ATOMIC_MEM__SRC_DATA_LO(x) (((unsigned)(x)) << 0)
|
||||
#define PACKET3_ATOMIC_MEM__SRC_DATA_HI(x) (((unsigned)(x)) << 0)
|
||||
#define PACKET3_ATOMIC_MEM__CMP_DATA_LO(x) (((unsigned)(x)) << 0)
|
||||
#define PACKET3_ATOMIC_MEM__CMP_DATA_HI(x) (((unsigned)(x)) << 0)
|
||||
#define PACKET3_ATOMIC_MEM__LOOP_INTERVAL(x) ((((unsigned)(x)) & 0x1FFF) << 0)
|
||||
#define PACKET3_ATOMIC_MEM__COMMAND__SINGLE_PASS_ATOMIC 0
|
||||
#define PACKET3_ATOMIC_MEM__COMMAND__LOOP_UNTIL_COMPARE_SATISFIED 1
|
||||
#define PACKET3_OCCLUSION_QUERY 0x1F
|
||||
#define PACKET3_SET_PREDICATION 0x20
|
||||
#define PACKET3_REG_RMW 0x21
|
||||
#define PACKET3_COND_EXEC 0x22
|
||||
#define PACKET3_PRED_EXEC 0x23
|
||||
#define PACKET3_PRED_EXEC__EXEC_COUNT(x) ((((unsigned)(x)) & 0x3FFF) << 0)
|
||||
#define PACKET3_PRED_EXEC__VIRTUAL_XCC_ID_SELECT(x) ((((unsigned)(x)) & 0xFF) << 24)
|
||||
#define PACKET3_DRAW_INDIRECT 0x24
|
||||
#define PACKET3_DRAW_INDEX_INDIRECT 0x25
|
||||
#define PACKET3_INDEX_BASE 0x26
|
||||
#define PACKET3_DRAW_INDEX_2 0x27
|
||||
#define PACKET3_CONTEXT_CONTROL 0x28
|
||||
#define PACKET3_INDEX_TYPE 0x2A
|
||||
#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
|
||||
#define PACKET3_DRAW_INDEX_AUTO 0x2D
|
||||
#define PACKET3_NUM_INSTANCES 0x2F
|
||||
#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
|
||||
#define PACKET3_INDIRECT_BUFFER_CONST 0x33
|
||||
#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
|
||||
#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
|
||||
#define PACKET3_DRAW_PREAMBLE 0x36
|
||||
#define PACKET3_WRITE_DATA 0x37
|
||||
#define WRITE_DATA_DST_SEL(x) ((x) << 8)
|
||||
/* 0 - register
|
||||
* 1 - memory (sync - via GRBM)
|
||||
* 2 - gl2
|
||||
* 3 - gds
|
||||
* 4 - reserved
|
||||
* 5 - memory (async - direct)
|
||||
*/
|
||||
#define WR_ONE_ADDR (1 << 16)
|
||||
#define WR_CONFIRM (1 << 20)
|
||||
#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
|
||||
/* 0 - LRU
|
||||
* 1 - Stream
|
||||
*/
|
||||
#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
|
||||
/* 0 - me
|
||||
* 1 - pfp
|
||||
* 2 - ce
|
||||
*/
|
||||
#define PACKET3_WRITE_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8)
|
||||
#define PACKET3_WRITE_DATA__ADDR_INCR(x) ((((unsigned)(x)) & 0x1) << 16)
|
||||
#define PACKET3_WRITE_DATA__RESUME_VF_MI300(x) ((((unsigned)(x)) & 0x1) << 19)
|
||||
#define PACKET3_WRITE_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20)
|
||||
#define PACKET3_WRITE_DATA__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
|
||||
#define PACKET3_WRITE_DATA__DST_MMREG_ADDR(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
|
||||
#define PACKET3_WRITE_DATA__DST_GDS_ADDR(x) ((((unsigned)(x)) & 0xFFFF) << 0)
|
||||
#define PACKET3_WRITE_DATA__DST_MEM_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
|
||||
#define PACKET3_WRITE_DATA__DST_MEM_ADDR_HI(x) ((unsigned)(x))
|
||||
#define PACKET3_WRITE_DATA__DST_SEL__MEM_MAPPED_REGISTER 0
|
||||
#define PACKET3_WRITE_DATA__DST_SEL__TC_L2 2
|
||||
#define PACKET3_WRITE_DATA__DST_SEL__GDS 3
|
||||
#define PACKET3_WRITE_DATA__DST_SEL__MEMORY 5
|
||||
#define PACKET3_WRITE_DATA__DST_SEL__MEMORY_MAPPED_ADC_PERSISTENT_STATE 6
|
||||
#define PACKET3_WRITE_DATA__ADDR_INCR__INCREMENT_ADDRESS 0
|
||||
#define PACKET3_WRITE_DATA__ADDR_INCR__DO_NOT_INCREMENT_ADDRESS 1
|
||||
#define PACKET3_WRITE_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_WRITE_CONFIRMATION 0
|
||||
#define PACKET3_WRITE_DATA__WR_CONFIRM__WAIT_FOR_WRITE_CONFIRMATION 1
|
||||
#define PACKET3_WRITE_DATA__CACHE_POLICY__LRU 0
|
||||
#define PACKET3_WRITE_DATA__CACHE_POLICY__STREAM 1
|
||||
#define PACKET3_WRITE_DATA__CACHE_POLICY__NOA 2
|
||||
#define PACKET3_WRITE_DATA__CACHE_POLICY__BYPASS 3
|
||||
#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
|
||||
#define PACKET3_MEM_SEMAPHORE 0x39
|
||||
# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
|
||||
# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
|
||||
# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
|
||||
# define PACKET3_SEM_SEL_WAIT (0x7 << 29)
|
||||
#define PACKET3_WAIT_REG_MEM 0x3C
|
||||
#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
|
||||
/* 0 - always
|
||||
* 1 - <
|
||||
* 2 - <=
|
||||
* 3 - ==
|
||||
* 4 - !=
|
||||
* 5 - >=
|
||||
* 6 - >
|
||||
*/
|
||||
#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
|
||||
/* 0 - reg
|
||||
* 1 - mem
|
||||
*/
|
||||
#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
|
||||
/* 0 - wait_reg_mem
|
||||
* 1 - wr_wait_wr_reg
|
||||
*/
|
||||
#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
|
||||
/* 0 - me
|
||||
* 1 - pfp
|
||||
*/
|
||||
#define PACKET3_WAIT_REG_MEM__FUNCTION(x) ((((unsigned)(x)) & 0x7) << 0)
|
||||
#define PACKET3_WAIT_REG_MEM__MEM_SPACE(x) ((((unsigned)(x)) & 0x3) << 4)
|
||||
#define PACKET3_WAIT_REG_MEM__OPERATION(x) ((((unsigned)(x)) & 0x3) << 6)
|
||||
#define PACKET3_WAIT_REG_MEM__MES_INTR_PIPE(x) ((((unsigned)(x)) & 0x3) << 22)
|
||||
#define PACKET3_WAIT_REG_MEM__MES_ACTION(x) ((((unsigned)(x)) & 0x1) << 24)
|
||||
#define PACKET3_WAIT_REG_MEM__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
|
||||
#define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
|
||||
#define PACKET3_WAIT_REG_MEM__REG_POLL_ADDR(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
|
||||
#define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR1(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
|
||||
#define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI(x) ((unsigned)(x))
|
||||
#define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR2(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
|
||||
#define PACKET3_WAIT_REG_MEM__REFERENCE(x) ((unsigned)(x))
|
||||
#define PACKET3_WAIT_REG_MEM__MASK(x) ((unsigned)(x))
|
||||
#define PACKET3_WAIT_REG_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0)
|
||||
#define PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE(x) ((((unsigned)(x)) & 0x1) << 31)
|
||||
#define PACKET3_WAIT_REG_MEM__FUNCTION__ALWAYS_PASS 0
|
||||
#define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_REF_VALUE 1
|
||||
#define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_EQUAL_TO_THE_REF_VALUE 2
|
||||
#define PACKET3_WAIT_REG_MEM__FUNCTION__EQUAL_TO_THE_REFERENCE_VALUE 3
|
||||
#define PACKET3_WAIT_REG_MEM__FUNCTION__NOT_EQUAL_REFERENCE_VALUE 4
|
||||
#define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_OR_EQUAL_REFERENCE_VALUE 5
|
||||
#define PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_REFERENCE_VALUE 6
|
||||
#define PACKET3_WAIT_REG_MEM__MEM_SPACE__REGISTER_SPACE 0
|
||||
#define PACKET3_WAIT_REG_MEM__MEM_SPACE__MEMORY_SPACE 1
|
||||
#define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_REG_MEM 0
|
||||
#define PACKET3_WAIT_REG_MEM__OPERATION__WR_WAIT_WR_REG 1
|
||||
#define PACKET3_WAIT_REG_MEM__OPERATION__WAIT_MEM_PREEMPTABLE 3
|
||||
#define PACKET3_INDIRECT_BUFFER 0x3F
|
||||
#define INDIRECT_BUFFER_VALID (1 << 23)
|
||||
#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
|
||||
/* 0 - LRU
|
||||
* 1 - Stream
|
||||
* 2 - Bypass
|
||||
*/
|
||||
#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21)
|
||||
#define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30)
|
||||
#define PACKET3_INDIRECT_BUFFER__IB_BASE_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
|
||||
#define PACKET3_INDIRECT_BUFFER__IB_BASE_HI(x) ((unsigned)(x))
|
||||
#define PACKET3_INDIRECT_BUFFER__IB_SIZE(x) ((((unsigned)(x)) & 0xFFFFF) << 0)
|
||||
#define PACKET3_INDIRECT_BUFFER__CHAIN(x) ((((unsigned)(x)) & 0x1) << 20)
|
||||
#define PACKET3_INDIRECT_BUFFER__OFFLOAD_POLLING(x) ((((unsigned)(x)) & 0x1) << 21)
|
||||
#define PACKET3_INDIRECT_BUFFER__VALID(x) ((((unsigned)(x)) & 0x1) << 23)
|
||||
#define PACKET3_INDIRECT_BUFFER__VMID(x) ((((unsigned)(x)) & 0xF) << 24)
|
||||
#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 28)
|
||||
#define PACKET3_INDIRECT_BUFFER__PRIV(x) ((((unsigned)(x)) & 0x1) << 31)
|
||||
#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__LRU 0
|
||||
#define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__STREAM 1
|
||||
#define PACKET3_COPY_DATA 0x40
|
||||
#define PACKET3_COPY_DATA__SRC_SEL(x) ((((unsigned)(x)) & 0xF) << 0)
|
||||
#define PACKET3_COPY_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8)
|
||||
#define PACKET3_COPY_DATA__SRC_CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 13)
|
||||
#define PACKET3_COPY_DATA__COUNT_SEL(x) ((((unsigned)(x)) & 0x1) << 16)
|
||||
#define PACKET3_COPY_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20)
|
||||
#define PACKET3_COPY_DATA__DST_CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
|
||||
#define PACKET3_COPY_DATA__PQ_EXE_STATUS(x) ((((unsigned)(x)) & 0x1) << 29)
|
||||
#define PACKET3_COPY_DATA__SRC_REG_OFFSET(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
|
||||
#define PACKET3_COPY_DATA__SRC_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
|
||||
#define PACKET3_COPY_DATA__SRC_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
|
||||
#define PACKET3_COPY_DATA__SRC_GDS_ADDR_LO(x) ((((unsigned)(x)) & 0xFFFF) << 0)
|
||||
#define PACKET3_COPY_DATA__IMM_DATA(x) ((unsigned)(x))
|
||||
#define PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI(x) ((unsigned)(x))
|
||||
#define PACKET3_COPY_DATA__SRC_IMM_DATA(x) ((unsigned)(x))
|
||||
#define PACKET3_COPY_DATA__DST_REG_OFFSET(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
|
||||
#define PACKET3_COPY_DATA__DST_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
|
||||
#define PACKET3_COPY_DATA__DST_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
|
||||
#define PACKET3_COPY_DATA__DST_GDS_ADDR_LO(x) ((((unsigned)(x)) & 0xFFFF) << 0)
|
||||
#define PACKET3_COPY_DATA__DST_ADDR_HI(x) ((unsigned)(x))
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__MEM_MAPPED_REGISTER 0
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__MEMORY 1
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__TC_L2 2
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__GDS 3
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__PERFCOUNTERS 4
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__IMMEDIATE_DATA 5
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__ATOMIC_RETURN_DATA 6
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA0 7
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA1 8
|
||||
#define PACKET3_COPY_DATA__SRC_SEL__GPU_CLOCK_COUNT 9
|
||||
#define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER 0
|
||||
#define PACKET3_COPY_DATA__DST_SEL__TC_L2 2
|
||||
#define PACKET3_COPY_DATA__DST_SEL__GDS 3
|
||||
#define PACKET3_COPY_DATA__DST_SEL__PERFCOUNTERS 4
|
||||
#define PACKET3_COPY_DATA__DST_SEL__MEMORY 5
|
||||
#define PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REG_DC 6
|
||||
#define PACKET3_COPY_DATA__SRC_CACHE_POLICY__LRU 0
|
||||
#define PACKET3_COPY_DATA__SRC_CACHE_POLICY__STREAM 1
|
||||
#define PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA 0
|
||||
#define PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA 1
|
||||
#define PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION 0
|
||||
#define PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION 1
|
||||
#define PACKET3_COPY_DATA__DST_CACHE_POLICY__LRU 0
|
||||
#define PACKET3_COPY_DATA__DST_CACHE_POLICY__STREAM 1
|
||||
#define PACKET3_COPY_DATA__PQ_EXE_STATUS__DEFAULT 0
|
||||
#define PACKET3_COPY_DATA__PQ_EXE_STATUS__PHASE_UPDATE 1
|
||||
#define PACKET3_PFP_SYNC_ME 0x42
|
||||
#define PACKET3_COND_WRITE 0x45
|
||||
#define PACKET3_EVENT_WRITE 0x46
|
||||
#define EVENT_TYPE(x) ((x) << 0)
|
||||
#define EVENT_INDEX(x) ((x) << 8)
|
||||
/* 0 - any non-TS event
|
||||
* 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
|
||||
* 2 - SAMPLE_PIPELINESTAT
|
||||
* 3 - SAMPLE_STREAMOUTSTAT*
|
||||
* 4 - *S_PARTIAL_FLUSH
|
||||
*/
|
||||
#define PACKET3_EVENT_WRITE__EVENT_TYPE(x) ((((unsigned)(x)) & 0x3F) << 0)
|
||||
#define PACKET3_EVENT_WRITE__EVENT_INDEX(x) ((((unsigned)(x)) & 0xF) << 8)
|
||||
#define PACKET3_EVENT_WRITE__OFFLOAD_ENABLE(x) ((((unsigned)(x)) & 0x1) << 31)
|
||||
#define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE(x) ((((unsigned)(x)) & 0x3) << 29)
|
||||
#define PACKET3_EVENT_WRITE__ADDRESS_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
|
||||
#define PACKET3_EVENT_WRITE__ADDRESS_HI(x) (((unsigned)(x)) << 0)
|
||||
#define PACKET3_EVENT_WRITE__EVENT_INDEX__OTHER 0
|
||||
#define PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_PIPELINESTATS 2
|
||||
#define PACKET3_EVENT_WRITE__EVENT_INDEX__CS_PARTIAL_FLUSH 4
|
||||
#define PACKET3_RELEASE_MEM 0x49
|
||||
#define EVENT_TYPE(x) ((x) << 0)
|
||||
#define EVENT_INDEX(x) ((x) << 8)
|
||||
#define EOP_TCL1_VOL_ACTION_EN (1 << 12)
|
||||
#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
|
||||
#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
|
||||
#define EOP_TCL1_ACTION_EN (1 << 16)
|
||||
#define EOP_TC_ACTION_EN (1 << 17) /* L2 */
|
||||
#define EOP_TC_NC_ACTION_EN (1 << 19)
|
||||
#define EOP_TC_MD_ACTION_EN (1 << 21) /* L2 metadata */
|
||||
#define EOP_EXEC (1 << 28) /* For Trailing Fence */
|
||||
|
||||
#define DATA_SEL(x) ((x) << 29)
|
||||
/* 0 - discard
|
||||
* 1 - send low 32bit data
|
||||
* 2 - send 64bit data
|
||||
* 3 - send 64bit GPU counter value
|
||||
* 4 - send 64bit sys counter value
|
||||
*/
|
||||
#define INT_SEL(x) ((x) << 24)
|
||||
/* 0 - none
|
||||
* 1 - interrupt only (DATA_SEL = 0)
|
||||
* 2 - interrupt when data write is confirmed
|
||||
*/
|
||||
#define DST_SEL(x) ((x) << 16)
|
||||
/* 0 - MC
|
||||
* 1 - TC/L2
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#define PACKET3_PREAMBLE_CNTL 0x4A
|
||||
# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
|
||||
# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
|
||||
#define PACKET3_DMA_DATA 0x50
|
||||
/* 1. header
|
||||
* 2. CONTROL
|
||||
* 3. SRC_ADDR_LO or DATA [31:0]
|
||||
* 4. SRC_ADDR_HI [31:0]
|
||||
* 5. DST_ADDR_LO [31:0]
|
||||
* 6. DST_ADDR_HI [7:0]
|
||||
* 7. COMMAND [30:21] | BYTE_COUNT [20:0]
|
||||
*/
|
||||
/* CONTROL */
|
||||
# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
|
||||
/* 0 - ME
|
||||
* 1 - PFP
|
||||
*/
|
||||
# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
|
||||
/* 0 - LRU
|
||||
* 1 - Stream
|
||||
*/
|
||||
# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
|
||||
/* 0 - DST_ADDR using DAS
|
||||
* 1 - GDS
|
||||
* 3 - DST_ADDR using L2
|
||||
*/
|
||||
# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
|
||||
/* 0 - LRU
|
||||
* 1 - Stream
|
||||
*/
|
||||
# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
|
||||
/* 0 - SRC_ADDR using SAS
|
||||
* 1 - GDS
|
||||
* 2 - DATA
|
||||
* 3 - SRC_ADDR using L2
|
||||
*/
|
||||
# define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
|
||||
/* COMMAND */
|
||||
# define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
|
||||
/* 0 - memory
|
||||
* 1 - register
|
||||
*/
|
||||
# define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
|
||||
/* 0 - memory
|
||||
* 1 - register
|
||||
*/
|
||||
# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
|
||||
# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
|
||||
# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
|
||||
#define PACKET3_ACQUIRE_MEM 0x58
|
||||
/* 1. HEADER
|
||||
* 2. COHER_CNTL [30:0]
|
||||
* 2.1 ENGINE_SEL [31:31]
|
||||
* 3. COHER_SIZE [31:0]
|
||||
* 4. COHER_SIZE_HI [7:0]
|
||||
* 5. COHER_BASE_LO [31:0]
|
||||
* 6. COHER_BASE_HI [23:0]
|
||||
* 7. POLL_INTERVAL [15:0]
|
||||
*/
|
||||
/* COHER_CNTL fields for CP_COHER_CNTL */
|
||||
#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) ((x) << 3)
|
||||
#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x) ((x) << 4)
|
||||
#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x) ((x) << 5)
|
||||
#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x) ((x) << 15)
|
||||
#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x) ((x) << 18)
|
||||
#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x) ((x) << 22)
|
||||
#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x) ((x) << 23)
|
||||
#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x) ((x) << 25)
|
||||
#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x) ((x) << 26)
|
||||
#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x) ((x) << 27)
|
||||
#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x) ((x) << 28)
|
||||
#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x) ((x) << 29)
|
||||
#define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x) ((x) << 30)
|
||||
#define PACKET3_REWIND 0x59
|
||||
#define PACKET3_ACQUIRE_MEM__COHER_SIZE(x) ((unsigned)(x))
|
||||
#define PACKET3_ACQUIRE_MEM__COHER_SIZE_HI(x) ((((unsigned)(x)) & 0xFF) << 0)
|
||||
#define PACKET3_ACQUIRE_MEM__COHER_SIZE_HI_VG10(x) ((((unsigned)(x)) & 0xFFFFFF) << 0)
|
||||
#define PACKET3_ACQUIRE_MEM__COHER_BASE_LO(x) ((unsigned)(x))
|
||||
#define PACKET3_ACQUIRE_MEM__COHER_BASE_HI(x) ((((unsigned)(x)) & 0xFFFFFF) << 0)
|
||||
#define PACKET3_ACQUIRE_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0)
|
||||
#define PACKET3_ACQUIRE_MEM__GCR_CNTL(x) ((((unsigned)(x)) & 0x7FF) << 0)
|
||||
#define PACKET3_LOAD_UCONFIG_REG 0x5E
|
||||
#define PACKET3_LOAD_SH_REG 0x5F
|
||||
#define PACKET3_LOAD_CONFIG_REG 0x60
|
||||
#define PACKET3_LOAD_CONTEXT_REG 0x61
|
||||
#define PACKET3_SET_CONFIG_REG 0x68
|
||||
#define PACKET3_SET_CONFIG_REG_START 0x00002000
|
||||
#define PACKET3_SET_CONFIG_REG_END 0x00002c00
|
||||
#define PACKET3_SET_CONTEXT_REG 0x69
|
||||
#define PACKET3_SET_CONTEXT_REG_START 0x0000a000
|
||||
#define PACKET3_SET_CONTEXT_REG_END 0x0000a400
|
||||
#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
|
||||
#define PACKET3_SET_SH_REG 0x76
|
||||
#define PACKET3_SET_SH_REG_START 0x00002c00
|
||||
#define PACKET3_SET_SH_REG_END 0x00003000
|
||||
#define PACKET3_SET_SH_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0)
|
||||
#define PACKET3_SET_SH_REG__VMID_SHIFT(x) ((((unsigned)(x)) & 0x1F) << 23)
|
||||
#define PACKET3_SET_SH_REG__INDEX(x) ((((unsigned)(x)) & 0xF) << 28)
|
||||
#define PACKET3_SET_SH_REG_OFFSET 0x77
|
||||
#define PACKET3_SET_QUEUE_REG 0x78
|
||||
#define PACKET3_SET_UCONFIG_REG 0x79
|
||||
#define PACKET3_SET_UCONFIG_REG_START 0x0000c000
|
||||
#define PACKET3_SET_UCONFIG_REG_END 0x0000c400
|
||||
#define PACKET3_SET_UCONFIG_REG_INDEX_TYPE (2 << 28)
|
||||
#define PACKET3_SET_UCONFIG_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0)
|
||||
#define PACKET3_SCRATCH_RAM_WRITE 0x7D
|
||||
#define PACKET3_SCRATCH_RAM_READ 0x7E
|
||||
#define PACKET3_LOAD_CONST_RAM 0x80
|
||||
#define PACKET3_WRITE_CONST_RAM 0x81
|
||||
#define PACKET3_DUMP_CONST_RAM 0x83
|
||||
#define PACKET3_INCREMENT_CE_COUNTER 0x84
|
||||
#define PACKET3_INCREMENT_DE_COUNTER 0x85
|
||||
#define PACKET3_WAIT_ON_CE_COUNTER 0x86
|
||||
#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
|
||||
#define PACKET3_SWITCH_BUFFER 0x8B
|
||||
#define PACKET3_FRAME_CONTROL 0x90
|
||||
# define FRAME_TMZ (1 << 0)
|
||||
# define FRAME_CMD(x) ((x) << 28)
|
||||
/*
|
||||
* x=0: tmz_begin
|
||||
* x=1: tmz_end
|
||||
*/
|
||||
|
||||
#define PACKET3_INVALIDATE_TLBS 0x98
|
||||
# define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0)
|
||||
# define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4)
|
||||
# define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5)
|
||||
# define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29)
|
||||
#define PACKET3_SET_RESOURCES 0xA0
|
||||
/* 1. header
|
||||
* 2. CONTROL
|
||||
* 3. QUEUE_MASK_LO [31:0]
|
||||
* 4. QUEUE_MASK_HI [31:0]
|
||||
* 5. GWS_MASK_LO [31:0]
|
||||
* 6. GWS_MASK_HI [31:0]
|
||||
* 7. OAC_MASK [15:0]
|
||||
* 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0]
|
||||
*/
|
||||
# define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0)
|
||||
# define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16)
|
||||
# define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29)
|
||||
#define PACKET3_MAP_QUEUES 0xA2
|
||||
/* 1. header
|
||||
* 2. CONTROL
|
||||
* 3. CONTROL2
|
||||
* 4. MQD_ADDR_LO [31:0]
|
||||
* 5. MQD_ADDR_HI [31:0]
|
||||
* 6. WPTR_ADDR_LO [31:0]
|
||||
* 7. WPTR_ADDR_HI [31:0]
|
||||
*/
|
||||
/* CONTROL */
|
||||
# define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
|
||||
# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8)
|
||||
# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13)
|
||||
# define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16)
|
||||
# define PACKET3_MAP_QUEUES_ME(x) ((x) << 18)
|
||||
# define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21)
|
||||
# define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24)
|
||||
# define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26)
|
||||
# define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29)
|
||||
/* CONTROL2 */
|
||||
# define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1)
|
||||
# define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2)
|
||||
#define PACKET3_UNMAP_QUEUES 0xA3
|
||||
/* 1. header
|
||||
* 2. CONTROL
|
||||
* 3. CONTROL2
|
||||
* 4. CONTROL3
|
||||
* 5. CONTROL4
|
||||
* 6. CONTROL5
|
||||
*/
|
||||
/* CONTROL */
|
||||
# define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0)
|
||||
/* 0 - PREEMPT_QUEUES
|
||||
* 1 - RESET_QUEUES
|
||||
* 2 - DISABLE_PROCESS_QUEUES
|
||||
* 3 - PREEMPT_QUEUES_NO_UNMAP
|
||||
*/
|
||||
# define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
|
||||
# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26)
|
||||
# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29)
|
||||
/* CONTROL2a */
|
||||
# define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0)
|
||||
/* CONTROL2b */
|
||||
# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2)
|
||||
/* CONTROL3a */
|
||||
# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2)
|
||||
/* CONTROL3b */
|
||||
# define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0)
|
||||
/* CONTROL4 */
|
||||
# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2)
|
||||
/* CONTROL5 */
|
||||
# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2)
|
||||
#define PACKET3_QUERY_STATUS 0xA4
|
||||
/* 1. header
|
||||
* 2. CONTROL
|
||||
* 3. CONTROL2
|
||||
* 4. ADDR_LO [31:0]
|
||||
* 5. ADDR_HI [31:0]
|
||||
* 6. DATA_LO [31:0]
|
||||
* 7. DATA_HI [31:0]
|
||||
*/
|
||||
/* CONTROL */
|
||||
# define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0)
|
||||
# define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28)
|
||||
# define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30)
|
||||
/* CONTROL2a */
|
||||
# define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0)
|
||||
/* CONTROL2b */
|
||||
# define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2)
|
||||
# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25)
|
||||
|
||||
#define PACKET3_RUN_CLEANER_SHADER 0xD2
|
||||
/* 1. header
|
||||
* 2. RESERVED [31:0]
|
||||
*/
|
||||
|
||||
#define VCE_CMD_NO_OP 0x00000000
|
||||
#define VCE_CMD_END 0x00000001
|
||||
#define VCE_CMD_IB 0x00000002
|
||||
#define VCE_CMD_FENCE 0x00000003
|
||||
#define VCE_CMD_TRAP 0x00000004
|
||||
#define VCE_CMD_IB_AUTO 0x00000005
|
||||
#define VCE_CMD_SEMAPHORE 0x00000006
|
||||
|
||||
#define VCE_CMD_IB_VM 0x00000102
|
||||
#define VCE_CMD_WAIT_GE 0x00000106
|
||||
#define VCE_CMD_UPDATE_PTB 0x00000107
|
||||
#define VCE_CMD_FLUSH_TLB 0x00000108
|
||||
#define VCE_CMD_REG_WRITE 0x00000109
|
||||
#define VCE_CMD_REG_WAIT 0x0000010a
|
||||
|
||||
#define HEVC_ENC_CMD_NO_OP 0x00000000
|
||||
#define HEVC_ENC_CMD_END 0x00000001
|
||||
#define HEVC_ENC_CMD_FENCE 0x00000003
|
||||
#define HEVC_ENC_CMD_TRAP 0x00000004
|
||||
#define HEVC_ENC_CMD_IB_VM 0x00000102
|
||||
#define HEVC_ENC_CMD_REG_WRITE 0x00000109
|
||||
#define HEVC_ENC_CMD_REG_WAIT 0x0000010a
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,453 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef _athub_1_0_OFFSET_HEADER
|
||||
#define _athub_1_0_OFFSET_HEADER
|
||||
|
||||
|
||||
|
||||
// addressBlock: athub_atsdec
|
||||
// base address: 0x3080
|
||||
#define mmATC_ATS_CNTL 0x0000
|
||||
#define mmATC_ATS_CNTL_BASE_IDX 0
|
||||
#define mmATC_ATS_STATUS 0x0003
|
||||
#define mmATC_ATS_STATUS_BASE_IDX 0
|
||||
#define mmATC_ATS_FAULT_CNTL 0x0004
|
||||
#define mmATC_ATS_FAULT_CNTL_BASE_IDX 0
|
||||
#define mmATC_ATS_FAULT_STATUS_INFO 0x0005
|
||||
#define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0
|
||||
#define mmATC_ATS_FAULT_STATUS_ADDR 0x0006
|
||||
#define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0
|
||||
#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0007
|
||||
#define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0
|
||||
#define mmATC_TRANS_FAULT_RSPCNTRL 0x0008
|
||||
#define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0
|
||||
#define mmATC_ATS_FAULT_STATUS_INFO2 0x0009
|
||||
#define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0
|
||||
#define mmATHUB_MISC_CNTL 0x000a
|
||||
#define mmATHUB_MISC_CNTL_BASE_IDX 0
|
||||
#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x000b
|
||||
#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0
|
||||
#define mmATC_VMID0_PASID_MAPPING 0x000c
|
||||
#define mmATC_VMID0_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID1_PASID_MAPPING 0x000d
|
||||
#define mmATC_VMID1_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID2_PASID_MAPPING 0x000e
|
||||
#define mmATC_VMID2_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID3_PASID_MAPPING 0x000f
|
||||
#define mmATC_VMID3_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID4_PASID_MAPPING 0x0010
|
||||
#define mmATC_VMID4_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID5_PASID_MAPPING 0x0011
|
||||
#define mmATC_VMID5_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID6_PASID_MAPPING 0x0012
|
||||
#define mmATC_VMID6_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID7_PASID_MAPPING 0x0013
|
||||
#define mmATC_VMID7_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID8_PASID_MAPPING 0x0014
|
||||
#define mmATC_VMID8_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID9_PASID_MAPPING 0x0015
|
||||
#define mmATC_VMID9_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID10_PASID_MAPPING 0x0016
|
||||
#define mmATC_VMID10_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID11_PASID_MAPPING 0x0017
|
||||
#define mmATC_VMID11_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID12_PASID_MAPPING 0x0018
|
||||
#define mmATC_VMID12_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID13_PASID_MAPPING 0x0019
|
||||
#define mmATC_VMID13_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID14_PASID_MAPPING 0x001a
|
||||
#define mmATC_VMID14_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID15_PASID_MAPPING 0x001b
|
||||
#define mmATC_VMID15_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_ATS_VMID_STATUS 0x001c
|
||||
#define mmATC_ATS_VMID_STATUS_BASE_IDX 0
|
||||
#define mmATC_ATS_GFX_ATCL2_STATUS 0x001d
|
||||
#define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX 0
|
||||
#define mmATC_PERFCOUNTER0_CFG 0x001e
|
||||
#define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0
|
||||
#define mmATC_PERFCOUNTER1_CFG 0x001f
|
||||
#define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0
|
||||
#define mmATC_PERFCOUNTER2_CFG 0x0020
|
||||
#define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0
|
||||
#define mmATC_PERFCOUNTER3_CFG 0x0021
|
||||
#define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0
|
||||
#define mmATC_PERFCOUNTER_RSLT_CNTL 0x0022
|
||||
#define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
|
||||
#define mmATC_PERFCOUNTER_LO 0x0023
|
||||
#define mmATC_PERFCOUNTER_LO_BASE_IDX 0
|
||||
#define mmATC_PERFCOUNTER_HI 0x0024
|
||||
#define mmATC_PERFCOUNTER_HI_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL 0x0025
|
||||
#define mmATHUB_PCIE_ATS_CNTL_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_PASID_CNTL 0x0026
|
||||
#define mmATHUB_PCIE_PASID_CNTL_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0027
|
||||
#define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0028
|
||||
#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0
|
||||
#define mmATHUB_COMMAND 0x0029
|
||||
#define mmATHUB_COMMAND_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_0 0x002a
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_1 0x002b
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_2 0x002c
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_3 0x002d
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_4 0x002e
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_5 0x002f
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0030
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_7 0x0031
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_8 0x0032
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_9 0x0033
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_10 0x0034
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_11 0x0035
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_12 0x0036
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_13 0x0037
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_14 0x0038
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_15 0x0039
|
||||
#define mmATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0
|
||||
#define mmATHUB_MEM_POWER_LS 0x003a
|
||||
#define mmATHUB_MEM_POWER_LS_BASE_IDX 0
|
||||
#define mmATS_IH_CREDIT 0x003b
|
||||
#define mmATS_IH_CREDIT_BASE_IDX 0
|
||||
#define mmATHUB_IH_CREDIT 0x003c
|
||||
#define mmATHUB_IH_CREDIT_BASE_IDX 0
|
||||
#define mmATC_VMID16_PASID_MAPPING 0x003d
|
||||
#define mmATC_VMID16_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID17_PASID_MAPPING 0x003e
|
||||
#define mmATC_VMID17_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID18_PASID_MAPPING 0x003f
|
||||
#define mmATC_VMID18_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID19_PASID_MAPPING 0x0040
|
||||
#define mmATC_VMID19_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID20_PASID_MAPPING 0x0041
|
||||
#define mmATC_VMID20_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID21_PASID_MAPPING 0x0042
|
||||
#define mmATC_VMID21_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID22_PASID_MAPPING 0x0043
|
||||
#define mmATC_VMID22_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID23_PASID_MAPPING 0x0044
|
||||
#define mmATC_VMID23_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID24_PASID_MAPPING 0x0045
|
||||
#define mmATC_VMID24_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID25_PASID_MAPPING 0x0046
|
||||
#define mmATC_VMID25_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID26_PASID_MAPPING 0x0047
|
||||
#define mmATC_VMID26_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID27_PASID_MAPPING 0x0048
|
||||
#define mmATC_VMID27_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID28_PASID_MAPPING 0x0049
|
||||
#define mmATC_VMID28_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID29_PASID_MAPPING 0x004a
|
||||
#define mmATC_VMID29_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID30_PASID_MAPPING 0x004b
|
||||
#define mmATC_VMID30_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_VMID31_PASID_MAPPING 0x004c
|
||||
#define mmATC_VMID31_PASID_MAPPING_BASE_IDX 0
|
||||
#define mmATC_ATS_MMHUB_ATCL2_STATUS 0x004d
|
||||
#define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX 0
|
||||
#define mmATHUB_SHARED_VIRT_RESET_REQ 0x004e
|
||||
#define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0
|
||||
#define mmATHUB_SHARED_ACTIVE_FCN_ID 0x004f
|
||||
#define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0
|
||||
#define mmATC_ATS_SDPPORT_CNTL 0x0050
|
||||
#define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0
|
||||
#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT 0x0052
|
||||
#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_BASE_IDX 0
|
||||
#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 0x0053
|
||||
#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_BASE_IDX 0
|
||||
|
||||
|
||||
// addressBlock: athub_xpbdec
|
||||
// base address: 0x31f0
|
||||
#define mmXPB_RTR_SRC_APRTR0 0x005c
|
||||
#define mmXPB_RTR_SRC_APRTR0_BASE_IDX 0
|
||||
#define mmXPB_RTR_SRC_APRTR1 0x005d
|
||||
#define mmXPB_RTR_SRC_APRTR1_BASE_IDX 0
|
||||
#define mmXPB_RTR_SRC_APRTR2 0x005e
|
||||
#define mmXPB_RTR_SRC_APRTR2_BASE_IDX 0
|
||||
#define mmXPB_RTR_SRC_APRTR3 0x005f
|
||||
#define mmXPB_RTR_SRC_APRTR3_BASE_IDX 0
|
||||
#define mmXPB_RTR_SRC_APRTR4 0x0060
|
||||
#define mmXPB_RTR_SRC_APRTR4_BASE_IDX 0
|
||||
#define mmXPB_RTR_SRC_APRTR5 0x0061
|
||||
#define mmXPB_RTR_SRC_APRTR5_BASE_IDX 0
|
||||
#define mmXPB_RTR_SRC_APRTR6 0x0062
|
||||
#define mmXPB_RTR_SRC_APRTR6_BASE_IDX 0
|
||||
#define mmXPB_RTR_SRC_APRTR7 0x0063
|
||||
#define mmXPB_RTR_SRC_APRTR7_BASE_IDX 0
|
||||
#define mmXPB_RTR_SRC_APRTR8 0x0064
|
||||
#define mmXPB_RTR_SRC_APRTR8_BASE_IDX 0
|
||||
#define mmXPB_RTR_SRC_APRTR9 0x0065
|
||||
#define mmXPB_RTR_SRC_APRTR9_BASE_IDX 0
|
||||
#define mmXPB_XDMA_RTR_SRC_APRTR0 0x0066
|
||||
#define mmXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 0
|
||||
#define mmXPB_XDMA_RTR_SRC_APRTR1 0x0067
|
||||
#define mmXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 0
|
||||
#define mmXPB_XDMA_RTR_SRC_APRTR2 0x0068
|
||||
#define mmXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 0
|
||||
#define mmXPB_XDMA_RTR_SRC_APRTR3 0x0069
|
||||
#define mmXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 0
|
||||
#define mmXPB_RTR_DEST_MAP0 0x006a
|
||||
#define mmXPB_RTR_DEST_MAP0_BASE_IDX 0
|
||||
#define mmXPB_RTR_DEST_MAP1 0x006b
|
||||
#define mmXPB_RTR_DEST_MAP1_BASE_IDX 0
|
||||
#define mmXPB_RTR_DEST_MAP2 0x006c
|
||||
#define mmXPB_RTR_DEST_MAP2_BASE_IDX 0
|
||||
#define mmXPB_RTR_DEST_MAP3 0x006d
|
||||
#define mmXPB_RTR_DEST_MAP3_BASE_IDX 0
|
||||
#define mmXPB_RTR_DEST_MAP4 0x006e
|
||||
#define mmXPB_RTR_DEST_MAP4_BASE_IDX 0
|
||||
#define mmXPB_RTR_DEST_MAP5 0x006f
|
||||
#define mmXPB_RTR_DEST_MAP5_BASE_IDX 0
|
||||
#define mmXPB_RTR_DEST_MAP6 0x0070
|
||||
#define mmXPB_RTR_DEST_MAP6_BASE_IDX 0
|
||||
#define mmXPB_RTR_DEST_MAP7 0x0071
|
||||
#define mmXPB_RTR_DEST_MAP7_BASE_IDX 0
|
||||
#define mmXPB_RTR_DEST_MAP8 0x0072
|
||||
#define mmXPB_RTR_DEST_MAP8_BASE_IDX 0
|
||||
#define mmXPB_RTR_DEST_MAP9 0x0073
|
||||
#define mmXPB_RTR_DEST_MAP9_BASE_IDX 0
|
||||
#define mmXPB_XDMA_RTR_DEST_MAP0 0x0074
|
||||
#define mmXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 0
|
||||
#define mmXPB_XDMA_RTR_DEST_MAP1 0x0075
|
||||
#define mmXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 0
|
||||
#define mmXPB_XDMA_RTR_DEST_MAP2 0x0076
|
||||
#define mmXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 0
|
||||
#define mmXPB_XDMA_RTR_DEST_MAP3 0x0077
|
||||
#define mmXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 0
|
||||
#define mmXPB_CLG_CFG0 0x0078
|
||||
#define mmXPB_CLG_CFG0_BASE_IDX 0
|
||||
#define mmXPB_CLG_CFG1 0x0079
|
||||
#define mmXPB_CLG_CFG1_BASE_IDX 0
|
||||
#define mmXPB_CLG_CFG2 0x007a
|
||||
#define mmXPB_CLG_CFG2_BASE_IDX 0
|
||||
#define mmXPB_CLG_CFG3 0x007b
|
||||
#define mmXPB_CLG_CFG3_BASE_IDX 0
|
||||
#define mmXPB_CLG_CFG4 0x007c
|
||||
#define mmXPB_CLG_CFG4_BASE_IDX 0
|
||||
#define mmXPB_CLG_CFG5 0x007d
|
||||
#define mmXPB_CLG_CFG5_BASE_IDX 0
|
||||
#define mmXPB_CLG_CFG6 0x007e
|
||||
#define mmXPB_CLG_CFG6_BASE_IDX 0
|
||||
#define mmXPB_CLG_CFG7 0x007f
|
||||
#define mmXPB_CLG_CFG7_BASE_IDX 0
|
||||
#define mmXPB_CLG_EXTRA 0x0080
|
||||
#define mmXPB_CLG_EXTRA_BASE_IDX 0
|
||||
#define mmXPB_CLG_EXTRA_MSK 0x0081
|
||||
#define mmXPB_CLG_EXTRA_MSK_BASE_IDX 0
|
||||
#define mmXPB_LB_ADDR 0x0082
|
||||
#define mmXPB_LB_ADDR_BASE_IDX 0
|
||||
#define mmXPB_WCB_STS 0x0083
|
||||
#define mmXPB_WCB_STS_BASE_IDX 0
|
||||
#define mmXPB_HST_CFG 0x0084
|
||||
#define mmXPB_HST_CFG_BASE_IDX 0
|
||||
#define mmXPB_P2P_BAR_CFG 0x0085
|
||||
#define mmXPB_P2P_BAR_CFG_BASE_IDX 0
|
||||
#define mmXPB_P2P_BAR0 0x0086
|
||||
#define mmXPB_P2P_BAR0_BASE_IDX 0
|
||||
#define mmXPB_P2P_BAR1 0x0087
|
||||
#define mmXPB_P2P_BAR1_BASE_IDX 0
|
||||
#define mmXPB_P2P_BAR2 0x0088
|
||||
#define mmXPB_P2P_BAR2_BASE_IDX 0
|
||||
#define mmXPB_P2P_BAR3 0x0089
|
||||
#define mmXPB_P2P_BAR3_BASE_IDX 0
|
||||
#define mmXPB_P2P_BAR4 0x008a
|
||||
#define mmXPB_P2P_BAR4_BASE_IDX 0
|
||||
#define mmXPB_P2P_BAR5 0x008b
|
||||
#define mmXPB_P2P_BAR5_BASE_IDX 0
|
||||
#define mmXPB_P2P_BAR6 0x008c
|
||||
#define mmXPB_P2P_BAR6_BASE_IDX 0
|
||||
#define mmXPB_P2P_BAR7 0x008d
|
||||
#define mmXPB_P2P_BAR7_BASE_IDX 0
|
||||
#define mmXPB_P2P_BAR_SETUP 0x008e
|
||||
#define mmXPB_P2P_BAR_SETUP_BASE_IDX 0
|
||||
#define mmXPB_P2P_BAR_DELTA_ABOVE 0x0090
|
||||
#define mmXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0
|
||||
#define mmXPB_P2P_BAR_DELTA_BELOW 0x0091
|
||||
#define mmXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0
|
||||
#define mmXPB_PEER_SYS_BAR0 0x0092
|
||||
#define mmXPB_PEER_SYS_BAR0_BASE_IDX 0
|
||||
#define mmXPB_PEER_SYS_BAR1 0x0093
|
||||
#define mmXPB_PEER_SYS_BAR1_BASE_IDX 0
|
||||
#define mmXPB_PEER_SYS_BAR2 0x0094
|
||||
#define mmXPB_PEER_SYS_BAR2_BASE_IDX 0
|
||||
#define mmXPB_PEER_SYS_BAR3 0x0095
|
||||
#define mmXPB_PEER_SYS_BAR3_BASE_IDX 0
|
||||
#define mmXPB_PEER_SYS_BAR4 0x0096
|
||||
#define mmXPB_PEER_SYS_BAR4_BASE_IDX 0
|
||||
#define mmXPB_PEER_SYS_BAR5 0x0097
|
||||
#define mmXPB_PEER_SYS_BAR5_BASE_IDX 0
|
||||
#define mmXPB_PEER_SYS_BAR6 0x0098
|
||||
#define mmXPB_PEER_SYS_BAR6_BASE_IDX 0
|
||||
#define mmXPB_PEER_SYS_BAR7 0x0099
|
||||
#define mmXPB_PEER_SYS_BAR7_BASE_IDX 0
|
||||
#define mmXPB_PEER_SYS_BAR8 0x009a
|
||||
#define mmXPB_PEER_SYS_BAR8_BASE_IDX 0
|
||||
#define mmXPB_PEER_SYS_BAR9 0x009b
|
||||
#define mmXPB_PEER_SYS_BAR9_BASE_IDX 0
|
||||
#define mmXPB_XDMA_PEER_SYS_BAR0 0x009c
|
||||
#define mmXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 0
|
||||
#define mmXPB_XDMA_PEER_SYS_BAR1 0x009d
|
||||
#define mmXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 0
|
||||
#define mmXPB_XDMA_PEER_SYS_BAR2 0x009e
|
||||
#define mmXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 0
|
||||
#define mmXPB_XDMA_PEER_SYS_BAR3 0x009f
|
||||
#define mmXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 0
|
||||
#define mmXPB_CLK_GAT 0x00a0
|
||||
#define mmXPB_CLK_GAT_BASE_IDX 0
|
||||
#define mmXPB_INTF_CFG 0x00a1
|
||||
#define mmXPB_INTF_CFG_BASE_IDX 0
|
||||
#define mmXPB_INTF_STS 0x00a2
|
||||
#define mmXPB_INTF_STS_BASE_IDX 0
|
||||
#define mmXPB_PIPE_STS 0x00a3
|
||||
#define mmXPB_PIPE_STS_BASE_IDX 0
|
||||
#define mmXPB_SUB_CTRL 0x00a4
|
||||
#define mmXPB_SUB_CTRL_BASE_IDX 0
|
||||
#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB 0x00a5
|
||||
#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0
|
||||
#define mmXPB_PERF_KNOBS 0x00a6
|
||||
#define mmXPB_PERF_KNOBS_BASE_IDX 0
|
||||
#define mmXPB_STICKY 0x00a7
|
||||
#define mmXPB_STICKY_BASE_IDX 0
|
||||
#define mmXPB_STICKY_W1C 0x00a8
|
||||
#define mmXPB_STICKY_W1C_BASE_IDX 0
|
||||
#define mmXPB_MISC_CFG 0x00a9
|
||||
#define mmXPB_MISC_CFG_BASE_IDX 0
|
||||
#define mmXPB_INTF_CFG2 0x00aa
|
||||
#define mmXPB_INTF_CFG2_BASE_IDX 0
|
||||
#define mmXPB_CLG_EXTRA_RD 0x00ab
|
||||
#define mmXPB_CLG_EXTRA_RD_BASE_IDX 0
|
||||
#define mmXPB_CLG_EXTRA_MSK_RD 0x00ac
|
||||
#define mmXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0
|
||||
#define mmXPB_CLG_GFX_MATCH 0x00ad
|
||||
#define mmXPB_CLG_GFX_MATCH_BASE_IDX 0
|
||||
#define mmXPB_CLG_GFX_MATCH_MSK 0x00ae
|
||||
#define mmXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0
|
||||
#define mmXPB_CLG_MM_MATCH 0x00af
|
||||
#define mmXPB_CLG_MM_MATCH_BASE_IDX 0
|
||||
#define mmXPB_CLG_MM_MATCH_MSK 0x00b0
|
||||
#define mmXPB_CLG_MM_MATCH_MSK_BASE_IDX 0
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING0 0x00b1
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 0
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING1 0x00b2
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 0
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING2 0x00b3
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 0
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING3 0x00b4
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 0
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING4 0x00b5
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 0
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING5 0x00b6
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 0
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING6 0x00b7
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 0
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING7 0x00b8
|
||||
#define mmXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 0
|
||||
#define mmXPB_CLG_MM_UNITID_MAPPING0 0x00b9
|
||||
#define mmXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 0
|
||||
#define mmXPB_CLG_MM_UNITID_MAPPING1 0x00ba
|
||||
#define mmXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 0
|
||||
#define mmXPB_CLG_MM_UNITID_MAPPING2 0x00bb
|
||||
#define mmXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 0
|
||||
#define mmXPB_CLG_MM_UNITID_MAPPING3 0x00bc
|
||||
#define mmXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 0
|
||||
|
||||
|
||||
// addressBlock: athub_rpbdec
|
||||
// base address: 0x33b0
|
||||
#define mmRPB_PASSPW_CONF 0x00cc
|
||||
#define mmRPB_PASSPW_CONF_BASE_IDX 0
|
||||
#define mmRPB_BLOCKLEVEL_CONF 0x00cd
|
||||
#define mmRPB_BLOCKLEVEL_CONF_BASE_IDX 0
|
||||
#define mmRPB_TAG_CONF 0x00cf
|
||||
#define mmRPB_TAG_CONF_BASE_IDX 0
|
||||
#define mmRPB_EFF_CNTL 0x00d1
|
||||
#define mmRPB_EFF_CNTL_BASE_IDX 0
|
||||
#define mmRPB_ARB_CNTL 0x00d2
|
||||
#define mmRPB_ARB_CNTL_BASE_IDX 0
|
||||
#define mmRPB_ARB_CNTL2 0x00d3
|
||||
#define mmRPB_ARB_CNTL2_BASE_IDX 0
|
||||
#define mmRPB_BIF_CNTL 0x00d4
|
||||
#define mmRPB_BIF_CNTL_BASE_IDX 0
|
||||
#define mmRPB_WR_SWITCH_CNTL 0x00d5
|
||||
#define mmRPB_WR_SWITCH_CNTL_BASE_IDX 0
|
||||
#define mmRPB_RD_SWITCH_CNTL 0x00d7
|
||||
#define mmRPB_RD_SWITCH_CNTL_BASE_IDX 0
|
||||
#define mmRPB_CID_QUEUE_WR 0x00d8
|
||||
#define mmRPB_CID_QUEUE_WR_BASE_IDX 0
|
||||
#define mmRPB_CID_QUEUE_RD 0x00d9
|
||||
#define mmRPB_CID_QUEUE_RD_BASE_IDX 0
|
||||
#define mmRPB_CID_QUEUE_EX 0x00dc
|
||||
#define mmRPB_CID_QUEUE_EX_BASE_IDX 0
|
||||
#define mmRPB_CID_QUEUE_EX_DATA 0x00dd
|
||||
#define mmRPB_CID_QUEUE_EX_DATA_BASE_IDX 0
|
||||
#define mmRPB_SWITCH_CNTL2 0x00de
|
||||
#define mmRPB_SWITCH_CNTL2_BASE_IDX 0
|
||||
#define mmRPB_DEINTRLV_COMBINE_CNTL 0x00df
|
||||
#define mmRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0
|
||||
#define mmRPB_VC_SWITCH_RDWR 0x00e0
|
||||
#define mmRPB_VC_SWITCH_RDWR_BASE_IDX 0
|
||||
#define mmRPB_PERFCOUNTER_LO 0x00e1
|
||||
#define mmRPB_PERFCOUNTER_LO_BASE_IDX 0
|
||||
#define mmRPB_PERFCOUNTER_HI 0x00e2
|
||||
#define mmRPB_PERFCOUNTER_HI_BASE_IDX 0
|
||||
#define mmRPB_PERFCOUNTER0_CFG 0x00e3
|
||||
#define mmRPB_PERFCOUNTER0_CFG_BASE_IDX 0
|
||||
#define mmRPB_PERFCOUNTER1_CFG 0x00e4
|
||||
#define mmRPB_PERFCOUNTER1_CFG_BASE_IDX 0
|
||||
#define mmRPB_PERFCOUNTER2_CFG 0x00e5
|
||||
#define mmRPB_PERFCOUNTER2_CFG_BASE_IDX 0
|
||||
#define mmRPB_PERFCOUNTER3_CFG 0x00e6
|
||||
#define mmRPB_PERFCOUNTER3_CFG_BASE_IDX 0
|
||||
#define mmRPB_PERFCOUNTER_RSLT_CNTL 0x00e7
|
||||
#define mmRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
|
||||
#define mmRPB_RD_QUEUE_CNTL 0x00e9
|
||||
#define mmRPB_RD_QUEUE_CNTL_BASE_IDX 0
|
||||
#define mmRPB_RD_QUEUE_CNTL2 0x00ea
|
||||
#define mmRPB_RD_QUEUE_CNTL2_BASE_IDX 0
|
||||
#define mmRPB_WR_QUEUE_CNTL 0x00eb
|
||||
#define mmRPB_WR_QUEUE_CNTL_BASE_IDX 0
|
||||
#define mmRPB_WR_QUEUE_CNTL2 0x00ec
|
||||
#define mmRPB_WR_QUEUE_CNTL2_BASE_IDX 0
|
||||
#define mmRPB_EA_QUEUE_WR 0x00ed
|
||||
#define mmRPB_EA_QUEUE_WR_BASE_IDX 0
|
||||
#define mmRPB_ATS_CNTL 0x00ee
|
||||
#define mmRPB_ATS_CNTL_BASE_IDX 0
|
||||
#define mmRPB_ATS_CNTL2 0x00ef
|
||||
#define mmRPB_ATS_CNTL2_BASE_IDX 0
|
||||
#define mmRPB_SDPPORT_CNTL 0x00f0
|
||||
#define mmRPB_SDPPORT_CNTL_BASE_IDX 0
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+22484
File diff suppressed because it is too large
Load Diff
+21106
File diff suppressed because it is too large
Load Diff
+22544
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user