2.9.6-1
Add support for CUDA graphs.
Fuse BCM Gen4 switches to avoid suboptimal performance on some platforms. Issue #439.
Fix bootstrap issue caused by connection reordering.
Fix CPU locking block.
Improve CollNet algorithm.
Improve performance on DGX A100 for communicators with only one GPU per node.
[ROCm/rccl commit: a46ea10583]
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@@ -4,7 +4,7 @@
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* Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
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* Copyright (c) 2005 PathScale, Inc. All rights reserved.
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*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2015-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* See LICENSE.txt for license information
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************************************************************************/
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@@ -1089,7 +1089,7 @@ static inline int ibv_post_send(struct ibv_qp *qp, struct ibv_send_wr *wr, struc
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static inline ncclResult_t wrap_ibv_post_send(struct ibv_qp *qp, struct ibv_send_wr *wr, struct ibv_send_wr **bad_wr) {
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int ret = qp->context->ops.post_send(qp, wr, bad_wr); /*returns 0 on success, or the value of errno on failure (which indicates the failure reason)*/
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if (ret != IBV_SUCCESS) {
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WARN("ibv_post_send() failed with error %s", strerror(ret));
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WARN("ibv_post_send() failed with error %s, Bad WR %p, First WR %p", strerror(ret), wr, *bad_wr);
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return ncclSystemError;
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}
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return ncclSuccess;
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