From 219cc0d16a52a999869d00cc9251e0593d3fdf81 Mon Sep 17 00:00:00 2001 From: coleramos425 Date: Mon, 15 Jan 2024 17:07:08 -0600 Subject: [PATCH] Update config files for new l2 cache per channel structure and general counter updates Co-authored-by: fei.zheng Signed-off-by: coleramos425 [ROCm/rocprofiler-compute commit: 19ad88a04e58c565a4b0e1149225fa59f893f38b] --- .../gfx908/0300_mem_chart.yaml | 313 +++ .../1000_compute-unit-instruction-mix.yaml | 6 +- .../1100_compute-unit-compute-pipeline.yaml | 4 +- .../analysis_configs/gfx908/1200_lds.yaml | 4 +- .../gfx908/1300_instruction-cache.yaml | 4 +- .../gfx908/1400_constant-cache.yaml | 4 +- .../gfx908/1600_L1_cache.yaml | 4 +- .../gfx908/1700_L2_cache.yaml | 6 +- .../gfx908/1800_L2_cache_per_channel.yaml | 2286 ++--------------- .../gfx908/1900_memory_chart.yaml | 259 -- .../gfx90a/0300_mem_chart.yaml | 313 +++ .../gfx90a/0400_roofline_chart.yaml | 11 + .../1000_compute-unit-instruction-mix.yaml | 6 +- .../1100_compute-unit-compute-pipeline.yaml | 2 +- .../analysis_configs/gfx90a/1200_lds.yaml | 4 +- .../gfx90a/1300_instruction-cache.yaml | 4 +- .../gfx90a/1400_constant-cache.yaml | 4 +- .../gfx90a/1600_L1_cache.yaml | 6 +- .../gfx90a/1700_L2_cache.yaml | 6 +- .../gfx90a/1800_L2_cache_per_channel.yaml | 2151 ++-------------- .../gfx90a/1900_memory_chart.yaml | 259 -- 21 files changed, 990 insertions(+), 4666 deletions(-) create mode 100644 projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/0300_mem_chart.yaml delete mode 100644 projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1900_memory_chart.yaml create mode 100644 projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/0300_mem_chart.yaml create mode 100644 projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/0400_roofline_chart.yaml delete mode 100644 projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1900_memory_chart.yaml diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/0300_mem_chart.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/0300_mem_chart.yaml new file mode 100644 index 0000000000..acdc18c56c --- /dev/null +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/0300_mem_chart.yaml @@ -0,0 +1,313 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 300 + title: Memory Chart + data source: + - metric_table: + id: 301 + header: + metric: Metric + #alias: #alias + value: Value + tips: Tips + metric: + # ---------------------------------------- + # Instr Buff Block + + #TODO: double check wave_occupancy + Wavefront Occupancy: + #alias: wave_occ_ + value: ROUND(AVG((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE) / $numActiveCUs), 0) + coll_level: SQ_LEVEL_WAVES + tips: + Wave Life: + #alias: wave_life_ + value: ROUND(AVG(((4 * (SQ_WAVE_CYCLES / SQ_WAVES)) if (SQ_WAVES != 0) else 0)), 0) + tips: + + # ---------------------------------------- + # Instr Dispatch Block + SALU: + #alias: salu_ + value: ROUND(AVG((SQ_INSTS_SALU / $denom)), 0) + tips: + SMEM: + #alias: smem_ + value: ROUND(AVG((SQ_INSTS_SMEM / $denom)), 0) + tips: + VALU: + #alias: valu_ + value: ROUND(AVG((SQ_INSTS_VALU / $denom)), 0) + tips: + MFMA: + #alias: mfma_ + value: ROUND(AVG((SQ_INSTS_MFMA / $denom)), 0) + tips: + VMEM: + #alias: vmem_ + value: ROUND(AVG((SQ_INSTS_VMEM / $denom)), 0) + tips: + LDS: + #alias: lds_ + value: ROUND(AVG((SQ_INSTS_LDS / $denom)), 0) + tips: + GWS: + #alias: gws_ + value: ROUND(AVG((SQ_INSTS_GDS / $denom)), 0) + tips: + BR: + #alias: br_ + value: ROUND(AVG((SQ_INSTS_BRANCH / $denom)), 0) + tips: + + # ---------------------------------------- + # Exec Block + Active CUs: + #alias: active_cu_ + value: $numActiveCUs + tips: + Num CUs: + #alias: num_cu_ + value: $numCU + tips: + VGPR: + #alias: vgpr_ + value: ROUND(AVG(vgpr), 0) + tips: + SGPR: + #alias: sgpr_ + value: ROUND(AVG(sgpr), 0) + tips: + LDS Allocation: + #alias: lds_alloc_ + value: ROUND(AVG(lds), 0) + tips: + Scratch Allocation: + #alias: scratch_alloc_ + value: ROUND(AVG(scr), 0) + tips: + Wavefronts: + #alias: wavefronts_ + value: ROUND(AVG(SPI_CSN_WAVE), 0) + tips: + Workgroups: + #alias: workgroups_ + value: ROUND(AVG(SPI_CSN_NUM_THREADGROUPS), 0) + tips: + + # ---------------------------------------- + # LDS Block + LDS Req: + #alias: lds_req_ + value: ROUND(AVG((SQ_INSTS_LDS / $denom)), 0) + tips: + LDS Util: + #alias: lds_util_ + value: + ROUND(AVG(((100 * SQ_LDS_IDX_ACTIVE) / (GRBM_GUI_ACTIVE * $numCU))), + 0) + tips: + LDS Latency: + #alias: lds_lat + value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)),0) + coll_level: SQ_INST_LEVEL_LDS + tips: + + # ---------------------------------------- + # Vector L1 Cache Block + VL1 Rd: + #alias: vl1_rd_ + value: ROUND(AVG((TCP_TOTAL_READ_sum / $denom)), 0) + tips: + VL1 Wr: + #alias: vl1_wr_ + value: ROUND(AVG((TCP_TOTAL_WRITE_sum / $denom)), 0) + tips: + VL1 Atomic: + #alias: vl1_atom_ + value: + ROUND(AVG(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) + / $denom)), 0) + tips: + + VL1 Hit: + #alias: vl1_hit_ + value: + ROUND(AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None )), 0) + tips: + VL1 Lat: + #alias: vl1_lat_ + value: + ROUND(AVG(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum + != 0) else None)), 0) + tips: + VL1 Coalesce: + #alias: vl1_coales_ + value: + ROUND(AVG(((((TA_TOTAL_WAVEFRONTS_sum * 64) * 100) / (TCP_TOTAL_ACCESSES_sum + * 4)) if (TCP_TOTAL_ACCESSES_sum != None) else 0)), 0) + tips: + VL1 Stall: + #alias: vl1_stall_ + value: + ROUND(AVG((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)), 0) + tips: + + VL1_L2 Rd: + #alias: vl1_l2_rd_ + value: ROUND(AVG((TCP_TCC_READ_REQ_sum / $denom)), 0) + tips: + VL1_L2 Wr: + #alias: vl1_l2_wr_ + value: ROUND(AVG((TCP_TCC_WRITE_REQ_sum / $denom)), 0) + tips: + VL1_L2 Atomic: + #alias: vl1_l2_atom_ + value: + ROUND(AVG(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + / $denom)), 0) + tips: + + # ---------------------------------------- + # Scalar L1D Cache Block + VL1D Rd: + #alias: sl1_rd_ + value: ROUND(AVG((SQC_DCACHE_REQ / $denom)), 0) + tips: + VL1D Hit: + #alias: sl1_hit_ + value: + ROUND((AVG(((SQC_DCACHE_HITS / SQC_DCACHE_REQ) if (SQC_DCACHE_REQ != + 0) else None)) * 100), 0) + tips: + VL1D Lat: + #alias: sl1_lat_ + value: + ROUND((AVG(((SQ_ACCUM_PREV_HIRES / SQC_DCACHE_REQ) if (SQC_DCACHE_REQ != + 0) else None)) * 100), 0) + coll_level: SQC_DCACHE_INFLIGHT_LEVEL + tips: + + VL1D_L2 Rd: + #alias: sl1_l2_rd_ + value: ROUND(AVG((SQC_TC_DATA_READ_REQ / $denom)), 0) + tips: + VL1D_L2 Wr: + #alias: sl1_l2_wr_ + value: ROUND(AVG((SQC_TC_DATA_WRITE_REQ / $denom)), 0) + tips: + VL1D_L2 Atomic: + #alias: sl1_l2_atom_ + value: ROUND(AVG((SQC_TC_DATA_ATOMIC_REQ / $denom)), 0) + tips: + + # ---------------------------------------- + # Instr L1 Cache Block + IL1 Fetch: + #alias: il1_fetch_ + value: ROUND(AVG((SQC_ICACHE_REQ / $denom)), 0) + tips: + IL1 Hit: + #alias: il1_hit_ + value: ROUND((AVG((SQC_ICACHE_HITS / SQC_ICACHE_REQ)) * 100), 0) + tips: + IL1 Lat: + #alias: il1_lat_ + value: + ROUND((AVG(((SQ_ACCUM_PREV_HIRES / SQC_ICACHE_REQ) if (SQC_ICACHE_REQ != + 0) else None)) * 100), 0) + tips: # ??? coll_level: SQ_IFETCH_LEVEL + IL1_L2 Rd: + #alias: il1_l2_req_ + value: ROUND(AVG((SQC_TC_INST_REQ / $denom)), 0) + tips: + + # ---------------------------------------- + # L2 Cache Block(inside) + L2 Rd: + #alias: l2_rd_ + value: ROUND(AVG((TCC_READ_sum / $denom)), 0) + tips: + L2 Wr: + #alias: l2_wr_ + value: ROUND(AVG((TCC_WRITE_sum / $denom)), 0) + tips: + L2 Atomic: + #alias: l2_atom_ + value: ROUND(AVG((TCC_ATOMIC_sum / $denom)), 0) + tips: + L2 Hit: + #alias: l2_hit_ + value: + ROUND(AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else 0)), 0) + tips: + L2 Rd Lat: + #alias: l2_rd_lat_ + value: + ROUND(AVG(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) + if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)), + 0) + tips: + L2 Wr Lat: + #alias: l2_wr_lat_ + value: + ROUND(AVG(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + != 0) else None)), 0) + tips: + + # ---------------------------------------- + # Fabric Block + Fabric_L2 Rd: + #alias: l2_fabric_rd_ + value: ROUND(AVG((TCC_EA_RDREQ_sum / $denom)), 0) + tips: + Fabric_L2 Wr: + #alias: l2_fabric_wr_ + value: ROUND(AVG((TCC_EA_WRREQ_sum / $denom)), 0) + tips: + Fabric_L2 Atomic: + #alias: l2_fabric_atom_ + value: ROUND(AVG((TCC_EA_ATOMIC_sum / $denom)), 0) + tips: + + Fabric Rd Lat: + #alias: fabric_rd_lat_ + value: + ROUND(AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum + != 0) else 0)), 0) + tips: + Fabric Wr Lat: + #alias: fabric_wr_lat_ + value: + ROUND(AVG(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum + != 0) else 0)), 0) + tips: + Fabric Atomic Lat: + #alias: fabric_atom_lat_ + value: + ROUND(AVG(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum + != 0) else 0)), 0) + tips: + + HBM Rd: + #alias: hbm_rd_ + value: ROUND(AVG((TCC_EA_RDREQ_DRAM_sum / $denom)), 0) + tips: + HBM Wr: + #alias: hbm_wr_ + value: ROUND(AVG((TCC_EA_WRREQ_DRAM_sum / $denom)), 0) + tips: + + comparable: false # for now + cli_style: mem_chart \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1000_compute-unit-instruction-mix.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1000_compute-unit-instruction-mix.yaml index 13c27dd209..4d8f36a237 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1000_compute-unit-instruction-mix.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1000_compute-unit-instruction-mix.yaml @@ -18,7 +18,7 @@ Panel Config: max: Max unit: Unit tips: Tips - style: + cli_style: type: simple_bar label_txt: (# of instr + $normUnit) metric: @@ -81,7 +81,7 @@ Panel Config: max: Max unit: Unit tips: Tips - style: + cli_style: type: simple_bar label_txt: (# of instr + $normUnit) metric: @@ -231,4 +231,4 @@ Panel Config: tips: MFMA-F64: count: None # No HW module - tips: + tips: \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1100_compute-unit-compute-pipeline.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1100_compute-unit-compute-pipeline.yaml index 061311d62d..8e749cf3da 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1100_compute-unit-compute-pipeline.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1100_compute-unit-compute-pipeline.yaml @@ -15,7 +15,7 @@ Panel Config: metric: Metric value: Value tips: Tips - style: + cli_style: type: simple_bar range_color: [1, 100] label_txt: (%) @@ -152,4 +152,4 @@ Panel Config: unit: (OPs + $normUnit) tips: - + \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1200_lds.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1200_lds.yaml index 3fd52c3b1b..f720bfb84b 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1200_lds.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1200_lds.yaml @@ -16,7 +16,7 @@ Panel Config: value: Value unit: Unit tips: Tips - style: + cli_style: type: simple_bar range_color: [1, 100] label_txt: (%) @@ -118,4 +118,4 @@ Panel Config: max: MAX(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)) unit: Cycles coll_level: SQ_INST_LEVEL_LDS - tips: + tips: \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1300_instruction-cache.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1300_instruction-cache.yaml index 05dc759803..17ca1c0716 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1300_instruction-cache.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1300_instruction-cache.yaml @@ -16,7 +16,7 @@ Panel Config: value: Value unit: Unit tips: Tips - style: + cli_style: type: simple_bar range_color: [1, 100] label_txt: (%) @@ -76,4 +76,4 @@ Panel Config: max: MAX(((100 * SQC_ICACHE_HITS) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + SQC_ICACHE_MISSES_DUPLICATE))) unit: pct - tips: + tips: \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1400_constant-cache.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1400_constant-cache.yaml index 563caad13f..4d4a6c8c95 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1400_constant-cache.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1400_constant-cache.yaml @@ -16,7 +16,7 @@ Panel Config: value: Value unit: Unit tips: Tips - style: + cli_style: type: simple_bar range_color: [1, 100] label_txt: (%) @@ -161,4 +161,4 @@ Panel Config: min: MIN((SQC_TC_STALL / $denom)) max: MAX((SQC_TC_STALL / $denom)) unit: (Cycles + $normUnit) - tips: + tips: \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1600_L1_cache.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1600_L1_cache.yaml index cac92b1f2b..a476dc3523 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1600_L1_cache.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1600_L1_cache.yaml @@ -16,7 +16,7 @@ Panel Config: value: Value unit: Unit tips: Tips - style: + cli_style: type: simple_bar range_color: [1, 100] label_txt: (%) @@ -258,7 +258,7 @@ Panel Config: max: Max unit: Unit tips: Tips - style: + cli_style: type: simple_multi_bar metric: NC - Read: diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1700_L2_cache.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1700_L2_cache.yaml index 0c7b03811a..42245be4b2 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1700_L2_cache.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1700_L2_cache.yaml @@ -16,7 +16,7 @@ Panel Config: value: Value unit: Unit tips: Tips - style: + cli_style: type: simple_bar metric: L2 Util: @@ -303,7 +303,7 @@ Panel Config: max: Max unit: Unit tips: Tips - style: + cli_style: type: simple_multi_bar metric: Read - Remote Socket Stall: @@ -361,4 +361,4 @@ Panel Config: min: MIN((TCC_TOO_MANY_EA_WRREQS_STALL_sum / $denom)) max: MAX((TCC_TOO_MANY_EA_WRREQS_STALL_sum / $denom)) unit: (Req + $normUnit) - tips: + tips: \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1800_L2_cache_per_channel.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1800_L2_cache_per_channel.yaml index 45f8abb413..117b8e0a87 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1800_L2_cache_per_channel.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1800_L2_cache_per_channel.yaml @@ -167,2131 +167,169 @@ Panel Config: + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31])) != 0) else None)) unit: pct tips: - Req: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) - + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) - + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) - + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) - + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) - + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) - + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) - + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) - + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) - + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) - + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) - + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) - + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) - + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) - + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) - + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) - + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) - + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) - + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) - + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) - + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) - + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) - + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) - + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) - + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) - + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) - + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) - + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) - + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) - + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) - + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) - + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) - + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) - unit: (Req + $normUnit) - tips: - L1 - L2 Read Req: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) - + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) - + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) - + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + - TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) - + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + - TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) - + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + - TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) - + TO_INT(TCC_READ[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) - + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) - + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) - + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + - TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) - + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + - TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) - + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + - TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) - + TO_INT(TCC_READ[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) - + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) - + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) - + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + - TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) - + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + - TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) - + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + - TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) - + TO_INT(TCC_READ[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) - + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) - + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) - + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + - TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) - + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + - TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) - + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + - TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) - + TO_INT(TCC_READ[31])) / 32) / $denom)) - unit: (Req + $normUnit) - tips: - L1 - L2 Write Req: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) - + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + - TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) - + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) - + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) - + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) - + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) - + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) - + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) - + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) - + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) - + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + - TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) - + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) - + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) - + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) - + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) - + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) - + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) - + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) - + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) - + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + - TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) - + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) - + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) - + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) - + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) - + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) - + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) - + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) - + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) - + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + - TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) - + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) - + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) - + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) - + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) - + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) - + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) - + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) - + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) - unit: (Req + $normUnit) - tips: - L1 - L2 Atomic Req: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) - + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) - + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) - + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) - + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) - + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) - + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) - + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) - + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) - + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) - + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) - / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) - + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) - + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) - + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) - + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) - + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) - + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) - + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) - + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) - + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) - + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) - / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) - + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) - + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) - + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) - + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) - + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) - + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) - + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) - + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) - + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) - + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) - / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) - + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) - + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) - + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) - + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) - + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) - + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) - + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) - + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) - + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) - + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) - / 32) / $denom)) - unit: (Req + $normUnit) - tips: - L2 - EA Read Req: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) - + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) - + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) - + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) - + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) - + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) - + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) - + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) - + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) - + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) - + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) - / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) - + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) - + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) - + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) - + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) - + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) - + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) - + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) - + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) - + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) - + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) - / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) - + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) - + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) - + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) - + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) - + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) - + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) - + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) - + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) - + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) - + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) - / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) - + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) - + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) - + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) - + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) - + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) - + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) - + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) - + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) - + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) - + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) - / 32) / $denom)) - unit: (Req + $normUnit) - tips: - L2 - EA Write Req: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) - + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) - + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) - + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) - + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) - + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) - + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) - + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) - + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) - + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) - + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) - / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) - + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) - + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) - + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) - + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) - + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) - + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) - + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) - + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) - + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) - + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) - / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) - + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) - + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) - + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) - + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) - + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) - + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) - + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) - + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) - + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) - + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) - / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) - + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) - + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) - + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) - + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) - + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) - + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) - + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) - + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) - + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) - + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) - / 32) / $denom)) - unit: (Req + $normUnit) - tips: - L2 - EA Atomic Req: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) - + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) - + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) - + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) - + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) - + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) - + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) - + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) - + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) - + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) - + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) - / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) - + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) - + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) - + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) - + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) - + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) - + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) - + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) - + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) - + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) - + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) - / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) - + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) - + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) - + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) - + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) - + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) - + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) - + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) - + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) - + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) - + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) - / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) - + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) - + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) - + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) - + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) - + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) - + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) - + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) - + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) - + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) - + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) - / 32) / $denom)) - unit: (Req + $normUnit) - tips: - L2 - EA Read Lat: - avg: AVG((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) - + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) - + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) - + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) - + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) - + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) - + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) - + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) - + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) - + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) - + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) - + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) - + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) - + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) - + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) - + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) - + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) - + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) - + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + - TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) - + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) - + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) - + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) - + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) - + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) - + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) - + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) - std dev: STD((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) - + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) - + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) - + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) - + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) - + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) - + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) - + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) - + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) - + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) - + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) - + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) - + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) - + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) - + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) - + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) - + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) - + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) - + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + - TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) - + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) - + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) - + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) - + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) - + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) - + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) - + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) - min: MIN((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) - + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) - + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) - + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) - + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) - + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) - + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) - + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) - + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) - + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) - + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) - + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) - + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) - + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) - + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) - + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) - + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) - + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) - + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + - TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) - + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) - + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) - + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) - + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) - + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) - + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) - + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) - max: MAX((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) - + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) - + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) - + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) - + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) - + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) - + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) - + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) - + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) - + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) - + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) - + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) - + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) - + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) - + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) - + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) - + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) - + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) - + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + - TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) - + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) - + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) - + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) - + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) - + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) - + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) - + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) - unit: Cycles - tips: - L2 - EA Write Lat: - avg: AVG((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) - + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) - + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) - + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) - + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) - + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) - + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) - + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) - + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) - + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) - + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) - + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) - + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) - + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) - + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) - + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) - + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) - + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) - + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + - TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) - + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) - + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) - + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) - + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) - + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) - + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) - + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) - std dev: STD((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) - + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) - + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) - + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) - + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) - + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) - + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) - + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) - + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) - + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) - + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) - + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) - + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) - + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) - + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) - + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) - + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) - + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) - + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + - TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) - + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) - + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) - + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) - + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) - + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) - + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) - + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) - min: MIN((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) - + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) - + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) - + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) - + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) - + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) - + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) - + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) - + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) - + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) - + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) - + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) - + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) - + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) - + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) - + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) - + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) - + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) - + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + - TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) - + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) - + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) - + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) - + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) - + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) - + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) - + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) - max: MAX((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) - + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) - + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) - + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) - + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) - + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) - + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) - + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) - + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) - + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) - + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) - + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) - + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) - + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) - + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) - + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) - + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) - + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) - + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + - TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) - + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) - + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) - + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) - + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) - + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) - + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) - + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) - unit: Cycles - tips: - L2 - EA Atomic Lat: - avg: AVG((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) - + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) - + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) - + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) - + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) - + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) - + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) - + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) - + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) - + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) - + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) - + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) - + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) - + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) - + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) - + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) - + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) - + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) - + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] - + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) - + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) - + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) - + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) - + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) - + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) - + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) - + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else - None)) - std dev: STD((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) - + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) - + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) - + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) - + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) - + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) - + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) - + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) - + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) - + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) - + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) - + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) - + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) - + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) - + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) - + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) - + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) - + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) - + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] - + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) - + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) - + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) - + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) - + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) - + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) - + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) - + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else - None)) - min: MIN((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) - + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) - + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) - + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) - + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) - + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) - + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) - + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) - + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) - + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) - + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) - + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) - + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) - + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) - + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) - + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) - + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) - + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) - + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] - + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) - + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) - + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) - + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) - + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) - + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) - + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) - + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else - None)) - max: MAX((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) - + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) - + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) - + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) - + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) - + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) - + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) - + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) - + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) - + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) - + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) - + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) - + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) - + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) - + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) - + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) - + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) - + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) - + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] - + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) - + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) - + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) - + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) - + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) - + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) - + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) - + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else - None)) - unit: Cycles - tips: - L2 - EA Read Stall (IO): - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - unit: (Cycles + $normUnit) - tips: - L2 - EA Read Stall (GMI): - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - unit: (Cycles + $normUnit) - tips: - L2 - EA Read Stall (DRAM): - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - unit: (Cycles + $normUnit) - tips: - L2 - EA Write Stall (IO): - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - unit: (Cycles + $normUnit) - tips: - L2 - EA Write Stall (GMI): - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - unit: (Cycles + $normUnit) - tips: - L2 - EA Write Stall (DRAM): - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - unit: (Cycles + $normUnit) - tips: - L2 - EA Write Starve: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) - unit: (Cycles + $normUnit) - tips: - - metric_table: - id: 1802 - title: Channel 0-15 - columnwise: True - header: - channel: Channel - hit rate: L2 Cache Hit Rate (%) - req: Requests (Requests) - read req: L1-L2 Read (Requests) - write req: L1-L2 Write (Requests) - atomic req: L1-L2 Atomic (Requests) - ea read req: L2-EA Read (Requests) - ea write req: L2-EA Write (Requests) - ea atomic req: L2-EA Atomic (Requests) - ea read lat - cycles: L2-EA Read Latency (Cycles) - ea write lat - cycles: L2-EA Write Latency (Cycles) - ea atomic lat - cycles: L2-EA Atomic Latency (Cycles) - ea read stall - io: L2-EA Read Stall - IO (Cycles per) - ea read stall - gmi: L2-EA Read Stall - GMI (Cycles per) - ea read stall - dram: L2-EA Read Stall - DRAM (Cycles per) - ea write stall - io: L2-EA Write Stall - IO (Cycles per) - ea write stall - gmi: L2-EA Write Stall - GMI (Cycles per) - ea write stall - dram: L2-EA Write Stall - DRAM (Cycles per) - ea write stall - starve: L2-EA Write Stall - Starve (Cycles per) - tips: Tips - metric: - "0": - hit rate: - AVG((((100 * TCC_HIT[0]) / (TCC_HIT[0] + TCC_MISS[0])) if ((TCC_HIT[0] - + TCC_MISS[0]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[0]) / $denom)) - read req: AVG((TO_INT(TCC_READ[0]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[0]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[0]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[0]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[0]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[0]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[0] / TCC_EA_RDREQ[0]) if (TCC_EA_RDREQ[0] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[0] / TCC_EA_WRREQ[0]) if (TCC_EA_WRREQ[0] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[0] / TCC_EA_ATOMIC[0]) if - (TCC_EA_ATOMIC[0] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) / $denom)) - tips: - "1": - hit rate: - AVG((((100 * TCC_HIT[1]) / (TCC_HIT[1] + TCC_MISS[1])) if ((TCC_HIT[1] - + TCC_MISS[1]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[1]) / $denom)) - read req: AVG((TO_INT(TCC_READ[1]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[1]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[1]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[1]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[1]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[1]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[1] / TCC_EA_RDREQ[1]) if (TCC_EA_RDREQ[1] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[1] / TCC_EA_WRREQ[1]) if (TCC_EA_WRREQ[1] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[1] / TCC_EA_ATOMIC[1]) if - (TCC_EA_ATOMIC[1] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1]) / $denom)) - tips: - "2": - hit rate: - AVG((((100 * TCC_HIT[2]) / (TCC_HIT[2] + TCC_MISS[2])) if ((TCC_HIT[2] - + TCC_MISS[2]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[2]) / $denom)) - read req: AVG((TO_INT(TCC_READ[2]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[2]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[2]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[2]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[2]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[2]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[2] / TCC_EA_RDREQ[2]) if (TCC_EA_RDREQ[2] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[2] / TCC_EA_WRREQ[2]) if (TCC_EA_WRREQ[2] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[2] / TCC_EA_ATOMIC[2]) if - (TCC_EA_ATOMIC[2] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2]) / $denom)) - tips: - "3": - hit rate: - AVG((((100 * TCC_HIT[3]) / (TCC_HIT[3] + TCC_MISS[3])) if ((TCC_HIT[3] - + TCC_MISS[3]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[3]) / $denom)) - read req: AVG((TO_INT(TCC_READ[3]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[3]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[3]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[3]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[3]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[3]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[3] / TCC_EA_RDREQ[3]) if (TCC_EA_RDREQ[3] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[3] / TCC_EA_WRREQ[3]) if (TCC_EA_WRREQ[3] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[3] / TCC_EA_ATOMIC[3]) if - (TCC_EA_ATOMIC[3] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3]) / $denom)) - tips: - "4": - hit rate: - AVG((((100 * TCC_HIT[4]) / (TCC_HIT[4] + TCC_MISS[4])) if ((TCC_HIT[4] - + TCC_MISS[4]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[4]) / $denom)) - read req: AVG((TO_INT(TCC_READ[4]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[4]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[4]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[4]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[4]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[4]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[4] / TCC_EA_RDREQ[4]) if (TCC_EA_RDREQ[4] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[4] / TCC_EA_WRREQ[4]) if (TCC_EA_WRREQ[4] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[4] / TCC_EA_ATOMIC[4]) if - (TCC_EA_ATOMIC[4] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4]) / $denom)) - tips: - "5": - hit rate: - AVG((((100 * TCC_HIT[5]) / (TCC_HIT[5] + TCC_MISS[5])) if ((TCC_HIT[5] - + TCC_MISS[5]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[5]) / $denom)) - read req: AVG((TO_INT(TCC_READ[5]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[5]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[5]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[5]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[5]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[5]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[5] / TCC_EA_RDREQ[5]) if (TCC_EA_RDREQ[5] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[5] / TCC_EA_WRREQ[5]) if (TCC_EA_WRREQ[5] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[5] / TCC_EA_ATOMIC[5]) if - (TCC_EA_ATOMIC[5] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5]) / $denom)) - tips: - "6": - hit rate: - AVG((((100 * TCC_HIT[6]) / (TCC_HIT[6] + TCC_MISS[6])) if ((TCC_HIT[6] - + TCC_MISS[6]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[6]) / $denom)) - read req: AVG((TO_INT(TCC_READ[6]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[6]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[6]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[6]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[6]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[6]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[6] / TCC_EA_RDREQ[6]) if (TCC_EA_RDREQ[6] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[6] / TCC_EA_WRREQ[6]) if (TCC_EA_WRREQ[6] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[6] / TCC_EA_ATOMIC[6]) if - (TCC_EA_ATOMIC[6] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6]) / $denom)) - tips: - "7": - hit rate: - AVG((((100 * TCC_HIT[7]) / (TCC_HIT[7] + TCC_MISS[7])) if ((TCC_HIT[7] - + TCC_MISS[7]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[7]) / $denom)) - read req: AVG((TO_INT(TCC_READ[7]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[7]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[7]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[7]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[7]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[7]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[7] / TCC_EA_RDREQ[7]) if (TCC_EA_RDREQ[7] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[7] / TCC_EA_WRREQ[7]) if (TCC_EA_WRREQ[7] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[7] / TCC_EA_ATOMIC[7]) if - (TCC_EA_ATOMIC[7] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7]) / $denom)) - tips: - "8": - hit rate: - AVG((((100 * TCC_HIT[8]) / (TCC_HIT[8] + TCC_MISS[8])) if ((TCC_HIT[8] - + TCC_MISS[8]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[8]) / $denom)) - read req: AVG((TO_INT(TCC_READ[8]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[8]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[8]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[8]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[8]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[8]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[8] / TCC_EA_RDREQ[8]) if (TCC_EA_RDREQ[8] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[8] / TCC_EA_WRREQ[8]) if (TCC_EA_WRREQ[8] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[8] / TCC_EA_ATOMIC[8]) if - (TCC_EA_ATOMIC[8] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8]) / $denom)) - tips: - "9": - hit rate: - AVG((((100 * TCC_HIT[9]) / (TCC_HIT[9] + TCC_MISS[9])) if ((TCC_HIT[9] - + TCC_MISS[9]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[9]) / $denom)) - read req: AVG((TO_INT(TCC_READ[9]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[9]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[9]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[9]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[9]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[9]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[9] / TCC_EA_RDREQ[9]) if (TCC_EA_RDREQ[9] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[9] / TCC_EA_WRREQ[9]) if (TCC_EA_WRREQ[9] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[9] / TCC_EA_ATOMIC[9]) if - (TCC_EA_ATOMIC[9] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9]) / $denom)) - tips: - "10": - hit rate: - AVG((((100 * TCC_HIT[10]) / (TCC_HIT[10] + TCC_MISS[10])) if ((TCC_HIT[10] - + TCC_MISS[10]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[10]) / $denom)) - read req: AVG((TO_INT(TCC_READ[10]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[10]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[10]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[10]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[10]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[10]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[10] / TCC_EA_RDREQ[10]) if (TCC_EA_RDREQ[10] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[10] / TCC_EA_WRREQ[10]) if (TCC_EA_WRREQ[10] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[10] / TCC_EA_ATOMIC[10]) if - (TCC_EA_ATOMIC[10] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10]) / $denom)) - tips: - "11": - hit rate: - AVG((((100 * TCC_HIT[11]) / (TCC_HIT[11] + TCC_MISS[11])) if ((TCC_HIT[11] - + TCC_MISS[11]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[11]) / $denom)) - read req: AVG((TO_INT(TCC_READ[11]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[11]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[11]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[11]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[11]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[11]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[11] / TCC_EA_RDREQ[11]) if (TCC_EA_RDREQ[11] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[11] / TCC_EA_WRREQ[11]) if (TCC_EA_WRREQ[11] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[11] / TCC_EA_ATOMIC[11]) if - (TCC_EA_ATOMIC[11] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11]) / $denom)) - tips: - "12": - hit rate: - AVG((((100 * TCC_HIT[12]) / (TCC_HIT[12] + TCC_MISS[12])) if ((TCC_HIT[12] - + TCC_MISS[12]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[12]) / $denom)) - read req: AVG((TO_INT(TCC_READ[12]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[12]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[12]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[12]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[12]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[12]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[12] / TCC_EA_RDREQ[12]) if (TCC_EA_RDREQ[12] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[12] / TCC_EA_WRREQ[12]) if (TCC_EA_WRREQ[12] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[12] / TCC_EA_ATOMIC[12]) if - (TCC_EA_ATOMIC[12] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12]) / $denom)) - tips: - "13": - hit rate: - AVG((((100 * TCC_HIT[13]) / (TCC_HIT[13] + TCC_MISS[13])) if ((TCC_HIT[13] - + TCC_MISS[13]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[13]) / $denom)) - read req: AVG((TO_INT(TCC_READ[13]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[13]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[13]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[13]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[13]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[13]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[13] / TCC_EA_RDREQ[13]) if (TCC_EA_RDREQ[13] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[13] / TCC_EA_WRREQ[13]) if (TCC_EA_WRREQ[13] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[13] / TCC_EA_ATOMIC[13]) if - (TCC_EA_ATOMIC[13] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13]) / $denom)) - tips: - "14": - hit rate: - AVG((((100 * TCC_HIT[14]) / (TCC_HIT[14] + TCC_MISS[14])) if ((TCC_HIT[14] - + TCC_MISS[14]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[14]) / $denom)) - read req: AVG((TO_INT(TCC_READ[14]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[14]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[14]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[14]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[14]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[14]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[14] / TCC_EA_RDREQ[14]) if (TCC_EA_RDREQ[14] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[14] / TCC_EA_WRREQ[14]) if (TCC_EA_WRREQ[14] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[14] / TCC_EA_ATOMIC[14]) if - (TCC_EA_ATOMIC[14] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14]) / $denom)) - tips: - "15": - hit rate: - AVG((((100 * TCC_HIT[15]) / (TCC_HIT[15] + TCC_MISS[15])) if ((TCC_HIT[15] - + TCC_MISS[15]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[15]) / $denom)) - read req: AVG((TO_INT(TCC_READ[15]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[15]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[15]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[15]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[15]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[15]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[15] / TCC_EA_RDREQ[15]) if (TCC_EA_RDREQ[15] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[15] / TCC_EA_WRREQ[15]) if (TCC_EA_WRREQ[15] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[15] / TCC_EA_ATOMIC[15]) if - (TCC_EA_ATOMIC[15] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15]) / $denom)) - tips: + # FIXME: other arggr metrics!! - metric_table: - id: 1803 - title: Channel 16-31 - columnwise: True + id: 1802 + title: L2 Cache Hit Rate (%) header: - channel: Channel - hit rate: L2 Cache Hit Rate (%) - req: Requests (Requests) - read req: L1-L2 Read (Requests) - write req: L1-L2 Write (Requests) - atomic req: L1-L2 Atomic (Requests) - ea read req: L2-EA Read (Requests) - ea write req: L2-EA Write (Requests) - ea atomic req: L2-EA Atomic (Requests) - ea read lat - cycles: L2-EA Read Latency (Cycles) - ea write lat - cycles: L2-EA Write Latency (Cycles) - ea atomic lat - cycles: L2-EA Atomic Latency (Cycles) - ea read stall - io: L2-EA Read Stall - IO (Cycles per) - ea read stall - gmi: L2-EA Read Stall - GMI (Cycles per) - ea read stall - dram: L2-EA Read Stall - DRAM (Cycles per) - ea write stall - io: L2-EA Write Stall - IO (Cycles per) - ea write stall - gmi: L2-EA Write Stall - GMI (Cycles per) - ea write stall - dram: L2-EA Write Stall - DRAM (Cycles per) - ea write stall - starve: L2-EA Write Stall - Starve (Cycles per) - tips: Tips + metric: Metric + expr: Expression metric: - "16": - hit rate: - AVG((((100 * TCC_HIT[16]) / (TCC_HIT[16] + TCC_MISS[16])) if ((TCC_HIT[16] - + TCC_MISS[16]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[16]) / $denom)) - read req: AVG((TO_INT(TCC_READ[16]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[16]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[16]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[16]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[16]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[16]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[16] / TCC_EA_RDREQ[16]) if (TCC_EA_RDREQ[16] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[16] / TCC_EA_WRREQ[16]) if (TCC_EA_WRREQ[16] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[16] / TCC_EA_ATOMIC[16]) if - (TCC_EA_ATOMIC[16] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16]) / $denom)) - tips: - "17": - hit rate: - AVG((((100 * TCC_HIT[17]) / (TCC_HIT[17] + TCC_MISS[17])) if ((TCC_HIT[17] - + TCC_MISS[17]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[17]) / $denom)) - read req: AVG((TO_INT(TCC_READ[17]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[17]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[17]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[17]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[17]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[17]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[17] / TCC_EA_RDREQ[17]) if (TCC_EA_RDREQ[17] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[17] / TCC_EA_WRREQ[17]) if (TCC_EA_WRREQ[17] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[17] / TCC_EA_ATOMIC[17]) if - (TCC_EA_ATOMIC[17] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17]) / $denom)) - tips: - "18": - hit rate: - AVG((((100 * TCC_HIT[18]) / (TCC_HIT[18] + TCC_MISS[18])) if ((TCC_HIT[18] - + TCC_MISS[18]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[18]) / $denom)) - read req: AVG((TO_INT(TCC_READ[18]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[18]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[18]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[18]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[18]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[18]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[18] / TCC_EA_RDREQ[18]) if (TCC_EA_RDREQ[18] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[18] / TCC_EA_WRREQ[18]) if (TCC_EA_WRREQ[18] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[18] / TCC_EA_ATOMIC[18]) if - (TCC_EA_ATOMIC[18] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18]) / $denom)) - tips: - "19": - hit rate: - AVG((((100 * TCC_HIT[19]) / (TCC_HIT[19] + TCC_MISS[19])) if ((TCC_HIT[19] - + TCC_MISS[19]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[19]) / $denom)) - read req: AVG((TO_INT(TCC_READ[19]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[19]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[19]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[19]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[19]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[19]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[19] / TCC_EA_RDREQ[19]) if (TCC_EA_RDREQ[19] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[19] / TCC_EA_WRREQ[19]) if (TCC_EA_WRREQ[19] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[19] / TCC_EA_ATOMIC[19]) if - (TCC_EA_ATOMIC[19] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19]) / $denom)) - tips: - "20": - hit rate: - AVG((((100 * TCC_HIT[20]) / (TCC_HIT[20] + TCC_MISS[20])) if ((TCC_HIT[20] - + TCC_MISS[20]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[20]) / $denom)) - read req: AVG((TO_INT(TCC_READ[20]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[20]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[20]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[20]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[20]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[20]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[20] / TCC_EA_RDREQ[20]) if (TCC_EA_RDREQ[20] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[20] / TCC_EA_WRREQ[20]) if (TCC_EA_WRREQ[20] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[20] / TCC_EA_ATOMIC[20]) if - (TCC_EA_ATOMIC[20] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20]) / $denom)) - tips: - "21": - hit rate: - AVG((((100 * TCC_HIT[21]) / (TCC_HIT[21] + TCC_MISS[21])) if ((TCC_HIT[21] - + TCC_MISS[21]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[21]) / $denom)) - read req: AVG((TO_INT(TCC_READ[21]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[21]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[21]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[21]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[21]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[21]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[21] / TCC_EA_RDREQ[21]) if (TCC_EA_RDREQ[21] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[21] / TCC_EA_WRREQ[21]) if (TCC_EA_WRREQ[21] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[21] / TCC_EA_ATOMIC[21]) if - (TCC_EA_ATOMIC[21] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21]) / $denom)) - tips: - "22": - hit rate: - AVG((((100 * TCC_HIT[22]) / (TCC_HIT[22] + TCC_MISS[22])) if ((TCC_HIT[22] - + TCC_MISS[22]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[22]) / $denom)) - read req: AVG((TO_INT(TCC_READ[22]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[22]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[22]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[22]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[22]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[22]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[22] / TCC_EA_RDREQ[22]) if (TCC_EA_RDREQ[22] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[22] / TCC_EA_WRREQ[22]) if (TCC_EA_WRREQ[22] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[22] / TCC_EA_ATOMIC[22]) if - (TCC_EA_ATOMIC[22] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22]) / $denom)) - tips: - "23": - hit rate: - AVG((((100 * TCC_HIT[23]) / (TCC_HIT[23] + TCC_MISS[23])) if ((TCC_HIT[23] - + TCC_MISS[23]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[23]) / $denom)) - read req: AVG((TO_INT(TCC_READ[23]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[23]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[23]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[23]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[23]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[23]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[23] / TCC_EA_RDREQ[23]) if (TCC_EA_RDREQ[23] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[23] / TCC_EA_WRREQ[23]) if (TCC_EA_WRREQ[23] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[23] / TCC_EA_ATOMIC[23]) if - (TCC_EA_ATOMIC[23] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23]) / $denom)) - tips: - "24": - hit rate: - AVG((((100 * TCC_HIT[24]) / (TCC_HIT[24] + TCC_MISS[24])) if ((TCC_HIT[24] - + TCC_MISS[24]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[24]) / $denom)) - read req: AVG((TO_INT(TCC_READ[24]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[24]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[24]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[24]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[24]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[24]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[24] / TCC_EA_RDREQ[24]) if (TCC_EA_RDREQ[24] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[24] / TCC_EA_WRREQ[24]) if (TCC_EA_WRREQ[24] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[24] / TCC_EA_ATOMIC[24]) if - (TCC_EA_ATOMIC[24] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24]) / $denom)) - tips: - "25": - hit rate: - AVG((((100 * TCC_HIT[25]) / (TCC_HIT[25] + TCC_MISS[25])) if ((TCC_HIT[25] - + TCC_MISS[25]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[25]) / $denom)) - read req: AVG((TO_INT(TCC_READ[25]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[25]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[25]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[25]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[25]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[25]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[25] / TCC_EA_RDREQ[25]) if (TCC_EA_RDREQ[25] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[25] / TCC_EA_WRREQ[25]) if (TCC_EA_WRREQ[25] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[25] / TCC_EA_ATOMIC[25]) if - (TCC_EA_ATOMIC[25] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25]) / $denom)) - tips: - "26": - hit rate: - AVG((((100 * TCC_HIT[26]) / (TCC_HIT[26] + TCC_MISS[26])) if ((TCC_HIT[26] - + TCC_MISS[26]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[26]) / $denom)) - read req: AVG((TO_INT(TCC_READ[26]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[26]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[26]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[26]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[26]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[26]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[26] / TCC_EA_RDREQ[26]) if (TCC_EA_RDREQ[26] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[26] / TCC_EA_WRREQ[26]) if (TCC_EA_WRREQ[26] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[26] / TCC_EA_ATOMIC[26]) if - (TCC_EA_ATOMIC[26] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26]) / $denom)) - tips: - "27": - hit rate: - AVG((((100 * TCC_HIT[27]) / (TCC_HIT[27] + TCC_MISS[27])) if ((TCC_HIT[27] - + TCC_MISS[27]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[27]) / $denom)) - read req: AVG((TO_INT(TCC_READ[27]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[27]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[27]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[27]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[27]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[27]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[27] / TCC_EA_RDREQ[27]) if (TCC_EA_RDREQ[27] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[27] / TCC_EA_WRREQ[27]) if (TCC_EA_WRREQ[27] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[27] / TCC_EA_ATOMIC[27]) if - (TCC_EA_ATOMIC[27] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27]) / $denom)) - tips: - "28": - hit rate: - AVG((((100 * TCC_HIT[28]) / (TCC_HIT[28] + TCC_MISS[28])) if ((TCC_HIT[28] - + TCC_MISS[28]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[28]) / $denom)) - read req: AVG((TO_INT(TCC_READ[28]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[28]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[28]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[28]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[28]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[28]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[28] / TCC_EA_RDREQ[28]) if (TCC_EA_RDREQ[28] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[28] / TCC_EA_WRREQ[28]) if (TCC_EA_WRREQ[28] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[28] / TCC_EA_ATOMIC[28]) if - (TCC_EA_ATOMIC[28] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28]) / $denom)) - tips: - "29": - hit rate: - AVG((((100 * TCC_HIT[29]) / (TCC_HIT[29] + TCC_MISS[29])) if ((TCC_HIT[29] - + TCC_MISS[29]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[29]) / $denom)) - read req: AVG((TO_INT(TCC_READ[29]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[29]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[29]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[29]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[29]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[29]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[29] / TCC_EA_RDREQ[29]) if (TCC_EA_RDREQ[29] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[29] / TCC_EA_WRREQ[29]) if (TCC_EA_WRREQ[29] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[29] / TCC_EA_ATOMIC[29]) if - (TCC_EA_ATOMIC[29] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29]) / $denom)) - tips: - "30": - hit rate: - AVG((((100 * TCC_HIT[30]) / (TCC_HIT[30] + TCC_MISS[30])) if ((TCC_HIT[30] - + TCC_MISS[30]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[30]) / $denom)) - read req: AVG((TO_INT(TCC_READ[30]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[30]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[30]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[30]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[30]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[30]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[30] / TCC_EA_RDREQ[30]) if (TCC_EA_RDREQ[30] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[30] / TCC_EA_WRREQ[30]) if (TCC_EA_WRREQ[30] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[30] / TCC_EA_ATOMIC[30]) if - (TCC_EA_ATOMIC[30] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30]) / $denom)) - tips: - "31": - hit rate: - AVG((((100 * TCC_HIT[31]) / (TCC_HIT[31] + TCC_MISS[31])) if ((TCC_HIT[31] - + TCC_MISS[31]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[31]) / $denom)) - read req: AVG((TO_INT(TCC_READ[31]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[31]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[31]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[31]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[31]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[31]) / $denom)) - ea read lat - cycles: - AVG(((TCC_EA_RDREQ_LEVEL[31] / TCC_EA_RDREQ[31]) if (TCC_EA_RDREQ[31] - != 0) else None)) - ea write lat - cycles: - AVG(((TCC_EA_WRREQ_LEVEL[31] / TCC_EA_WRREQ[31]) if (TCC_EA_WRREQ[31] - != 0) else None)) - ea atomic lat - cycles: - AVG(((TCC_EA_ATOMIC_LEVEL[31] / TCC_EA_ATOMIC[31]) if - (TCC_EA_ATOMIC[31] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31]) / $denom)) - tips: + "::_1": + expr: + (((100 * TCC_HIT[::_1]) / (TCC_HIT[::_1] + TCC_MISS[::_1])) if ((TCC_HIT[::_1] + + TCC_MISS[::_1]) != 0) else None) + placeholder_range: + "::_1": 32 + cli_style: simple_box + + - metric_table: + id: 1803 + title: Requests (Requests) + header: + metric: Metric + expr: Expression + metric: + "::_1": + expr: (TO_INT(TCC_REQ[::_1]) / $denom) + placeholder_range: + "::_1": 32 + cli_style: simple_box + + - metric_table: + id: 1804 + title: L1-L2 Access (Requests) + header: + metric: Metric + read req: L1-L2 Read + write req: L1-L2 Write + atomic req: L1-L2 Atomic + metric: + "::_1": + read req: AVG((TO_INT(TCC_READ[::_1]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[::_1]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[::_1]) / $denom)) + placeholder_range: + "::_1": 32 + cli_style: simple_multiple_bar + + - metric_table: + id: 1805 + title: L2-EA Access (Requests) + header: + metric: Metric + read req: L2-EA Read + write req: L2-EA Write + atomic req: L2-EA Atomic + metric: + "::_1": + read req: AVG((TO_INT(TCC_EA_RDREQ[::_1]) / $denom)) + write req: AVG((TO_INT(TCC_EA_WRREQ[::_1]) / $denom)) + atomic req: AVG((TO_INT(TCC_EA_ATOMIC[::_1]) / $denom)) + placeholder_range: + "::_1": 32 + cli_style: simple_multiple_bar + + # - metric_table: + # id: 1806 + # title: L2-EA Latency (Cycles) + # header: + # metric: Metric + # read lat: L2-EA Read + # write lat: L2-EA Write + # atomic lat: L2-EA Atomic + # metric: + # "::_1": + # read lat: + # AVG(((TCC_EA_RDREQ_LEVEL[::_1] / TCC_EA_RDREQ[::_1]) if (TCC_EA_RDREQ[::_1] + # != 0) else None)) + # write lat: + # AVG(((TCC_EA_WRREQ_LEVEL[::_1] / TCC_EA_WRREQ[::_1]) if (TCC_EA_WRREQ[::_1] + # != 0) else None)) + # atomic lat: + # AVG(((TCC_EA_ATOMIC_LEVEL[::_1] / TCC_EA_ATOMIC[::_1]) if + # (TCC_EA_ATOMIC[::_1] != 0) else 0)) + # placeholder_range: + # "::_1": 32 + # cli_style: simple_multiple_bar + + - metric_table: + id: 1806 + title: L2-EA Read Latency (Cycles) + header: + metric: Metric + expr: Expression + metric: + "::_1": + expr: + ((TCC_EA_RDREQ_LEVEL[::_1] / TCC_EA_RDREQ[::_1]) if (TCC_EA_RDREQ[::_1] + != 0) else None) + placeholder_range: + "::_1": 32 + cli_style: simple_box + + - metric_table: + id: 1807 + title: L2-EA Write Latency (Cycles) + header: + metric: Metric + expr: Expression + metric: + "::_1": + expr: + ((TCC_EA_WRREQ_LEVEL[::_1] / TCC_EA_WRREQ[::_1]) if (TCC_EA_WRREQ[::_1] + != 0) else None) + placeholder_range: + "::_1": 32 + cli_style: simple_box + + - metric_table: + id: 1808 + title: L2-EA Atomic Latency (Cycles) + header: + metric: Metric + expr: Expression + metric: + "::_1": + expr: ((TCC_EA_ATOMIC_LEVEL[::_1] / TCC_EA_ATOMIC[::_1]) if + (TCC_EA_ATOMIC[::_1] != 0) else 0) + placeholder_range: + "::_1": 32 + cli_style: simple_box + + - metric_table: + id: 1809 + title: L2-EA Read Stall (Cycles per normUnit) + header: + metric: Metric + ea read stall - io: L2-EA Read Stall - IO + ea read stall - gmi: L2-EA Read Stall - GMI + ea read stall - dram: L2-EA Read Stall - DRAM + metric: + "::_1": + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[::_1]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[::_1]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[::_1]) / $denom)) + placeholder_range: + "::_1": 32 + cli_style: simple_multiple_bar + + - metric_table: + id: 1810 + title: L2-EA Write Stall (Cycles per normUnit) + header: + metric: Metric + ea write stall - io: L2-EA Write Stall - IO + ea write stall - gmi: L2-EA Write Stall - GMI + ea write stall - dram: L2-EA Write Stall - DRAM + ea write stall - starve: L2-EA Write Stall - Starve + metric: + "::_1": + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[::_1]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[::_1]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[::_1]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[::_1]) / $denom)) + placeholder_range: + "::_1": 32 + cli_style: simple_multiple_bar \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1900_memory_chart.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1900_memory_chart.yaml deleted file mode 100644 index 3728934e2b..0000000000 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx908/1900_memory_chart.yaml +++ /dev/null @@ -1,259 +0,0 @@ ---- -# Add description/tips for each metric in this section. -# So it could be shown in hover. -Metric Description: - -# Define the panel properties and properties of each metric in the panel. -Panel Config: - id: 1900 - title: Memory Chart Analysis - data source: - - metric_table: - id: 1901 - title: # subtitle for this table(optional) - header: - metric: Metric - value: Value - alias: Alias - tips: Tips - metric: - Wave Life: - value: ROUND(AVG(((4 * (SQ_WAVE_CYCLES / SQ_WAVES)) if (SQ_WAVES != 0) else - None)), 0) - alias: wave_life_ - tips: - Active CUs: - value: CONCAT(CONCAT($numActiveCUs, "/"), $numCU) - alias: active_cu_ - tips: - SALU: - value: ROUND(AVG((SQ_INSTS_SALU / $denom)), 0) - alias: salu_ - tips: - SMEM: - value: ROUND(AVG((SQ_INSTS_SMEM / $denom)), 0) - alias: smem_ - tips: - VALU: - value: ROUND(AVG((SQ_INSTS_VALU / $denom)), 0) - alias: valu_ - tips: - MFMA: - value: None # No perf counter - alias: mfma_ - tips: - VMEM: - value: ROUND(AVG((SQ_INSTS_VMEM / $denom)), 0) - alias: vmem_ - tips: - LDS: - value: ROUND(AVG((SQ_INSTS_LDS / $denom)), 0) - alias: lds_ - tips: - GWS: - value: ROUND(AVG((SQ_INSTS_GDS / $denom)), 0) - alias: gws_ - tips: - BR: - value: ROUND(AVG((SQ_INSTS_BRANCH / $denom)), 0) - alias: br_ - tips: - VGPR: - value: ROUND(AVG(vgpr), 0) - alias: vgpr_ - tips: - SGPR: - value: ROUND(AVG(sgpr), 0) - alias: sgpr_ - tips: - LDS Allocation: - value: ROUND(AVG(lds), 0) - alias: lds_alloc_ - tips: - Scratch Allocation: - value: ROUND(AVG(scr), 0) - alias: scratch_alloc_ - tips: - Wavefronts: - value: ROUND(AVG(SPI_CSN_WAVE), 0) - alias: wavefronts_ - tips: - Workgroups: - value: ROUND(AVG(SPI_CSN_NUM_THREADGROUPS), 0) - alias: workgroups_ - tips: - LDS Req: - value: ROUND(AVG((SQ_INSTS_LDS / $denom)), 0) - alias: lds_req_ - tips: - IL1 Fetch: - value: ROUND(AVG((SQC_ICACHE_REQ / $denom)), 0) - alias: il1_fetch_ - tips: - IL1 Hit: - value: ROUND((AVG((SQC_ICACHE_HITS / SQC_ICACHE_REQ)) * 100), 0) - alias: il1_hit_ - tips: - IL1_L2 Rd: - value: ROUND(AVG((SQC_TC_INST_REQ / $denom)), 0) - alias: il1_l2_req_ - tips: - vL1D Rd: - value: ROUND(AVG((SQC_DCACHE_REQ / $denom)), 0) - alias: sl1_rd_ - tips: - vL1D Hit: - value: ROUND((AVG(((SQC_DCACHE_HITS / SQC_DCACHE_REQ) if (SQC_DCACHE_REQ != - 0) else None)) * 100), 0) - alias: sl1_hit_ - tips: - vL1D_L2 Rd: - value: ROUND(AVG((SQC_TC_DATA_READ_REQ / $denom)), 0) - alias: sl1_l2_rd_ - tips: - vL1D_L2 Wr: - value: ROUND(AVG((SQC_TC_DATA_WRITE_REQ / $denom)), 0) - alias: sl1_l2_wr_ - tips: - vL1D_L2 Atomic: - value: ROUND(AVG((SQC_TC_DATA_ATOMIC_REQ / $denom)), 0) - alias: sl1_l2_atom_ - tips: - VL1 Rd: - value: ROUND(AVG((TCP_TOTAL_READ_sum / $denom)), 0) - alias: vl1_rd_ - tips: - VL1 Wr: - value: ROUND(AVG((TCP_TOTAL_WRITE_sum / $denom)), 0) - alias: vl1_wr_ - tips: - VL1 Atomic: - value: ROUND(AVG(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) - / $denom)), 0) - alias: vl1_atom_ - tips: - VL1 Hit: - value: ROUND(AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) - + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) - / TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else - None)), 0) - alias: vl1_hit_ - tips: - VL1 Lat: - value: ROUND(AVG(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum - != 0) else None)), 0) - alias: vl1_lat_ - tips: - VL1_L2 Rd: - value: ROUND(AVG((TCP_TCC_READ_REQ_sum / $denom)), 0) - alias: vl1_l2_rd_ - tips: - VL1_L2 Wr: - value: ROUND(AVG((TCP_TCC_WRITE_REQ_sum / $denom)), 0) - alias: vl1_l2_wr_ - tips: - vL1_L2 Atomic: - value: ROUND(AVG(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) - / $denom)), 0) - alias: vl1_l2_atom_ - tips: - L2 Rd: - value: ROUND(AVG((TCC_READ_sum / $denom)), 0) - alias: l2_rd_ - tips: - L2 Wr: - value: ROUND(AVG((TCC_WRITE_sum / $denom)), 0) - alias: l2_wr_ - tips: - L2 Atomic: - value: ROUND(AVG((TCC_ATOMIC_sum / $denom)), 0) - alias: l2_atom_ - tips: - L2 Hit: - value: ROUND(AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum - + TCC_MISS_sum) != 0) else None)), 0) - alias: l2_hit_ - tips: - L2 Rd Lat: - value: ROUND(AVG(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) - if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)), - 0) - alias: l2_rd_lat_ - tips: - L2 Wr Lat: - value: ROUND(AVG(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + - TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) - != 0) else None)), 0) - alias: l2_wr_lat_ - tips: - Fabric Rd Lat: - value: ROUND(AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum - != 0) else None)), 0) - alias: fabric_rd_lat_ - tips: - Fabric Wr Lat: - value: ROUND(AVG(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum - != 0) else None)), 0) - alias: fabric_wr_lat_ - tips: - Fabric Atomic Lat: - value: ROUND(AVG(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum - != 0) else None)), 0) - alias: fabric_atom_lat_ - tips: - Fabric_L2 Rd: - value: ROUND(AVG((TCC_EA_RDREQ_sum / $denom)), 0) - alias: l2_fabric_rd_ - tips: - Fabric_L2 Wr: - value: ROUND(AVG((TCC_EA_WRREQ_sum / $denom)), 0) - alias: l2_fabric_wr_ - tips: - Fabric_l2 Atomic: - value: ROUND(AVG((TCC_EA_ATOMIC_sum / $denom)), 0) - alias: l2_fabric_atom_ - tips: - HBM Rd: - value: ROUND(AVG((TCC_EA_RDREQ_DRAM_sum / $denom)), 0) - alias: hbm_rd_ - tips: - HBM Wr: - value: ROUND(AVG((TCC_EA_WRREQ_DRAM_sum / $denom)), 0) - alias: hbm_wr_ - tips: - LDS Util: - value: ROUND(AVG(((100 * SQ_LDS_IDX_ACTIVE) / (GRBM_GUI_ACTIVE * $numCU))), - 0) - alias: lds_util_ - tips: - VL1 Coalesce: - value: ROUND(AVG(((((TA_TOTAL_WAVEFRONTS_sum * 64) * 100) / (TCP_TOTAL_ACCESSES_sum - * 4)) if (TCP_TOTAL_ACCESSES_sum != 0) else 0)), 0) - alias: vl1_coales_ - tips: - VL1 Stall: - value: ROUND(AVG((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) - if (TCP_GATE_EN1_sum != 0) else None)), 0) - alias: vl1_stall_ - tips: - LDS Lat: - value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) - if (SQ_INSTS_LDS != 0) else None)), 0) - alias: lds_lat_ - coll_level: SQ_INST_LEVEL_LDS - tips: - vL1D Lat: - value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQC_DCACHE_REQ) - if (SQC_DCACHE_REQ != 0) else None)), 0) - alias: sl1_lat_ - tips: - IL1 Lat: - value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQC_ICACHE_REQ) - if (SQC_ICACHE_REQ != 0) else None)), 0) - alias: il1_lat_ - tips: - Wave Occupancy: - value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE) / $numActiveCUs)), 0) - alias: wave_occ_ - coll_level: SQ_LEVEL_WAVES - tips: diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/0300_mem_chart.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/0300_mem_chart.yaml new file mode 100644 index 0000000000..acdc18c56c --- /dev/null +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/0300_mem_chart.yaml @@ -0,0 +1,313 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 300 + title: Memory Chart + data source: + - metric_table: + id: 301 + header: + metric: Metric + #alias: #alias + value: Value + tips: Tips + metric: + # ---------------------------------------- + # Instr Buff Block + + #TODO: double check wave_occupancy + Wavefront Occupancy: + #alias: wave_occ_ + value: ROUND(AVG((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE) / $numActiveCUs), 0) + coll_level: SQ_LEVEL_WAVES + tips: + Wave Life: + #alias: wave_life_ + value: ROUND(AVG(((4 * (SQ_WAVE_CYCLES / SQ_WAVES)) if (SQ_WAVES != 0) else 0)), 0) + tips: + + # ---------------------------------------- + # Instr Dispatch Block + SALU: + #alias: salu_ + value: ROUND(AVG((SQ_INSTS_SALU / $denom)), 0) + tips: + SMEM: + #alias: smem_ + value: ROUND(AVG((SQ_INSTS_SMEM / $denom)), 0) + tips: + VALU: + #alias: valu_ + value: ROUND(AVG((SQ_INSTS_VALU / $denom)), 0) + tips: + MFMA: + #alias: mfma_ + value: ROUND(AVG((SQ_INSTS_MFMA / $denom)), 0) + tips: + VMEM: + #alias: vmem_ + value: ROUND(AVG((SQ_INSTS_VMEM / $denom)), 0) + tips: + LDS: + #alias: lds_ + value: ROUND(AVG((SQ_INSTS_LDS / $denom)), 0) + tips: + GWS: + #alias: gws_ + value: ROUND(AVG((SQ_INSTS_GDS / $denom)), 0) + tips: + BR: + #alias: br_ + value: ROUND(AVG((SQ_INSTS_BRANCH / $denom)), 0) + tips: + + # ---------------------------------------- + # Exec Block + Active CUs: + #alias: active_cu_ + value: $numActiveCUs + tips: + Num CUs: + #alias: num_cu_ + value: $numCU + tips: + VGPR: + #alias: vgpr_ + value: ROUND(AVG(vgpr), 0) + tips: + SGPR: + #alias: sgpr_ + value: ROUND(AVG(sgpr), 0) + tips: + LDS Allocation: + #alias: lds_alloc_ + value: ROUND(AVG(lds), 0) + tips: + Scratch Allocation: + #alias: scratch_alloc_ + value: ROUND(AVG(scr), 0) + tips: + Wavefronts: + #alias: wavefronts_ + value: ROUND(AVG(SPI_CSN_WAVE), 0) + tips: + Workgroups: + #alias: workgroups_ + value: ROUND(AVG(SPI_CSN_NUM_THREADGROUPS), 0) + tips: + + # ---------------------------------------- + # LDS Block + LDS Req: + #alias: lds_req_ + value: ROUND(AVG((SQ_INSTS_LDS / $denom)), 0) + tips: + LDS Util: + #alias: lds_util_ + value: + ROUND(AVG(((100 * SQ_LDS_IDX_ACTIVE) / (GRBM_GUI_ACTIVE * $numCU))), + 0) + tips: + LDS Latency: + #alias: lds_lat + value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)),0) + coll_level: SQ_INST_LEVEL_LDS + tips: + + # ---------------------------------------- + # Vector L1 Cache Block + VL1 Rd: + #alias: vl1_rd_ + value: ROUND(AVG((TCP_TOTAL_READ_sum / $denom)), 0) + tips: + VL1 Wr: + #alias: vl1_wr_ + value: ROUND(AVG((TCP_TOTAL_WRITE_sum / $denom)), 0) + tips: + VL1 Atomic: + #alias: vl1_atom_ + value: + ROUND(AVG(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) + / $denom)), 0) + tips: + + VL1 Hit: + #alias: vl1_hit_ + value: + ROUND(AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None )), 0) + tips: + VL1 Lat: + #alias: vl1_lat_ + value: + ROUND(AVG(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum + != 0) else None)), 0) + tips: + VL1 Coalesce: + #alias: vl1_coales_ + value: + ROUND(AVG(((((TA_TOTAL_WAVEFRONTS_sum * 64) * 100) / (TCP_TOTAL_ACCESSES_sum + * 4)) if (TCP_TOTAL_ACCESSES_sum != None) else 0)), 0) + tips: + VL1 Stall: + #alias: vl1_stall_ + value: + ROUND(AVG((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)), 0) + tips: + + VL1_L2 Rd: + #alias: vl1_l2_rd_ + value: ROUND(AVG((TCP_TCC_READ_REQ_sum / $denom)), 0) + tips: + VL1_L2 Wr: + #alias: vl1_l2_wr_ + value: ROUND(AVG((TCP_TCC_WRITE_REQ_sum / $denom)), 0) + tips: + VL1_L2 Atomic: + #alias: vl1_l2_atom_ + value: + ROUND(AVG(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + / $denom)), 0) + tips: + + # ---------------------------------------- + # Scalar L1D Cache Block + VL1D Rd: + #alias: sl1_rd_ + value: ROUND(AVG((SQC_DCACHE_REQ / $denom)), 0) + tips: + VL1D Hit: + #alias: sl1_hit_ + value: + ROUND((AVG(((SQC_DCACHE_HITS / SQC_DCACHE_REQ) if (SQC_DCACHE_REQ != + 0) else None)) * 100), 0) + tips: + VL1D Lat: + #alias: sl1_lat_ + value: + ROUND((AVG(((SQ_ACCUM_PREV_HIRES / SQC_DCACHE_REQ) if (SQC_DCACHE_REQ != + 0) else None)) * 100), 0) + coll_level: SQC_DCACHE_INFLIGHT_LEVEL + tips: + + VL1D_L2 Rd: + #alias: sl1_l2_rd_ + value: ROUND(AVG((SQC_TC_DATA_READ_REQ / $denom)), 0) + tips: + VL1D_L2 Wr: + #alias: sl1_l2_wr_ + value: ROUND(AVG((SQC_TC_DATA_WRITE_REQ / $denom)), 0) + tips: + VL1D_L2 Atomic: + #alias: sl1_l2_atom_ + value: ROUND(AVG((SQC_TC_DATA_ATOMIC_REQ / $denom)), 0) + tips: + + # ---------------------------------------- + # Instr L1 Cache Block + IL1 Fetch: + #alias: il1_fetch_ + value: ROUND(AVG((SQC_ICACHE_REQ / $denom)), 0) + tips: + IL1 Hit: + #alias: il1_hit_ + value: ROUND((AVG((SQC_ICACHE_HITS / SQC_ICACHE_REQ)) * 100), 0) + tips: + IL1 Lat: + #alias: il1_lat_ + value: + ROUND((AVG(((SQ_ACCUM_PREV_HIRES / SQC_ICACHE_REQ) if (SQC_ICACHE_REQ != + 0) else None)) * 100), 0) + tips: # ??? coll_level: SQ_IFETCH_LEVEL + IL1_L2 Rd: + #alias: il1_l2_req_ + value: ROUND(AVG((SQC_TC_INST_REQ / $denom)), 0) + tips: + + # ---------------------------------------- + # L2 Cache Block(inside) + L2 Rd: + #alias: l2_rd_ + value: ROUND(AVG((TCC_READ_sum / $denom)), 0) + tips: + L2 Wr: + #alias: l2_wr_ + value: ROUND(AVG((TCC_WRITE_sum / $denom)), 0) + tips: + L2 Atomic: + #alias: l2_atom_ + value: ROUND(AVG((TCC_ATOMIC_sum / $denom)), 0) + tips: + L2 Hit: + #alias: l2_hit_ + value: + ROUND(AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else 0)), 0) + tips: + L2 Rd Lat: + #alias: l2_rd_lat_ + value: + ROUND(AVG(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) + if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)), + 0) + tips: + L2 Wr Lat: + #alias: l2_wr_lat_ + value: + ROUND(AVG(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + != 0) else None)), 0) + tips: + + # ---------------------------------------- + # Fabric Block + Fabric_L2 Rd: + #alias: l2_fabric_rd_ + value: ROUND(AVG((TCC_EA_RDREQ_sum / $denom)), 0) + tips: + Fabric_L2 Wr: + #alias: l2_fabric_wr_ + value: ROUND(AVG((TCC_EA_WRREQ_sum / $denom)), 0) + tips: + Fabric_L2 Atomic: + #alias: l2_fabric_atom_ + value: ROUND(AVG((TCC_EA_ATOMIC_sum / $denom)), 0) + tips: + + Fabric Rd Lat: + #alias: fabric_rd_lat_ + value: + ROUND(AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum + != 0) else 0)), 0) + tips: + Fabric Wr Lat: + #alias: fabric_wr_lat_ + value: + ROUND(AVG(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum + != 0) else 0)), 0) + tips: + Fabric Atomic Lat: + #alias: fabric_atom_lat_ + value: + ROUND(AVG(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum + != 0) else 0)), 0) + tips: + + HBM Rd: + #alias: hbm_rd_ + value: ROUND(AVG((TCC_EA_RDREQ_DRAM_sum / $denom)), 0) + tips: + HBM Wr: + #alias: hbm_wr_ + value: ROUND(AVG((TCC_EA_WRREQ_DRAM_sum / $denom)), 0) + tips: + + comparable: false # for now + cli_style: mem_chart \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/0400_roofline_chart.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/0400_roofline_chart.yaml new file mode 100644 index 0000000000..0478d89a66 --- /dev/null +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/0400_roofline_chart.yaml @@ -0,0 +1,11 @@ +--- +Panel Config: + id: 400 + title: Roofline + data source: + - raw_csv_table: + id: 401 + source: roofline.csv + comparable: false # for now + cli_style: roofline_chart + # TODO: refactoring the data structure to have metrics here! \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1000_compute-unit-instruction-mix.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1000_compute-unit-instruction-mix.yaml index 8ffd87d2c8..92894b31d3 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1000_compute-unit-instruction-mix.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1000_compute-unit-instruction-mix.yaml @@ -18,7 +18,7 @@ Panel Config: max: Max unit: Unit tips: Tips - style: + cli_style: type: simple_bar label_txt: (# of instr + $normUnit) metric: @@ -81,7 +81,7 @@ Panel Config: max: Max unit: Unit tips: Tips - style: + cli_style: type: simple_bar label_txt: (# of instr + $normUnit) metric: @@ -231,4 +231,4 @@ Panel Config: tips: MFMA-F64: count: AVG((SQ_INSTS_VALU_MFMA_F64 / $denom)) - tips: + tips: \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1100_compute-unit-compute-pipeline.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1100_compute-unit-compute-pipeline.yaml index 5767fe771a..d4b1939642 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1100_compute-unit-compute-pipeline.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1100_compute-unit-compute-pipeline.yaml @@ -16,7 +16,7 @@ Panel Config: value: Value unit: Unit tips: Tips - style: + cli_style: type: simple_bar range_color: [1, 100] label_txt: (%) diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1200_lds.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1200_lds.yaml index 3fd52c3b1b..f720bfb84b 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1200_lds.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1200_lds.yaml @@ -16,7 +16,7 @@ Panel Config: value: Value unit: Unit tips: Tips - style: + cli_style: type: simple_bar range_color: [1, 100] label_txt: (%) @@ -118,4 +118,4 @@ Panel Config: max: MAX(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)) unit: Cycles coll_level: SQ_INST_LEVEL_LDS - tips: + tips: \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1300_instruction-cache.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1300_instruction-cache.yaml index 329a7edbad..ce0259eaec 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1300_instruction-cache.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1300_instruction-cache.yaml @@ -16,7 +16,7 @@ Panel Config: value: Value unit: Unit tips: Tips - style: + cli_style: type: simple_bar range_color: [1, 100] label_txt: (%) @@ -76,4 +76,4 @@ Panel Config: max: MAX(((100 * SQC_ICACHE_HITS) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + SQC_ICACHE_MISSES_DUPLICATE))) unit: pct - tips: + tips: \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1400_constant-cache.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1400_constant-cache.yaml index 563caad13f..4d4a6c8c95 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1400_constant-cache.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1400_constant-cache.yaml @@ -16,7 +16,7 @@ Panel Config: value: Value unit: Unit tips: Tips - style: + cli_style: type: simple_bar range_color: [1, 100] label_txt: (%) @@ -161,4 +161,4 @@ Panel Config: min: MIN((SQC_TC_STALL / $denom)) max: MAX((SQC_TC_STALL / $denom)) unit: (Cycles + $normUnit) - tips: + tips: \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1600_L1_cache.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1600_L1_cache.yaml index d9291de21d..79c5e5f0d9 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1600_L1_cache.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1600_L1_cache.yaml @@ -16,7 +16,7 @@ Panel Config: value: Value unit: Unit tips: Tips - style: + cli_style: type: simple_bar range_color: [1, 100] label_txt: (%) @@ -258,7 +258,7 @@ Panel Config: max: Max unit: Unit tips: Tips - style: + cli_style: type: simple_multi_bar metric: NC - Read: @@ -401,4 +401,4 @@ Panel Config: min: MIN((TCP_UTCL1_PERMISSION_MISS_sum / $denom)) max: MAX((TCP_UTCL1_PERMISSION_MISS_sum / $denom)) units: (Misses + $normUnit) - tips: + tips: \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1700_L2_cache.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1700_L2_cache.yaml index ddbaf91554..002802998c 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1700_L2_cache.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1700_L2_cache.yaml @@ -16,7 +16,7 @@ Panel Config: value: Value unit: Unit tips: Tips - style: + cli_style: type: simple_bar metric: L2 Util: @@ -303,7 +303,7 @@ Panel Config: max: Max unit: Unit tips: Tips - style: + cli_style: type: simple_multi_bar metric: Read - Remote Socket Stall: @@ -361,4 +361,4 @@ Panel Config: min: MIN((TCC_TOO_MANY_EA_WRREQS_STALL_sum / $denom)) max: MAX((TCC_TOO_MANY_EA_WRREQS_STALL_sum / $denom)) unit: (Req + $normUnit) - tips: + tips: \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1800_L2_cache_per_channel.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1800_L2_cache_per_channel.yaml index c6d93aa61b..5d54deeb9e 100644 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1800_L2_cache_per_channel.yaml +++ b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1800_L2_cache_per_channel.yaml @@ -167,2002 +167,169 @@ Panel Config: + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31])) != 0) else None)) unit: pct tips: - Req: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) - + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) - + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) - + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) - + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) - + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) - + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) - + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) - + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) - + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) - + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) - + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) - + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) - + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) - + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) - + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) - + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) - + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) - + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) - + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) - + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) - + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) - + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) - + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) - + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) - + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) - + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) - + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) - + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) - + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) - + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) - + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) - + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) - unit: (Req + $normUnit) - tips: - L1 - L2 Read Req: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) - + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) - + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) - + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + - TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) - + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + - TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) - + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + - TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) - + TO_INT(TCC_READ[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) - + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) - + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) - + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + - TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) - + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + - TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) - + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + - TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) - + TO_INT(TCC_READ[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) - + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) - + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) - + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + - TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) - + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + - TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) - + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + - TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) - + TO_INT(TCC_READ[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) - + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) - + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) - + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + - TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) - + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + - TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) - + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + - TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) - + TO_INT(TCC_READ[31])) / 32) / $denom)) - unit: (Req + $normUnit) - tips: - L1 - L2 Write Req: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) - + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + - TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) - + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) - + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) - + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) - + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) - + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) - + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) - + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) - + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) - + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + - TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) - + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) - + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) - + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) - + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) - + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) - + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) - + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) - + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) - + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + - TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) - + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) - + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) - + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) - + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) - + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) - + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) - + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) - + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) - + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + - TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) - + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) - + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) - + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) - + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) - + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) - + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) - + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) - + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) - unit: (Req + $normUnit) - tips: - L1 - L2 Atomic Req: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) - + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) - + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) - + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) - + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) - + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) - + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) - + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) - + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) - + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) - + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) - / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) - + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) - + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) - + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) - + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) - + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) - + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) - + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) - + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) - + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) - + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) - / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) - + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) - + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) - + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) - + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) - + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) - + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) - + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) - + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) - + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) - + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) - / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) - + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) - + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) - + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) - + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) - + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) - + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) - + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) - + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) - + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) - + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) - / 32) / $denom)) - unit: (Req + $normUnit) - tips: - L2 - EA Read Req: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) - + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) - + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) - + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) - + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) - + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) - + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) - + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) - + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) - + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) - + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) - / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) - + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) - + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) - + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) - + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) - + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) - + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) - + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) - + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) - + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) - + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) - / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) - + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) - + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) - + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) - + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) - + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) - + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) - + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) - + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) - + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) - + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) - / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) - + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) - + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) - + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) - + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) - + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) - + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) - + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) - + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) - + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) - + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) - / 32) / $denom)) - unit: (Req + $normUnit) - tips: - L2 - EA Write Req: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) - + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) - + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) - + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) - + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) - + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) - + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) - + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) - + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) - + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) - + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) - / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) - + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) - + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) - + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) - + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) - + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) - + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) - + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) - + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) - + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) - + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) - / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) - + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) - + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) - + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) - + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) - + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) - + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) - + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) - + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) - + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) - + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) - / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) - + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) - + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) - + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) - + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) - + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) - + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) - + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) - + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) - + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) - + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) - / 32) / $denom)) - unit: (Req + $normUnit) - tips: - L2 - EA Atomic Req: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) - + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) - + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) - + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) - + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) - + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) - + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) - + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) - + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) - + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) - + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) - / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) - + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) - + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) - + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) - + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) - + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) - + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) - + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) - + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) - + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) - + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) - / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) - + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) - + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) - + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) - + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) - + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) - + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) - + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) - + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) - + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) - + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) - / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) - + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) - + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) - + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) - + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) - + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) - + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) - + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) - + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) - + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) - + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) - / 32) / $denom)) - unit: (Req + $normUnit) - tips: - L2 - EA Read Lat: - avg: AVG((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) - + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) - + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) - + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) - + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) - + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) - + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) - + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) - + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) - + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) - + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) - + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) - + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) - + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) - + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) - + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) - + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) - + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) - + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + - TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) - + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) - + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) - + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) - + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) - + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) - + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) - + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) - std dev: STD((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) - + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) - + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) - + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) - + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) - + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) - + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) - + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) - + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) - + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) - + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) - + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) - + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) - + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) - + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) - + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) - + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) - + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) - + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + - TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) - + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) - + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) - + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) - + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) - + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) - + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) - + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) - min: MIN((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) - + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) - + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) - + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) - + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) - + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) - + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) - + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) - + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) - + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) - + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) - + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) - + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) - + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) - + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) - + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) - + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) - + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) - + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + - TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) - + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) - + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) - + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) - + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) - + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) - + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) - + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) - max: MAX((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) - + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) - + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) - + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) - + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) - + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) - + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) - + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) - + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) - + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) - + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) - + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) - + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) - + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) - + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) - + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) - + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) - + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) - + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + - TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) - + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) - + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) - + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) - + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) - + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) - + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) - + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) - unit: Cycles - tips: - L2 - EA Write Lat: - avg: AVG((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) - + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) - + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) - + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) - + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) - + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) - + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) - + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) - + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) - + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) - + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) - + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) - + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) - + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) - + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) - + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) - + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) - + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) - + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + - TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) - + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) - + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) - + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) - + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) - + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) - + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) - + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) - std dev: STD((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) - + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) - + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) - + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) - + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) - + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) - + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) - + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) - + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) - + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) - + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) - + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) - + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) - + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) - + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) - + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) - + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) - + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) - + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + - TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) - + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) - + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) - + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) - + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) - + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) - + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) - + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) - min: MIN((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) - + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) - + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) - + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) - + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) - + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) - + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) - + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) - + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) - + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) - + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) - + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) - + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) - + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) - + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) - + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) - + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) - + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) - + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + - TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) - + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) - + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) - + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) - + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) - + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) - + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) - + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) - max: MAX((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) - + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) - + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) - + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) - + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) - + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) - + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) - + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) - + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) - + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) - + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) - + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) - + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) - + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) - + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) - + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) - + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) - + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) - + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + - TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) - + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) - + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) - + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) - + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) - + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) - + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) - + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) - unit: Cycles - tips: - L2 - EA Atomic Lat: - avg: AVG((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) - + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) - + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) - + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) - + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) - + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) - + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) - + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) - + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) - + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) - + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) - + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) - + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) - + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) - + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) - + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) - + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) - + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) - + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] - + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) - + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) - + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) - + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) - + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) - + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) - + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) - + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else - None)) - std dev: STD((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) - + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) - + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) - + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) - + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) - + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) - + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) - + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) - + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) - + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) - + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) - + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) - + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) - + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) - + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) - + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) - + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) - + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) - + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] - + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) - + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) - + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) - + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) - + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) - + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) - + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) - + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else - None)) - min: MIN((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) - + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) - + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) - + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) - + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) - + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) - + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) - + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) - + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) - + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) - + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) - + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) - + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) - + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) - + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) - + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) - + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) - + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) - + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] - + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) - + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) - + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) - + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) - + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) - + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) - + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) - + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else - None)) - max: MAX((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) - + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) - + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) - + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) - + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) - + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) - + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) - + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) - + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) - + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) - + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) - / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) - + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) - + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) - + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) - + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) - + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) - + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) - + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) - + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] - + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) - + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) - + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) - + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) - + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) - + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) - + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) - + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else - None)) - unit: Cycles - tips: - L2 - EA Read Stall (IO): - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - unit: (Cycles + $normUnit) - tips: - L2 - EA Read Stall (GMI): - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - unit: (Cycles + $normUnit) - tips: - L2 - EA Read Stall (DRAM): - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - unit: (Cycles + $normUnit) - tips: - L2 - EA Write Stall (IO): - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) - unit: (Cycles + $normUnit) - tips: - L2 - EA Write Stall (GMI): - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) - unit: (Cycles + $normUnit) - tips: - L2 - EA Write Stall (DRAM): - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) - + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) - unit: (Cycles + $normUnit) - tips: - L2 - EA Write Starve: - avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) - std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) - min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) - max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) - + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) - unit: (Cycles + $normUnit) - tips: + # FIXME: other arggr metrics!! + - metric_table: id: 1802 - title: Channel 0-15 - columnwise: True + title: L2 Cache Hit Rate (%) header: - channel: Channel - hit rate: L2 Cache Hit Rate (%) - req: Requests (Requests) - read req: L1-L2 Read (Requests) - write req: L1-L2 Write (Requests) - atomic req: L1-L2 Atomic (Requests) - ea read req: L2-EA Read (Requests) - ea write req: L2-EA Write (Requests) - ea atomic req: L2-EA Atomic (Requests) - ea read lat - cycles: L2-EA Read Latency (Cycles) - ea write lat - cycles: L2-EA Write Latency (Cycles) - ea atomic lat - cycles: L2-EA Atomic Latency (Cycles) - ea read stall - io: L2-EA Read Stall - IO (Cycles per) - ea read stall - gmi: L2-EA Read Stall - GMI (Cycles per) - ea read stall - dram: L2-EA Read Stall - DRAM (Cycles per) - ea write stall - io: L2-EA Write Stall - IO (Cycles per) - ea write stall - gmi: L2-EA Write Stall - GMI (Cycles per) - ea write stall - dram: L2-EA Write Stall - DRAM (Cycles per) - ea write stall - starve: L2-EA Write Stall - Starve (Cycles per) - tips: Tips + metric: Metric + expr: Expression metric: - '0': - hit rate: AVG((((100 * TCC_HIT[0]) / (TCC_HIT[0] + TCC_MISS[0])) if ((TCC_HIT[0] - + TCC_MISS[0]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[0]) / $denom)) - read req: AVG((TO_INT(TCC_READ[0]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[0]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[0]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[0]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[0]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[0]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[0] / TCC_EA_RDREQ[0]) if (TCC_EA_RDREQ[0] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[0] / TCC_EA_WRREQ[0]) if (TCC_EA_WRREQ[0] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[0] / TCC_EA_ATOMIC[0]) if - (TCC_EA_ATOMIC[0] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) / $denom)) - tips: - '1': - hit rate: AVG((((100 * TCC_HIT[1]) / (TCC_HIT[1] + TCC_MISS[1])) if ((TCC_HIT[1] - + TCC_MISS[1]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[1]) / $denom)) - read req: AVG((TO_INT(TCC_READ[1]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[1]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[1]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[1]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[1]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[1]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[1] / TCC_EA_RDREQ[1]) if (TCC_EA_RDREQ[1] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[1] / TCC_EA_WRREQ[1]) if (TCC_EA_WRREQ[1] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[1] / TCC_EA_ATOMIC[1]) if - (TCC_EA_ATOMIC[1] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1]) / $denom)) - tips: - '2': - hit rate: AVG((((100 * TCC_HIT[2]) / (TCC_HIT[2] + TCC_MISS[2])) if ((TCC_HIT[2] - + TCC_MISS[2]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[2]) / $denom)) - read req: AVG((TO_INT(TCC_READ[2]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[2]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[2]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[2]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[2]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[2]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[2] / TCC_EA_RDREQ[2]) if (TCC_EA_RDREQ[2] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[2] / TCC_EA_WRREQ[2]) if (TCC_EA_WRREQ[2] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[2] / TCC_EA_ATOMIC[2]) if - (TCC_EA_ATOMIC[2] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2]) / $denom)) - tips: - '3': - hit rate: AVG((((100 * TCC_HIT[3]) / (TCC_HIT[3] + TCC_MISS[3])) if ((TCC_HIT[3] - + TCC_MISS[3]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[3]) / $denom)) - read req: AVG((TO_INT(TCC_READ[3]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[3]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[3]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[3]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[3]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[3]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[3] / TCC_EA_RDREQ[3]) if (TCC_EA_RDREQ[3] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[3] / TCC_EA_WRREQ[3]) if (TCC_EA_WRREQ[3] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[3] / TCC_EA_ATOMIC[3]) if - (TCC_EA_ATOMIC[3] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3]) / $denom)) - tips: - '4': - hit rate: AVG((((100 * TCC_HIT[4]) / (TCC_HIT[4] + TCC_MISS[4])) if ((TCC_HIT[4] - + TCC_MISS[4]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[4]) / $denom)) - read req: AVG((TO_INT(TCC_READ[4]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[4]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[4]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[4]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[4]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[4]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[4] / TCC_EA_RDREQ[4]) if (TCC_EA_RDREQ[4] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[4] / TCC_EA_WRREQ[4]) if (TCC_EA_WRREQ[4] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[4] / TCC_EA_ATOMIC[4]) if - (TCC_EA_ATOMIC[4] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4]) / $denom)) - tips: - '5': - hit rate: AVG((((100 * TCC_HIT[5]) / (TCC_HIT[5] + TCC_MISS[5])) if ((TCC_HIT[5] - + TCC_MISS[5]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[5]) / $denom)) - read req: AVG((TO_INT(TCC_READ[5]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[5]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[5]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[5]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[5]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[5]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[5] / TCC_EA_RDREQ[5]) if (TCC_EA_RDREQ[5] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[5] / TCC_EA_WRREQ[5]) if (TCC_EA_WRREQ[5] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[5] / TCC_EA_ATOMIC[5]) if - (TCC_EA_ATOMIC[5] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5]) / $denom)) - tips: - '6': - hit rate: AVG((((100 * TCC_HIT[6]) / (TCC_HIT[6] + TCC_MISS[6])) if ((TCC_HIT[6] - + TCC_MISS[6]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[6]) / $denom)) - read req: AVG((TO_INT(TCC_READ[6]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[6]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[6]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[6]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[6]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[6]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[6] / TCC_EA_RDREQ[6]) if (TCC_EA_RDREQ[6] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[6] / TCC_EA_WRREQ[6]) if (TCC_EA_WRREQ[6] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[6] / TCC_EA_ATOMIC[6]) if - (TCC_EA_ATOMIC[6] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6]) / $denom)) - tips: - '7': - hit rate: AVG((((100 * TCC_HIT[7]) / (TCC_HIT[7] + TCC_MISS[7])) if ((TCC_HIT[7] - + TCC_MISS[7]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[7]) / $denom)) - read req: AVG((TO_INT(TCC_READ[7]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[7]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[7]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[7]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[7]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[7]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[7] / TCC_EA_RDREQ[7]) if (TCC_EA_RDREQ[7] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[7] / TCC_EA_WRREQ[7]) if (TCC_EA_WRREQ[7] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[7] / TCC_EA_ATOMIC[7]) if - (TCC_EA_ATOMIC[7] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7]) / $denom)) - tips: - '8': - hit rate: AVG((((100 * TCC_HIT[8]) / (TCC_HIT[8] + TCC_MISS[8])) if ((TCC_HIT[8] - + TCC_MISS[8]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[8]) / $denom)) - read req: AVG((TO_INT(TCC_READ[8]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[8]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[8]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[8]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[8]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[8]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[8] / TCC_EA_RDREQ[8]) if (TCC_EA_RDREQ[8] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[8] / TCC_EA_WRREQ[8]) if (TCC_EA_WRREQ[8] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[8] / TCC_EA_ATOMIC[8]) if - (TCC_EA_ATOMIC[8] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8]) / $denom)) - tips: - '9': - hit rate: AVG((((100 * TCC_HIT[9]) / (TCC_HIT[9] + TCC_MISS[9])) if ((TCC_HIT[9] - + TCC_MISS[9]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[9]) / $denom)) - read req: AVG((TO_INT(TCC_READ[9]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[9]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[9]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[9]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[9]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[9]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[9] / TCC_EA_RDREQ[9]) if (TCC_EA_RDREQ[9] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[9] / TCC_EA_WRREQ[9]) if (TCC_EA_WRREQ[9] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[9] / TCC_EA_ATOMIC[9]) if - (TCC_EA_ATOMIC[9] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9]) / $denom)) - tips: - '10': - hit rate: AVG((((100 * TCC_HIT[10]) / (TCC_HIT[10] + TCC_MISS[10])) if ((TCC_HIT[10] - + TCC_MISS[10]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[10]) / $denom)) - read req: AVG((TO_INT(TCC_READ[10]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[10]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[10]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[10]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[10]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[10]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[10] / TCC_EA_RDREQ[10]) if (TCC_EA_RDREQ[10] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[10] / TCC_EA_WRREQ[10]) if (TCC_EA_WRREQ[10] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[10] / TCC_EA_ATOMIC[10]) if - (TCC_EA_ATOMIC[10] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10]) / $denom)) - tips: - '11': - hit rate: AVG((((100 * TCC_HIT[11]) / (TCC_HIT[11] + TCC_MISS[11])) if ((TCC_HIT[11] - + TCC_MISS[11]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[11]) / $denom)) - read req: AVG((TO_INT(TCC_READ[11]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[11]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[11]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[11]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[11]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[11]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[11] / TCC_EA_RDREQ[11]) if (TCC_EA_RDREQ[11] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[11] / TCC_EA_WRREQ[11]) if (TCC_EA_WRREQ[11] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[11] / TCC_EA_ATOMIC[11]) if - (TCC_EA_ATOMIC[11] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11]) / $denom)) - tips: - '12': - hit rate: AVG((((100 * TCC_HIT[12]) / (TCC_HIT[12] + TCC_MISS[12])) if ((TCC_HIT[12] - + TCC_MISS[12]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[12]) / $denom)) - read req: AVG((TO_INT(TCC_READ[12]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[12]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[12]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[12]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[12]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[12]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[12] / TCC_EA_RDREQ[12]) if (TCC_EA_RDREQ[12] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[12] / TCC_EA_WRREQ[12]) if (TCC_EA_WRREQ[12] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[12] / TCC_EA_ATOMIC[12]) if - (TCC_EA_ATOMIC[12] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12]) / $denom)) - tips: - '13': - hit rate: AVG((((100 * TCC_HIT[13]) / (TCC_HIT[13] + TCC_MISS[13])) if ((TCC_HIT[13] - + TCC_MISS[13]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[13]) / $denom)) - read req: AVG((TO_INT(TCC_READ[13]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[13]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[13]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[13]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[13]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[13]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[13] / TCC_EA_RDREQ[13]) if (TCC_EA_RDREQ[13] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[13] / TCC_EA_WRREQ[13]) if (TCC_EA_WRREQ[13] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[13] / TCC_EA_ATOMIC[13]) if - (TCC_EA_ATOMIC[13] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13]) / $denom)) - tips: - '14': - hit rate: AVG((((100 * TCC_HIT[14]) / (TCC_HIT[14] + TCC_MISS[14])) if ((TCC_HIT[14] - + TCC_MISS[14]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[14]) / $denom)) - read req: AVG((TO_INT(TCC_READ[14]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[14]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[14]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[14]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[14]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[14]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[14] / TCC_EA_RDREQ[14]) if (TCC_EA_RDREQ[14] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[14] / TCC_EA_WRREQ[14]) if (TCC_EA_WRREQ[14] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[14] / TCC_EA_ATOMIC[14]) if - (TCC_EA_ATOMIC[14] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14]) / $denom)) - tips: - '15': - hit rate: AVG((((100 * TCC_HIT[15]) / (TCC_HIT[15] + TCC_MISS[15])) if ((TCC_HIT[15] - + TCC_MISS[15]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[15]) / $denom)) - read req: AVG((TO_INT(TCC_READ[15]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[15]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[15]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[15]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[15]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[15]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[15] / TCC_EA_RDREQ[15]) if (TCC_EA_RDREQ[15] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[15] / TCC_EA_WRREQ[15]) if (TCC_EA_WRREQ[15] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[15] / TCC_EA_ATOMIC[15]) if - (TCC_EA_ATOMIC[15] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15]) / $denom)) - tips: + "::_1": + expr: + (((100 * TCC_HIT[::_1]) / (TCC_HIT[::_1] + TCC_MISS[::_1])) if ((TCC_HIT[::_1] + + TCC_MISS[::_1]) != 0) else None) + placeholder_range: + "::_1": 32 + cli_style: simple_box + - metric_table: id: 1803 - title: Channel 16-31 - columnwise: True + title: Requests (Requests) header: - channel: Channel - hit rate: L2 Cache Hit Rate (%) - req: Requests (Requests) - read req: L1-L2 Read (Requests) - write req: L1-L2 Write (Requests) - atomic req: L1-L2 Atomic (Requests) - ea read req: L2-EA Read (Requests) - ea write req: L2-EA Write (Requests) - ea atomic req: L2-EA Atomic (Requests) - ea read lat - cycles: L2-EA Read Latency (Cycles) - ea write lat - cycles: L2-EA Write Latency (Cycles) - ea atomic lat - cycles: L2-EA Atomic Latency (Cycles) - ea read stall - io: L2-EA Read Stall - IO (Cycles per) - ea read stall - gmi: L2-EA Read Stall - GMI (Cycles per) - ea read stall - dram: L2-EA Read Stall - DRAM (Cycles per) - ea write stall - io: L2-EA Write Stall - IO (Cycles per) - ea write stall - gmi: L2-EA Write Stall - GMI (Cycles per) - ea write stall - dram: L2-EA Write Stall - DRAM (Cycles per) - ea write stall - starve: L2-EA Write Stall - Starve (Cycles per) - tips: Tips - metric: - '16': - hit rate: AVG((((100 * TCC_HIT[16]) / (TCC_HIT[16] + TCC_MISS[16])) if ((TCC_HIT[16] - + TCC_MISS[16]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[16]) / $denom)) - read req: AVG((TO_INT(TCC_READ[16]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[16]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[16]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[16]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[16]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[16]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[16] / TCC_EA_RDREQ[16]) if (TCC_EA_RDREQ[16] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[16] / TCC_EA_WRREQ[16]) if (TCC_EA_WRREQ[16] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[16] / TCC_EA_ATOMIC[16]) if - (TCC_EA_ATOMIC[16] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16]) / $denom)) - tips: - '17': - hit rate: AVG((((100 * TCC_HIT[17]) / (TCC_HIT[17] + TCC_MISS[17])) if ((TCC_HIT[17] - + TCC_MISS[17]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[17]) / $denom)) - read req: AVG((TO_INT(TCC_READ[17]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[17]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[17]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[17]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[17]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[17]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[17] / TCC_EA_RDREQ[17]) if (TCC_EA_RDREQ[17] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[17] / TCC_EA_WRREQ[17]) if (TCC_EA_WRREQ[17] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[17] / TCC_EA_ATOMIC[17]) if - (TCC_EA_ATOMIC[17] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17]) / $denom)) - tips: - '18': - hit rate: AVG((((100 * TCC_HIT[18]) / (TCC_HIT[18] + TCC_MISS[18])) if ((TCC_HIT[18] - + TCC_MISS[18]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[18]) / $denom)) - read req: AVG((TO_INT(TCC_READ[18]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[18]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[18]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[18]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[18]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[18]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[18] / TCC_EA_RDREQ[18]) if (TCC_EA_RDREQ[18] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[18] / TCC_EA_WRREQ[18]) if (TCC_EA_WRREQ[18] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[18] / TCC_EA_ATOMIC[18]) if - (TCC_EA_ATOMIC[18] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18]) / $denom)) - tips: - '19': - hit rate: AVG((((100 * TCC_HIT[19]) / (TCC_HIT[19] + TCC_MISS[19])) if ((TCC_HIT[19] - + TCC_MISS[19]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[19]) / $denom)) - read req: AVG((TO_INT(TCC_READ[19]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[19]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[19]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[19]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[19]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[19]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[19] / TCC_EA_RDREQ[19]) if (TCC_EA_RDREQ[19] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[19] / TCC_EA_WRREQ[19]) if (TCC_EA_WRREQ[19] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[19] / TCC_EA_ATOMIC[19]) if - (TCC_EA_ATOMIC[19] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19]) / $denom)) - tips: - '20': - hit rate: AVG((((100 * TCC_HIT[20]) / (TCC_HIT[20] + TCC_MISS[20])) if ((TCC_HIT[20] - + TCC_MISS[20]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[20]) / $denom)) - read req: AVG((TO_INT(TCC_READ[20]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[20]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[20]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[20]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[20]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[20]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[20] / TCC_EA_RDREQ[20]) if (TCC_EA_RDREQ[20] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[20] / TCC_EA_WRREQ[20]) if (TCC_EA_WRREQ[20] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[20] / TCC_EA_ATOMIC[20]) if - (TCC_EA_ATOMIC[20] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20]) / $denom)) - tips: - '21': - hit rate: AVG((((100 * TCC_HIT[21]) / (TCC_HIT[21] + TCC_MISS[21])) if ((TCC_HIT[21] - + TCC_MISS[21]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[21]) / $denom)) - read req: AVG((TO_INT(TCC_READ[21]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[21]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[21]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[21]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[21]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[21]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[21] / TCC_EA_RDREQ[21]) if (TCC_EA_RDREQ[21] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[21] / TCC_EA_WRREQ[21]) if (TCC_EA_WRREQ[21] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[21] / TCC_EA_ATOMIC[21]) if - (TCC_EA_ATOMIC[21] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21]) / $denom)) - tips: - '22': - hit rate: AVG((((100 * TCC_HIT[22]) / (TCC_HIT[22] + TCC_MISS[22])) if ((TCC_HIT[22] - + TCC_MISS[22]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[22]) / $denom)) - read req: AVG((TO_INT(TCC_READ[22]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[22]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[22]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[22]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[22]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[22]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[22] / TCC_EA_RDREQ[22]) if (TCC_EA_RDREQ[22] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[22] / TCC_EA_WRREQ[22]) if (TCC_EA_WRREQ[22] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[22] / TCC_EA_ATOMIC[22]) if - (TCC_EA_ATOMIC[22] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22]) / $denom)) - tips: - '23': - hit rate: AVG((((100 * TCC_HIT[23]) / (TCC_HIT[23] + TCC_MISS[23])) if ((TCC_HIT[23] - + TCC_MISS[23]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[23]) / $denom)) - read req: AVG((TO_INT(TCC_READ[23]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[23]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[23]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[23]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[23]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[23]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[23] / TCC_EA_RDREQ[23]) if (TCC_EA_RDREQ[23] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[23] / TCC_EA_WRREQ[23]) if (TCC_EA_WRREQ[23] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[23] / TCC_EA_ATOMIC[23]) if - (TCC_EA_ATOMIC[23] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23]) / $denom)) - tips: - '24': - hit rate: AVG((((100 * TCC_HIT[24]) / (TCC_HIT[24] + TCC_MISS[24])) if ((TCC_HIT[24] - + TCC_MISS[24]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[24]) / $denom)) - read req: AVG((TO_INT(TCC_READ[24]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[24]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[24]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[24]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[24]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[24]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[24] / TCC_EA_RDREQ[24]) if (TCC_EA_RDREQ[24] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[24] / TCC_EA_WRREQ[24]) if (TCC_EA_WRREQ[24] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[24] / TCC_EA_ATOMIC[24]) if - (TCC_EA_ATOMIC[24] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24]) / $denom)) - tips: - '25': - hit rate: AVG((((100 * TCC_HIT[25]) / (TCC_HIT[25] + TCC_MISS[25])) if ((TCC_HIT[25] - + TCC_MISS[25]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[25]) / $denom)) - read req: AVG((TO_INT(TCC_READ[25]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[25]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[25]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[25]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[25]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[25]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[25] / TCC_EA_RDREQ[25]) if (TCC_EA_RDREQ[25] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[25] / TCC_EA_WRREQ[25]) if (TCC_EA_WRREQ[25] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[25] / TCC_EA_ATOMIC[25]) if - (TCC_EA_ATOMIC[25] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25]) / $denom)) - tips: - '26': - hit rate: AVG((((100 * TCC_HIT[26]) / (TCC_HIT[26] + TCC_MISS[26])) if ((TCC_HIT[26] - + TCC_MISS[26]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[26]) / $denom)) - read req: AVG((TO_INT(TCC_READ[26]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[26]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[26]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[26]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[26]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[26]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[26] / TCC_EA_RDREQ[26]) if (TCC_EA_RDREQ[26] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[26] / TCC_EA_WRREQ[26]) if (TCC_EA_WRREQ[26] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[26] / TCC_EA_ATOMIC[26]) if - (TCC_EA_ATOMIC[26] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26]) / $denom)) - tips: - '27': - hit rate: AVG((((100 * TCC_HIT[27]) / (TCC_HIT[27] + TCC_MISS[27])) if ((TCC_HIT[27] - + TCC_MISS[27]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[27]) / $denom)) - read req: AVG((TO_INT(TCC_READ[27]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[27]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[27]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[27]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[27]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[27]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[27] / TCC_EA_RDREQ[27]) if (TCC_EA_RDREQ[27] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[27] / TCC_EA_WRREQ[27]) if (TCC_EA_WRREQ[27] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[27] / TCC_EA_ATOMIC[27]) if - (TCC_EA_ATOMIC[27] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27]) / $denom)) - tips: - '28': - hit rate: AVG((((100 * TCC_HIT[28]) / (TCC_HIT[28] + TCC_MISS[28])) if ((TCC_HIT[28] - + TCC_MISS[28]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[28]) / $denom)) - read req: AVG((TO_INT(TCC_READ[28]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[28]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[28]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[28]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[28]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[28]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[28] / TCC_EA_RDREQ[28]) if (TCC_EA_RDREQ[28] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[28] / TCC_EA_WRREQ[28]) if (TCC_EA_WRREQ[28] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[28] / TCC_EA_ATOMIC[28]) if - (TCC_EA_ATOMIC[28] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28]) / $denom)) - tips: - '29': - hit rate: AVG((((100 * TCC_HIT[29]) / (TCC_HIT[29] + TCC_MISS[29])) if ((TCC_HIT[29] - + TCC_MISS[29]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[29]) / $denom)) - read req: AVG((TO_INT(TCC_READ[29]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[29]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[29]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[29]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[29]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[29]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[29] / TCC_EA_RDREQ[29]) if (TCC_EA_RDREQ[29] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[29] / TCC_EA_WRREQ[29]) if (TCC_EA_WRREQ[29] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[29] / TCC_EA_ATOMIC[29]) if - (TCC_EA_ATOMIC[29] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29]) / $denom)) - tips: - '30': - hit rate: AVG((((100 * TCC_HIT[30]) / (TCC_HIT[30] + TCC_MISS[30])) if ((TCC_HIT[30] - + TCC_MISS[30]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[30]) / $denom)) - read req: AVG((TO_INT(TCC_READ[30]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[30]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[30]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[30]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[30]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[30]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[30] / TCC_EA_RDREQ[30]) if (TCC_EA_RDREQ[30] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[30] / TCC_EA_WRREQ[30]) if (TCC_EA_WRREQ[30] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[30] / TCC_EA_ATOMIC[30]) if - (TCC_EA_ATOMIC[30] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30]) / $denom)) - tips: - '31': - hit rate: AVG((((100 * TCC_HIT[31]) / (TCC_HIT[31] + TCC_MISS[31])) if ((TCC_HIT[31] - + TCC_MISS[31]) != 0) else None)) - req: AVG((TO_INT(TCC_REQ[31]) / $denom)) - read req: AVG((TO_INT(TCC_READ[31]) / $denom)) - write req: AVG((TO_INT(TCC_WRITE[31]) / $denom)) - atomic req: AVG((TO_INT(TCC_ATOMIC[31]) / $denom)) - ea read req: AVG((TO_INT(TCC_EA_RDREQ[31]) / $denom)) - ea write req: AVG((TO_INT(TCC_EA_WRREQ[31]) / $denom)) - ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[31]) / $denom)) - ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[31] / TCC_EA_RDREQ[31]) if (TCC_EA_RDREQ[31] - != 0) else None)) - ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[31] / TCC_EA_WRREQ[31]) if (TCC_EA_WRREQ[31] - != 0) else None)) - ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[31] / TCC_EA_ATOMIC[31]) if - (TCC_EA_ATOMIC[31] != 0) else None)) - ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31]) / $denom)) - ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31]) / $denom)) - ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31]) / $denom)) - ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31]) / $denom)) - ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31]) / $denom)) - ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31]) / $denom)) - ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31]) / $denom)) - tips: + metric: Metric + expr: Expression + metric: + "::_1": + expr: (TO_INT(TCC_REQ[::_1]) / $denom) + placeholder_range: + "::_1": 32 + cli_style: simple_box + + - metric_table: + id: 1804 + title: L1-L2 Access (Requests) + header: + metric: Metric + read req: L1-L2 Read + write req: L1-L2 Write + atomic req: L1-L2 Atomic + metric: + "::_1": + read req: AVG((TO_INT(TCC_READ[::_1]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[::_1]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[::_1]) / $denom)) + placeholder_range: + "::_1": 32 + cli_style: simple_multiple_bar + + - metric_table: + id: 1805 + title: L2-EA Access (Requests) + header: + metric: Metric + read req: L2-EA Read + write req: L2-EA Write + atomic req: L2-EA Atomic + metric: + "::_1": + read req: AVG((TO_INT(TCC_EA_RDREQ[::_1]) / $denom)) + write req: AVG((TO_INT(TCC_EA_WRREQ[::_1]) / $denom)) + atomic req: AVG((TO_INT(TCC_EA_ATOMIC[::_1]) / $denom)) + placeholder_range: + "::_1": 32 + cli_style: simple_multiple_bar + + # - metric_table: + # id: 1806 + # title: L2-EA Latency (Cycles) + # header: + # metric: Metric + # read lat: L2-EA Read + # write lat: L2-EA Write + # atomic lat: L2-EA Atomic + # metric: + # "::_1": + # read lat: + # AVG(((TCC_EA_RDREQ_LEVEL[::_1] / TCC_EA_RDREQ[::_1]) if (TCC_EA_RDREQ[::_1] + # != 0) else None)) + # write lat: + # AVG(((TCC_EA_WRREQ_LEVEL[::_1] / TCC_EA_WRREQ[::_1]) if (TCC_EA_WRREQ[::_1] + # != 0) else None)) + # atomic lat: + # AVG(((TCC_EA_ATOMIC_LEVEL[::_1] / TCC_EA_ATOMIC[::_1]) if + # (TCC_EA_ATOMIC[::_1] != 0) else 0)) + # placeholder_range: + # "::_1": 32 + # cli_style: simple_multiple_bar + + - metric_table: + id: 1806 + title: L2-EA Read Latency (Cycles) + header: + metric: Metric + expr: Expression + metric: + "::_1": + expr: + ((TCC_EA_RDREQ_LEVEL[::_1] / TCC_EA_RDREQ[::_1]) if (TCC_EA_RDREQ[::_1] + != 0) else None) + placeholder_range: + "::_1": 32 + cli_style: simple_box + + - metric_table: + id: 1807 + title: L2-EA Write Latency (Cycles) + header: + metric: Metric + expr: Expression + metric: + "::_1": + expr: + ((TCC_EA_WRREQ_LEVEL[::_1] / TCC_EA_WRREQ[::_1]) if (TCC_EA_WRREQ[::_1] + != 0) else None) + placeholder_range: + "::_1": 32 + cli_style: simple_box + + - metric_table: + id: 1808 + title: L2-EA Atomic Latency (Cycles) + header: + metric: Metric + expr: Expression + metric: + "::_1": + expr: ((TCC_EA_ATOMIC_LEVEL[::_1] / TCC_EA_ATOMIC[::_1]) if + (TCC_EA_ATOMIC[::_1] != 0) else 0) + placeholder_range: + "::_1": 32 + cli_style: simple_box + + - metric_table: + id: 1809 + title: L2-EA Read Stall (Cycles per normUnit) + header: + metric: Metric + ea read stall - io: L2-EA Read Stall - IO + ea read stall - gmi: L2-EA Read Stall - GMI + ea read stall - dram: L2-EA Read Stall - DRAM + metric: + "::_1": + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[::_1]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[::_1]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[::_1]) / $denom)) + placeholder_range: + "::_1": 32 + cli_style: simple_multiple_bar + + - metric_table: + id: 1810 + title: L2-EA Write Stall (Cycles per normUnit) + header: + metric: Metric + ea write stall - io: L2-EA Write Stall - IO + ea write stall - gmi: L2-EA Write Stall - GMI + ea write stall - dram: L2-EA Write Stall - DRAM + ea write stall - starve: L2-EA Write Stall - Starve + metric: + "::_1": + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[::_1]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[::_1]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[::_1]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[::_1]) / $denom)) + placeholder_range: + "::_1": 32 + cli_style: simple_multiple_bar \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1900_memory_chart.yaml b/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1900_memory_chart.yaml deleted file mode 100644 index c0d086f121..0000000000 --- a/projects/rocprofiler-compute/src/omniperf_soc/analysis_configs/gfx90a/1900_memory_chart.yaml +++ /dev/null @@ -1,259 +0,0 @@ ---- -# Add description/tips for each metric in this section. -# So it could be shown in hover. -Metric Description: - -# Define the panel properties and properties of each metric in the panel. -Panel Config: - id: 1900 - title: Memory Chart Analysis - data source: - - metric_table: - id: 1901 - title: # subtitle for this table(optional) - header: - metric: Metric - value: Value - alias: Alias - tips: Tips - metric: - Wave Life: - value: ROUND(AVG(((4 * (SQ_WAVE_CYCLES / SQ_WAVES)) if (SQ_WAVES != 0) else - None)), 0) - alias: wave_life_ - tips: - Active CUs: - value: CONCAT(CONCAT($numActiveCUs, "/"), $numCU) - alias: active_cu_ - tips: - SALU: - value: ROUND(AVG((SQ_INSTS_SALU / $denom)), 0) - alias: salu_ - tips: - SMEM: - value: ROUND(AVG((SQ_INSTS_SMEM / $denom)), 0) - alias: smem_ - tips: - VALU: - value: ROUND(AVG((SQ_INSTS_VALU / $denom)), 0) - alias: valu_ - tips: - MFMA: - value: ROUND(AVG((SQ_INSTS_MFMA / $denom)), 0) - alias: mfma_ - tips: - VMEM: - value: ROUND(AVG((SQ_INSTS_VMEM / $denom)), 0) - alias: vmem_ - tips: - LDS: - value: ROUND(AVG((SQ_INSTS_LDS / $denom)), 0) - alias: lds_ - tips: - GWS: - value: ROUND(AVG((SQ_INSTS_GDS / $denom)), 0) - alias: gws_ - tips: - BR: - value: ROUND(AVG((SQ_INSTS_BRANCH / $denom)), 0) - alias: br_ - tips: - VGPR: - value: ROUND(AVG(vgpr), 0) - alias: vgpr_ - tips: - SGPR: - value: ROUND(AVG(sgpr), 0) - alias: sgpr_ - tips: - LDS Allocation: - value: ROUND(AVG(lds), 0) - alias: lds_alloc_ - tips: - Scratch Allocation: - value: ROUND(AVG(scr), 0) - alias: scratch_alloc_ - tips: - Wavefronts: - value: ROUND(AVG(SPI_CSN_WAVE), 0) - alias: wavefronts_ - tips: - Workgroups: - value: ROUND(AVG(SPI_CSN_NUM_THREADGROUPS), 0) - alias: workgroups_ - tips: - LDS Req: - value: ROUND(AVG((SQ_INSTS_LDS / $denom)), 0) - alias: lds_req_ - tips: - IL1 Fetch: - value: ROUND(AVG((SQC_ICACHE_REQ / $denom)), 0) - alias: il1_fetch_ - tips: - IL1 Hit: - value: ROUND((AVG((SQC_ICACHE_HITS / SQC_ICACHE_REQ)) * 100), 0) - alias: il1_hit_ - tips: - IL1_L2 Rd: - value: ROUND(AVG((SQC_TC_INST_REQ / $denom)), 0) - alias: il1_l2_req_ - tips: - vL1D Rd: - value: ROUND(AVG((SQC_DCACHE_REQ / $denom)), 0) - alias: sl1_rd_ - tips: - vL1D Hit: - value: ROUND((AVG(((SQC_DCACHE_HITS / SQC_DCACHE_REQ) if (SQC_DCACHE_REQ != - 0) else None)) * 100), 0) - alias: sl1_hit_ - tips: - vL1D_L2 Rd: - value: ROUND(AVG((SQC_TC_DATA_READ_REQ / $denom)), 0) - alias: sl1_l2_rd_ - tips: - vL1D_L2 Wr: - value: ROUND(AVG((SQC_TC_DATA_WRITE_REQ / $denom)), 0) - alias: sl1_l2_wr_ - tips: - vL1D_L2 Atomic: - value: ROUND(AVG((SQC_TC_DATA_ATOMIC_REQ / $denom)), 0) - alias: sl1_l2_atom_ - tips: - VL1 Rd: - value: ROUND(AVG((TCP_TOTAL_READ_sum / $denom)), 0) - alias: vl1_rd_ - tips: - VL1 Wr: - value: ROUND(AVG((TCP_TOTAL_WRITE_sum / $denom)), 0) - alias: vl1_wr_ - tips: - VL1 Atomic: - value: ROUND(AVG(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) - / $denom)), 0) - alias: vl1_atom_ - tips: - VL1 Hit: - value: ROUND(AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) - + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) - / TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else - None)), 0) - alias: vl1_hit_ - tips: - VL1 Lat: - value: ROUND(AVG(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum - != 0) else None)), 0) - alias: vl1_lat_ - tips: - VL1_L2 Rd: - value: ROUND(AVG((TCP_TCC_READ_REQ_sum / $denom)), 0) - alias: vl1_l2_rd_ - tips: - VL1_L2 Wr: - value: ROUND(AVG((TCP_TCC_WRITE_REQ_sum / $denom)), 0) - alias: vl1_l2_wr_ - tips: - vL1_L2 Atomic: - value: ROUND(AVG(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) - / $denom)), 0) - alias: vl1_l2_atom_ - tips: - L2 Rd: - value: ROUND(AVG((TCC_READ_sum / $denom)), 0) - alias: l2_rd_ - tips: - L2 Wr: - value: ROUND(AVG((TCC_WRITE_sum / $denom)), 0) - alias: l2_wr_ - tips: - L2 Atomic: - value: ROUND(AVG((TCC_ATOMIC_sum / $denom)), 0) - alias: l2_atom_ - tips: - L2 Hit: - value: ROUND(AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum - + TCC_MISS_sum) != 0) else None)), 0) - alias: l2_hit_ - tips: - L2 Rd Lat: - value: ROUND(AVG(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) - if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)), - 0) - alias: l2_rd_lat_ - tips: - L2 Wr Lat: - value: ROUND(AVG(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + - TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) - != 0) else None)), 0) - alias: l2_wr_lat_ - tips: - Fabric Rd Lat: - value: ROUND(AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum - != 0) else None)), 0) - alias: fabric_rd_lat_ - tips: - Fabric Wr Lat: - value: ROUND(AVG(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum - != 0) else None)), 0) - alias: fabric_wr_lat_ - tips: - Fabric Atomic Lat: - value: ROUND(AVG(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum - != 0) else None)), 0) - alias: fabric_atom_lat_ - tips: - Fabric_L2 Rd: - value: ROUND(AVG((TCC_EA_RDREQ_sum / $denom)), 0) - alias: l2_fabric_rd_ - tips: - Fabric_L2 Wr: - value: ROUND(AVG((TCC_EA_WRREQ_sum / $denom)), 0) - alias: l2_fabric_wr_ - tips: - Fabric_l2 Atomic: - value: ROUND(AVG((TCC_EA_ATOMIC_sum / $denom)), 0) - alias: l2_fabric_atom_ - tips: - HBM Rd: - value: ROUND(AVG((TCC_EA_RDREQ_DRAM_sum / $denom)), 0) - alias: hbm_rd_ - tips: - HBM Wr: - value: ROUND(AVG((TCC_EA_WRREQ_DRAM_sum / $denom)), 0) - alias: hbm_wr_ - tips: - LDS Util: - value: ROUND(AVG(((100 * SQ_LDS_IDX_ACTIVE) / (GRBM_GUI_ACTIVE * $numCU))), - 0) - alias: lds_util_ - tips: - VL1 Coalesce: - value: ROUND(AVG(((((TA_TOTAL_WAVEFRONTS_sum * 64) * 100) / (TCP_TOTAL_ACCESSES_sum - * 4)) if (TCP_TOTAL_ACCESSES_sum != 0) else 0)), 0) - alias: vl1_coales_ - tips: - VL1 Stall: - value: ROUND(AVG((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) - if (TCP_GATE_EN1_sum != 0) else None)), 0) - alias: vl1_stall_ - tips: - LDS Lat: - value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) - if (SQ_INSTS_LDS != 0) else None)), 0) - alias: lds_lat_ - coll_level: SQ_INST_LEVEL_LDS - tips: - vL1D Lat: - value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQC_DCACHE_REQ) - if (SQC_DCACHE_REQ != 0) else None)), 0) - alias: sl1_lat_ - tips: - IL1 Lat: - value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQC_ICACHE_REQ) - if (SQC_ICACHE_REQ != 0) else None)), 0) - alias: il1_lat_ - tips: - Wave Occupancy: - value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE) / $numActiveCUs)), 0) - alias: wave_occ_ - coll_level: SQ_LEVEL_WAVES - tips: