From 27266eb24276e8989ef6742a2508fb7bdf3dd52e Mon Sep 17 00:00:00 2001 From: "Baraldi, Giovanni" Date: Thu, 9 Jan 2025 22:27:16 +0100 Subject: [PATCH] SWDEV-508485: Adding MFMA F8 metric (#112) Co-authored-by: Giovanni Baraldi --- .../counters/yaml/counter_defs.yaml | 88 +++++++++++-------- 1 file changed, 51 insertions(+), 37 deletions(-) diff --git a/source/lib/rocprofiler-sdk/counters/yaml/counter_defs.yaml b/source/lib/rocprofiler-sdk/counters/yaml/counter_defs.yaml index 84917e7459..68708e7711 100644 --- a/source/lib/rocprofiler-sdk/counters/yaml/counter_defs.yaml +++ b/source/lib/rocprofiler-sdk/counters/yaml/counter_defs.yaml @@ -1303,7 +1303,7 @@ SQ_INSTS_VALU_ADD_F16: block: SQ event: 27 description: The number of VALU (Vector ALU) ADD/SUB instructions on float16. For maximum performance - lower percision floating point ops are preferred to higher percision ones. The value is returned per-SE + lower precision floating point ops are preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on VALU instructions. SQ_INSTS_VALU_ADD_F32: architectures: @@ -1311,15 +1311,15 @@ SQ_INSTS_VALU_ADD_F32: block: SQ event: 31 description: The number of VALU (Vector ALU) ADD/SUB instructions on float32. For maximum performance - lower percision floating point ops are preferred to higher percision ones. The value is returned per-SE + lower precision floating point ops are preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on VALU instructions. SQ_INSTS_VALU_ADD_F64: architectures: gfx942/gfx941/gfx940/gfx90a: block: SQ event: 35 - description: The number of VALU ADD/SUB instructions on float64. For maximum performance lower percision - floating point ops are preferred to higher percision ones. The value is returned per-SE (aggregate + description: The number of VALU ADD/SUB instructions on float64. For maximum performance lower precision + floating point ops are preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on VALU instructions. SQ_INSTS_VALU_CVT: architectures: @@ -1335,7 +1335,7 @@ SQ_INSTS_VALU_FMA_F16: block: SQ event: 29 description: The number of VALU (Vector ALU) FMA (Fused-Multiply-Add)/MAD(Multiply-Add) instructions - on float16. For maximum performance lower percision floating point ops are preferred to higher percision + on float16. For maximum performance lower precision floating point ops are preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on VALU instructions. SQ_INSTS_VALU_FMA_F32: @@ -1344,7 +1344,7 @@ SQ_INSTS_VALU_FMA_F32: block: SQ event: 33 description: The number of VALU (Vector ALU) FMA (Fused-Multiply-Add)/MAD(Multiply-Add) instructions - on float32. For maximum performance lower percision floating point ops are preferred to higher percision + on float32. For maximum performance lower precision floating point ops are preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on VALU instructions. SQ_INSTS_VALU_FMA_F64: @@ -1353,7 +1353,7 @@ SQ_INSTS_VALU_FMA_F64: block: SQ event: 37 description: The number of VALU (Vector ALU) FMA (Fused-Multiply-Add)/MAD(Multiply-Add) instructions - on float64. For maximum performance lower percision floating point ops are preferred to higher percision + on float64. For maximum performance lower precision floating point ops are preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on VALU instructions. SQ_INSTS_VALU_INT32: @@ -1377,44 +1377,51 @@ SQ_INSTS_VALU_MFMA_BF16: gfx942/gfx941/gfx940/gfx90a: block: SQ event: 44 - description: The number of VALU (Vector ALU) MFMA (Matrix-Fused-Multiply-Add) BF16 (outputing bfloat16 - format) instructions (V_MFMA_*_BF16). For maximum performance lower percision floating point ops are - preferred to higher percision ones. The value is returned per-SE (aggregate of values in SIMDs in + description: The number of MFMA (Matrix-Fused-Multiply-Add) operating on BF16 format + (V_MFMA or V_SMFMAC). For maximum performance lower precision floating point ops are + preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on MFMA instructions. SQ_INSTS_VALU_MFMA_F16: architectures: gfx942/gfx941/gfx940/gfx90a: block: SQ event: 43 - description: The number of VALU (Vector ALU) MFMA (Matrix-Fused-Multiply-Add) F16 (outputing float16 - format) instructions (V_MFMA_*_F16). For maximum performance lower percision floating point ops are - preferred to higher percision ones. The value is returned per-SE (aggregate of values in SIMDs in + description: The number of MFMA (Matrix-Fused-Multiply-Add) operating on F16 format + (V_MFMA or V_SMFMAC). For maximum performance lower precision floating point ops are + preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on MFMA instructions. SQ_INSTS_VALU_MFMA_F32: architectures: gfx942/gfx941/gfx940/gfx90a: block: SQ event: 45 - description: The number of VALU (Vector ALU) MFMA (Matrix-Fused-Multiply-Add) F32 (outputing float32 - format) instructions (V_MFMA_*_F32). For maximum performance lower percision floating point ops are - preferred to higher percision ones. The value is returned per-SE (aggregate of values in SIMDs in + description: The number of MFMA (Matrix-Fused-Multiply-Add) operating on F32 format + (V_MFMA or V_SMFMAC). For maximum performance lower precision floating point ops are + preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on MFMA instructions. SQ_INSTS_VALU_MFMA_F64: architectures: gfx942/gfx941/gfx940/gfx90a: block: SQ event: 46 - description: The number of VALU (Vector ALU) MFMA (Matrix-Fused-Multiply-Add) F64 (outputing float32 - format) instructions (V_MFMA_*_F64). For maximum performance lower percision floating point ops are - preferred to higher percision ones. The value is returned per-SE (aggregate of values in SIMDs in + description: The number of MFMA (Matrix-Fused-Multiply-Add) operating on F64 format + (V_MFMA_F64_*). For maximum performance lower precision floating point ops are + preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on MFMA instructions. SQ_INSTS_VALU_MFMA_I8: architectures: gfx942/gfx941/gfx940/gfx90a: block: SQ event: 42 - description: The number of VALU (Vector ALU) MFMA (Matrix-Fused-Multiply-Add) I8 (outputing 8bit intergers) - instructions (V_MFMA_*_I8). See AMD ISAs for more information on MFMA instructions. + description: The number of MFMA (Matrix-Fused-Multiply-Add) operating on I8 format + (V_MFMA or V_SMFMAC). See AMD ISAs for more information on MFMA instructions. +SQ_INSTS_VALU_MFMA_F8: + architectures: + gfx942/gfx941/gfx940: + block: SQ + event: 48 + description: The number of MFMA (Matrix-Fused-Multiply-Add) operating on F8 format + (V_MFMA or V_SMFMAC). See AMD CDNA3 ISA for more informations. SQ_INSTS_VALU_MFMA_MOPS_BF16: architectures: gfx90a: @@ -1425,7 +1432,7 @@ SQ_INSTS_VALU_MFMA_MOPS_BF16: event: 51 description: The number of math operation instructions on the VALU (Vector ALU) using MFMA (Matrix-Fused-Multiply-Add) and operating on BF16 (bfloat16) data. Captures add or mul ops performed divided by 512. For maximum - performance lower percision floating point ops are preferred to higher percision ones. The value is + performance lower precision floating point ops are preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on MFMA instructions. SQ_INSTS_VALU_MFMA_MOPS_F16: @@ -1438,7 +1445,7 @@ SQ_INSTS_VALU_MFMA_MOPS_F16: event: 50 description: The number of math operation instructions on the VALU (Vector ALU) using MFMA (Matrix-Fused-Multiply-Add) and operating on F16 (float16) data. Captures add or mul ops performed divided by 512. For maximum - performance lower percision floating point ops are preferred to higher percision ones. The value is + performance lower precision floating point ops are preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on MFMA instructions. SQ_INSTS_VALU_MFMA_MOPS_F32: @@ -1451,7 +1458,7 @@ SQ_INSTS_VALU_MFMA_MOPS_F32: event: 52 description: The number of math operation instructions on the VALU (Vector ALU) using MFMA (Matrix-Fused-Multiply-Add) and operating on F32 (float32) data. Captures add or mul ops performed divided by 512. For maximum - performance lower percision floating point ops are preferred to higher percision ones. The value is + performance lower precision floating point ops are preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on MFMA instructions. SQ_INSTS_VALU_MFMA_MOPS_F64: @@ -1464,7 +1471,7 @@ SQ_INSTS_VALU_MFMA_MOPS_F64: event: 53 description: The number of math operation instructions on the VALU (Vector ALU) using MFMA (Matrix-Fused-Multiply-Add) and operating on F64 (float64) data. Captures add or mul ops performed divided by 512. For maximum - performance lower percision floating point ops are preferred to higher percision ones. The value is + performance lower precision floating point ops are preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on MFMA instructions. SQ_INSTS_VALU_MFMA_MOPS_I8: @@ -1479,29 +1486,36 @@ SQ_INSTS_VALU_MFMA_MOPS_I8: and operating on I8 (8 bit int) data. Captures add or mul ops performed divided by 512. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on MFMA instructions. +SQ_INSTS_VALU_MFMA_MOPS_F8: + architectures: + gfx942/gfx941/gfx940: + block: SQ + event: 55 + description: The number of math operation on F8 datatype. Captures add or mul ops performed divided by 512. The value + is returned per-SE (aggregate of values in SIMDs in the SE). See AMD CDNA3 ISA for more information on MFMA F8 instructions. SQ_INSTS_VALU_MUL_F16: architectures: gfx942/gfx941/gfx940/gfx90a: block: SQ event: 28 - description: The number of VALU MUL instructions on float16 data. For maximum performance lower percision - floating point ops are preferred to higher percision ones. The value is returned per-SE (aggregate + description: The number of VALU MUL instructions on float16 data. For maximum performance lower precision + floating point ops are preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on VALU instructions. SQ_INSTS_VALU_MUL_F32: architectures: gfx942/gfx941/gfx940/gfx90a: block: SQ event: 32 - description: The number of VALU MUL instructions on float32 data. For maximum performance lower percision - floating point ops are preferred to higher percision ones. The value is returned per-SE (aggregate + description: The number of VALU MUL instructions on float32 data. For maximum performance lower precision + floating point ops are preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on VALU instructions. SQ_INSTS_VALU_MUL_F64: architectures: gfx942/gfx941/gfx940/gfx90a: block: SQ event: 36 - description: The number of VALU MUL instructions on float64 data. For maximum performance lower percision - floating point ops are preferred to higher percision ones. The value is returned per-SE (aggregate + description: The number of VALU MUL instructions on float64 data. For maximum performance lower precision + floating point ops are preferred to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on VALU instructions. SQ_INSTS_VALU_TRANS_F16: architectures: @@ -1509,8 +1523,8 @@ SQ_INSTS_VALU_TRANS_F16: block: SQ event: 30 description: The number of VALU transcendental instructions on float16 data. Transcendental instructions - include sin, cos, exp, log, etc. For maximum performance lower percision floating point ops are preferred - to higher percision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See + include sin, cos, exp, log, etc. For maximum performance lower precision floating point ops are preferred + to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on VALU instructions. SQ_INSTS_VALU_TRANS_F32: architectures: @@ -1518,8 +1532,8 @@ SQ_INSTS_VALU_TRANS_F32: block: SQ event: 34 description: The number of VALU transcendental instructions on float32 data. Transcendental instructions - include sin, cos, exp, log, etc. For maximum performance lower percision floating point ops are preferred - to higher percision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See + include sin, cos, exp, log, etc. For maximum performance lower precision floating point ops are preferred + to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on VALU instructions. SQ_INSTS_VALU_TRANS_F64: architectures: @@ -1527,8 +1541,8 @@ SQ_INSTS_VALU_TRANS_F64: block: SQ event: 38 description: The number of VALU transcendental instructions on float64 data. Transcendental instructions - include sin, cos, exp, log, etc. For maximum performance lower percision floating point ops are preferred - to higher percision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See + include sin, cos, exp, log, etc. For maximum performance lower precision floating point ops are preferred + to higher precision ones. The value is returned per-SE (aggregate of values in SIMDs in the SE). See AMD ISAs for more information on VALU instructions. SQ_INSTS_VMEM: architectures: