From 27585a8a2bf3a6acd18f486a3f1dfd4d72f3e95b Mon Sep 17 00:00:00 2001 From: vedithal-amd Date: Thu, 3 Apr 2025 02:21:18 -0400 Subject: [PATCH] Support MI 350 profiling (#632) * Add MI 350 hardware information * Refactor MI GPU YAML file and corresponding interface * Add SoC file for gfx950 architecture * Add analysis report configs for MI 350 containing existing metrics * Add placeholder None valued metrics for previous architectures to make baseline comparison work * Enable testing on MI 350 * Analysis config metric changes - SPI changes - Update metric formula for default SPI pipe counter - Use efficiently collected pipe wise SPI counters - Add SPI Wave Occupancy - Add Scheduler-Pipe Wave Utilization - Update formula for VGPR Writes - Add Scheduler-Pipe FIFO Full Rate - CPC changes - Add CPC SYNC FIFO Full Rate - Add CPC CANE Stall Rate - Add CPC ADC Utilization - SQ changes - Add VALU co-issue efficiency - Add F6F4 datatype metrics - Update formula for total FLOPs by adding F6F4 counters - Add LDS STORE / LOAD / ATOMIC metrics - Add LDS STORE / LOAD / ATOMIC bandwidth - Add LDS FIFO and TA ADDR / CMD / DATA FIFO full rates * Collect TCP_TCP_LATENCY_sum only for gfx950 (MI 350) * Do not inject SQ_ACCUM_PREV_HIRES unnecesarily * Do not hardcode memory and shader clock speeds * Write num_hbm_channels to sysinfo.csv instead of hbm_bw while profiling * Move generate sysinfo.csv to pre processing step of profiling * Add warnings to use --specs-correction for missing sysinfo.csv values during analysis phase * Update CHANGELOG * Analysis phase warning to use --specs-correction when needed [ROCm/rocprofiler-compute commit: f9aa7be97cbcd5d96546b9fcbc634210a7e22906] --- projects/rocprofiler-compute/CHANGELOG.md | 34 +- projects/rocprofiler-compute/CMakeLists.txt | 5 +- projects/rocprofiler-compute/src/argparser.py | 2 +- .../rocprof_compute_analyze/analysis_webui.py | 7 +- .../rocprof_compute_profile/profiler_base.py | 30 +- .../gfx906/0200_system-speed-of-light.yaml | 15 +- .../gfx906/0500_command-processor.yaml | 18 + .../gfx906/0600_shader-processor-input.yaml | 21 + .../1000_compute-unit-instruction-mix.yaml | 14 + .../1100_compute-unit-compute-pipeline.yaml | 21 + .../analysis_configs/gfx906/1200_lds.yaml | 56 + .../gfx906/1500_TA_and_TD.yaml | 21 + .../gfx906/1700_L2_cache.yaml | 4 + .../gfx908/0200_system-speed-of-light.yaml | 15 +- .../gfx908/0500_command-processor.yaml | 21 + .../gfx908/0600_shader-processor-input.yaml | 21 + .../1000_compute-unit-instruction-mix.yaml | 14 + .../1100_compute-unit-compute-pipeline.yaml | 21 + .../analysis_configs/gfx908/1200_lds.yaml | 56 + .../gfx908/1500_TA_and_TD.yaml | 21 + .../gfx908/1700_L2_cache.yaml | 4 + .../gfx90a/0200_system-speed-of-light.yaml | 15 +- .../gfx90a/0500_command-processor.yaml | 18 + .../gfx90a/0600_shader-processor-input.yaml | 21 + .../1000_compute-unit-instruction-mix.yaml | 14 + .../1100_compute-unit-compute-pipeline.yaml | 21 + .../analysis_configs/gfx90a/1200_lds.yaml | 56 + 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6 - .../src/rocprof_compute_soc/soc_gfx942.py | 6 - .../src/rocprof_compute_soc/soc_gfx950.py | 117 + projects/rocprofiler-compute/src/utils/gui.py | 5 +- .../src/utils/mi_gpu_spec.py | 122 +- .../src/utils/mi_gpu_spec.yaml | 62 +- .../rocprofiler-compute/src/utils/parser.py | 68 +- .../rocprofiler-compute/src/utils/specs.py | 40 +- .../rocprofiler-compute/src/utils/utils.py | 83 +- .../tests/test_TCP_counters.py | 2 +- .../tests/test_analyze_commands.py | 7 +- .../tests/test_analyze_workloads.py | 7 + .../tests/test_profile_general.py | 218 +- .../workloads/device_filter/MI100/sysinfo.csv | 4 +- .../workloads/device_filter/MI200/sysinfo.csv | 4 +- .../MI300A_A1/pmc_dispatch_info.csv | 4 + .../device_filter/MI300A_A1/sysinfo.csv | 4 +- .../MI300X_A1/pmc_dispatch_info.csv | 4 + .../device_filter/MI300X_A1/sysinfo.csv | 4 +- .../device_inv_int/MI100/sysinfo.csv | 4 +- .../device_inv_int/MI200/sysinfo.csv | 4 +- .../MI300A_A1/pmc_dispatch_info.csv | 4 + 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projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_3.csv create mode 100644 projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_4.csv create mode 100644 projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_5.csv create mode 100644 projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_6.csv create mode 100644 projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_7.csv create mode 100644 projects/rocprofiler-compute/tests/workloads/vcopy/MI350/profiling_config.yaml create mode 100644 projects/rocprofiler-compute/tests/workloads/vcopy/MI350/sysinfo.csv diff --git a/projects/rocprofiler-compute/CHANGELOG.md b/projects/rocprofiler-compute/CHANGELOG.md index a529917d6d..e8a054b5a2 100644 --- a/projects/rocprofiler-compute/CHANGELOG.md +++ b/projects/rocprofiler-compute/CHANGELOG.md @@ -22,17 +22,33 @@ Full documentation for ROCm Compute Profiler is available at [https://rocm.docs. * Support host-trap PC Sampling on CLI (beta version) -* Add support for tuned performance counters for gfx950 GPUs - * Add L1 latencies - * Add L2 latencies - * Add L2 to EA stalls - * Add L2 to EA stalls per channel +* Support for AMD Instinct MI350 series GPUs with the addition of the following counters: + * VALU co-issue (Two VALUs are issued instructions) efficiency + * Stream Processor Instruction (SPI) Wave Occupancy + * Scheduler-Pipe Wave Utilization + * Scheduler FIFO Full Rate + * CPC ADC Utilization + * F6F4 datatype metrics + * Update formula for total FLOPs while taking into account F6F4 ops + * LDS STORE, LDS LOAD, LDS ATOMIC instruction count metrics + * LDS STORE, LDS LOAD, LDS ATOMIC bandwidth metrics + * LDS FIFO full rate + * Sequencer -> TA ADDR Stall rates + * Sequencer -> TA CMD Stall rates + * Sequencer -> TA DATA Stall rates + * L1 latencies + * L2 latencies + * L2 to EA stalls + * L2 to EA stalls per channel ### Changed * Change normal_unit default to per_kernel * Change dependency from rocm-smi to amd-smi * Decrease profiling time by not collecting counters not used in post analysis +* Update definition of following metrics for MI 350: + * VGPR Writes + * Total FLOPs (consider fp6 and fp4 ops) ### Resolved issues @@ -44,6 +60,14 @@ Full documentation for ROCm Compute Profiler is available at [https://rocm.docs. * GPU id filtering is not supported when using rocprof v3 +* Analysis of previously collected workload data will not work due to sysinfo.csv schema change + * As a workaround, run the profiling operation again for the workload and interrupt the process after ten seconds. + Followed by copying the `sysinfo.csv` file from the new data folder to the old one. + This assumes your system specification hasn't changed since the creation of the previous workload data. + +* Analysis of new workloads might require providing shader/memory clock speed using +--specs-correction operation if `amd-smi` or `rocminfo` does not provide clock speeds. + ## ROCm Compute Profiler 3.1.0 for ROCm 6.4.0 ### Added diff --git a/projects/rocprofiler-compute/CMakeLists.txt b/projects/rocprofiler-compute/CMakeLists.txt index 93dc58e11e..4e7caf003f 100644 --- a/projects/rocprofiler-compute/CMakeLists.txt +++ b/projects/rocprofiler-compute/CMakeLists.txt @@ -292,9 +292,8 @@ add_test( add_test( NAME test_L1_cache_counters COMMAND - ${Python3_EXECUTABLE} -m pytest -m L1_cache - --junitxml=tests/test_TCP_counters.xml ${COV_OPTION} - ${PROJECT_SOURCE_DIR}/tests/test_TCP_counters.py + ${Python3_EXECUTABLE} -m pytest -m L1_cache --junitxml=tests/test_TCP_counters.xml + ${COV_OPTION} ${PROJECT_SOURCE_DIR}/tests/test_TCP_counters.py WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}) # --------- diff --git a/projects/rocprofiler-compute/src/argparser.py b/projects/rocprofiler-compute/src/argparser.py index e0a1bb480f..ed17d68790 100644 --- a/projects/rocprofiler-compute/src/argparser.py +++ b/projects/rocprofiler-compute/src/argparser.py @@ -673,7 +673,7 @@ Examples: "--specs-correction", type=str, metavar="", - help="\t\tSpecify the specs to correct.", + help="\t\tSpecify the specs to correct. e.g. --specs-correction='specname1:specvalue1,specname2:specvalue2'", ) analyze_advanced_group.add_argument( "--list-nodes", diff --git a/projects/rocprofiler-compute/src/rocprof_compute_analyze/analysis_webui.py b/projects/rocprofiler-compute/src/rocprof_compute_analyze/analysis_webui.py index 589c99b33f..15747df5f1 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_analyze/analysis_webui.py +++ b/projects/rocprofiler-compute/src/rocprof_compute_analyze/analysis_webui.py @@ -107,7 +107,6 @@ class webui_analysis(OmniAnalyze_Base): console_debug("analysis", "gui normalization is %s" % norm_filt) base_data = self.initalize_runs() # Re-initalizes everything - hbm_bw = base_data[base_run].sys_info["hbm_bw"][0] panel_configs = copy.deepcopy(arch_configs.panel_configs) # Generate original raw df base_data[base_run].raw_pmc = file_io.create_df_pmc( @@ -231,7 +230,6 @@ class webui_analysis(OmniAnalyze_Base): norm_filt=norm_filt, comparable_columns=comparable_columns, decimal=self.get_args().decimal, - hbm_bw=base_data[base_run].sys_info["hbm_bw"][0], ) # Update content for this section @@ -358,7 +356,6 @@ def determine_chart_type( norm_filt, comparable_columns, decimal, - hbm_bw, ): content = [] @@ -372,9 +369,7 @@ def determine_chart_type( # Determine chart type: # a) Barchart if table_config["id"] in [x for i in barchart_elements.values() for x in i]: - d_figs = build_bar_chart( - display_df, table_config, barchart_elements, norm_filt, hbm_bw - ) + d_figs = build_bar_chart(display_df, table_config, barchart_elements, norm_filt) # Smaller formatting if barchart yeilds several graphs if ( len(d_figs) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_profile/profiler_base.py b/projects/rocprofiler-compute/src/rocprof_compute_profile/profiler_base.py index fd647b83d0..4e9f5f3bbb 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_profile/profiler_base.py +++ b/projects/rocprofiler-compute/src/rocprof_compute_profile/profiler_base.py @@ -311,6 +311,21 @@ class RocProfCompute_Base: if self.__args.name.find(".") != -1 or self.__args.name.find("-") != -1: console_error("'-' and '.' are not permitted in -n/--name") + gen_sysinfo( + workload_name=self.__args.name, + workload_dir=self.get_args().path, + ip_blocks=[ + name + for name, type in self.__args.filter_blocks.items() + if type == "hardware_block" + ], + app_cmd=self.__args.remaining, + skip_roof=self.__args.no_roof, + roof_only=self.__args.roof_only, + mspec=self._soc._mspec, + soc=self._soc, + ) + @abstractmethod def run_profiling(self, version: str, prog: str): """Run profiling.""" @@ -446,21 +461,6 @@ class RocProfCompute_Base: "performing post-processing using %s profiler" % self.__profiler, ) - gen_sysinfo( - workload_name=self.__args.name, - workload_dir=self.get_args().path, - ip_blocks=[ - name - for name, type in self.__args.filter_blocks.items() - if type == "hardware_block" - ], - app_cmd=self.__args.remaining, - skip_roof=self.__args.no_roof, - roof_only=self.__args.roof_only, - mspec=self._soc._mspec, - soc=self._soc, - ) - def test_df_column_equality(df): return df.eq(df.iloc[:, 0], axis=0).all(1).all() diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/0200_system-speed-of-light.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/0200_system-speed-of-light.yaml index 3ab7a6b9d6..c2c11bbe4e 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/0200_system-speed-of-light.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/0200_system-speed-of-light.yaml @@ -62,6 +62,13 @@ Panel Config: peak: ((($max_sclk * $cu_per_gpu) * 256) / 1000) pop: None # No perf counter tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + MFMA FLOPs (F6F4): + value: None + unit: GFLOP + peak: None + pop: None + tips: MFMA IOPs (Int8): value: None # No perf counter unit: GOPs @@ -179,17 +186,17 @@ Panel Config: value: AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) * 64)) / (End_Timestamp - Start_Timestamp))) unit: GB/s - peak: $hbm_bw + peak: $hbmBandwidth pop: ((100 * AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) - * 64)) / (End_Timestamp - Start_Timestamp)))) / $hbm_bw) + * 64)) / (End_Timestamp - Start_Timestamp)))) / $hbmBandwidth) tips: L2-Fabric Write BW: value: AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) * 32)) / (End_Timestamp - Start_Timestamp))) unit: GB/s - peak: $hbm_bw + peak: $hbmBandwidth pop: ((100 * AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) - * 32)) / (End_Timestamp - Start_Timestamp)))) / $hbm_bw) + * 32)) / (End_Timestamp - Start_Timestamp)))) / $hbmBandwidth) tips: L2-Fabric Read Latency: value: AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/0500_command-processor.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/0500_command-processor.yaml index 164b3552bf..834ca2de6b 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/0500_command-processor.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/0500_command-processor.yaml @@ -19,6 +19,24 @@ Panel Config: unit: Unit tips: Tips metric: + CPC SYNC FIFO Full Rate: + avg: None + min: None + max: None + unit: pct + tips: + CPC CANE Stall Rate: + avg: None + min: None + max: None + unit: pct + tips: + CPC ADC Utilization: + avg: None + min: None + max: None + unit: pct + tips: CPF Utilization: avg: AVG((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/0600_shader-processor-input.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/0600_shader-processor-input.yaml index c78c3645a0..2459e41db9 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/0600_shader-processor-input.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/0600_shader-processor-input.yaml @@ -19,6 +19,13 @@ Panel Config: unit: Unit tips: Tips metric: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Schedule-Pipe Wave Occupancy: + avg: None + min: None + max: None + unit: Wave + tips: Accelerator Utilization: avg: AVG(100 * $GRBM_GUI_ACTIVE_PER_XCD / $GRBM_COUNT_PER_XCD) min: MIN(100 * $GRBM_GUI_ACTIVE_PER_XCD / $GRBM_COUNT_PER_XCD) @@ -31,6 +38,13 @@ Panel Config: max: MAX(100 * SPI_CSN_BUSY / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu)) unit: Pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Scheduler-Pipe Wave Utilization: + avg: None + min: None + max: None + unit: Pct + tips: Workgroup Manager Utilization: avg: AVG(100 * $GRBM_SPI_BUSY_PER_XCD / $GRBM_GUI_ACTIVE_PER_XCD) min: MIN(100 * $GRBM_SPI_BUSY_PER_XCD / $GRBM_GUI_ACTIVE_PER_XCD) @@ -108,6 +122,13 @@ Panel Config: 0) else None) unit: Pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Scheduler-Pipe FIFO Full Rate: + avg: None + min: None + max: None + unit: Pct + tips: Scheduler-Pipe Stall Rate: avg: AVG((((100 * SPI_RA_RES_STALL_CSN) / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != 0) else None)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1000_compute-unit-instruction-mix.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1000_compute-unit-instruction-mix.yaml index 9aa329c1c5..48499d3579 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1000_compute-unit-instruction-mix.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1000_compute-unit-instruction-mix.yaml @@ -181,6 +181,13 @@ Panel Config: max: MAX((TA_FLAT_WAVEFRONTS_sum / $denom)) unit: (instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + Spill/Stack Coalesceable Instr: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: Global/Generic Coalesceable Instr: avg: None # No perf counter min: None # No perf counter @@ -283,3 +290,10 @@ Panel Config: max: None # No HW module unit: (instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + MFMA-F6F4: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: \ No newline at end of file diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1100_compute-unit-compute-pipeline.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1100_compute-unit-compute-pipeline.yaml index 81b232f034..41bb9563f5 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1100_compute-unit-compute-pipeline.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1100_compute-unit-compute-pipeline.yaml @@ -61,6 +61,13 @@ Panel Config: peak: None pop: None tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + MFMA FLOPs (F6F4): + value: None + unit: GFLOP + peak: None + pop: None + tips: MFMA IOPs (INT8): value: None # No perf counter unit: None @@ -109,6 +116,13 @@ Panel Config: max: MAX((((100 * SQ_ACTIVE_INST_VALU) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) unit: pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + VALU Co-Issue Efficiency: + avg: None + min: None + max: None + unit: pct + tips: VMEM Utilization: avg: None # No HW module min: None # No HW module @@ -210,6 +224,13 @@ Panel Config: max: None # No perf counter unit: (OPs + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + F6F4 OPs: + avg: None + min: None + max: None + unit: (OPs + $normUnit) + tips: INT8 OPs: avg: None # No perf counter min: None # No perf counter diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1200_lds.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1200_lds.yaml index 9c908e8589..f40d07132e 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1200_lds.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1200_lds.yaml @@ -55,6 +55,48 @@ Panel Config: max: MAX((SQ_INSTS_LDS / $denom)) unit: (Instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS LOAD: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS STORE: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS ATOMIC: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS LOAD Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS STORE Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS ATOMIC Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: Theoretical Bandwidth: avg: AVG(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($lds_banks_per_cu)) / $denom)) @@ -116,3 +158,17 @@ Panel Config: max: MAX((SQ_LDS_MEM_VIOLATIONS / $denom)) unit: (Accesses + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS Command FIFO Full Rate: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS Data FIFO Full Rate: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1500_TA_and_TD.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1500_TA_and_TD.yaml index 43996908bb..ab85cf5459 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1500_TA_and_TD.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1500_TA_and_TD.yaml @@ -43,6 +43,27 @@ Panel Config: max: MAX(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))) unit: pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Address Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Command Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Data Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: Total Instructions: avg: AVG((TA_TOTAL_WAVEFRONTS_sum / $denom)) min: MIN((TA_TOTAL_WAVEFRONTS_sum / $denom)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1700_L2_cache.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1700_L2_cache.yaml index 54527268fb..f762728210 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1700_L2_cache.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx906/1700_L2_cache.yaml @@ -40,6 +40,10 @@ Panel Config: * 32)) / (End_Timestamp - Start_Timestamp))) unit: GB/s tips: + HBM Bandwidth: + value: $hbmBandwidth + unit: GB/s + tips: - metric_table: id: 1702 diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/0200_system-speed-of-light.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/0200_system-speed-of-light.yaml index 8e52572ff3..28b1a76139 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/0200_system-speed-of-light.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/0200_system-speed-of-light.yaml @@ -62,6 +62,13 @@ Panel Config: peak: ((($max_sclk * $cu_per_gpu) * 256) / 1000) pop: None # No perf counter tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + MFMA FLOPs (F6F4): + value: None + unit: GFLOP + peak: None + pop: None + tips: MFMA IOPs (Int8): value: None # No perf counter unit: GOPs @@ -179,17 +186,17 @@ Panel Config: value: AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) * 64)) / (End_Timestamp - Start_Timestamp))) unit: GB/s - peak: $hbm_bw + peak: $hbmBandwidth pop: ((100 * AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) - * 64)) / (End_Timestamp - Start_Timestamp)))) / $hbm_bw) + * 64)) / (End_Timestamp - Start_Timestamp)))) / $hbmBandwidth) tips: L2-Fabric Write BW: value: AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) * 32)) / (End_Timestamp - Start_Timestamp))) unit: GB/s - peak: $hbm_bw + peak: $hbmBandwidth pop: ((100 * AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) - * 32)) / (End_Timestamp - Start_Timestamp)))) / $hbm_bw) + * 32)) / (End_Timestamp - Start_Timestamp)))) / $hbmBandwidth) tips: L2-Fabric Read Latency: value: AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/0500_command-processor.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/0500_command-processor.yaml index 164b3552bf..22213e355e 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/0500_command-processor.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/0500_command-processor.yaml @@ -19,6 +19,27 @@ Panel Config: unit: Unit tips: Tips metric: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + CPC SYNC FIFO Full Rate: + avg: None + min: None + max: None + unit: pct + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + CPC CANE Stall Rate: + avg: None + min: None + max: None + unit: pct + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + CPC ADC Utilization: + avg: None + min: None + max: None + unit: pct + tips: CPF Utilization: avg: AVG((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/0600_shader-processor-input.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/0600_shader-processor-input.yaml index c78c3645a0..2459e41db9 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/0600_shader-processor-input.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/0600_shader-processor-input.yaml @@ -19,6 +19,13 @@ Panel Config: unit: Unit tips: Tips metric: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Schedule-Pipe Wave Occupancy: + avg: None + min: None + max: None + unit: Wave + tips: Accelerator Utilization: avg: AVG(100 * $GRBM_GUI_ACTIVE_PER_XCD / $GRBM_COUNT_PER_XCD) min: MIN(100 * $GRBM_GUI_ACTIVE_PER_XCD / $GRBM_COUNT_PER_XCD) @@ -31,6 +38,13 @@ Panel Config: max: MAX(100 * SPI_CSN_BUSY / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu)) unit: Pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Scheduler-Pipe Wave Utilization: + avg: None + min: None + max: None + unit: Pct + tips: Workgroup Manager Utilization: avg: AVG(100 * $GRBM_SPI_BUSY_PER_XCD / $GRBM_GUI_ACTIVE_PER_XCD) min: MIN(100 * $GRBM_SPI_BUSY_PER_XCD / $GRBM_GUI_ACTIVE_PER_XCD) @@ -108,6 +122,13 @@ Panel Config: 0) else None) unit: Pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Scheduler-Pipe FIFO Full Rate: + avg: None + min: None + max: None + unit: Pct + tips: Scheduler-Pipe Stall Rate: avg: AVG((((100 * SPI_RA_RES_STALL_CSN) / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != 0) else None)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1000_compute-unit-instruction-mix.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1000_compute-unit-instruction-mix.yaml index 91ccbb9e5e..c4e282ac5c 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1000_compute-unit-instruction-mix.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1000_compute-unit-instruction-mix.yaml @@ -181,6 +181,13 @@ Panel Config: max: MAX((TA_FLAT_WAVEFRONTS_sum / $denom)) unit: (instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + Spill/Stack Coalesceable Instr: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: Global/Generic Read: avg: AVG((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) min: MIN((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) @@ -271,3 +278,10 @@ Panel Config: max: None # No HW module unit: (instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + MFMA-F6F4: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1100_compute-unit-compute-pipeline.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1100_compute-unit-compute-pipeline.yaml index 81b232f034..41bb9563f5 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1100_compute-unit-compute-pipeline.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1100_compute-unit-compute-pipeline.yaml @@ -61,6 +61,13 @@ Panel Config: peak: None pop: None tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + MFMA FLOPs (F6F4): + value: None + unit: GFLOP + peak: None + pop: None + tips: MFMA IOPs (INT8): value: None # No perf counter unit: None @@ -109,6 +116,13 @@ Panel Config: max: MAX((((100 * SQ_ACTIVE_INST_VALU) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) unit: pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + VALU Co-Issue Efficiency: + avg: None + min: None + max: None + unit: pct + tips: VMEM Utilization: avg: None # No HW module min: None # No HW module @@ -210,6 +224,13 @@ Panel Config: max: None # No perf counter unit: (OPs + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + F6F4 OPs: + avg: None + min: None + max: None + unit: (OPs + $normUnit) + tips: INT8 OPs: avg: None # No perf counter min: None # No perf counter diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1200_lds.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1200_lds.yaml index 2c3fc34b2a..9ee74470a8 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1200_lds.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1200_lds.yaml @@ -55,6 +55,48 @@ Panel Config: max: MAX((SQ_INSTS_LDS / $denom)) unit: (Instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS LOAD: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS STORE: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS ATOMIC: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS LOAD Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS STORE Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS ATOMIC Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: Theoretical Bandwidth: avg: AVG(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($lds_banks_per_cu)) / $denom)) @@ -116,3 +158,17 @@ Panel Config: max: MAX((SQ_LDS_MEM_VIOLATIONS / $denom)) unit: (Accesses + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS Command FIFO Full Rate: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS Data FIFO Full Rate: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1500_TA_and_TD.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1500_TA_and_TD.yaml index 6259eb5ab2..c7d1a59133 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1500_TA_and_TD.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1500_TA_and_TD.yaml @@ -43,6 +43,27 @@ Panel Config: max: MAX(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))) unit: pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Address Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Command Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Data Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: Total Instructions: avg: AVG((TA_TOTAL_WAVEFRONTS_sum / $denom)) min: MIN((TA_TOTAL_WAVEFRONTS_sum / $denom)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1700_L2_cache.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1700_L2_cache.yaml index 5c3d6d14ee..07c39cb7a6 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1700_L2_cache.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/1700_L2_cache.yaml @@ -40,6 +40,10 @@ Panel Config: * 32)) / (End_Timestamp - Start_Timestamp))) unit: GB/s tips: + HBM Bandwidth: + value: $hbmBandwidth + unit: GB/s + tips: - metric_table: id: 1702 diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/0200_system-speed-of-light.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/0200_system-speed-of-light.yaml index 583ce554ea..5c4ef84923 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/0200_system-speed-of-light.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/0200_system-speed-of-light.yaml @@ -76,6 +76,13 @@ Panel Config: pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 256) / 1000)) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + MFMA FLOPs (F6F4): + value: None + unit: GFLOP + peak: None + pop: None + tips: MFMA IOPs (Int8): value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp))) unit: GIOP @@ -197,17 +204,17 @@ Panel Config: value: AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) * 64)) / (End_Timestamp - Start_Timestamp))) unit: GB/s - peak: $hbm_bw + peak: $hbmBandwidth pop: ((100 * AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) - * 64)) / (End_Timestamp - Start_Timestamp)))) / $hbm_bw) + * 64)) / (End_Timestamp - Start_Timestamp)))) / $hbmBandwidth) tips: L2-Fabric Write BW: value: AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) * 32)) / (End_Timestamp - Start_Timestamp))) unit: GB/s - peak: $hbm_bw + peak: $hbmBandwidth pop: ((100 * AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) - * 32)) / (End_Timestamp - Start_Timestamp)))) / $hbm_bw) + * 32)) / (End_Timestamp - Start_Timestamp)))) / $hbmBandwidth) tips: L2-Fabric Read Latency: value: AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/0500_command-processor.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/0500_command-processor.yaml index 164b3552bf..834ca2de6b 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/0500_command-processor.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/0500_command-processor.yaml @@ -19,6 +19,24 @@ Panel Config: unit: Unit tips: Tips metric: + CPC SYNC FIFO Full Rate: + avg: None + min: None + max: None + unit: pct + tips: + CPC CANE Stall Rate: + avg: None + min: None + max: None + unit: pct + tips: + CPC ADC Utilization: + avg: None + min: None + max: None + unit: pct + tips: CPF Utilization: avg: AVG((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/0600_shader-processor-input.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/0600_shader-processor-input.yaml index c78c3645a0..2459e41db9 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/0600_shader-processor-input.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/0600_shader-processor-input.yaml @@ -19,6 +19,13 @@ Panel Config: unit: Unit tips: Tips metric: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Schedule-Pipe Wave Occupancy: + avg: None + min: None + max: None + unit: Wave + tips: Accelerator Utilization: avg: AVG(100 * $GRBM_GUI_ACTIVE_PER_XCD / $GRBM_COUNT_PER_XCD) min: MIN(100 * $GRBM_GUI_ACTIVE_PER_XCD / $GRBM_COUNT_PER_XCD) @@ -31,6 +38,13 @@ Panel Config: max: MAX(100 * SPI_CSN_BUSY / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu)) unit: Pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Scheduler-Pipe Wave Utilization: + avg: None + min: None + max: None + unit: Pct + tips: Workgroup Manager Utilization: avg: AVG(100 * $GRBM_SPI_BUSY_PER_XCD / $GRBM_GUI_ACTIVE_PER_XCD) min: MIN(100 * $GRBM_SPI_BUSY_PER_XCD / $GRBM_GUI_ACTIVE_PER_XCD) @@ -108,6 +122,13 @@ Panel Config: 0) else None) unit: Pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Scheduler-Pipe FIFO Full Rate: + avg: None + min: None + max: None + unit: Pct + tips: Scheduler-Pipe Stall Rate: avg: AVG((((100 * SPI_RA_RES_STALL_CSN) / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != 0) else None)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1000_compute-unit-instruction-mix.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1000_compute-unit-instruction-mix.yaml index b1079479f4..93f303deb6 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1000_compute-unit-instruction-mix.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1000_compute-unit-instruction-mix.yaml @@ -181,6 +181,13 @@ Panel Config: max: MAX((TA_FLAT_WAVEFRONTS_sum / $denom)) unit: (instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + Spill/Stack Coalesceable Instr: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: Global/Generic Read: avg: AVG((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) min: MIN((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) @@ -271,3 +278,10 @@ Panel Config: max: MAX((SQ_INSTS_VALU_MFMA_F64 / $denom)) unit: (instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + MFMA-F6F4: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1100_compute-unit-compute-pipeline.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1100_compute-unit-compute-pipeline.yaml index f0a13d44ab..1ec04d7a3e 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1100_compute-unit-compute-pipeline.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1100_compute-unit-compute-pipeline.yaml @@ -75,6 +75,13 @@ Panel Config: pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 256) / 1000)) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + MFMA FLOPs (F6F4): + value: None + unit: GFLOP + peak: None + pop: None + tips: MFMA IOPs (INT8): value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp))) unit: GIOP @@ -124,6 +131,13 @@ Panel Config: max: MAX((((100 * SQ_ACTIVE_INST_VALU) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) unit: pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + VALU Co-Issue Efficiency: + avg: None + min: None + max: None + unit: pct + tips: VMEM Utilization: avg: AVG((((100 * (SQ_ACTIVE_INST_FLAT+SQ_ACTIVE_INST_VMEM)) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) min: MIN((((100 * (SQ_ACTIVE_INST_FLAT+SQ_ACTIVE_INST_VMEM)) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) @@ -264,6 +278,13 @@ Panel Config: + (SQ_INSTS_VALU_FMA_F64 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64)) / $denom)) unit: (OPs + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + F6F4 OPs: + avg: None + min: None + max: None + unit: (OPs + $normUnit) + tips: INT8 OPs: avg: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / $denom)) min: MIN(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / $denom)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1200_lds.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1200_lds.yaml index 2c3fc34b2a..9ee74470a8 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1200_lds.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1200_lds.yaml @@ -55,6 +55,48 @@ Panel Config: max: MAX((SQ_INSTS_LDS / $denom)) unit: (Instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS LOAD: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS STORE: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS ATOMIC: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS LOAD Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS STORE Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS ATOMIC Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: Theoretical Bandwidth: avg: AVG(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($lds_banks_per_cu)) / $denom)) @@ -116,3 +158,17 @@ Panel Config: max: MAX((SQ_LDS_MEM_VIOLATIONS / $denom)) unit: (Accesses + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS Command FIFO Full Rate: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS Data FIFO Full Rate: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1500_TA_and_TD.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1500_TA_and_TD.yaml index d60868f760..855c071506 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1500_TA_and_TD.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1500_TA_and_TD.yaml @@ -43,6 +43,27 @@ Panel Config: max: MAX(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))) unit: pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Address Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Command Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Data Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: Total Instructions: avg: AVG((TA_TOTAL_WAVEFRONTS_sum / $denom)) min: MIN((TA_TOTAL_WAVEFRONTS_sum / $denom)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1700_L2_cache.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1700_L2_cache.yaml index 8f03bcbcb7..c55cbfc787 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1700_L2_cache.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/1700_L2_cache.yaml @@ -40,6 +40,10 @@ Panel Config: * 32)) / (End_Timestamp - Start_Timestamp))) unit: GB/s tips: + HBM Bandwidth: + value: $hbmBandwidth + unit: GB/s + tips: - metric_table: id: 1702 diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/0200_system-speed-of-light.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/0200_system-speed-of-light.yaml index b0a7399e5d..5aa277a1d1 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/0200_system-speed-of-light.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/0200_system-speed-of-light.yaml @@ -77,6 +77,13 @@ Panel Config: pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 256) / 1000)) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + MFMA FLOPs (F6F4): + value: None + unit: GFLOP + peak: None + pop: None + tips: MFMA IOPs (Int8): value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp))) unit: GIOP @@ -198,18 +205,18 @@ Panel Config: 64 * (TCC_EA0_RDREQ_sum - TCC_BUBBLE_sum - TCC_EA0_RDREQ_32B_sum) + 32 * TCC_EA0_RDREQ_32B_sum) / (End_Timestamp - Start_Timestamp)) unit: GB/s - peak: $hbm_bw + peak: $hbmBandwidth pop: ((100 * (AVG((128 * TCC_BUBBLE_sum + 64 * (TCC_EA0_RDREQ_sum - TCC_BUBBLE_sum - TCC_EA0_RDREQ_32B_sum) + - 32 * TCC_EA0_RDREQ_32B_sum) / (End_Timestamp - Start_Timestamp)))) / $hbm_bw) + 32 * TCC_EA0_RDREQ_32B_sum) / (End_Timestamp - Start_Timestamp)))) / $hbmBandwidth) tips: L2-Fabric Write BW: value: AVG((((TCC_EA0_WRREQ_64B_sum * 64) + ((TCC_EA0_WRREQ_sum - TCC_EA0_WRREQ_64B_sum) * 32)) / (End_Timestamp - Start_Timestamp))) unit: GB/s - peak: $hbm_bw + peak: $hbmBandwidth pop: ((100 * AVG((((TCC_EA0_WRREQ_64B_sum * 64) + ((TCC_EA0_WRREQ_sum - TCC_EA0_WRREQ_64B_sum) - * 32)) / (End_Timestamp - Start_Timestamp)))) / $hbm_bw) + * 32)) / (End_Timestamp - Start_Timestamp)))) / $hbmBandwidth) tips: L2-Fabric Read Latency: value: AVG(((TCC_EA0_RDREQ_LEVEL_sum / TCC_EA0_RDREQ_sum) if (TCC_EA0_RDREQ_sum diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/0500_command-processor.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/0500_command-processor.yaml index 164b3552bf..22213e355e 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/0500_command-processor.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/0500_command-processor.yaml @@ -19,6 +19,27 @@ Panel Config: unit: Unit tips: Tips metric: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + CPC SYNC FIFO Full Rate: + avg: None + min: None + max: None + unit: pct + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + CPC CANE Stall Rate: + avg: None + min: None + max: None + unit: pct + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + CPC ADC Utilization: + avg: None + min: None + max: None + unit: pct + tips: CPF Utilization: avg: AVG((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/0600_shader-processor-input.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/0600_shader-processor-input.yaml index c78c3645a0..2459e41db9 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/0600_shader-processor-input.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/0600_shader-processor-input.yaml @@ -19,6 +19,13 @@ Panel Config: unit: Unit tips: Tips metric: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Schedule-Pipe Wave Occupancy: + avg: None + min: None + max: None + unit: Wave + tips: Accelerator Utilization: avg: AVG(100 * $GRBM_GUI_ACTIVE_PER_XCD / $GRBM_COUNT_PER_XCD) min: MIN(100 * $GRBM_GUI_ACTIVE_PER_XCD / $GRBM_COUNT_PER_XCD) @@ -31,6 +38,13 @@ Panel Config: max: MAX(100 * SPI_CSN_BUSY / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu)) unit: Pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Scheduler-Pipe Wave Utilization: + avg: None + min: None + max: None + unit: Pct + tips: Workgroup Manager Utilization: avg: AVG(100 * $GRBM_SPI_BUSY_PER_XCD / $GRBM_GUI_ACTIVE_PER_XCD) min: MIN(100 * $GRBM_SPI_BUSY_PER_XCD / $GRBM_GUI_ACTIVE_PER_XCD) @@ -108,6 +122,13 @@ Panel Config: 0) else None) unit: Pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Scheduler-Pipe FIFO Full Rate: + avg: None + min: None + max: None + unit: Pct + tips: Scheduler-Pipe Stall Rate: avg: AVG((((100 * SPI_RA_RES_STALL_CSN) / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != 0) else None)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1000_compute-unit-instruction-mix.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1000_compute-unit-instruction-mix.yaml index 83ba5367a7..96ed523023 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1000_compute-unit-instruction-mix.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1000_compute-unit-instruction-mix.yaml @@ -209,6 +209,13 @@ Panel Config: max: MAX((TA_BUFFER_WAVEFRONTS_sum / $denom)) unit: (instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + Spill/Stack Coalesceable Instr: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: Spill/Stack Read: avg: AVG((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) min: MIN((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) @@ -274,4 +281,11 @@ Panel Config: min: MIN((SQ_INSTS_VALU_MFMA_F64 / $denom)) max: MAX((SQ_INSTS_VALU_MFMA_F64 / $denom)) unit: (instr + $normUnit) + # TODO: Fix baseline comparision logic to handle non existent metrics, then + MFMA-F6F4: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1100_compute-unit-compute-pipeline.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1100_compute-unit-compute-pipeline.yaml index 932d9cb5d3..a9fe1307c5 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1100_compute-unit-compute-pipeline.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1100_compute-unit-compute-pipeline.yaml @@ -76,6 +76,13 @@ Panel Config: pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 256) / 1000)) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + MFMA FLOPs (F6F4): + value: None + unit: GFLOP + peak: None + pop: None + tips: MFMA IOPs (INT8): value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp))) unit: GIOP @@ -125,6 +132,13 @@ Panel Config: max: MAX((((100 * SQ_ACTIVE_INST_VALU) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) unit: pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + VALU Co-Issue Efficiency: + avg: None + min: None + max: None + unit: pct + tips: VMEM Utilization: avg: AVG((((100 * (SQ_ACTIVE_INST_FLAT+SQ_ACTIVE_INST_VMEM)) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) min: MIN((((100 * (SQ_ACTIVE_INST_FLAT+SQ_ACTIVE_INST_VMEM)) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) @@ -265,6 +279,13 @@ Panel Config: + (SQ_INSTS_VALU_FMA_F64 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64)) / $denom)) unit: (OPs + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + F6F4 OPs: + avg: None + min: None + max: None + unit: (OPs + $normUnit) + tips: INT8 OPs: avg: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / $denom)) min: MIN(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / $denom)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1200_lds.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1200_lds.yaml index c687e7c471..7f054c2af6 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1200_lds.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1200_lds.yaml @@ -55,6 +55,48 @@ Panel Config: max: MAX((SQ_INSTS_LDS / $denom)) unit: (Instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS LOAD: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS STORE: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS ATOMIC: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS LOAD Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS STORE Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS ATOMIC Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: Theoretical Bandwidth: avg: AVG(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($lds_banks_per_cu)) / $denom)) @@ -116,3 +158,17 @@ Panel Config: max: MAX((SQ_LDS_MEM_VIOLATIONS / $denom)) unit: (Accesses + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS Command FIFO Full Rate: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS Data FIFO Full Rate: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1500_TA_and_TD.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1500_TA_and_TD.yaml index d60868f760..855c071506 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1500_TA_and_TD.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1500_TA_and_TD.yaml @@ -43,6 +43,27 @@ Panel Config: max: MAX(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))) unit: pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Address Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Command Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Data Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: Total Instructions: avg: AVG((TA_TOTAL_WAVEFRONTS_sum / $denom)) min: MIN((TA_TOTAL_WAVEFRONTS_sum / $denom)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1700_L2_cache.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1700_L2_cache.yaml index fcdeace122..e7045e29df 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1700_L2_cache.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/1700_L2_cache.yaml @@ -40,6 +40,10 @@ Panel Config: * 32)) / (End_Timestamp - Start_Timestamp))) unit: GB/s tips: + HBM Bandwidth: + value: $hbmBandwidth + unit: GB/s + tips: - metric_table: id: 1702 diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/0200_system-speed-of-light.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/0200_system-speed-of-light.yaml index b0a7399e5d..5aa277a1d1 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/0200_system-speed-of-light.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/0200_system-speed-of-light.yaml @@ -77,6 +77,13 @@ Panel Config: pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 256) / 1000)) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + MFMA FLOPs (F6F4): + value: None + unit: GFLOP + peak: None + pop: None + tips: MFMA IOPs (Int8): value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp))) unit: GIOP @@ -198,18 +205,18 @@ Panel Config: 64 * (TCC_EA0_RDREQ_sum - TCC_BUBBLE_sum - TCC_EA0_RDREQ_32B_sum) + 32 * TCC_EA0_RDREQ_32B_sum) / (End_Timestamp - Start_Timestamp)) unit: GB/s - peak: $hbm_bw + peak: $hbmBandwidth pop: ((100 * (AVG((128 * TCC_BUBBLE_sum + 64 * (TCC_EA0_RDREQ_sum - TCC_BUBBLE_sum - TCC_EA0_RDREQ_32B_sum) + - 32 * TCC_EA0_RDREQ_32B_sum) / (End_Timestamp - Start_Timestamp)))) / $hbm_bw) + 32 * TCC_EA0_RDREQ_32B_sum) / (End_Timestamp - Start_Timestamp)))) / $hbmBandwidth) tips: L2-Fabric Write BW: value: AVG((((TCC_EA0_WRREQ_64B_sum * 64) + ((TCC_EA0_WRREQ_sum - TCC_EA0_WRREQ_64B_sum) * 32)) / (End_Timestamp - Start_Timestamp))) unit: GB/s - peak: $hbm_bw + peak: $hbmBandwidth pop: ((100 * AVG((((TCC_EA0_WRREQ_64B_sum * 64) + ((TCC_EA0_WRREQ_sum - TCC_EA0_WRREQ_64B_sum) - * 32)) / (End_Timestamp - Start_Timestamp)))) / $hbm_bw) + * 32)) / (End_Timestamp - Start_Timestamp)))) / $hbmBandwidth) tips: L2-Fabric Read Latency: value: AVG(((TCC_EA0_RDREQ_LEVEL_sum / TCC_EA0_RDREQ_sum) if (TCC_EA0_RDREQ_sum diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/0500_command-processor.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/0500_command-processor.yaml index 164b3552bf..e9d9927466 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/0500_command-processor.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/0500_command-processor.yaml @@ -19,6 +19,27 @@ Panel Config: unit: Unit tips: Tips metric: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + CPC SYNC FIFO Full Rate: + avg: None + min: None + max: None + unit: pct + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + CPC CANE Stall Rate: + avg: None + min: None + max: None + unit: pct + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + CPC ADC Utilization: + avg: None + min: None + max: None + unit: pct + tips: CPF Utilization: avg: AVG((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/0600_shader-processor-input.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/0600_shader-processor-input.yaml index c78c3645a0..2459e41db9 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/0600_shader-processor-input.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/0600_shader-processor-input.yaml @@ -19,6 +19,13 @@ Panel Config: unit: Unit tips: Tips metric: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Schedule-Pipe Wave Occupancy: + avg: None + min: None + max: None + unit: Wave + tips: Accelerator Utilization: avg: AVG(100 * $GRBM_GUI_ACTIVE_PER_XCD / $GRBM_COUNT_PER_XCD) min: MIN(100 * $GRBM_GUI_ACTIVE_PER_XCD / $GRBM_COUNT_PER_XCD) @@ -31,6 +38,13 @@ Panel Config: max: MAX(100 * SPI_CSN_BUSY / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu)) unit: Pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Scheduler-Pipe Wave Utilization: + avg: None + min: None + max: None + unit: Pct + tips: Workgroup Manager Utilization: avg: AVG(100 * $GRBM_SPI_BUSY_PER_XCD / $GRBM_GUI_ACTIVE_PER_XCD) min: MIN(100 * $GRBM_SPI_BUSY_PER_XCD / $GRBM_GUI_ACTIVE_PER_XCD) @@ -108,6 +122,13 @@ Panel Config: 0) else None) unit: Pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Scheduler-Pipe FIFO Full Rate: + avg: None + min: None + max: None + unit: Pct + tips: Scheduler-Pipe Stall Rate: avg: AVG((((100 * SPI_RA_RES_STALL_CSN) / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != 0) else None)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1000_compute-unit-instruction-mix.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1000_compute-unit-instruction-mix.yaml index 83ba5367a7..56262065d0 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1000_compute-unit-instruction-mix.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1000_compute-unit-instruction-mix.yaml @@ -209,6 +209,13 @@ Panel Config: max: MAX((TA_BUFFER_WAVEFRONTS_sum / $denom)) unit: (instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + Spill/Stack Coalesceable Instr: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: Spill/Stack Read: avg: AVG((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) min: MIN((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) @@ -275,3 +282,10 @@ Panel Config: max: MAX((SQ_INSTS_VALU_MFMA_F64 / $denom)) unit: (instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + MFMA-F6F4: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1100_compute-unit-compute-pipeline.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1100_compute-unit-compute-pipeline.yaml index 932d9cb5d3..a9fe1307c5 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1100_compute-unit-compute-pipeline.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1100_compute-unit-compute-pipeline.yaml @@ -76,6 +76,13 @@ Panel Config: pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 256) / 1000)) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + MFMA FLOPs (F6F4): + value: None + unit: GFLOP + peak: None + pop: None + tips: MFMA IOPs (INT8): value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp))) unit: GIOP @@ -125,6 +132,13 @@ Panel Config: max: MAX((((100 * SQ_ACTIVE_INST_VALU) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) unit: pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + VALU Co-Issue Efficiency: + avg: None + min: None + max: None + unit: pct + tips: VMEM Utilization: avg: AVG((((100 * (SQ_ACTIVE_INST_FLAT+SQ_ACTIVE_INST_VMEM)) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) min: MIN((((100 * (SQ_ACTIVE_INST_FLAT+SQ_ACTIVE_INST_VMEM)) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) @@ -265,6 +279,13 @@ Panel Config: + (SQ_INSTS_VALU_FMA_F64 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64)) / $denom)) unit: (OPs + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + F6F4 OPs: + avg: None + min: None + max: None + unit: (OPs + $normUnit) + tips: INT8 OPs: avg: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / $denom)) min: MIN(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / $denom)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1200_lds.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1200_lds.yaml index c687e7c471..7f054c2af6 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1200_lds.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1200_lds.yaml @@ -55,6 +55,48 @@ Panel Config: max: MAX((SQ_INSTS_LDS / $denom)) unit: (Instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS LOAD: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS STORE: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS ATOMIC: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS LOAD Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS STORE Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS ATOMIC Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: Theoretical Bandwidth: avg: AVG(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($lds_banks_per_cu)) / $denom)) @@ -116,3 +158,17 @@ Panel Config: max: MAX((SQ_LDS_MEM_VIOLATIONS / $denom)) unit: (Accesses + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS Command FIFO Full Rate: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS Data FIFO Full Rate: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1500_TA_and_TD.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1500_TA_and_TD.yaml index d60868f760..855c071506 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1500_TA_and_TD.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1500_TA_and_TD.yaml @@ -43,6 +43,27 @@ Panel Config: max: MAX(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))) unit: pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Address Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Command Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Data Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: Total Instructions: avg: AVG((TA_TOTAL_WAVEFRONTS_sum / $denom)) min: MIN((TA_TOTAL_WAVEFRONTS_sum / $denom)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1700_L2_cache.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1700_L2_cache.yaml index 181f671502..3d34614ab8 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1700_L2_cache.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/1700_L2_cache.yaml @@ -40,6 +40,10 @@ Panel Config: * 32)) / (End_Timestamp - Start_Timestamp))) unit: GB/s tips: + HBM Bandwidth: + value: $hbmBandwidth + unit: GB/s + tips: - metric_table: id: 1702 diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/0200_system-speed-of-light.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/0200_system-speed-of-light.yaml index b0a7399e5d..5aa277a1d1 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/0200_system-speed-of-light.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/0200_system-speed-of-light.yaml @@ -77,6 +77,13 @@ Panel Config: pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 256) / 1000)) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + MFMA FLOPs (F6F4): + value: None + unit: GFLOP + peak: None + pop: None + tips: MFMA IOPs (Int8): value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp))) unit: GIOP @@ -198,18 +205,18 @@ Panel Config: 64 * (TCC_EA0_RDREQ_sum - TCC_BUBBLE_sum - TCC_EA0_RDREQ_32B_sum) + 32 * TCC_EA0_RDREQ_32B_sum) / (End_Timestamp - Start_Timestamp)) unit: GB/s - peak: $hbm_bw + peak: $hbmBandwidth pop: ((100 * (AVG((128 * TCC_BUBBLE_sum + 64 * (TCC_EA0_RDREQ_sum - TCC_BUBBLE_sum - TCC_EA0_RDREQ_32B_sum) + - 32 * TCC_EA0_RDREQ_32B_sum) / (End_Timestamp - Start_Timestamp)))) / $hbm_bw) + 32 * TCC_EA0_RDREQ_32B_sum) / (End_Timestamp - Start_Timestamp)))) / $hbmBandwidth) tips: L2-Fabric Write BW: value: AVG((((TCC_EA0_WRREQ_64B_sum * 64) + ((TCC_EA0_WRREQ_sum - TCC_EA0_WRREQ_64B_sum) * 32)) / (End_Timestamp - Start_Timestamp))) unit: GB/s - peak: $hbm_bw + peak: $hbmBandwidth pop: ((100 * AVG((((TCC_EA0_WRREQ_64B_sum * 64) + ((TCC_EA0_WRREQ_sum - TCC_EA0_WRREQ_64B_sum) - * 32)) / (End_Timestamp - Start_Timestamp)))) / $hbm_bw) + * 32)) / (End_Timestamp - Start_Timestamp)))) / $hbmBandwidth) tips: L2-Fabric Read Latency: value: AVG(((TCC_EA0_RDREQ_LEVEL_sum / TCC_EA0_RDREQ_sum) if (TCC_EA0_RDREQ_sum diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/0500_command-processor.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/0500_command-processor.yaml index 164b3552bf..fcb59ac0bf 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/0500_command-processor.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/0500_command-processor.yaml @@ -76,6 +76,27 @@ Panel Config: unit: Unit tips: Tips metric: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + CPC SYNC FIFO Full Rate: + avg: None + min: None + max: None + unit: pct + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + CPC CANE Stall Rate: + avg: None + min: None + max: None + unit: pct + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + CPC ADC Utilization: + avg: None + min: None + max: None + unit: pct + tips: CPC Utilization: avg: AVG((((100 * CPC_CPC_STAT_BUSY) / (CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE)) if ((CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE) != 0) else None)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/0600_shader-processor-input.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/0600_shader-processor-input.yaml index c78c3645a0..2459e41db9 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/0600_shader-processor-input.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/0600_shader-processor-input.yaml @@ -19,6 +19,13 @@ Panel Config: unit: Unit tips: Tips metric: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Schedule-Pipe Wave Occupancy: + avg: None + min: None + max: None + unit: Wave + tips: Accelerator Utilization: avg: AVG(100 * $GRBM_GUI_ACTIVE_PER_XCD / $GRBM_COUNT_PER_XCD) min: MIN(100 * $GRBM_GUI_ACTIVE_PER_XCD / $GRBM_COUNT_PER_XCD) @@ -31,6 +38,13 @@ Panel Config: max: MAX(100 * SPI_CSN_BUSY / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu)) unit: Pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Scheduler-Pipe Wave Utilization: + avg: None + min: None + max: None + unit: Pct + tips: Workgroup Manager Utilization: avg: AVG(100 * $GRBM_SPI_BUSY_PER_XCD / $GRBM_GUI_ACTIVE_PER_XCD) min: MIN(100 * $GRBM_SPI_BUSY_PER_XCD / $GRBM_GUI_ACTIVE_PER_XCD) @@ -108,6 +122,13 @@ Panel Config: 0) else None) unit: Pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Scheduler-Pipe FIFO Full Rate: + avg: None + min: None + max: None + unit: Pct + tips: Scheduler-Pipe Stall Rate: avg: AVG((((100 * SPI_RA_RES_STALL_CSN) / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != 0) else None)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1000_compute-unit-instruction-mix.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1000_compute-unit-instruction-mix.yaml index 83ba5367a7..56262065d0 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1000_compute-unit-instruction-mix.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1000_compute-unit-instruction-mix.yaml @@ -209,6 +209,13 @@ Panel Config: max: MAX((TA_BUFFER_WAVEFRONTS_sum / $denom)) unit: (instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then remove this + Spill/Stack Coalesceable Instr: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: Spill/Stack Read: avg: AVG((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) min: MIN((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) @@ -275,3 +282,10 @@ Panel Config: max: MAX((SQ_INSTS_VALU_MFMA_F64 / $denom)) unit: (instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + MFMA-F6F4: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1100_compute-unit-compute-pipeline.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1100_compute-unit-compute-pipeline.yaml index 932d9cb5d3..a9fe1307c5 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1100_compute-unit-compute-pipeline.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1100_compute-unit-compute-pipeline.yaml @@ -76,6 +76,13 @@ Panel Config: pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 256) / 1000)) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + MFMA FLOPs (F6F4): + value: None + unit: GFLOP + peak: None + pop: None + tips: MFMA IOPs (INT8): value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp))) unit: GIOP @@ -125,6 +132,13 @@ Panel Config: max: MAX((((100 * SQ_ACTIVE_INST_VALU) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) unit: pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + VALU Co-Issue Efficiency: + avg: None + min: None + max: None + unit: pct + tips: VMEM Utilization: avg: AVG((((100 * (SQ_ACTIVE_INST_FLAT+SQ_ACTIVE_INST_VMEM)) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) min: MIN((((100 * (SQ_ACTIVE_INST_FLAT+SQ_ACTIVE_INST_VMEM)) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) @@ -265,6 +279,13 @@ Panel Config: + (SQ_INSTS_VALU_FMA_F64 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64)) / $denom)) unit: (OPs + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + F6F4 OPs: + avg: None + min: None + max: None + unit: (OPs + $normUnit) + tips: INT8 OPs: avg: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / $denom)) min: MIN(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / $denom)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1200_lds.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1200_lds.yaml index c687e7c471..7f054c2af6 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1200_lds.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1200_lds.yaml @@ -55,6 +55,48 @@ Panel Config: max: MAX((SQ_INSTS_LDS / $denom)) unit: (Instr + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS LOAD: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS STORE: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS ATOMIC: + avg: None + min: None + max: None + unit: (instr + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS LOAD Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS STORE Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS ATOMIC Bandwidth: + avg: None + min: None + max: None + units: Gbps + tips: Theoretical Bandwidth: avg: AVG(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($lds_banks_per_cu)) / $denom)) @@ -116,3 +158,17 @@ Panel Config: max: MAX((SQ_LDS_MEM_VIOLATIONS / $denom)) unit: (Accesses + $normUnit) tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS Command FIFO Full Rate: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + LDS Data FIFO Full Rate: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1500_TA_and_TD.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1500_TA_and_TD.yaml index d60868f760..855c071506 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1500_TA_and_TD.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1500_TA_and_TD.yaml @@ -43,6 +43,27 @@ Panel Config: max: MAX(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))) unit: pct tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Address Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Command Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: + # TODO: Fix baseline comparision logic to handle non existent metrics, then + Sequencer → TA Data Stall: + avg: None + min: None + max: None + unit: (Cycles + $normUnit) + tips: Total Instructions: avg: AVG((TA_TOTAL_WAVEFRONTS_sum / $denom)) min: MIN((TA_TOTAL_WAVEFRONTS_sum / $denom)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1700_L2_cache.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1700_L2_cache.yaml index 34dbc4c551..656534081b 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1700_L2_cache.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/1700_L2_cache.yaml @@ -41,6 +41,10 @@ Panel Config: * 32)) / (End_Timestamp - Start_Timestamp))) unit: GB/s tips: + HBM Bandwidth: + value: $hbmBandwidth + unit: GB/s + tips: - metric_table: id: 1702 diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0000_top_stats.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0000_top_stats.yaml new file mode 100644 index 0000000000..ccf1309850 --- /dev/null +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0000_top_stats.yaml @@ -0,0 +1,14 @@ +--- +Panel Config: + id: 000 + title: Top Stats + data source: + - raw_csv_table: + id: 001 + title: Top Kernels + source: pmc_kernel_top.csv + + - raw_csv_table: + id: 002 + title: Dispatch List + source: pmc_dispatch_info.csv diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0100_system_info.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0100_system_info.yaml new file mode 100644 index 0000000000..b7ec29eaf9 --- /dev/null +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0100_system_info.yaml @@ -0,0 +1,9 @@ +--- +Panel Config: + id: 100 + title: System Info + data source: + - raw_csv_table: + id: 101 + source: sysinfo.csv + columnwise: True diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0200_system-speed-of-light.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0200_system-speed-of-light.yaml new file mode 100644 index 0000000000..cfbb5232d0 --- /dev/null +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0200_system-speed-of-light.yaml @@ -0,0 +1,269 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + SALU: &SALU_anchor Scalar Arithmetic Logic Unit + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 200 + title: System Speed-of-Light + data source: + - metric_table: + id: 201 + title: Speed-of-Light + header: + metric: Metric + value: Avg + unit: Unit + peak: Peak + pop: Pct of Peak + tips: Tips + metric: + VALU FLOPs: + value: AVG(((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + + (2 * SQ_INSTS_VALU_FMA_F16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + + SQ_INSTS_VALU_TRANS_F32) + (2 * SQ_INSTS_VALU_FMA_F32)))) + (64 * (((SQ_INSTS_VALU_ADD_F64 + + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (2 * SQ_INSTS_VALU_FMA_F64)))) + / (End_Timestamp - Start_Timestamp))) + unit: GFLOP + peak: (((($max_sclk * $cu_per_gpu) * 64) * 2) / 1000) + pop: ((100 * AVG(((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + + SQ_INSTS_VALU_TRANS_F16) + (2 * SQ_INSTS_VALU_FMA_F16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (2 * SQ_INSTS_VALU_FMA_F32)))) + + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (2 * SQ_INSTS_VALU_FMA_F64)))) / (End_Timestamp - Start_Timestamp)))) / (((($max_sclk + * $cu_per_gpu) * 64) * 2) / 1000)) + tips: + VALU IOPs: + value: AVG(((64 * (SQ_INSTS_VALU_INT32 + SQ_INSTS_VALU_INT64)) / (End_Timestamp - Start_Timestamp))) + unit: GIOP + peak: (((($max_sclk * $cu_per_gpu) * 64) * 2) / 1000) + pop: ((100 * AVG(((64 * (SQ_INSTS_VALU_INT32 + SQ_INSTS_VALU_INT64)) / (End_Timestamp + - Start_Timestamp)))) / (((($max_sclk * $cu_per_gpu) * 64) * 2) / 1000)) + tips: + MFMA FLOPs (F8): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) / (End_Timestamp - Start_Timestamp))) + unit: GFLOP + peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk * $cu_per_gpu) * 8192) / 1000)) + tips: + MFMA FLOPs (BF16): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) / (End_Timestamp - Start_Timestamp))) + unit: GFLOP + peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk * $cu_per_gpu) * 4096) / 1000)) + tips: + MFMA FLOPs (F16): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (End_Timestamp - Start_Timestamp))) + unit: GFLOP + peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk * $cu_per_gpu) * 4096) / 1000)) + tips: + MFMA FLOPs (F32): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) / (End_Timestamp - Start_Timestamp))) + unit: GFLOP + peak: ((($max_sclk * $cu_per_gpu) * 256) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk * $cu_per_gpu) * 256) / 1000)) + tips: + MFMA FLOPs (F64): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp))) + unit: GFLOP + peak: ((($max_sclk * $cu_per_gpu) * 256) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk * $cu_per_gpu) * 256) / 1000)) + tips: + MFMA FLOPs (F6F4): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) / (End_Timestamp - Start_Timestamp))) + unit: GFLOP + peak: ((($max_sclk * $cu_per_gpu) * 256) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk * $cu_per_gpu) * 256) / 1000)) + tips: + MFMA IOPs (Int8): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp))) + unit: GIOP + peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk * $cu_per_gpu) * 8192) / 1000)) + tips: + Active CUs: + value: $numActiveCUs + unit: CUs + peak: $cu_per_gpu + pop: ((100 * $numActiveCUs) / $cu_per_gpu) + tips: + SALU Utilization: + value: AVG(((100 * SQ_ACTIVE_INST_SCA) / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))) + unit: pct + peak: 100 + pop: AVG(((100 * SQ_ACTIVE_INST_SCA) / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))) + tips: + VALU Utilization: + value: AVG(((100 * SQ_ACTIVE_INST_VALU) / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))) + unit: pct + peak: 100 + pop: AVG(((100 * SQ_ACTIVE_INST_VALU) / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))) + tips: + MFMA Utilization: + value: AVG(((100 * SQ_VALU_MFMA_BUSY_CYCLES) / (($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu) + * 4))) + unit: pct + peak: 100 + pop: AVG(((100 * SQ_VALU_MFMA_BUSY_CYCLES) / (($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu) + * 4))) + tips: + VMEM Utilization: + value: AVG((((100 * (SQ_ACTIVE_INST_FLAT+SQ_ACTIVE_INST_VMEM)) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + unit: pct + peak: 100 + pop: AVG((((100 * (SQ_ACTIVE_INST_FLAT+SQ_ACTIVE_INST_VMEM)) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + tips: + Branch Utilization: + value: AVG((((100 * SQ_ACTIVE_INST_MISC) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + unit: pct + peak: 100 + pop: AVG((((100 * SQ_ACTIVE_INST_MISC) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + tips: + VALU Active Threads: + value: AVG(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + unit: Threads + peak: $wave_size + pop: (100 * AVG((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU / $wave_size) if (SQ_ACTIVE_INST_VALU != 0) else None)) + tips: + IPC: + value: AVG((SQ_INSTS / SQ_BUSY_CU_CYCLES)) + unit: Instr/cycle + peak: 5 + pop: ((100 * AVG((SQ_INSTS / SQ_BUSY_CU_CYCLES))) / 5) + tips: + Wavefront Occupancy: + value: AVG((SQ_ACCUM_PREV_HIRES / $GRBM_GUI_ACTIVE_PER_XCD)) + unit: Wavefronts + peak: ($max_waves_per_cu * $cu_per_gpu) + pop: (100 * AVG(((SQ_ACCUM_PREV_HIRES / $GRBM_GUI_ACTIVE_PER_XCD) / ($max_waves_per_cu + * $cu_per_gpu)))) + coll_level: SQ_LEVEL_WAVES + tips: + Theoretical LDS Bandwidth: + value: AVG(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($lds_banks_per_cu)) + / (End_Timestamp - Start_Timestamp))) + unit: GB/s + peak: (($max_sclk * $cu_per_gpu) * 0.128) + pop: AVG((((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($lds_banks_per_cu)) + / (End_Timestamp - Start_Timestamp)) / (($max_sclk * $cu_per_gpu) * 0.00128))) + tips: + LDS Bank Conflicts/Access: + value: AVG(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + unit: Conflicts/access + peak: 32 + pop: ((100 * AVG(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None))) / 32) + tips: + vL1D Cache Hit Rate: + value: AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + unit: pct + peak: 100 + pop: AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / + TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + tips: + vL1D Cache BW: + value: AVG(((TCP_TOTAL_CACHE_ACCESSES_sum * 128) / (End_Timestamp - Start_Timestamp))) + unit: GB/s + peak: ((($max_sclk / 1000) * 128) * $cu_per_gpu) + pop: ((100 * AVG(((TCP_TOTAL_CACHE_ACCESSES_sum * 128) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk / 1000) * 128) * $cu_per_gpu)) + tips: + L2 Cache Hit Rate: + value: AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + unit: pct + peak: 100 + pop: AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + tips: + L2 Cache BW: + value: AVG(((TCC_REQ_sum * 128) / (End_Timestamp - Start_Timestamp))) + unit: GB/s + peak: ((($max_sclk / 1000) * 128) * TO_INT($total_l2_chan)) + pop: ((100 * AVG(((TCC_REQ_sum * 128) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk / 1000) * 128) * TO_INT($total_l2_chan))) + tips: + L2-Fabric Read BW: + value: AVG((128 * TCC_BUBBLE_sum + + 64 * (TCC_EA0_RDREQ_sum - TCC_BUBBLE_sum - TCC_EA0_RDREQ_32B_sum) + + 32 * TCC_EA0_RDREQ_32B_sum) / (End_Timestamp - Start_Timestamp)) + unit: GB/s + peak: $hbmBandwidth + pop: ((100 * (AVG((128 * TCC_BUBBLE_sum + + 64 * (TCC_EA0_RDREQ_sum - TCC_BUBBLE_sum - TCC_EA0_RDREQ_32B_sum) + + 32 * TCC_EA0_RDREQ_32B_sum) / (End_Timestamp - Start_Timestamp)))) / $hbmBandwidth) + tips: + L2-Fabric Write BW: + value: AVG((((TCC_EA0_WRREQ_64B_sum * 64) + ((TCC_EA0_WRREQ_sum - TCC_EA0_WRREQ_64B_sum) + * 32)) / (End_Timestamp - Start_Timestamp))) + unit: GB/s + peak: $hbmBandwidth + pop: ((100 * AVG((((TCC_EA0_WRREQ_64B_sum * 64) + ((TCC_EA0_WRREQ_sum - TCC_EA0_WRREQ_64B_sum) + * 32)) / (End_Timestamp - Start_Timestamp)))) / $hbmBandwidth) + tips: + L2-Fabric Read Latency: + value: AVG(((TCC_EA0_RDREQ_LEVEL_sum / TCC_EA0_RDREQ_sum) if (TCC_EA0_RDREQ_sum + != 0) else None)) + unit: Cycles + peak: None + pop: None + tips: + L2-Fabric Write Latency: + value: AVG(((TCC_EA0_WRREQ_LEVEL_sum / TCC_EA0_WRREQ_sum) if (TCC_EA0_WRREQ_sum + != 0) else None)) + unit: Cycles + peak: None + pop: None + tips: + sL1D Cache Hit Rate: + value: AVG((((100 * SQC_DCACHE_HITS) / (SQC_DCACHE_HITS + SQC_DCACHE_MISSES)) + if ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) != 0) else None)) + unit: pct + peak: 100 + pop: AVG((((100 * SQC_DCACHE_HITS) / (SQC_DCACHE_HITS + SQC_DCACHE_MISSES)) + if ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) != 0) else None)) + tips: + sL1D Cache BW: + value: AVG(((SQC_DCACHE_REQ / (End_Timestamp - Start_Timestamp)) * 64)) + unit: GB/s + peak: ((($max_sclk / 1000) * 64) * $sqc_per_gpu) + pop: ((100 * AVG(((SQC_DCACHE_REQ / (End_Timestamp - Start_Timestamp)) * 64))) / ((($max_sclk + / 1000) * 64) * $sqc_per_gpu)) + tips: + L1I Hit Rate: + value: AVG(((100 * SQC_ICACHE_HITS) / (SQC_ICACHE_HITS + SQC_ICACHE_MISSES))) + unit: pct + peak: 100 + pop: AVG(((100 * SQC_ICACHE_HITS) / (SQC_ICACHE_HITS + SQC_ICACHE_MISSES))) + tips: + L1I BW: + value: AVG(((SQC_ICACHE_REQ / (End_Timestamp - Start_Timestamp)) * 64)) + unit: GB/s + peak: ((($max_sclk / 1000) * 64) * $sqc_per_gpu) + pop: ((100 * AVG(((SQC_ICACHE_REQ / (End_Timestamp - Start_Timestamp)) * 64))) / ((($max_sclk + / 1000) * 64) * $sqc_per_gpu)) + tips: + L1I Fetch Latency: + value: AVG((SQ_ACCUM_PREV_HIRES / SQ_IFETCH)) + unit: Cycles + peak: None + pop: None + coll_level: SQ_IFETCH_LEVEL + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0500_command-processor.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0500_command-processor.yaml new file mode 100644 index 0000000000..3e1a0d5f65 --- /dev/null +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0500_command-processor.yaml @@ -0,0 +1,153 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 500 + title: Command Processor (CPC/CPF) + data source: + - metric_table: + id: 501 + title: Command Processor Fetcher + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + CPF Utilization: + avg: AVG((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) + if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) + min: MIN((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) + if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) + max: MAX((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) + if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) + unit: pct + tips: + CPF Stall: + avg: AVG((((100 * CPF_CPF_STAT_STALL) / CPF_CPF_STAT_BUSY) if (CPF_CPF_STAT_BUSY + != 0) else None)) + min: MIN((((100 * CPF_CPF_STAT_STALL) / CPF_CPF_STAT_BUSY) if (CPF_CPF_STAT_BUSY + != 0) else None)) + max: MAX((((100 * CPF_CPF_STAT_STALL) / CPF_CPF_STAT_BUSY) if (CPF_CPF_STAT_BUSY + != 0) else None)) + unit: pct + tips: + CPF-L2 Utilization: + avg: AVG((((100 * CPF_CPF_TCIU_BUSY) / (CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE)) + if ((CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE) != 0) else None)) + min: MIN((((100 * CPF_CPF_TCIU_BUSY) / (CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE)) + if ((CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE) != 0) else None)) + max: MAX((((100 * CPF_CPF_TCIU_BUSY) / (CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE)) + if ((CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE) != 0) else None)) + unit: pct + tips: + CPF-L2 Stall: + avg: AVG((((100 * CPF_CPF_TCIU_STALL) / CPF_CPF_TCIU_BUSY) if (CPF_CPF_TCIU_BUSY + != 0) else None)) + min: MIN((((100 * CPF_CPF_TCIU_STALL) / CPF_CPF_TCIU_BUSY) if (CPF_CPF_TCIU_BUSY + != 0) else None)) + max: MAX((((100 * CPF_CPF_TCIU_STALL) / CPF_CPF_TCIU_BUSY) if (CPF_CPF_TCIU_BUSY + != 0) else None)) + unit: pct + tips: + CPF-UTCL1 Stall: + avg: AVG(((100 * CPF_CMP_UTCL1_STALL_ON_TRANSLATION) / CPF_CPF_STAT_BUSY) if (CPF_CPF_STAT_BUSY + != 0) else None) + min: MIN(((100 * CPF_CMP_UTCL1_STALL_ON_TRANSLATION) / CPF_CPF_STAT_BUSY) if (CPF_CPF_STAT_BUSY + != 0) else None) + max: MAX(((100 * CPF_CMP_UTCL1_STALL_ON_TRANSLATION) / CPF_CPF_STAT_BUSY) if (CPF_CPF_STAT_BUSY + != 0) else None) + unit: pct + tips: + + - metric_table: + id: 502 + title: Packet Processor + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + CPC SYNC FIFO Full Rate: + avg: AVG((100 * CPC_SYNC_FIFO_FULL) / CPC_SYNC_WRREQ_FIFO_BUSY if (CPC_SYNC_WRREQ_FIFO_BUSY != 0) else None) + min: MIN((100 * CPC_SYNC_FIFO_FULL) / CPC_SYNC_WRREQ_FIFO_BUSY if (CPC_SYNC_WRREQ_FIFO_BUSY != 0) else None) + max: MAX((100 * CPC_SYNC_FIFO_FULL) / CPC_SYNC_WRREQ_FIFO_BUSY if (CPC_SYNC_WRREQ_FIFO_BUSY != 0) else None) + unit: pct + tips: + CPC CANE Stall Rate: + avg: AVG((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None) + min: MIN((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None) + max: MAX((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None) + unit: pct + tips: + CPC ADC Utilization: + avg: AVG((100 * CPC_TG_SEND) / CPC_GD_BUSY if (CPC_GD_BUSY != 0) else None) + min: MIN((100 * CPC_TG_SEND) / CPC_GD_BUSY if (CPC_GD_BUSY != 0) else None) + max: MAX((100 * CPC_TG_SEND) / CPC_GD_BUSY if (CPC_GD_BUSY != 0) else None) + unit: pct + tips: + CPC Utilization: + avg: AVG((((100 * CPC_CPC_STAT_BUSY) / (CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE)) + if ((CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE) != 0) else None)) + min: MIN((((100 * CPC_CPC_STAT_BUSY) / (CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE)) + if ((CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE) != 0) else None)) + max: MAX((((100 * CPC_CPC_STAT_BUSY) / (CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE)) + if ((CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE) != 0) else None)) + unit: pct + tips: + CPC Stall Rate: + avg: AVG((((100 * CPC_CPC_STAT_STALL) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + min: MIN((((100 * CPC_CPC_STAT_STALL) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + max: MAX((((100 * CPC_CPC_STAT_STALL) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + unit: pct + tips: + CPC Packet Decoding Utilization: + avg: AVG((100 * CPC_ME1_BUSY_FOR_PACKET_DECODE) / CPC_CPC_STAT_BUSY if (CPC_CPC_STAT_BUSY != 0) else None) + min: MIN((100 * CPC_ME1_BUSY_FOR_PACKET_DECODE) / CPC_CPC_STAT_BUSY if (CPC_CPC_STAT_BUSY != 0) else None) + max: MAX((100 * CPC_ME1_BUSY_FOR_PACKET_DECODE) / CPC_CPC_STAT_BUSY if (CPC_CPC_STAT_BUSY != 0) else None) + unit: pct + tips: + CPC-Workgroup Manager Utilization: + avg: AVG((100 * CPC_ME1_DC0_SPI_BUSY) / CPC_CPC_STAT_BUSY if (CPC_CPC_STAT_BUSY != 0) else None) + min: MIN((100 * CPC_ME1_DC0_SPI_BUSY) / CPC_CPC_STAT_BUSY if (CPC_CPC_STAT_BUSY != 0) else None) + max: MAX((100 * CPC_ME1_DC0_SPI_BUSY) / CPC_CPC_STAT_BUSY if (CPC_CPC_STAT_BUSY != 0) else None) + unit: Pct + tips: + CPC-L2 Utilization: + avg: AVG((((100 * CPC_CPC_TCIU_BUSY) / (CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE)) + if ((CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE) != 0) else None)) + min: MIN((((100 * CPC_CPC_TCIU_BUSY) / (CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE)) + if ((CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE) != 0) else None)) + max: MAX((((100 * CPC_CPC_TCIU_BUSY) / (CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE)) + if ((CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE) != 0) else None)) + unit: pct + tips: + CPC-UTCL1 Stall: + avg: AVG(((100 * CPC_UTCL1_STALL_ON_TRANSLATION) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None) + min: MIN(((100 * CPC_UTCL1_STALL_ON_TRANSLATION) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None) + max: MAX(((100 * CPC_UTCL1_STALL_ON_TRANSLATION) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None) + unit: pct + tips: + CPC-UTCL2 Utilization: + avg: AVG((((100 * CPC_CPC_UTCL2IU_BUSY) / (CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE)) + if ((CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE) != 0) else None)) + min: MIN((((100 * CPC_CPC_UTCL2IU_BUSY) / (CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE)) + if ((CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE) != 0) else None)) + max: MAX((((100 * CPC_CPC_UTCL2IU_BUSY) / (CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE)) + if ((CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE) != 0) else None)) + unit: pct + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0600_shader-processor-input.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0600_shader-processor-input.yaml new file mode 100644 index 0000000000..d2b5944459 --- /dev/null +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0600_shader-processor-input.yaml @@ -0,0 +1,188 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 600 + title: Workgroup Manager (SPI) + data source: + - metric_table: + id: 601 + title: Workgroup Manager Utilizations + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Schedule-Pipe Wave Occupancy: + avg: AVG(SPI_CSQ_P0_OCCUPANCY + SPI_CSQ_P1_OCCUPANCY + SPI_CSQ_P2_OCCUPANCY + SPI_CSQ_P3_OCCUPANCY) + min: MIN(SPI_CSQ_P0_OCCUPANCY + SPI_CSQ_P1_OCCUPANCY + SPI_CSQ_P2_OCCUPANCY + SPI_CSQ_P3_OCCUPANCY) + max: MAX(SPI_CSQ_P0_OCCUPANCY + SPI_CSQ_P1_OCCUPANCY + SPI_CSQ_P2_OCCUPANCY + SPI_CSQ_P3_OCCUPANCY) + unit: Wave + tips: + Accelerator Utilization: + avg: AVG(100 * $GRBM_GUI_ACTIVE_PER_XCD / $GRBM_COUNT_PER_XCD) + min: MIN(100 * $GRBM_GUI_ACTIVE_PER_XCD / $GRBM_COUNT_PER_XCD) + max: MAX(100 * $GRBM_GUI_ACTIVE_PER_XCD / $GRBM_COUNT_PER_XCD) + unit: Pct + tips: + Scheduler-Pipe Utilization: + avg: AVG(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu)) + min: MIN(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu)) + max: MAX(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu)) + unit: Pct + tips: + Scheduler-Pipe Wave Utilization: + avg: AVG(100 * (SPI_CSC_WAVE_CNT_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu)) + min: MIN(100 * (SPI_CSC_WAVE_CNT_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu)) + max: MAX(100 * (SPI_CSC_WAVE_CNT_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu)) + unit: Pct + tips: + Workgroup Manager Utilization: + avg: AVG(100 * $GRBM_SPI_BUSY_PER_XCD / $GRBM_GUI_ACTIVE_PER_XCD) + min: MIN(100 * $GRBM_SPI_BUSY_PER_XCD / $GRBM_GUI_ACTIVE_PER_XCD) + max: MAX(100 * $GRBM_SPI_BUSY_PER_XCD / $GRBM_GUI_ACTIVE_PER_XCD) + unit: Pct + tips: + Shader Engine Utilization: + avg: AVG(100 * SQ_BUSY_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $se_per_gpu)) + min: MIN(100 * SQ_BUSY_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $se_per_gpu)) + max: MAX(100 * SQ_BUSY_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $se_per_gpu)) + unit: Pct + tips: + SIMD Utilization: + avg: AVG(100 * SQ_BUSY_CU_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + min: MIN(100 * SQ_BUSY_CU_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + max: MAX(100 * SQ_BUSY_CU_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + unit: Pct + tips: + Dispatched Workgroups: + avg: AVG(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS) + min: MIN(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS) + max: MAX(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS) + unit: Workgroups + tips: + Dispatched Wavefronts: + avg: AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) + min: MIN(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) + max: MAX(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) + unit: Wavefronts + tips: + VGPR Writes: + avg: AVG((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else + None)) + min: MIN((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else + None)) + max: MAX((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else + None)) + unit: Cycles/wave + tips: + SGPR Writes: + avg: AVG((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else + None)) + min: MIN((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else + None)) + max: MAX((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else + None)) + unit: Cycles/wave + tips: + - metric_table: + id: 602 + title: Workgroup Manager - Resource Allocation + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Not-scheduled Rate (Workgroup Manager): + avg: AVG((100 * SPI_RA_REQ_NO_ALLOC_CSN / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != + 0) else None) + min: MIN((100 * SPI_RA_REQ_NO_ALLOC_CSN / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != + 0) else None) + max: MAX((100 * SPI_RA_REQ_NO_ALLOC_CSN / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != + 0) else None) + unit: Pct + tips: + Not-scheduled Rate (Scheduler-Pipe): + avg: AVG((100 * SPI_RA_REQ_NO_ALLOC / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != + 0) else None) + min: MIN((100 * SPI_RA_REQ_NO_ALLOC / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != + 0) else None) + max: MAX((100 * SPI_RA_REQ_NO_ALLOC / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != + 0) else None) + unit: Pct + tips: + Scheduler-Pipe FIFO Full Rate: + avg: AVG((100 * (SPI_CS0_CRAWLER_STALL + SPI_CS1_CRAWLER_STALL + SPI_CS2_CRAWLER_STALL + SPI_CS3_CRAWLER_STALL) / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != + 0) else None) + min: MIN((100 * (SPI_CS0_CRAWLER_STALL + SPI_CS1_CRAWLER_STALL + SPI_CS2_CRAWLER_STALL + SPI_CS3_CRAWLER_STALL) / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != + 0) else None) + max: MAX((100 * (SPI_CS0_CRAWLER_STALL + SPI_CS1_CRAWLER_STALL + SPI_CS2_CRAWLER_STALL + SPI_CS3_CRAWLER_STALL) / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != + 0) else None) + unit: Pct + tips: + Scheduler-Pipe Stall Rate: + avg: AVG((((100 * SPI_RA_RES_STALL_CSN) / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != + 0) else None)) + min: MIN((((100 * SPI_RA_RES_STALL_CSN) / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != + 0) else None)) + max: MAX((((100 * SPI_RA_RES_STALL_CSN) / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != + 0) else None)) + unit: Pct + tips: + Scratch Stall Rate: + avg: AVG((100 * SPI_RA_TMP_STALL_CSN / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != 0) else None) + min: MIN((100 * SPI_RA_TMP_STALL_CSN / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != 0) else None) + max: MAX((100 * SPI_RA_TMP_STALL_CSN / ($GRBM_SPI_BUSY_PER_XCD * $se_per_gpu)) if ($GRBM_SPI_BUSY_PER_XCD != 0) else None) + unit: Pct + tips: + Insufficient SIMD Waveslots: + avg: AVG(100 * SPI_RA_WAVE_SIMD_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + min: MIN(100 * SPI_RA_WAVE_SIMD_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + max: MAX(100 * SPI_RA_WAVE_SIMD_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + unit: Pct + tips: + Insufficient SIMD VGPRs: + avg: AVG(100 * SPI_RA_VGPR_SIMD_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + min: MIN(100 * SPI_RA_VGPR_SIMD_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + max: MAX(100 * SPI_RA_VGPR_SIMD_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + unit: Pct + tips: + Insufficient SIMD SGPRs: + avg: AVG(100 * SPI_RA_SGPR_SIMD_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + min: MIN(100 * SPI_RA_SGPR_SIMD_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + max: MAX(100 * SPI_RA_SGPR_SIMD_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + unit: Pct + tips: + Insufficient CU LDS: + avg: AVG(400 * SPI_RA_LDS_CU_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + min: MIN(400 * SPI_RA_LDS_CU_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + max: MAX(400 * SPI_RA_LDS_CU_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + unit: Pct + tips: + Insufficient CU Barriers: + avg: AVG(400 * SPI_RA_BAR_CU_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + min: MIN(400 * SPI_RA_BAR_CU_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + max: MAX(400 * SPI_RA_BAR_CU_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + unit: Pct + tips: + Reached CU Workgroup Limit: + avg: AVG(400 * SPI_RA_TGLIM_CU_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + min: MIN(400 * SPI_RA_TGLIM_CU_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + max: MAX(400 * SPI_RA_TGLIM_CU_FULL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + unit: Pct + tips: + Reached CU Wavefront Limit: + avg: AVG(400 * SPI_RA_WVLIM_STALL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + min: MIN(400 * SPI_RA_WVLIM_STALL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + max: MAX(400 * SPI_RA_WVLIM_STALL_CSN / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu)) + unit: Pct + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0700_wavefront-launch.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0700_wavefront-launch.yaml new file mode 100644 index 0000000000..7a3317e514 --- /dev/null +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0700_wavefront-launch.yaml @@ -0,0 +1,142 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 700 + title: Wavefront + data source: + - metric_table: + id: 701 + title: Wavefront Launch Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Grid Size: + avg: AVG(Grid_Size) + min: MIN(Grid_Size) + max: MAX(Grid_Size) + unit: Work Items + tips: + Workgroup Size: + avg: AVG(Workgroup_Size) + min: MIN(Workgroup_Size) + max: MAX(Workgroup_Size) + unit: Work Items + tips: + Total Wavefronts: + avg: AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) + min: MIN(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) + max: MAX(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) + unit: Wavefronts + tips: + Saved Wavefronts: + avg: AVG(SQ_WAVES_SAVED) + min: MIN(SQ_WAVES_SAVED) + max: MAX(SQ_WAVES_SAVED) + unit: Wavefronts + tips: + Restored Wavefronts: + avg: AVG(SQ_WAVES_RESTORED) + min: MIN(SQ_WAVES_RESTORED) + max: MAX(SQ_WAVES_RESTORED) + unit: Wavefronts + tips: + VGPRs: + avg: AVG(Arch_VGPR) + min: MIN(Arch_VGPR) + max: MAX(Arch_VGPR) + unit: Registers + tips: + AGPRs: + avg: AVG(Accum_VGPR) + min: MIN(Accum_VGPR) + max: MAX(Accum_VGPR) + unit: Registers + tips: + SGPRs: + avg: AVG(SGPR) + min: MIN(SGPR) + max: MAX(SGPR) + unit: Registers + tips: + LDS Allocation: + avg: AVG(LDS_Per_Workgroup) + min: MIN(LDS_Per_Workgroup) + max: MAX(LDS_Per_Workgroup) + unit: Bytes + tips: + Scratch Allocation: + avg: AVG(Scratch_Per_Workitem) + min: MIN(Scratch_Per_Workitem) + max: MAX(Scratch_Per_Workitem) + unit: Bytes/Workitem + tips: + + - metric_table: + id: 702 + title: Wavefront Runtime Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Kernel Time (Nanosec): + avg: AVG((End_Timestamp - Start_Timestamp)) + min: MIN((End_Timestamp - Start_Timestamp)) + max: MAX((End_Timestamp - Start_Timestamp)) + unit: ns + tips: + Kernel Time (Cycles): + avg: AVG($GRBM_GUI_ACTIVE_PER_XCD) + min: MIN($GRBM_GUI_ACTIVE_PER_XCD) + max: MAX($GRBM_GUI_ACTIVE_PER_XCD) + unit: Cycle + tips: + Instructions per wavefront: + avg: AVG((SQ_INSTS / SQ_WAVES)) + min: MIN((SQ_INSTS / SQ_WAVES)) + max: MAX((SQ_INSTS / SQ_WAVES)) + unit: Instr/wavefront + tips: + Wave Cycles: + avg: AVG(((4 * SQ_WAVE_CYCLES) / $denom)) + min: MIN(((4 * SQ_WAVE_CYCLES) / $denom)) + max: MAX(((4 * SQ_WAVE_CYCLES) / $denom)) + unit: (Cycles + $normUnit) + tips: + Dependency Wait Cycles: + avg: AVG(((4 * SQ_WAIT_ANY) / $denom)) + min: MIN(((4 * SQ_WAIT_ANY) / $denom)) + max: MAX(((4 * SQ_WAIT_ANY) / $denom)) + unit: (Cycles + $normUnit) + tips: + Issue Wait Cycles: + avg: AVG(((4 * SQ_WAIT_INST_ANY) / $denom)) + min: MIN(((4 * SQ_WAIT_INST_ANY) / $denom)) + max: MAX(((4 * SQ_WAIT_INST_ANY) / $denom)) + unit: (Cycles + $normUnit) + tips: + Active Cycles: + avg: AVG(((4 * SQ_ACTIVE_INST_ANY) / $denom)) + min: MIN(((4 * SQ_ACTIVE_INST_ANY) / $denom)) + max: MAX(((4 * SQ_ACTIVE_INST_ANY) / $denom)) + unit: (Cycles + $normUnit) + tips: + Wavefront Occupancy: + avg: AVG((SQ_ACCUM_PREV_HIRES / $GRBM_GUI_ACTIVE_PER_XCD)) + min: MIN((SQ_ACCUM_PREV_HIRES / $GRBM_GUI_ACTIVE_PER_XCD)) + max: MAX((SQ_ACCUM_PREV_HIRES / $GRBM_GUI_ACTIVE_PER_XCD)) + unit: Wavefronts + coll_level: SQ_LEVEL_WAVES + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1000_compute-unit-instruction-mix.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1000_compute-unit-instruction-mix.yaml index c27ce84c8c..bdc273dfad 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1000_compute-unit-instruction-mix.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1000_compute-unit-instruction-mix.yaml @@ -185,15 +185,6 @@ Panel Config: max: MAX((TA_FLAT_WAVEFRONTS_sum / $denom)) unit: (instr + $normUnit) tips: - Global/Generic Coalesceable Instr: - avg: None - # AVG((TA_FLAT_COALESCEABLE_WAVEFRONTS_sum / $denom)) - min: None - # MIN((TA_FLAT_COALESCEABLE_WAVEFRONTS_sum / $denom)) - max: None - # MAX((TA_FLAT_COALESCEABLE_WAVEFRONTS_sum / $denom)) - unit: (instr + $normUnit) - tips: Global/Generic Read: avg: AVG((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) min: MIN((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) @@ -290,3 +281,9 @@ Panel Config: max: MAX((SQ_INSTS_VALU_MFMA_F64 / $denom)) unit: (instr + $normUnit) tips: + MFMA-F6F4: + avg: AVG((SQ_INSTS_VALU_MFMA_F6F4 / $denom)) + min: MIN((SQ_INSTS_VALU_MFMA_F6F4 / $denom)) + max: MAX((SQ_INSTS_VALU_MFMA_F6F4 / $denom)) + unit: (instr + $normUnit) + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1100_compute-unit-compute-pipeline.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1100_compute-unit-compute-pipeline.yaml new file mode 100644 index 0000000000..6c0674ec77 --- /dev/null +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1100_compute-unit-compute-pipeline.yaml @@ -0,0 +1,293 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1100 + title: Compute Units - Compute Pipeline + data source: + - metric_table: + id: 1101 + title: Speed-of-Light + header: + metric: Metric + value: Avg + unit: Unit + peak: Peak + pop: Pct of Peak + tips: Tips + metric: + VALU FLOPs: + value: AVG(((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + + (2 * SQ_INSTS_VALU_FMA_F16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + + SQ_INSTS_VALU_TRANS_F32) + (2 * SQ_INSTS_VALU_FMA_F32)))) + (64 * (((SQ_INSTS_VALU_ADD_F64 + + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (2 * SQ_INSTS_VALU_FMA_F64)))) + / (End_Timestamp - Start_Timestamp))) + unit: GFLOP + peak: (((($max_sclk * $cu_per_gpu) * 64) * 2) / 1000) + pop: ((100 * AVG(((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + + SQ_INSTS_VALU_TRANS_F16) + (2 * SQ_INSTS_VALU_FMA_F16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (2 * SQ_INSTS_VALU_FMA_F32)))) + + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (2 * SQ_INSTS_VALU_FMA_F64)))) / (End_Timestamp - Start_Timestamp)))) / (((($max_sclk + * $cu_per_gpu) * 64) * 2) / 1000)) + tips: + VALU IOPs: + value: AVG(((64 * (SQ_INSTS_VALU_INT32 + SQ_INSTS_VALU_INT64)) / (End_Timestamp - Start_Timestamp))) + unit: GIOP + peak: (((($max_sclk * $cu_per_gpu) * 64) * 2) / 1000) + pop: ((100 * AVG(((64 * (SQ_INSTS_VALU_INT32 + SQ_INSTS_VALU_INT64)) / (End_Timestamp + - Start_Timestamp)))) / (((($max_sclk * $cu_per_gpu) * 64) * 2) / 1000)) + tips: + MFMA FLOPs (F8): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) / (End_Timestamp - Start_Timestamp))) + unit: GFLOP + peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk * $cu_per_gpu) * 8192) / 1000)) + tips: + MFMA FLOPs (BF16): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) / (End_Timestamp - Start_Timestamp))) + unit: GFLOP + peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk * $cu_per_gpu) * 4096) / 1000)) + tips: + MFMA FLOPs (F16): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (End_Timestamp - Start_Timestamp))) + unit: GFLOP + peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk * $cu_per_gpu) * 4096) / 1000)) + tips: + MFMA FLOPs (F32): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) / (End_Timestamp - Start_Timestamp))) + unit: GFLOP + peak: ((($max_sclk * $cu_per_gpu) * 256) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk * $cu_per_gpu) * 256) / 1000)) + tips: + MFMA FLOPs (F64): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp))) + unit: GFLOP + peak: ((($max_sclk * $cu_per_gpu) * 256) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk * $cu_per_gpu) * 256) / 1000)) + tips: + MFMA FLOPs (F6F4): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) / (End_Timestamp - Start_Timestamp))) + unit: GFLOP + peak: ((($max_sclk * $cu_per_gpu) * 256) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk * $cu_per_gpu) * 256) / 1000)) + tips: + MFMA IOPs (INT8): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp))) + unit: GIOP + peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp)))) + / ((($max_sclk * $cu_per_gpu) * 8192) / 1000)) + tips: + + - metric_table: + id: 1102 + title: Pipeline Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + IPC: + avg: AVG((SQ_INSTS / SQ_BUSY_CU_CYCLES)) + min: MIN((SQ_INSTS / SQ_BUSY_CU_CYCLES)) + max: MAX((SQ_INSTS / SQ_BUSY_CU_CYCLES)) + unit: Instr/cycle + tips: + IPC (Issued): + avg: AVG(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM)) + + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED + SQ_INSTS_LDS) + / SQ_ACTIVE_INST_ANY)) + min: MIN(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM)) + + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED + SQ_INSTS_LDS) + / SQ_ACTIVE_INST_ANY)) + max: MAX(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM)) + + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED + SQ_INSTS_LDS) + / SQ_ACTIVE_INST_ANY)) + unit: Instr/cycle + tips: + SALU Utilization: + avg: AVG((((100 * SQ_ACTIVE_INST_SCA) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + min: MIN((((100 * SQ_ACTIVE_INST_SCA) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + max: MAX((((100 * SQ_ACTIVE_INST_SCA) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + unit: pct + tips: + VALU Utilization: + avg: AVG((((100 * SQ_ACTIVE_INST_VALU) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + min: MIN((((100 * SQ_ACTIVE_INST_VALU) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + max: MAX((((100 * SQ_ACTIVE_INST_VALU) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + unit: pct + tips: + # Precentage of VALU instructions which are issued to two VALUs at a time + VALU Co-Issue Efficiency: + avg: AVG((100 * SQ_ACTIVE_INST_VALU2) / (SQ_ACTIVE_INST_VALU - SQ_ACTIVE_INST_VALU2)) + min: MIN((100 * SQ_ACTIVE_INST_VALU2) / (SQ_ACTIVE_INST_VALU - SQ_ACTIVE_INST_VALU2)) + max: MAX((100 * SQ_ACTIVE_INST_VALU2) / (SQ_ACTIVE_INST_VALU - SQ_ACTIVE_INST_VALU2)) + unit: pct + tips: + VMEM Utilization: + avg: AVG((((100 * (SQ_ACTIVE_INST_FLAT+SQ_ACTIVE_INST_VMEM)) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + min: MIN((((100 * (SQ_ACTIVE_INST_FLAT+SQ_ACTIVE_INST_VMEM)) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + max: MAX((((100 * (SQ_ACTIVE_INST_FLAT+SQ_ACTIVE_INST_VMEM)) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + unit: pct + tips: + Branch Utilization: + avg: AVG((((100 * SQ_ACTIVE_INST_MISC) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + min: MIN((((100 * SQ_ACTIVE_INST_MISC) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + max: MAX((((100 * SQ_ACTIVE_INST_MISC) / $GRBM_GUI_ACTIVE_PER_XCD) / $cu_per_gpu)) + unit: pct + tips: + VALU Active Threads: + avg: AVG(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + min: MIN(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + max: MAX(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + unit: Threads + tips: + MFMA Utilization: + avg: AVG(((100 * SQ_VALU_MFMA_BUSY_CYCLES) / ((4 * $cu_per_gpu) * $GRBM_GUI_ACTIVE_PER_XCD))) + min: MIN(((100 * SQ_VALU_MFMA_BUSY_CYCLES) / ((4 * $cu_per_gpu) * $GRBM_GUI_ACTIVE_PER_XCD))) + max: MAX(((100 * SQ_VALU_MFMA_BUSY_CYCLES) / ((4 * $cu_per_gpu) * $GRBM_GUI_ACTIVE_PER_XCD))) + unit: pct + tips: + MFMA Instr Cycles: + avg: AVG(((SQ_VALU_MFMA_BUSY_CYCLES / SQ_INSTS_MFMA) if (SQ_INSTS_MFMA != 0) + else None)) + min: MIN(((SQ_VALU_MFMA_BUSY_CYCLES / SQ_INSTS_MFMA) if (SQ_INSTS_MFMA != 0) + else None)) + max: MAX(((SQ_VALU_MFMA_BUSY_CYCLES / SQ_INSTS_MFMA) if (SQ_INSTS_MFMA != 0) + else None)) + unit: cycles/instr + tips: + VMEM Latency: + avg: AVG(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_VMEM) if (SQ_INSTS_VMEM != 0) + else None)) + min: MIN(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_VMEM) if (SQ_INSTS_VMEM != 0) + else None)) + max: MAX(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_VMEM) if (SQ_INSTS_VMEM != 0) + else None)) + unit: Cycles + coll_level: SQ_INST_LEVEL_VMEM + tips: + SMEM Latency: + avg: AVG(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_SMEM) if (SQ_INSTS_SMEM != 0) + else None)) + min: MIN(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_SMEM) if (SQ_INSTS_SMEM != 0) + else None)) + max: MAX(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_SMEM) if (SQ_INSTS_SMEM != 0) + else None)) + unit: Cycles + coll_level: SQ_INST_LEVEL_SMEM + tips: + + - metric_table: + id: 1103 + title: Arithmetic Operations + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + FLOPs (Total): + avg: AVG((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 + * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / + $denom)) + min: MIN((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 + * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / + $denom)) + max: MAX((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 + * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / + $denom)) + unit: (OPs + $normUnit) + tips: + IOPs (Total): + avg: AVG(((64 * (SQ_INSTS_VALU_INT32 + SQ_INSTS_VALU_INT64)) + (SQ_INSTS_VALU_MFMA_MOPS_I8 * 512)) / $denom) + min: MIN(((64 * (SQ_INSTS_VALU_INT32 + SQ_INSTS_VALU_INT64)) + (SQ_INSTS_VALU_MFMA_MOPS_I8 * 512)) / $denom) + max: MAX(((64 * (SQ_INSTS_VALU_INT32 + SQ_INSTS_VALU_INT64)) + (SQ_INSTS_VALU_MFMA_MOPS_I8 * 512)) / $denom) + unit: (OPs + $normUnit) + tips: + F8 OPs: + avg: AVG(((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) / $denom)) + min: MIN(((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) / $denom)) + max: MAX(((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) / $denom)) + unit: (OPs + $normUnit) + tips: + F16 OPs: + avg: AVG(((((((64 * SQ_INSTS_VALU_ADD_F16) + (64 * SQ_INSTS_VALU_MUL_F16)) + + (64 * SQ_INSTS_VALU_TRANS_F16)) + (128 * SQ_INSTS_VALU_FMA_F16)) + (512 * + SQ_INSTS_VALU_MFMA_MOPS_F16)) / $denom)) + min: MIN(((((((64 * SQ_INSTS_VALU_ADD_F16) + (64 * SQ_INSTS_VALU_MUL_F16)) + + (64 * SQ_INSTS_VALU_TRANS_F16)) + (128 * SQ_INSTS_VALU_FMA_F16)) + (512 * + SQ_INSTS_VALU_MFMA_MOPS_F16)) / $denom)) + max: MAX(((((((64 * SQ_INSTS_VALU_ADD_F16) + (64 * SQ_INSTS_VALU_MUL_F16)) + + (64 * SQ_INSTS_VALU_TRANS_F16)) + (128 * SQ_INSTS_VALU_FMA_F16)) + (512 * + SQ_INSTS_VALU_MFMA_MOPS_F16)) / $denom)) + unit: (OPs + $normUnit) + tips: + BF16 OPs: + avg: AVG(((512 * SQ_INSTS_VALU_MFMA_MOPS_BF16) / $denom)) + min: MIN(((512 * SQ_INSTS_VALU_MFMA_MOPS_BF16) / $denom)) + max: MAX(((512 * SQ_INSTS_VALU_MFMA_MOPS_BF16) / $denom)) + unit: (OPs + $normUnit) + tips: + F32 OPs: + avg: AVG((((64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + + (SQ_INSTS_VALU_FMA_F32 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) / $denom)) + min: MIN((((64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + + (SQ_INSTS_VALU_FMA_F32 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) / $denom)) + max: MAX((((64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + + (SQ_INSTS_VALU_FMA_F32 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) / $denom)) + unit: (OPs + $normUnit) + tips: + F64 OPs: + avg: AVG((((64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (SQ_INSTS_VALU_FMA_F64 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64)) / $denom)) + min: MIN((((64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (SQ_INSTS_VALU_FMA_F64 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64)) / $denom)) + max: MAX((((64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (SQ_INSTS_VALU_FMA_F64 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64)) / $denom)) + unit: (OPs + $normUnit) + tips: + F6F4 OPs: + avg: AVG((512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4) / $denom) + min: MIN((512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4) / $denom) + max: MAX((512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4) / $denom) + unit: (OPs + $normUnit) + tips: + INT8 OPs: + avg: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / $denom)) + min: MIN(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / $denom)) + max: MAX(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / $denom)) + unit: (OPs + $normUnit) + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1200_lds.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1200_lds.yaml new file mode 100644 index 0000000000..3b0669d4de --- /dev/null +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1200_lds.yaml @@ -0,0 +1,166 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1200 + title: Local Data Share (LDS) + data source: + - metric_table: + id: 1201 + title: Speed-of-Light + header: + metric: Metric + value: Avg + unit: Unit + tips: Tips + metric: + Utilization: + value: AVG(((100 * SQ_LDS_IDX_ACTIVE) / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))) + unit: Pct of Peak + tips: + Access Rate: + value: AVG(((200 * SQ_ACTIVE_INST_LDS) / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))) + unit: Pct of Peak + tips: + Theoretical Bandwidth (% of Peak): + value: AVG((((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($lds_banks_per_cu)) + / (End_Timestamp - Start_Timestamp)) / (($max_sclk * $cu_per_gpu) * 0.00128))) + unit: Pct of Peak + tips: + Bank Conflict Rate: + value: AVG((((SQ_LDS_BANK_CONFLICT * 3.125) / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + unit: Pct of Peak + tips: + comparable: false # for now + cli_style: simple_bar + + - metric_table: + id: 1202 + title: LDS Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + LDS Instrs: + avg: AVG((SQ_INSTS_LDS / $denom)) + min: MIN((SQ_INSTS_LDS / $denom)) + max: MAX((SQ_INSTS_LDS / $denom)) + unit: (Instr + $normUnit) + tips: + LDS LOAD: + avg: AVG((SQ_INSTS_LDS_LOAD / $denom)) + min: MIN((SQ_INSTS_LDS_LOAD / $denom)) + max: MAX((SQ_INSTS_LDS_LOAD / $denom)) + unit: (instr + $normUnit) + tips: + LDS STORE: + avg: AVG((SQ_INSTS_LDS_STORE / $denom)) + min: MIN((SQ_INSTS_LDS_STORE / $denom)) + max: MAX((SQ_INSTS_LDS_STORE / $denom)) + unit: (instr + $normUnit) + tips: + LDS ATOMIC: + avg: AVG((SQ_INSTS_LDS_ATOMIC / $denom)) + min: MIN((SQ_INSTS_LDS_ATOMIC / $denom)) + max: MAX((SQ_INSTS_LDS_ATOMIC / $denom)) + unit: (instr + $normUnit) + tips: + LDS LOAD Bandwidth: + avg: AVG(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp)) + min: MIN(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp)) + max: MAX(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp)) + units: Gbps + tips: + LDS STORE Bandwidth: + avg: AVG(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp)) + min: MIN(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp)) + max: MAX(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp)) + units: Gbps + tips: + LDS ATOMIC Bandwidth: + avg: AVG(64 * SQ_INSTS_LDS_ATOMIC_BANDWIDTH / (End_Timestamp - Start_Timestamp)) + min: MIN(64 * SQ_INSTS_LDS_ATOMIC_BANDWIDTH / (End_Timestamp - Start_Timestamp)) + max: MAX(64 * SQ_INSTS_LDS_ATOMIC_BANDWIDTH / (End_Timestamp - Start_Timestamp)) + units: Gbps + tips: + Theoretical Bandwidth: + avg: AVG(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($lds_banks_per_cu)) + / $denom)) + min: MIN(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($lds_banks_per_cu)) + / $denom)) + max: MAX(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($lds_banks_per_cu)) + / $denom)) + unit: (Bytes + $normUnit) + tips: + LDS Latency: + avg: AVG(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)) + min: MIN(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)) + max: MAX(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)) + unit: Cycles + coll_level: SQ_INST_LEVEL_LDS + tips: + Bank Conflicts/Access: + avg: AVG(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + min: MIN(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + max: MAX(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + unit: Conflicts/Access + tips: + Index Accesses: + avg: AVG((SQ_LDS_IDX_ACTIVE / $denom)) + min: MIN((SQ_LDS_IDX_ACTIVE / $denom)) + max: MAX((SQ_LDS_IDX_ACTIVE / $denom)) + unit: (Cycles + $normUnit) + tips: + Atomic Return Cycles: + avg: AVG((SQ_LDS_ATOMIC_RETURN / $denom)) + min: MIN((SQ_LDS_ATOMIC_RETURN / $denom)) + max: MAX((SQ_LDS_ATOMIC_RETURN / $denom)) + unit: (Cycles + $normUnit) + tips: + Bank Conflict: + avg: AVG((SQ_LDS_BANK_CONFLICT / $denom)) + min: MIN((SQ_LDS_BANK_CONFLICT / $denom)) + max: MAX((SQ_LDS_BANK_CONFLICT / $denom)) + unit: (Cycles + $normUnit) + tips: + Addr Conflict: + avg: AVG((SQ_LDS_ADDR_CONFLICT / $denom)) + min: MIN((SQ_LDS_ADDR_CONFLICT / $denom)) + max: MAX((SQ_LDS_ADDR_CONFLICT / $denom)) + unit: (Cycles + $normUnit) + tips: + Unaligned Stall: + avg: AVG((SQ_LDS_UNALIGNED_STALL / $denom)) + min: MIN((SQ_LDS_UNALIGNED_STALL / $denom)) + max: MAX((SQ_LDS_UNALIGNED_STALL / $denom)) + unit: (Cycles + $normUnit) + tips: + Mem Violations: + avg: AVG((SQ_LDS_MEM_VIOLATIONS / $denom)) + min: MIN((SQ_LDS_MEM_VIOLATIONS / $denom)) + max: MAX((SQ_LDS_MEM_VIOLATIONS / $denom)) + unit: (Accesses + $normUnit) + tips: + LDS Command FIFO Full Rate: + avg: AVG((SQ_LDS_CMD_FIFO_FULL / $denom)) + min: MIN((SQ_LDS_CMD_FIFO_FULL / $denom)) + max: MAX((SQ_LDS_CMD_FIFO_FULL / $denom)) + unit: (Cycles + $normUnit) + tips: + LDS Data FIFO Full Rate: + avg: AVG((SQ_LDS_DATA_FIFO_FULL / $denom)) + min: MIN((SQ_LDS_DATA_FIFO_FULL / $denom)) + max: MAX((SQ_LDS_DATA_FIFO_FULL / $denom)) + unit: (Cycles + $normUnit) + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1300_instruction-cache.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1300_instruction-cache.yaml new file mode 100644 index 0000000000..209a42726e --- /dev/null +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1300_instruction-cache.yaml @@ -0,0 +1,105 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1300 + title: Instruction Cache + data source: + - metric_table: + id: 1301 + title: Speed-of-Light + header: + metric: Metric + value: Avg + unit: Unit + tips: Tips + metric: + Bandwidth: + value: AVG(((SQC_ICACHE_REQ * 100000) / (($max_sclk * $sqc_per_gpu) + * (End_Timestamp - Start_Timestamp)))) + unit: Pct of Peak + tips: + Cache Hit Rate: + value: AVG(((SQC_ICACHE_HITS * 100) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + unit: Pct of Peak + tips: + L1I-L2 Bandwidth: + value: AVG(((SQC_TC_INST_REQ * 100000) / (2 * ($max_sclk * $sqc_per_gpu) + * (End_Timestamp - Start_Timestamp)))) + unit: Pct of Peak + tips: + comparable: false # for now + cli_style: simple_bar + + - metric_table: + id: 1302 + title: Instruction Cache Accesses + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Req: + avg: AVG((SQC_ICACHE_REQ / $denom)) + min: MIN((SQC_ICACHE_REQ / $denom)) + max: MAX((SQC_ICACHE_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Hits: + avg: AVG((SQC_ICACHE_HITS / $denom)) + min: MIN((SQC_ICACHE_HITS / $denom)) + max: MAX((SQC_ICACHE_HITS / $denom)) + unit: (Hits + $normUnit) + tips: + Misses - Non Duplicated: + avg: AVG((SQC_ICACHE_MISSES / $denom)) + min: MIN((SQC_ICACHE_MISSES / $denom)) + max: MAX((SQC_ICACHE_MISSES / $denom)) + unit: (Misses + $normUnit) + tips: + Misses - Duplicated: + avg: AVG((SQC_ICACHE_MISSES_DUPLICATE / $denom)) + min: MIN((SQC_ICACHE_MISSES_DUPLICATE / $denom)) + max: MAX((SQC_ICACHE_MISSES_DUPLICATE / $denom)) + unit: (Misses + $normUnit) + tips: + Cache Hit Rate: + avg: AVG(((100 * SQC_ICACHE_HITS) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + min: MIN(((100 * SQC_ICACHE_HITS) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + max: MAX(((100 * SQC_ICACHE_HITS) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + unit: pct + tips: + Instruction Fetch Latency: + avg: AVG((SQ_ACCUM_PREV_HIRES / SQ_IFETCH)) + min: MIN((SQ_ACCUM_PREV_HIRES / SQ_IFETCH)) + max: MAX((SQ_ACCUM_PREV_HIRES / SQ_IFETCH)) + unit: Cycles + coll_level: SQ_IFETCH_LEVEL + tips: + - metric_table: + id: 1303 + title: Instruction Cache - L2 Interface + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + L1I-L2 Bandwidth: + avg: AVG(((SQC_TC_INST_REQ * 64) / $denom)) + min: MIN(((SQC_TC_INST_REQ * 64) / $denom)) + max: MAX(((SQC_TC_INST_REQ * 64) / $denom)) + unit: (Bytes + $normUnit) + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1400_constant-cache.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1400_constant-cache.yaml new file mode 100644 index 0000000000..669a5834b9 --- /dev/null +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1400_constant-cache.yaml @@ -0,0 +1,171 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1400 + title: Scalar L1 Data Cache + data source: + - metric_table: + id: 1401 + title: Speed-of-Light + header: + metric: Metric + value: Avg + unit: Unit + tips: Tips + metric: + Bandwidth: + value: AVG(((SQC_DCACHE_REQ * 100000) / (($max_sclk * $sqc_per_gpu) + * (End_Timestamp - Start_Timestamp)))) + unit: Pct of Peak + tips: + Cache Hit Rate: + value: AVG((((SQC_DCACHE_HITS * 100) / (SQC_DCACHE_HITS + SQC_DCACHE_MISSES + SQC_DCACHE_MISSES_DUPLICATE)) + if ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + unit: Pct of Peak + tips: + sL1D-L2 BW: + value: AVG(((SQC_TC_DATA_READ_REQ + SQC_TC_DATA_WRITE_REQ + SQC_TC_DATA_ATOMIC_REQ) * 100000) + / (2 * ($max_sclk * $sqc_per_gpu) * (End_Timestamp - Start_Timestamp))) + unit: Pct of Peak + tips: + comparable: false # for now + cli_style: simple_bar + + - metric_table: + id: 1402 + title: Scalar L1D Cache Accesses + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Req: + avg: AVG((SQC_DCACHE_REQ / $denom)) + min: MIN((SQC_DCACHE_REQ / $denom)) + max: MAX((SQC_DCACHE_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Hits: + avg: AVG((SQC_DCACHE_HITS / $denom)) + min: MIN((SQC_DCACHE_HITS / $denom)) + max: MAX((SQC_DCACHE_HITS / $denom)) + unit: (Req + $normUnit) + tips: + Misses - Non Duplicated: + avg: AVG((SQC_DCACHE_MISSES / $denom)) + min: MIN((SQC_DCACHE_MISSES / $denom)) + max: MAX((SQC_DCACHE_MISSES / $denom)) + unit: (Req + $normUnit) + tips: + Misses- Duplicated: + avg: AVG((SQC_DCACHE_MISSES_DUPLICATE / $denom)) + min: MIN((SQC_DCACHE_MISSES_DUPLICATE / $denom)) + max: MAX((SQC_DCACHE_MISSES_DUPLICATE / $denom)) + unit: (Req + $normUnit) + tips: + Cache Hit Rate: + avg: AVG((((100 * SQC_DCACHE_HITS) / ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE)) if (((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + min: MIN((((100 * SQC_DCACHE_HITS) / ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE)) if (((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + max: MAX((((100 * SQC_DCACHE_HITS) / ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE)) if (((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + unit: pct + tips: + Read Req (Total): + avg: AVG((((((SQC_DCACHE_REQ_READ_1 + SQC_DCACHE_REQ_READ_2) + SQC_DCACHE_REQ_READ_4) + + SQC_DCACHE_REQ_READ_8) + SQC_DCACHE_REQ_READ_16) / $denom)) + min: MIN((((((SQC_DCACHE_REQ_READ_1 + SQC_DCACHE_REQ_READ_2) + SQC_DCACHE_REQ_READ_4) + + SQC_DCACHE_REQ_READ_8) + SQC_DCACHE_REQ_READ_16) / $denom)) + max: MAX((((((SQC_DCACHE_REQ_READ_1 + SQC_DCACHE_REQ_READ_2) + SQC_DCACHE_REQ_READ_4) + + SQC_DCACHE_REQ_READ_8) + SQC_DCACHE_REQ_READ_16) / $denom)) + unit: (Req + $normUnit) + tips: + Atomic Req: + avg: AVG((SQC_DCACHE_ATOMIC / $denom)) + min: MIN((SQC_DCACHE_ATOMIC / $denom)) + max: MAX((SQC_DCACHE_ATOMIC / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (1 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_1 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_1 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_1 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (2 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_2 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_2 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_2 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (4 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_4 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_4 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_4 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (8 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_8 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_8 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_8 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (16 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_16 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_16 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_16 / $denom)) + unit: (Req + $normUnit) + tips: + + - metric_table: + id: 1403 + title: Scalar L1D Cache - L2 Interface + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + sL1D-L2 BW: + avg: AVG(((((SQC_TC_DATA_READ_REQ + SQC_TC_DATA_WRITE_REQ + SQC_TC_DATA_ATOMIC_REQ) * 64)) / $denom)) + min: MIN(((((SQC_TC_DATA_READ_REQ + SQC_TC_DATA_WRITE_REQ + SQC_TC_DATA_ATOMIC_REQ) * 64)) / $denom)) + max: MAX(((((SQC_TC_DATA_READ_REQ + SQC_TC_DATA_WRITE_REQ + SQC_TC_DATA_ATOMIC_REQ) * 64)) / $denom)) + unit: (Bytes + $normUnit) + tips: + Read Req: + avg: AVG((SQC_TC_DATA_READ_REQ / $denom)) + min: MIN((SQC_TC_DATA_READ_REQ / $denom)) + max: MAX((SQC_TC_DATA_READ_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Write Req: + avg: AVG((SQC_TC_DATA_WRITE_REQ / $denom)) + min: MIN((SQC_TC_DATA_WRITE_REQ / $denom)) + max: MAX((SQC_TC_DATA_WRITE_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Atomic Req: + avg: AVG((SQC_TC_DATA_ATOMIC_REQ / $denom)) + min: MIN((SQC_TC_DATA_ATOMIC_REQ / $denom)) + max: MAX((SQC_TC_DATA_ATOMIC_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Stall Cycles: + avg: AVG((SQC_TC_STALL / $denom)) + min: MIN((SQC_TC_STALL / $denom)) + max: MAX((SQC_TC_STALL / $denom)) + unit: (Cycles + $normUnit) + tips: diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1500_TA_and_TD.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1500_TA_and_TD.yaml index e67355a21a..07b46993bb 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1500_TA_and_TD.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1500_TA_and_TD.yaml @@ -43,6 +43,24 @@ Panel Config: max: MAX(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))) unit: pct tips: + Sequencer → TA Address Stall: + avg: AVG((SQ_VMEM_TA_ADDR_FIFO_FULL / $denom)) + min: MIN((SQ_VMEM_TA_ADDR_FIFO_FULL / $denom)) + max: MAX((SQ_VMEM_TA_ADDR_FIFO_FULL / $denom)) + unit: (Cycles + $normUnit) + tips: + Sequencer → TA Command Stall: + avg: AVG((SQ_VMEM_TA_CMD_FIFO_FULL / $denom)) + min: MIN((SQ_VMEM_TA_CMD_FIFO_FULL / $denom)) + max: MAX((SQ_VMEM_TA_CMD_FIFO_FULL / $denom)) + unit: (Cycles + $normUnit) + tips: + Sequencer → TA Data Stall: + avg: AVG((SQ_VMEM_WR_TA_DATA_FIFO_FULL / $denom)) + min: MIN((SQ_VMEM_WR_TA_DATA_FIFO_FULL / $denom)) + max: MAX((SQ_VMEM_WR_TA_DATA_FIFO_FULL / $denom)) + unit: (Cycles + $normUnit) + tips: Total Instructions: avg: AVG((TA_TOTAL_WAVEFRONTS_sum / $denom)) min: MIN((TA_TOTAL_WAVEFRONTS_sum / $denom)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1700_L2_cache.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1700_L2_cache.yaml index a34f3445c3..c6e5479d36 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1700_L2_cache.yaml +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/1700_L2_cache.yaml @@ -32,12 +32,12 @@ Panel Config: tips: L2-Fabric Read BW: value: AVG((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum - * 128)) / (End_Timestamp - Start_Timestamp)) + * 128)) / (End_Timestamp - Start_Timestamp))) unit: GB/s tips: L2-Fabric Write and Atomic BW: value: AVG((((TCC_EA0_WRREQ_64B_sum * 64) + ((TCC_EA0_WRREQ_sum - TCC_EA0_WRREQ_64B_sum) - * 32)) / (End_Timestamp - Start_Timestamp)) + * 32)) / (End_Timestamp - Start_Timestamp))) unit: GB/s tips: @@ -52,6 +52,15 @@ Panel Config: unit: Unit tips: Tips metric: + Read BW: + avg: AVG((((TCC_EA0_RDREQ_32B_sum * 32) + ((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_32B_sum) + * 64)) / $denom)) + min: MIN((((TCC_EA0_RDREQ_32B_sum * 32) + ((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_32B_sum) + * 64)) / $denom)) + max: MAX((((TCC_EA0_RDREQ_32B_sum * 32) + ((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_32B_sum) + * 64)) / $denom)) + unit: (Bytes + $normUnit) + tips: Read BW: avg: AVG((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / $denom)) min: MIN((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / $denom)) @@ -457,13 +466,13 @@ Panel Config: max: MAX((TCC_EA0_RD_UNCACHED_32B_sum / $denom)) unit: (Req + $normUnit) tips: - Read - HBM: + HBM Read: avg: AVG((TCC_EA0_RDREQ_DRAM_sum / $denom)) min: MIN((TCC_EA0_RDREQ_DRAM_sum / $denom)) max: MAX((TCC_EA0_RDREQ_DRAM_sum / $denom)) unit: (Req + $normUnit) tips: - Read - Remote: + Remote Read: avg: AVG((MAX((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_DRAM_sum), 0) / $denom)) min: MIN((MAX((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_DRAM_sum), 0) / $denom)) max: MAX((MAX((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_DRAM_sum), 0) / $denom)) @@ -505,13 +514,13 @@ Panel Config: max: MAX((TCC_EA0_WRREQ_64B_sum / $denom)) unit: (Req + $normUnit) tips: - Write - HBM: + HBM Write and Atomic: avg: AVG((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom)) min: MIN((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom)) max: MAX((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom)) unit: (Req + $normUnit) tips: - Write and Atomic - Remote: + Remote Write and Atomic: avg: AVG((MAX((TCC_EA0_WRREQ_sum - TCC_EA0_WRREQ_DRAM_sum), 0) / $denom)) min: MIN((MAX((TCC_EA0_WRREQ_sum - TCC_EA0_WRREQ_DRAM_sum), 0) / $denom)) max: MAX((MAX((TCC_EA0_WRREQ_sum - TCC_EA0_WRREQ_DRAM_sum), 0) / $denom)) diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/2100_pc_sampling.yaml b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/2100_pc_sampling.yaml new file mode 100644 index 0000000000..9fb55fa91d --- /dev/null +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/2100_pc_sampling.yaml @@ -0,0 +1,9 @@ +--- +Panel Config: + id: 2100 + title: PC Sampling + data source: + - pc_sampling_table: + id: 2101 + source: ps_file + comparable: false # enable it later diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_base.py b/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_base.py index 7dd9fb4706..12fe7e03cd 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_base.py +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_base.py @@ -42,15 +42,16 @@ from utils.logger import ( console_warning, demarcate, ) -from utils.mi_gpu_spec import get_gpu_model, get_gpu_series +from utils.mi_gpu_spec import get_gpu_model, get_gpu_series, get_num_xcds from utils.parser import build_in_vars, supported_denom from utils.utils import ( capture_subprocess_output, convert_metric_id_to_panel_idx, detect_rocprof, + get_base_spi_pipe_counter, get_submodules, + is_spi_pipe_counter, is_tcc_channel_counter, - total_xcds, using_v3, ) @@ -186,7 +187,7 @@ class OmniSoC_Base: self._mspec.gpu_arch, self._mspec.gpu_chip_id ) self._mspec.num_xcd = str( - total_xcds(self._mspec.gpu_model, self._mspec.compute_partition) + get_num_xcds(self._mspec.gpu_model, self._mspec.compute_partition) ) @demarcate @@ -316,10 +317,10 @@ class OmniSoC_Base: counters = counters - {"SQ_INSTS_VALU_MFMA_F8", "SQ_INSTS_VALU_MFMA_MOPS_F8"} # Following counters are not supported - # TCP_TCP_LATENCY_sum (except for gfx908 and gfx90a) + # TCP_TCP_LATENCY_sum (except for gfx950) # SQC_DCACHE_INFLIGHT_LEVEL counters = counters - {"SQC_DCACHE_INFLIGHT_LEVEL"} - if self.__arch not in ("gfx908", "gfx90a"): + if self.__arch != "gfx950": counters = counters - {"TCP_TCP_LATENCY_sum"} # SQ_ACCUM_PREV_HIRES will be injected for level counters later on @@ -510,6 +511,8 @@ class OmniSoC_Base: file_count = 0 # Store all channels for a TCC channel counter in the same file tcc_channel_counter_file_map = dict() + # Store all pipes for SPI pipe counters in the same file + spi_pipe_counter_file_map = dict() for ctr in counters: # Store all channels for a TCC channel counter in the same file if is_tcc_channel_counter(ctr): @@ -517,13 +520,27 @@ class OmniSoC_Base: if output_file: output_file.add(ctr) continue + # Store all pipes for SPI pipe counters in the same file + if is_spi_pipe_counter(ctr): + output_file = spi_pipe_counter_file_map.get( + get_base_spi_pipe_counter(ctr) + ) + if output_file: + output_file.add(ctr) + continue # Add counter to first file that has room added = False for i in range(len(output_files)): if output_files[i].add(ctr): added = True + # Store all channels for a TCC channel counter in the same file if is_tcc_channel_counter(ctr): tcc_channel_counter_file_map[ctr.split("[")[0]] = output_files[i] + # Store all pipes for SPI pipe counters in the same file + if is_spi_pipe_counter(ctr): + spi_pipe_counter_file_map[get_base_spi_pipe_counter(ctr)] = ( + output_files[i] + ) break # All files are full, create a new file @@ -711,8 +728,18 @@ class LimitedSet: if e.split("[")[0] in {element.split("[")[0] for element in self.elements}: self.elements.append(e) return True + # Store all pipes for SPI pipe counters in the same file + if is_spi_pipe_counter(e) and get_base_spi_pipe_counter(e) in { + get_base_spi_pipe_counter(element) for element in self.elements + }: + self.elements.append(e) + return True if self.avail > 0: - self.avail -= 1 + # SPI pipe counters take space of 2 counters + if is_spi_pipe_counter(e): + self.avail -= 2 + else: + self.avail -= 1 self.elements.append(e) return True return False diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_gfx908.py b/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_gfx908.py index ed0d5caa77..4208efb25b 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_gfx908.py +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_gfx908.py @@ -54,10 +54,6 @@ class gfx908_soc(OmniSoC_Base): self._mspec._l2_banks = 32 self._mspec.lds_banks_per_cu = 32 self._mspec.pipes_per_gpu = 4 - # --showmclkrange is broken in Mi100, hardcode freq - if self._mspec.max_mclk is None or self._mspec.cur_mclk is None: - self._mspec.max_mclk = 1200 - self._mspec.cur_mclk = 1200 # ----------------------- # Required child methods diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_gfx90a.py b/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_gfx90a.py index 470e7bfa71..9d5f22ce0f 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_gfx90a.py +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_gfx90a.py @@ -64,12 +64,6 @@ class gfx90a_soc(OmniSoC_Base): ) self.roofline_obj = Roofline(args, self._mspec) - # Workaround for broken --showmclkrange - # MI210/MI250/MI250X have 1600MHz mclk - if self._mspec.max_mclk is None or self._mspec.cur_mclk is None: - self._mspec.max_mclk = 1600 - self._mspec.cur_mclk = 1600 - # Set arch specific specs self._mspec._l2_banks = 32 self._mspec.lds_banks_per_cu = 32 diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_gfx942.py b/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_gfx942.py index bd65216ed4..038b28aa24 100644 --- a/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_gfx942.py +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_gfx942.py @@ -64,12 +64,6 @@ class gfx942_soc(OmniSoC_Base): ) self.roofline_obj = Roofline(args, self._mspec) - # Workaround for broken --showmclkrange - # MI300X/MI300A/MI308X have 1300MHz mclk - if self._mspec.max_mclk is None or self._mspec.cur_mclk is None: - self._mspec.max_mclk = 1300 - self._mspec.cur_mclk = 1300 - # Set arch specific specs self._mspec._l2_banks = 16 self._mspec.lds_banks_per_cu = 32 diff --git a/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_gfx950.py b/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_gfx950.py new file mode 100644 index 0000000000..e3e3a1bdfb --- /dev/null +++ b/projects/rocprofiler-compute/src/rocprof_compute_soc/soc_gfx950.py @@ -0,0 +1,117 @@ +##############################################################################bl +# MIT License +# +# Copyright (c) 2021 - 2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +##############################################################################el + +from pathlib import Path + +import config +from rocprof_compute_soc.soc_base import OmniSoC_Base +from roofline import Roofline +from utils.logger import demarcate +from utils.utils import console_error, console_log, mibench + + +class gfx950_soc(OmniSoC_Base): + def __init__(self, args, mspec): + super().__init__(args, mspec) + self.set_arch("gfx950") + if hasattr(self.get_args(), "roof_only") and self.get_args().roof_only: + self.set_perfmon_dir( + str( + Path(str(config.rocprof_compute_home)).joinpath( + "rocprof_compute_soc", + "profile_configs", + "gfx950", + "roofline", + ) + ) + ) + else: + # NB: We're using generalized Mi300 perfmon configs + self.set_perfmon_dir( + str( + Path(str(config.rocprof_compute_home)).joinpath( + "rocprof_compute_soc", + "profile_configs", + "gfx950", + ) + ) + ) + self.set_compatible_profilers(["rocprofv3"]) + # Per IP block max number of simultaneous counters. GFX IP Blocks + self.set_perfmon_config( + { + "SQ": 8, + "TA": 2, + "TD": 2, + "TCP": 4, + "TCC": 4, + "CPC": 2, + "CPF": 2, + "SPI": 2, + "GRBM": 2, + "GDS": 4, + "TCC_channels": 16, + } + ) + self.roofline_obj = Roofline(args, self._mspec) + + # Set arch specific specs + self._mspec._l2_banks = 16 + self._mspec.lds_banks_per_cu = 32 + self._mspec.pipes_per_gpu = 4 + + # ----------------------- + # Required child methods + # ----------------------- + @demarcate + def profiling_setup(self): + """Perform any SoC-specific setup prior to profiling.""" + super().profiling_setup() + # Performance counter filtering + self.perfmon_filter(self.get_args().roof_only) + + @demarcate + def post_profiling(self): + """Perform any SoC-specific post profiling activities.""" + super().post_profiling() + + if not self.get_args().no_roof: + console_log( + "roofline", "Checking for roofline.csv in " + str(self.get_args().path) + ) + if not Path(self.get_args().path).joinpath("roofline.csv").is_file(): + mibench(self.get_args(), self._mspec) + self.roofline_obj.post_processing() + else: + console_log("roofline", "Skipping roofline") + + @demarcate + def analysis_setup(self, roofline_parameters=None): + """Perform any SoC-specific setup prior to analysis.""" + super().analysis_setup() + # configure roofline for analysis + if roofline_parameters: + self.roofline_obj = Roofline( + self.get_args(), self._mspec, roofline_parameters + ) diff --git a/projects/rocprofiler-compute/src/utils/gui.py b/projects/rocprofiler-compute/src/utils/gui.py index 8e3d532453..05f44617be 100644 --- a/projects/rocprofiler-compute/src/utils/gui.py +++ b/projects/rocprofiler-compute/src/utils/gui.py @@ -120,7 +120,7 @@ def discrete_background_color_bins(df, n_bins=5, columns="all"): #################### # GRAPHICAL ELEMENTS #################### -def build_bar_chart(display_df, table_config, barchart_elements, norm_filt, hbm_bw): +def build_bar_chart(display_df, table_config, barchart_elements, norm_filt): """ Read data into a bar chart. ID will determine which subtype of barchart. """ @@ -214,6 +214,9 @@ def build_bar_chart(display_df, table_config, barchart_elements, norm_filt, hbm_ orientation="h", ).update_xaxes(range=[0, 110], ticks="inside", title="%") ) # append first % chart + hbm_bw = float( + display_df[display_df["Metric"] == "HBM Bandwidth"]["Avg"].iloc[0] + ) d_figs.append( px.bar( display_df[display_df["Unit"] == "Gb/s"], diff --git a/projects/rocprofiler-compute/src/utils/mi_gpu_spec.py b/projects/rocprofiler-compute/src/utils/mi_gpu_spec.py index 957e5ae955..eaee6e7bb2 100644 --- a/projects/rocprofiler-compute/src/utils/mi_gpu_spec.py +++ b/projects/rocprofiler-compute/src/utils/mi_gpu_spec.py @@ -1,7 +1,5 @@ import os -import sys -from dataclasses import dataclass, field -from typing import Any, Dict, List, Optional, Union +from typing import Any, Dict import yaml @@ -13,14 +11,20 @@ MI50 = 0 MI100 = 1 MI200 = 2 MI300 = 3 +MI350 = 4 -MI_CONSTANS = {MI50: "mi50", MI100: "mi100", MI200: "mi200", MI300: "mi300"} +MI_CONSTANS = { + MI50: "mi50", + MI100: "mi100", + MI200: "mi200", + MI300: "mi300", + MI350: "mi350", +} gpu_series_dict = {} # key: gpu arch gpu_model_dict = {} # key: gpu_arch -mi300_num_xcds_dict = {} # key: gpu model -mi300_nps_dict = {} # key: gpu model -mi300_chip_id_dict = {} # key: chip id (int) +num_xcds_dict = {} # key: gpu model +chip_id_dict = {} # key: chip id (int) # ---------------------------- @@ -60,10 +64,9 @@ def parse_mi_gpu_spec(): MI GPUs |-- series |-- architecture (list) - |-- models - |-- chip_ids - |-- mi300_arch - |-- partition_mode + |-- gpu model + |-- chip_ids + |-- partition_mode """ current_dir = os.path.dirname(__file__) @@ -71,61 +74,26 @@ def parse_mi_gpu_spec(): # Load the YAML data yaml_data = load_yaml(yaml_file_path) - mi300_models_dict = {} - for mi_index, mi_series in MI_CONSTANS.items(): - if mi_series != MI_CONSTANS[MI300]: - console_debug("[parse_mi_gpu_spec] Processing series: %s" % mi_series) - for key, value in yaml_data.items(): - # parse out gpu series and gpu model information for mi50, 100, 200 - curr_gpu_arch = value[mi_index]["gpu_archs"][0]["gpu_arch"] - gpu_series_dict[curr_gpu_arch] = mi_series - gpu_model_dict[curr_gpu_arch] = [] - for models in value[mi_index]["gpu_archs"][0]["models"]: - gpu_model_dict[curr_gpu_arch].append(models["gpu_model"]) - elif mi_series == MI_CONSTANS[MI300]: - # MI300 requires specific processing - for key, value in yaml_data.items(): - mi300_gpu_archs_list = [] - # NOTE: only MI300 have multiple architectures - for archs in value[MI300]["gpu_archs"]: - curr_gpu_arch = archs["gpu_arch"] - mi300_gpu_archs_list.append(curr_gpu_arch) - gpu_series_dict[curr_gpu_arch] = mi_series - - for idx, arch in enumerate(mi300_gpu_archs_list): - mi300_models_dict[arch] = [] - for models in value[MI300]["gpu_archs"][idx]["models"]: - gpu_model = models["gpu_model"] - - # 1. Parse compute partition. NOTE: compute partition mode num xcds is available for all mi300 gpu models - mi300_num_xcds_dict[gpu_model] = models["partition_mode"][ - "compute_partition_mode" - ]["num_xcds"] - - # 2. Parse memory_partition. NOTE: memory partition mode nps is available for all mi300 gpu models - mi300_nps_dict[gpu_model] = models["partition_mode"][ - "memory_partition_mode" - ] - - # 3. Parse chip id (physical and virtual). - if models["chip_ids"]["physical"]: - # save chip_id, gpu_model pair if chip id is available - # NOTE: chip id is available for all gfx942 machines - mi300_chip_id_dict[models["chip_ids"]["physical"]] = models[ - "gpu_model" - ] - - if models["chip_ids"]["virtual"]: - # save chip_id, gpu_model pair if chip id is available - # NOTE: chip id is available for all gfx942 machines - mi300_chip_id_dict[models["chip_ids"]["virtual"]] = models[ - "gpu_model" - ] - - mi300_models_dict[arch].append(gpu_model) - - gpu_model_dict.update(mi300_models_dict) + for series in yaml_data["mi_gpu_spec"]: + curr_gpu_series = series["gpu_series"] + console_debug("[parse_mi_gpu_spec] Processing series: %s" % curr_gpu_series) + for archs in series["gpu_archs"]: + curr_gpu_arch = archs["gpu_arch"] + gpu_series_dict[curr_gpu_arch] = curr_gpu_series + gpu_model_dict[curr_gpu_arch] = [] + for models in archs["models"]: + curr_gpu_model = models["gpu_model"] + gpu_model_dict[curr_gpu_arch].append(curr_gpu_model) + num_xcds_dict[curr_gpu_model] = ( + models.get("partition_mode", {}) + .get("compute_partition_mode", {}) + .get("num_xcds", {}) + ) + if "chip_ids" in models and "physical" in models["chip_ids"]: + chip_id_dict[models["chip_ids"]["physical"]] = curr_gpu_model + if "chip_ids" in models and "virtual" in models["chip_ids"]: + chip_id_dict[models["chip_ids"]["virtual"]] = curr_gpu_model def get_gpu_series_dict(): @@ -164,9 +132,9 @@ def get_gpu_model(gpu_arch_, chip_id_): gpu_arch_lower = gpu_arch_.lower() # Handle gfx942 with chip_id mapping - if gpu_arch_lower == "gfx942": - if chip_id_ and int(chip_id_) in mi300_chip_id_dict: - gpu_model = mi300_chip_id_dict.get(int(chip_id_)) + if gpu_arch_lower not in ("gfx906", "gfx908", "gfx90a"): + if chip_id_ and int(chip_id_) in chip_id_dict: + gpu_model = chip_id_dict.get(int(chip_id_)) else: console_warning(f"No gpu model found for chip id: {chip_id_}") return None @@ -186,8 +154,12 @@ def get_gpu_model(gpu_arch_, chip_id_): return gpu_model.upper() -def get_mi300_num_xcds(gpu_model_, compute_partition_): - if not mi300_num_xcds_dict: +def get_num_xcds(gpu_model_, compute_partition_): + # Only gpu in and above mi 300 series have more than one XCDs + if gpu_model_.lower() in ("mi50", "mi60", "mi100", "mi210", "mi250", "mi250x"): + return 1 + + if not num_xcds_dict: console_error( "mi300_num_xcds_dict not yet populated, did you run parse_mi_gpu_spec()?" ) @@ -196,10 +168,10 @@ def get_mi300_num_xcds(gpu_model_, compute_partition_): gpu_model_lower = gpu_model_.lower() partition_lower = compute_partition_.lower() - if gpu_model_lower not in mi300_num_xcds_dict: + if gpu_model_lower not in num_xcds_dict: return None - model_dict = mi300_num_xcds_dict[gpu_model_lower] + model_dict = num_xcds_dict[gpu_model_lower] if partition_lower not in model_dict: console_log(f"Unknown compute partition: {compute_partition_}") return None @@ -214,9 +186,9 @@ def get_mi300_num_xcds(gpu_model_, compute_partition_): return num_xcds -def get_mi300_chip_id_dict(): - if mi300_chip_id_dict: - return mi300_chip_id_dict +def get_chip_id_dict(): + if chip_id_dict: + return chip_id_dict else: console_error( "mi300_chip_id_dict not yet populated, did you run parse_mi_gpu_spec()?" diff --git a/projects/rocprofiler-compute/src/utils/mi_gpu_spec.yaml b/projects/rocprofiler-compute/src/utils/mi_gpu_spec.yaml index a86779a62e..fb4b79fa6d 100644 --- a/projects/rocprofiler-compute/src/utils/mi_gpu_spec.yaml +++ b/projects/rocprofiler-compute/src/utils/mi_gpu_spec.yaml @@ -9,11 +9,11 @@ # MI GPUs # |-- series: the specific MI series; mi50, mi100, mi200, mi300 # |-- architecture: currently, only mi300 gpus hold different architectures -# |-- models -# |-- chip_ids: chip id is specific to the environment the gpu is being used on -# |-- partition_mode: currently, only mi300 gpus hold partition mode information -# two types: compute partition mode, memory partition mode, -# currently only mi300 gpus contains compute partition mode information on number of xcds +# |-- gpu model +# |-- chip_ids: chip id is specific to the environment the gpu is being used on +# |-- partition_mode +# | -- compute partition mode +# | -- memory partition mode # # -------------------------------------------------------------------------------- @@ -23,45 +23,31 @@ mi_gpu_spec: - gpu_arch: gfx906 models: - gpu_model: mi50 - partition_mode: null - chip_ids: - physical: null - virtual: null - gpu_model: mi60 - partition_mode: null - chip_ids: - physical: null - virtual: null - gpu_series: mi100 gpu_archs: - gpu_arch: gfx908 models: - gpu_model: mi100 - partition_mode: null chip_ids: physical: 29580 - virtual: null - gpu_series: mi200 gpu_archs: - gpu_arch: gfx90a models: - gpu_model: mi210 - partition_mode: null chip_ids: physical: 29711 - virtual: null - gpu_model: mi250 - partition_mode: null chip_ids: physical: 29708 - virtual: null - gpu_model: mi250x - partition_mode: null chip_ids: physical: 29704 - virtual: null + - gpu_model: mi250 + - gpu_model: mi250x - gpu_series: mi300 gpu_archs: @@ -72,16 +58,10 @@ mi_gpu_spec: compute_partition_mode: num_xcds: spx: 6 - dpx: null tpx: 2 - qpx: null - cpx: null memory_partition_mode: nps4: [tpx] nps1: [spx, tpx] - chip_ids: - physical: null - virtual: null - gpu_arch: gfx941 models: @@ -91,15 +71,11 @@ mi_gpu_spec: num_xcds: spx: 8 dpx: 4 - tpx: null qpx: 2 cpx: 1 memory_partition_mode: nps4: [qpx, cpx] nps1: [spx, qpx, cpx] - chip_ids: - physical: null - virtual: null - gpu_arch: gfx942 models: @@ -108,10 +84,7 @@ mi_gpu_spec: compute_partition_mode: num_xcds: spx: 6 - dpx: null tpx: 2 - qpx: null - cpx: null memory_partition_mode: nps4: [tpx] nps1: [spx, tpx] @@ -125,7 +98,6 @@ mi_gpu_spec: num_xcds: spx: 8 dpx: 4 - tpx: null qpx: 2 cpx: 1 memory_partition_mode: @@ -141,8 +113,6 @@ mi_gpu_spec: num_xcds: spx: 4 dpx: 2 - tpx: null - qpx: null cpx: 1 memory_partition_mode: nps4: [cpx] @@ -150,3 +120,21 @@ mi_gpu_spec: chip_ids: physical: 29858 virtual: 29878 + + - gpu_series: mi350 + gpu_archs: + - gpu_arch: gfx950 + models: + - gpu_model: mi350 + partition_mode: + compute_partition_mode: + num_xcds: + spx: 8 + dpx: 4 + qpx: 2 + cpx: 1 + memory_partition_mode: + nps1: [spx, dpx, qpx, cpx] + nps4: [qpx, cpx] + chip_ids: + physical: 30112 diff --git a/projects/rocprofiler-compute/src/utils/parser.py b/projects/rocprofiler-compute/src/utils/parser.py index 7b27cfae98..01fef7c699 100644 --- a/projects/rocprofiler-compute/src/utils/parser.py +++ b/projects/rocprofiler-compute/src/utils/parser.py @@ -86,6 +86,7 @@ build_in_vars = { 0) / $max_waves_per_cu) * 8) + MIN(MOD(ROUND(AVG(((4 * SQ_BUSY_CU_CYCLES) \ / $GRBM_GUI_ACTIVE_PER_XCD)), 0), $max_waves_per_cu), 8)), $cu_per_gpu))", "kernelBusyCycles": "ROUND(AVG((((End_Timestamp - Start_Timestamp) / 1000) * $max_sclk)), 0)", + "hbmBandwidth": "($max_mclk / 1000 * 32 * $num_hbm_channels)", } supported_call = { @@ -700,19 +701,80 @@ def eval_metric(dfs, dfs_type, sys_info, raw_pmc_df, debug): console_error("Hauting execution for warning above.") ammolite__se_per_gpu = int(sys_info.se_per_gpu) + if np.isnan(ammolite__se_per_gpu) or ammolite__se_per_gpu == 0: + console_warning( + "se_per_gpu is not available in sysinfo.csv, please provide the correct value using --specs-correction" + ) ammolite__pipes_per_gpu = int(sys_info.pipes_per_gpu) + if np.isnan(ammolite__pipes_per_gpu) or ammolite__pipes_per_gpu == 0: + console_warning( + "pipes_per_gpu is not available in sysinfo.csv, please provide the correct value using --specs-correction" + ) ammolite__cu_per_gpu = int(sys_info.cu_per_gpu) + if np.isnan(ammolite__cu_per_gpu) or ammolite__cu_per_gpu == 0: + console_warning( + "cu_per_gpu is not available in sysinfo.csv, please provide the correct value using --specs-correction" + ) ammolite__simd_per_cu = int(sys_info.simd_per_cu) # not used + if np.isnan(ammolite__simd_per_cu) or ammolite__simd_per_cu == 0: + console_warning( + "simd_per_cu is not available in sysinfo.csv, please provide the correct value using --specs-correction" + ) ammolite__sqc_per_gpu = int(sys_info.sqc_per_gpu) + if np.isnan(ammolite__sqc_per_gpu) or ammolite__sqc_per_gpu == 0: + console_warning( + "sqc_per_gpu is not available in sysinfo.csv, please provide the correct value using --specs-correction" + ) ammolite__lds_banks_per_cu = int(sys_info.lds_banks_per_cu) + if np.isnan(ammolite__lds_banks_per_cu) or ammolite__lds_banks_per_cu == 0: + console_warning( + "lds_banks_per_cu is not available in sysinfo.csv, please provide the correct value using --specs-correction" + ) ammolite__cur_sclk = float(sys_info.cur_sclk) # not used - ammolite__mclk = float(sys_info.cur_mclk) # not used + if np.isnan(ammolite__cur_sclk) or ammolite__cur_sclk == 0: + console_warning( + "cur_sclk is not available in sysinfo.csv, please provide the correct value using --specs-correction" + ) + ammolite__cur_mclk = float(sys_info.cur_mclk) # not used + if np.isnan(ammolite__cur_mclk) or ammolite__cur_mclk == 0: + console_warning( + "cur_mclk is not available in sysinfo.csv, please provide the correct value using --specs-correction" + ) + ammolite__max_mclk = float(sys_info.max_mclk) + if np.isnan(ammolite__max_mclk) or ammolite__max_mclk == 0: + console_warning( + "max_mclk is not available in sysinfo.csv, please provide the correct value using --specs-correction" + ) ammolite__max_sclk = float(sys_info.max_sclk) + if np.isnan(ammolite__max_sclk) or ammolite__max_sclk == 0: + console_warning( + "max_sclk is not available in sysinfo.csv, please provide the correct value using --specs-correction" + ) ammolite__max_waves_per_cu = int(sys_info.max_waves_per_cu) - ammolite__hbm_bw = float(sys_info.hbm_bw) + if np.isnan(ammolite__max_waves_per_cu) or ammolite__max_waves_per_cu == 0: + console_warning( + "max_waver_per_cu is not available in sysinfo.csv, please provide the correct value using --specs-correction" + ) + ammolite__num_hbm_channels = float(sys_info.num_hbm_channels) + if np.isnan(ammolite__num_hbm_channels) or ammolite__num_hbm_channels == 0: + console_warning( + "num_hbm_channels is not available in sysinfo.csv, please provide the correct value using --specs-correction" + ) ammolite__total_l2_chan = calc_builtin_var("$total_l2_chan", sys_info) + if np.isnan(ammolite__total_l2_chan) or ammolite__total_l2_chan == 0: + console_warning( + "total_l2_chan is not available in sysinfo.csv, please provide the correct value using --specs-correction" + ) ammolite__num_xcd = int(sys_info.num_xcd) + if np.isnan(ammolite__num_xcd) or ammolite__num_xcd == 0: + console_warning( + "num_xcd is not available in sysinfo.csv, please provide the correct value using --specs-correction" + ) ammolite__wave_size = int(sys_info.wave_size) + if np.isnan(ammolite__wave_size) or ammolite__wave_size == 0: + console_warning( + "wave_size is not available in sysinfo.csv, please provide the correct value using --specs-correction" + ) # TODO: fix all $normUnit in Unit column or title @@ -751,6 +813,7 @@ def eval_metric(dfs, dfs_type, sys_info, raw_pmc_df, debug): ammolite__build_in[key] = None ammolite__numActiveCUs = ammolite__build_in["numActiveCUs"] ammolite__kernelBusyCycles = ammolite__build_in["kernelBusyCycles"] + ammolite__hbmBandwidth = ammolite__build_in["hbmBandwidth"] # Hmmm... apply + lambda should just work # df['Value'] = df['Value'].apply(lambda s: eval(compile(str(s), '', 'eval'))) @@ -821,7 +884,6 @@ def eval_metric(dfs, dfs_type, sys_info, raw_pmc_df, debug): else: console_error("analysis", str(ae)) - # print("eval_metric", id, expr) try: out = eval(compile(row[expr], "", "eval")) diff --git a/projects/rocprofiler-compute/src/utils/specs.py b/projects/rocprofiler-compute/src/utils/specs.py index c0bf2a326a..2b9cb2b1dd 100644 --- a/projects/rocprofiler-compute/src/utils/specs.py +++ b/projects/rocprofiler-compute/src/utils/specs.py @@ -39,9 +39,9 @@ import pandas as pd import config from utils.logger import console_debug, console_error, console_log, console_warning -from utils.mi_gpu_spec import get_gpu_series_dict, get_mi300_chip_id_dict +from utils.mi_gpu_spec import get_chip_id_dict, get_gpu_series_dict, get_num_xcds from utils.tty import get_table_string -from utils.utils import get_version, total_xcds +from utils.utils import get_version VERSION_LOC = [ "version", @@ -72,7 +72,6 @@ def detect_arch(_rocminfo): def detect_gpu_chip_id(_rocminfo): gpu_chip_id = None - mi300_chip_id_dict = get_mi300_chip_id_dict().keys() for idx1, linetext in enumerate(_rocminfo): # NOTE: current supported socs only have numbers in Chip ID @@ -84,8 +83,8 @@ def detect_gpu_chip_id(_rocminfo): if not gpu_chip_id: console_warning("No Chip ID detected: " + str(gpu_chip_id)) elif ( - gpu_chip_id not in mi300_chip_id_dict - and int(gpu_chip_id) not in mi300_chip_id_dict + gpu_chip_id not in get_chip_id_dict().keys() + and int(gpu_chip_id) not in get_chip_id_dict().keys() ): console_warning("Unknown Chip ID detected: " + str(gpu_chip_id)) return gpu_chip_id @@ -214,7 +213,7 @@ def generate_machine_specs(args, sysinfo: dict = None): specs.total_l2_chan: str = total_l2_banks( specs.gpu_model, int(specs._l2_banks), specs.compute_partition ) - specs.hbm_bw: str = str(int(specs.max_mclk) / 1000 * 32 * specs.get_hbm_channels()) + specs.num_hbm_channels: str = str(specs.get_hbm_channels()) return specs @@ -518,15 +517,6 @@ class MachineSpecs: "name": "Pipes per GPU", }, ) - hbm_bw: str = field( - default=None, - metadata={ - "doc": "The peak theoretical HBM bandwidth for the accelerators/GPUs in the system. On systems with\n" - "configurable partitioning, (e.g., MI300) this is the peak theoretical HBM bandwidth for a partition.", - "name": "HBM BW", - "unit": "GB/s", - }, - ) num_xcd: str = field( default=None, metadata={ @@ -536,14 +526,13 @@ class MachineSpecs: "unit": "XCDs", }, ) + num_hbm_channels: str = field( + default=None, + metadata={"doc": "Number of HBM channels", "name": "HBM channels"}, + ) def get_hbm_channels(self): - # check MI300 has a valid compute partition - mi300a_archs = ["mi300a_a0", "mi300a_a1"] - mi300x_archs = ["mi300x_a0", "mi300x_a1"] - mi308x_archs = ["mi308x"] - - if self.gpu_model.lower() in mi300a_archs + mi300x_archs + mi308x_archs: + if self.memory_partition.lower().startswith("nps"): hbmchannels = 128 if self.memory_partition.lower() == "nps2": hbmchannels /= 2 @@ -551,10 +540,9 @@ class MachineSpecs: hbmchannels /= 4 elif self.memory_partition.lower() == "nps8": hbmchannels /= 8 - return int(hbmchannels) + return hbmchannels else: - hbmchannels = int(self.total_l2_chan) - return hbmchannels + return int(self.total_l2_chan) def get_class_members(self): all_populated = True @@ -581,7 +569,7 @@ class MachineSpecs: data[name] = value if not all_populated: - console_error("Missing specs fields for %s" % self.gpu_arch) + console_warning("Missing specs fields for %s" % self.gpu_arch) return pd.DataFrame(data, index=[0]) def __repr__(self): @@ -682,7 +670,7 @@ def total_sqc(archname, numCUs, numSEs): def total_l2_banks(archname, L2Banks, compute_partition): - xcds = total_xcds(archname, compute_partition) + xcds = get_num_xcds(archname, compute_partition) totalL2Banks = L2Banks * xcds return totalL2Banks diff --git a/projects/rocprofiler-compute/src/utils/utils.py b/projects/rocprofiler-compute/src/utils/utils.py index f37f8da74a..0d87cce95e 100644 --- a/projects/rocprofiler-compute/src/utils/utils.py +++ b/projects/rocprofiler-compute/src/utils/utils.py @@ -43,16 +43,32 @@ import pandas as pd import config from utils.logger import console_debug, console_error, console_log, console_warning -from utils.mi_gpu_spec import get_mi300_num_xcds +from utils.mi_gpu_spec import get_num_xcds rocprof_cmd = "" rocprof_args = "" +spi_pipe_counter_regexs = [r"SPI_CS\d+_(.*)", r"SPI_CSQ_P\d+_(.*)"] def is_tcc_channel_counter(counter): return counter.startswith("TCC") and counter.endswith("]") +def is_spi_pipe_counter(counter): + for pattern in spi_pipe_counter_regexs: + if re.match(pattern, counter): + return True + return False + + +def get_base_spi_pipe_counter(counter): + for pattern in spi_pipe_counter_regexs: + match = re.match(pattern, counter) + if match: + return match.group(1) + return "" + + def using_v1(): return "ROCPROF" not in os.environ.keys() or ( @@ -571,12 +587,7 @@ def run_prof( # set required env var for mi300 new_env = None - if ( - mspec.gpu_model.lower() == "mi300x_a0" - or mspec.gpu_model.lower() == "mi300x_a1" - or mspec.gpu_model.lower() == "mi300a_a0" - or mspec.gpu_model.lower() == "mi300a_a1" - ): + if mspec.gpu_model.lower() not in ("mi50", "mi60", "mi210", "mi250", "mi250x"): new_env = os.environ.copy() new_env["ROCPROFILER_INDIVIDUAL_XCC_MODE"] = "1" @@ -661,7 +672,7 @@ def run_prof( if new_env and not using_v3() and not using_v1(): # flatten tcc for applicable mi300 input f = path(workload_dir + "/out/pmc_1/results_" + fbase + ".csv") - xcds = total_xcds(mspec.gpu_model, mspec.compute_partition) + xcds = get_num_xcds(mspec.gpu_model, mspec.compute_partition) df = flatten_tcc_info_across_xcds(f, xcds, int(mspec._l2_banks)) df.to_csv(f, index=False) @@ -1065,62 +1076,6 @@ def flatten_tcc_info_across_xcds(file, xcds, tcc_channel_per_xcd): return df -def total_xcds(gpu_model, compute_partition): - """ - Returns the number of xcds for a gpu model and compute_partition pair. - """ - - # For mi300 chips, return result from mi_gpu_spec - result = get_mi300_num_xcds(gpu_model, compute_partition) - if result: - return result - - # For other systems, use manual check - # check MI300 has a valid compute partition - mi300a_model = ["mi300a_a0", "mi300a_a1"] - mi300x_model = ["mi300x_a0", "mi300x_a1"] - mi308x_model = ["mi308x"] - if ( - gpu_model.lower() in mi300a_model + mi300x_model + mi308x_model - and compute_partition == "NA" - ): - console_error("Invalid compute partition found for {}".format(gpu_model)) - - if gpu_model.lower() not in mi300a_model + mi300x_model + mi308x_model: - return 1 - # from the whitepaper - # https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/white-papers/amd-cdna-3-white-paper.pdf - if compute_partition.lower() == "spx": - if gpu_model.lower() in mi300a_model: - return 6 - if gpu_model.lower() in mi300x_model: - return 8 - if gpu_model.lower() in mi308x_model: - return 4 - if compute_partition.lower() == "tpx": - if gpu_model.lower() in mi300a_model: - return 2 - if compute_partition.lower() == "dpx": - if gpu_model.lower() in mi300x_model: - return 4 - if gpu_model.lower() in mi308x_model: - return 2 - if compute_partition.lower() == "qpx": - if gpu_model.lower() in mi300x_model: - return 2 - if compute_partition.lower() == "cpx": - if gpu_model.lower() in mi300x_model: - return 1 - if gpu_model.lower() in mi308x_model: - return 1 - # TODO implement other archs here as needed - console_error( - "Unknown compute partition / arch found for {} / {}".format( - compute_partition, gpu_model - ) - ) - - def get_submodules(package_name): """List all submodules for a target package""" import importlib diff --git a/projects/rocprofiler-compute/tests/test_TCP_counters.py b/projects/rocprofiler-compute/tests/test_TCP_counters.py index 826a383c11..c304a9b48f 100644 --- a/projects/rocprofiler-compute/tests/test_TCP_counters.py +++ b/projects/rocprofiler-compute/tests/test_TCP_counters.py @@ -136,7 +136,7 @@ def test_L1_cache_counters( options, check_success=False, roof=False, - app_name=app_name + app_name=app_name, ) assert return_code == 0 diff --git a/projects/rocprofiler-compute/tests/test_analyze_commands.py b/projects/rocprofiler-compute/tests/test_analyze_commands.py index df1e9603de..c7835a0d6f 100644 --- a/projects/rocprofiler-compute/tests/test_analyze_commands.py +++ b/projects/rocprofiler-compute/tests/test_analyze_commands.py @@ -15,6 +15,7 @@ indirs = [ "tests/workloads/vcopy/MI200", "tests/workloads/vcopy/MI300A_A1", "tests/workloads/vcopy/MI300X_A1", + "tests/workloads/vcopy/MI350", ] @@ -255,9 +256,13 @@ def test_dispatch_5(binary_handler_analyze_rocprof_compute): @pytest.mark.misc def test_gpu_ids(binary_handler_analyze_rocprof_compute): for dir in indirs: + if dir.endswith("MI350"): + gpu_id = "0" + else: + gpu_id = "2" workload_dir = test_utils.setup_workload_dir(dir) code = binary_handler_analyze_rocprof_compute( - ["analyze", "--path", workload_dir, "--gpu-id", "2"] + ["analyze", "--path", workload_dir, "--gpu-id", gpu_id] ) assert code == 0 diff --git a/projects/rocprofiler-compute/tests/test_analyze_workloads.py b/projects/rocprofiler-compute/tests/test_analyze_workloads.py index 94d96f8e85..0610b32e6e 100644 --- a/projects/rocprofiler-compute/tests/test_analyze_workloads.py +++ b/projects/rocprofiler-compute/tests/test_analyze_workloads.py @@ -112,6 +112,13 @@ def test_analyze_ipblocks_TCC_MI200(binary_handler_analyze_rocprof_compute): assert code == 0 +def test_analyze_no_roof_MI350(binary_handler_analyze_rocprof_compute): + code = binary_handler_analyze_rocprof_compute( + ["analyze", "--path", "tests/workloads/no_roof/MI350"] + ) + assert code == 0 + + def test_analyze_no_roof_MI300X_A1(binary_handler_analyze_rocprof_compute): code = binary_handler_analyze_rocprof_compute( ["analyze", "--path", "tests/workloads/no_roof/MI300X_A1"] diff --git a/projects/rocprofiler-compute/tests/test_profile_general.py b/projects/rocprofiler-compute/tests/test_profile_general.py index 212d58be21..55c5e3c5bc 100644 --- a/projects/rocprofiler-compute/tests/test_profile_general.py +++ b/projects/rocprofiler-compute/tests/test_profile_general.py @@ -14,6 +14,7 @@ import test_utils # Globals +# TODO: MI350 What are the gpu models in MI 350 series SUPPORTED_ARCHS = { "gfx906": {"mi50": ["MI50", "MI60"]}, "gfx908": {"mi100": ["MI100"]}, @@ -21,12 +22,14 @@ SUPPORTED_ARCHS = { "gfx940": {"mi300": ["MI300A_A0"]}, "gfx941": {"mi300": ["MI300X_A0"]}, "gfx942": {"mi300": ["MI300A_A1", "MI300X_A1"]}, + "gfx950": {"mi350": ["MI350"]}, } -MI300_CHIP_IDS = { +CHIP_IDS = { "29856": "MI300A_A1", "29857": "MI300X_A1", "29858": "MI308X", + "30112": "MI350", } @@ -106,6 +109,25 @@ ALL_CSVS_MI300 = sorted( "timestamps.csv", ] ) +ALL_CSVS_MI350 = sorted( + [ + "SQ_IFETCH_LEVEL.csv", + "SQ_INST_LEVEL_LDS.csv", + "SQ_INST_LEVEL_SMEM.csv", + "SQ_INST_LEVEL_VMEM.csv", + "SQ_LEVEL_WAVES.csv", + "pmc_perf.csv", + "pmc_perf_0.csv", + "pmc_perf_1.csv", + "pmc_perf_2.csv", + "pmc_perf_3.csv", + "pmc_perf_4.csv", + "pmc_perf_5.csv", + "pmc_perf_6.csv", + "pmc_perf_7.csv", + "sysinfo.csv", + ] +) ROOF_ONLY_FILES = sorted( [ @@ -290,9 +312,9 @@ def gpu_soc(): ## 3) Deduce gpu model name from arch gpu_model = list(SUPPORTED_ARCHS[gpu_arch].keys())[0].upper() - if gpu_model == "MI300": - if chip_id in MI300_CHIP_IDS: - gpu_model = MI300_CHIP_IDS[chip_id] + if gpu_model not in ("MI50", "MI100", "MI200"): + if chip_id in CHIP_IDS: + gpu_model = CHIP_IDS[chip_id] return gpu_model @@ -303,6 +325,9 @@ soc = gpu_soc() if "MI300" in soc: os.environ["ROCPROF"] = "rocprofv2" +if "MI350" in soc: + os.environ["ROCPROF"] = "rocprofv3" + Baseline_dir = str(Path("tests/workloads/vcopy/" + soc).resolve()) @@ -491,6 +516,8 @@ def test_path(binary_handler_profile_rocprof_compute): assert sorted(list(file_dict.keys())) == sorted(ALL_CSVS_MI200) elif "MI300" in soc: assert sorted(list(file_dict.keys())) == sorted(ALL_CSVS_MI300) + elif "MI350" in soc: + assert sorted(list(file_dict.keys())) == sorted(ALL_CSVS_MI350) else: print("This test is not supported for {}".format(soc)) assert 0 @@ -502,7 +529,7 @@ def test_path(binary_handler_profile_rocprof_compute): @pytest.mark.misc def test_roof_kernel_names(binary_handler_profile_rocprof_compute): - if soc == "MI100": + if soc in ("MI100", "MI350"): # roofline is not supported on MI100 assert True # Do not continue testing @@ -517,7 +544,7 @@ def test_roof_kernel_names(binary_handler_profile_rocprof_compute): # assert successful run assert returncode == 0 file_dict = test_utils.check_csv_files(workload_dir, 1, num_kernels) - if soc == "MI200" or "MI300" in soc: + if soc == "MI200" in soc or "MI300" in soc: assert sorted(list(file_dict.keys())) == sorted( ROOF_ONLY_FILES + ["kernelName_legend.pdf"] ) @@ -546,6 +573,8 @@ def test_device_filter(binary_handler_profile_rocprof_compute): assert sorted(list(file_dict.keys())) == sorted(ALL_CSVS_MI200) elif "MI300" in soc: assert sorted(list(file_dict.keys())) == sorted(ALL_CSVS_MI300) + elif "MI350" in soc: + assert sorted(list(file_dict.keys())) == sorted(ALL_CSVS_MI350) else: print("Testing isn't supported yet for {}".format(soc)) assert 0 @@ -574,6 +603,8 @@ def test_kernel(binary_handler_profile_rocprof_compute): assert sorted(list(file_dict.keys())) == sorted(ALL_CSVS_MI200) elif "MI300" in soc: assert sorted(list(file_dict.keys())) == sorted(ALL_CSVS_MI300) + elif "MI350" in soc: + assert sorted(list(file_dict.keys())) == sorted(ALL_CSVS_MI350) else: print("Testing isn't supported yet for {}".format(soc)) assert 0 @@ -625,6 +656,24 @@ def test_block_SQ(binary_handler_profile_rocprof_compute): "sysinfo.csv", "timestamps.csv", ] + if soc == "MI350": + expected_csvs = [ + "SQ_IFETCH_LEVEL.csv", + "SQ_INST_LEVEL_LDS.csv", + "SQ_INST_LEVEL_SMEM.csv", + "SQ_INST_LEVEL_VMEM.csv", + "SQ_LEVEL_WAVES.csv", + "pmc_perf.csv", + "pmc_perf_0.csv", + "pmc_perf_1.csv", + "pmc_perf_2.csv", + "pmc_perf_3.csv", + "pmc_perf_4.csv", + "pmc_perf_5.csv", + "pmc_perf_6.csv", + "pmc_perf_7.csv", + "sysinfo.csv", + ] assert sorted(list(file_dict.keys())) == sorted(expected_csvs) @@ -652,6 +701,8 @@ def test_block_SQC(binary_handler_profile_rocprof_compute): "sysinfo.csv", "timestamps.csv", ] + if soc == "MI350": + expected_csvs.remove("timestamps.csv") assert sorted(list(file_dict.keys())) == sorted(expected_csvs) @@ -684,6 +735,8 @@ def test_block_TA(binary_handler_profile_rocprof_compute): "sysinfo.csv", "timestamps.csv", ] + if soc == "MI350": + expected_csvs.remove("timestamps.csv") assert sorted(list(file_dict.keys())) == sorted(expected_csvs) @@ -721,6 +774,15 @@ def test_block_TD(binary_handler_profile_rocprof_compute): "sysinfo.csv", "timestamps.csv", ] + if soc == "MI350": + expected_csvs = [ + "pmc_perf.csv", + "pmc_perf_0.csv", + "pmc_perf_1.csv", + "pmc_perf_2.csv", + "pmc_perf_3.csv", + "sysinfo.csv", + ] assert sorted(list(file_dict.keys())) == sorted(expected_csvs) @@ -771,6 +833,8 @@ def test_block_TCP(binary_handler_profile_rocprof_compute): "sysinfo.csv", "timestamps.csv", ] + if soc == "MI350": + expected_csvs.remove("timestamps.csv") assert sorted(list(file_dict.keys())) == sorted(expected_csvs) @@ -825,6 +889,8 @@ def test_block_TCC(binary_handler_profile_rocprof_compute): "sysinfo.csv", "timestamps.csv", ] + if soc == "MI350": + expected_csvs.remove("timestamps.csv") assert sorted(list(file_dict.keys())) == sorted(expected_csvs) @@ -857,6 +923,23 @@ def test_block_SPI(binary_handler_profile_rocprof_compute): "sysinfo.csv", "timestamps.csv", ] + if soc == "MI350": + expected_csvs = [ + "pmc_perf.csv", + "pmc_perf_0.csv", + "pmc_perf_1.csv", + "pmc_perf_2.csv", + "pmc_perf_3.csv", + "pmc_perf_4.csv", + "pmc_perf_5.csv", + "pmc_perf_6.csv", + "pmc_perf_7.csv", + "pmc_perf_8.csv", + "pmc_perf_9.csv", + "pmc_perf_10.csv", + "pmc_perf_11.csv", + "sysinfo.csv", + ] assert sorted(list(file_dict.keys())) == sorted(expected_csvs) @@ -886,6 +969,19 @@ def test_block_CPC(binary_handler_profile_rocprof_compute): "sysinfo.csv", "timestamps.csv", ] + if soc == "MI350": + expected_csvs = [ + "pmc_perf.csv", + "pmc_perf_0.csv", + "pmc_perf_1.csv", + "pmc_perf_2.csv", + "pmc_perf_3.csv", + "pmc_perf_4.csv", + "pmc_perf_5.csv", + "pmc_perf_6.csv", + "pmc_perf_7.csv", + "sysinfo.csv", + ] assert sorted(list(file_dict.keys())) == sorted(expected_csvs) @@ -910,6 +1006,8 @@ def test_block_CPF(binary_handler_profile_rocprof_compute): "sysinfo.csv", "timestamps.csv", ] + if soc == "MI350": + expected_csvs.remove("timestamps.csv") assert sorted(list(file_dict.keys())) == sorted(expected_csvs) validate( @@ -959,6 +1057,24 @@ def test_block_SQ_CPC(binary_handler_profile_rocprof_compute): "sysinfo.csv", "timestamps.csv", ] + if soc == "MI350": + expected_csvs = [ + "SQ_IFETCH_LEVEL.csv", + "SQ_INST_LEVEL_LDS.csv", + "SQ_INST_LEVEL_SMEM.csv", + "SQ_INST_LEVEL_VMEM.csv", + "SQ_LEVEL_WAVES.csv", + "pmc_perf.csv", + "pmc_perf_0.csv", + "pmc_perf_1.csv", + "pmc_perf_2.csv", + "pmc_perf_3.csv", + "pmc_perf_4.csv", + "pmc_perf_5.csv", + "pmc_perf_6.csv", + "pmc_perf_7.csv", + "sysinfo.csv", + ] assert sorted(list(file_dict.keys())) == sorted(expected_csvs) @@ -1009,6 +1125,24 @@ def test_block_SQ_TA(binary_handler_profile_rocprof_compute): "sysinfo.csv", "timestamps.csv", ] + if soc == "MI350": + expected_csvs = [ + "SQ_IFETCH_LEVEL.csv", + "SQ_INST_LEVEL_LDS.csv", + "SQ_INST_LEVEL_SMEM.csv", + "SQ_INST_LEVEL_VMEM.csv", + "SQ_LEVEL_WAVES.csv", + "pmc_perf.csv", + "pmc_perf_0.csv", + "pmc_perf_1.csv", + "pmc_perf_2.csv", + "pmc_perf_3.csv", + "pmc_perf_4.csv", + "pmc_perf_5.csv", + "pmc_perf_6.csv", + "pmc_perf_7.csv", + "sysinfo.csv", + ] assert sorted(list(file_dict.keys())) == sorted(expected_csvs) @@ -1055,6 +1189,24 @@ def test_block_SQ_SPI(binary_handler_profile_rocprof_compute): "sysinfo.csv", "timestamps.csv", ] + if soc == "MI350": + expected_csvs = [ + "SQ_IFETCH_LEVEL.csv", + "SQ_INST_LEVEL_LDS.csv", + "SQ_INST_LEVEL_SMEM.csv", + "SQ_INST_LEVEL_VMEM.csv", + "SQ_LEVEL_WAVES.csv", + "pmc_perf.csv", + "pmc_perf_0.csv", + "pmc_perf_1.csv", + "pmc_perf_2.csv", + "pmc_perf_3.csv", + "pmc_perf_4.csv", + "pmc_perf_5.csv", + "pmc_perf_6.csv", + "pmc_perf_7.csv", + "sysinfo.csv", + ] assert sorted(list(file_dict.keys())) == sorted(expected_csvs) @@ -1106,6 +1258,24 @@ def test_block_SQ_SQC_TCP_CPC(binary_handler_profile_rocprof_compute): "sysinfo.csv", "timestamps.csv", ] + if soc == "MI350": + expected_csvs = [ + "SQ_IFETCH_LEVEL.csv", + "SQ_INST_LEVEL_LDS.csv", + "SQ_INST_LEVEL_SMEM.csv", + "SQ_INST_LEVEL_VMEM.csv", + "SQ_LEVEL_WAVES.csv", + "pmc_perf.csv", + "pmc_perf_0.csv", + "pmc_perf_1.csv", + "pmc_perf_2.csv", + "pmc_perf_3.csv", + "pmc_perf_4.csv", + "pmc_perf_5.csv", + "pmc_perf_6.csv", + "pmc_perf_7.csv", + "sysinfo.csv", + ] assert sorted(list(file_dict.keys())) == sorted(expected_csvs) @@ -1171,6 +1341,24 @@ def test_block_SQ_SPI_TA_TCC_CPF(binary_handler_profile_rocprof_compute): "sysinfo.csv", "timestamps.csv", ] + if soc == "MI350": + expected_csvs = [ + "SQ_IFETCH_LEVEL.csv", + "SQ_INST_LEVEL_LDS.csv", + "SQ_INST_LEVEL_SMEM.csv", + "SQ_INST_LEVEL_VMEM.csv", + "SQ_LEVEL_WAVES.csv", + "pmc_perf.csv", + "pmc_perf_0.csv", + "pmc_perf_1.csv", + "pmc_perf_2.csv", + "pmc_perf_3.csv", + "pmc_perf_4.csv", + "pmc_perf_5.csv", + "pmc_perf_6.csv", + "pmc_perf_7.csv", + "sysinfo.csv", + ] assert sorted(list(file_dict.keys())) == sorted(expected_csvs) @@ -1196,6 +1384,8 @@ def test_dispatch_0(binary_handler_profile_rocprof_compute): assert sorted(list(file_dict.keys())) == ALL_CSVS_MI200 elif "MI300" in soc: assert sorted(list(file_dict.keys())) == ALL_CSVS_MI300 + elif "MI350" in soc: + assert sorted(list(file_dict.keys())) == sorted(ALL_CSVS_MI350) else: print("Testing isn't supported yet for {}".format(soc)) assert 0 @@ -1226,6 +1416,8 @@ def test_dispatch_0_1(binary_handler_profile_rocprof_compute): assert sorted(list(file_dict.keys())) == ALL_CSVS_MI200 elif "MI300" in soc: assert sorted(list(file_dict.keys())) == ALL_CSVS_MI300 + elif "MI350" in soc: + assert sorted(list(file_dict.keys())) == sorted(ALL_CSVS_MI350) else: print("Testing isn't supported yet for {}".format(soc)) assert 0 @@ -1253,6 +1445,8 @@ def test_dispatch_2(binary_handler_profile_rocprof_compute): assert sorted(list(file_dict.keys())) == ALL_CSVS_MI200 elif "MI300" in soc: assert sorted(list(file_dict.keys())) == ALL_CSVS_MI300 + elif "MI350" in soc: + assert sorted(list(file_dict.keys())) == sorted(ALL_CSVS_MI350) else: print("Testing isn't supported yet for {}".format(soc)) assert 0 @@ -1283,6 +1477,8 @@ def test_join_type_grid(binary_handler_profile_rocprof_compute): assert sorted(list(file_dict.keys())) == ALL_CSVS_MI200 elif "MI300" in soc: assert sorted(list(file_dict.keys())) == ALL_CSVS_MI300 + elif "MI350" in soc: + assert sorted(list(file_dict.keys())) == sorted(ALL_CSVS_MI350) else: print("Testing isn't supported yet for {}".format(soc)) assert 0 @@ -1310,6 +1506,8 @@ def test_join_type_kernel(binary_handler_profile_rocprof_compute): assert sorted(list(file_dict.keys())) == ALL_CSVS_MI200 elif "MI300" in soc: assert sorted(list(file_dict.keys())) == ALL_CSVS_MI300 + elif "MI350" in soc: + assert sorted(list(file_dict.keys())) == sorted(ALL_CSVS_MI350) else: print("Testing isn't supported yet for {}".format(soc)) assert 0 @@ -1326,7 +1524,7 @@ def test_join_type_kernel(binary_handler_profile_rocprof_compute): @pytest.mark.sort def test_roof_sort_dispatches(binary_handler_profile_rocprof_compute): # only test 1 device for roofline - if soc == "MI100": + if soc in ("MI100", "MI350"): # roofline is not supported on MI100 assert True # Do not continue testing @@ -1356,7 +1554,7 @@ def test_roof_sort_dispatches(binary_handler_profile_rocprof_compute): @pytest.mark.sort def test_roof_sort_kernels(binary_handler_profile_rocprof_compute): # only test 1 device for roofline - if soc == "MI100": + if soc in ("MI100", "MI350"): # roofline is not supported on MI100 assert True # Do not continue testing @@ -1386,7 +1584,7 @@ def test_roof_sort_kernels(binary_handler_profile_rocprof_compute): @pytest.mark.mem def test_roof_mem_levels_vL1D(binary_handler_profile_rocprof_compute): # only test 1 device for roofline - if soc == "MI100": + if soc in ("MI100", "MI350"): # roofline is not supported on MI100 assert True # Do not continue testing @@ -1416,7 +1614,7 @@ def test_roof_mem_levels_vL1D(binary_handler_profile_rocprof_compute): @pytest.mark.mem def test_roof_mem_levels_LDS(binary_handler_profile_rocprof_compute): # only test 1 device for roofline - if soc == "MI100": + if soc in ("MI100", "MI350"): # roofline is not supported on MI100 assert True # Do not continue testing diff --git a/projects/rocprofiler-compute/tests/workloads/device_filter/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/device_filter/MI100/sysinfo.csv index 1085042716..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/device_filter/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/device_filter/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -device_filter,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:54:18 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/device_filter/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/device_filter/MI200/sysinfo.csv index 3f85440ab2..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/device_filter/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/device_filter/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -device_filter,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:35:56 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/device_filter/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/device_filter/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/device_filter/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/device_filter/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/device_filter/MI300A_A1/sysinfo.csv index c0f20e28fb..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/device_filter/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/device_filter/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -device_filter,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:39:25 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/device_filter/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/device_filter/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/device_filter/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/device_filter/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/device_filter/MI300X_A1/sysinfo.csv index e442600526..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/device_filter/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/device_filter/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -device_filter,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 12:03:10 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI100/sysinfo.csv index 3beb72b6ec..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -device_inv_int,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:53:52 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI200/sysinfo.csv index 4ccc6bd554..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -device_inv_int,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:33:56 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI300A_A1/sysinfo.csv index 824e74d982..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -device_inv_int,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:38:17 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI300X_A1/sysinfo.csv index 8398177bcb..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/device_inv_int/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -device_inv_int,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 12:02:25 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI100/sysinfo.csv index b688f42cd4..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_0,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:53:14 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI200/sysinfo.csv index f74fde750f..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_0,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:24:01 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI300A_A1/sysinfo.csv index 9bc5f9c787..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_0,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:36:42 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI300X_A1/sysinfo.csv index 5721c48f38..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_0/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_0,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 12:01:22 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI100/sysinfo.csv index 9523e9c63e..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_0_1,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:53:28 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI200/sysinfo.csv index 722ff11d3b..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_0_1,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:27:24 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI300A_A1/sysinfo.csv index 912d8123d9..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_0_1,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:37:17 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI300X_A1/sysinfo.csv index 1b04d84fa1..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_0_1/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_0_1,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 12:01:45 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI100/sysinfo.csv index 6f43e7d3d9..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_2,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:53:00 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI200/sysinfo.csv index f8cdcd5c3d..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_2,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:22:15 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI300A_A1/sysinfo.csv index 36f84f532c..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_2,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:36:08 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI300X_A1/sysinfo.csv index 4a17c06a03..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_2/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_2,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 12:00:59 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI100/sysinfo.csv index 2c4893682f..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_6_8,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:54:58 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI200/sysinfo.csv index e1554780b5..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_6_8,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:47:59 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI300A_A1/sysinfo.csv index 0ededf25dc..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_6_8,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:41:21 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI300X_A1/sysinfo.csv index cfe2913817..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_6_8/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_6_8,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 12:04:26 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI100/sysinfo.csv index 67532231bb..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_7,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:47 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI200/sysinfo.csv index 6a2b895ba0..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_7,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:22:01 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI300A_A1/sysinfo.csv index c04f406b67..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_7,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:35:34 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI300X_A1/sysinfo.csv index 57080613a9..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_7/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_7,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 12:00:37 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI100/sysinfo.csv index 8ca917541c..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_inv,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:50:46 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI200/sysinfo.csv index 63bd297bf4..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_inv,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:02:53 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI300A_A1/sysinfo.csv index 94076fe3b6..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_inv,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:30:08 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI300X_A1/sysinfo.csv index 62c90e56a2..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/dispatch_inv/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -dispatch_inv,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 11:57:01 AM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI100/sysinfo.csv index 02ac37cca6..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_CPC,./tests/vcopy -n 1048576 -b 256 -i 3,cpc,Thu 21 Mar 2024 03:53:48 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI200/sysinfo.csv index 923b77ce74..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_CPC,./tests/vcopy -n 1048576 -b 256 -i 3,cpc|roofline,Thu 21 Mar 2024 04:32:20 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI300A_A1/sysinfo.csv index 4a1a8a1b53..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_CPC,./tests/vcopy -n 1048576 -b 256 -i 3,cpc,Wed 29 May 2024 01:38:07 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI300X_A1/sysinfo.csv index 1449d3414b..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPC/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_CPC,./tests/vcopy -n 1048576 -b 256 -i 3,cpc,Wed 29 May 2024 12:02:18 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI100/sysinfo.csv index d457074075..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_CPF,./tests/vcopy -n 1048576 -b 256 -i 3,cpf,Thu 21 Mar 2024 03:53:45 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI200/sysinfo.csv index cc4e1a516a..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_CPF,./tests/vcopy -n 1048576 -b 256 -i 3,cpf|roofline,Thu 21 Mar 2024 04:30:45 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI300A_A1/sysinfo.csv index dd765013da..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_CPF,./tests/vcopy -n 1048576 -b 256 -i 3,cpf,Wed 29 May 2024 01:37:59 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI300X_A1/sysinfo.csv index 0082d377bc..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_CPF/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_CPF,./tests/vcopy -n 1048576 -b 256 -i 3,cpf,Wed 29 May 2024 12:02:13 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI100/sysinfo.csv index 0d32662af6..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SPI,./tests/vcopy -n 1048576 -b 256 -i 3,spi,Thu 21 Mar 2024 03:55:15 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI200/sysinfo.csv index 3aa3e9ed13..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SPI,./tests/vcopy -n 1048576 -b 256 -i 3,spi|roofline,Thu 21 Mar 2024 04:53:04 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI300A_A1/sysinfo.csv index 8dffd88a9c..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SPI,./tests/vcopy -n 1048576 -b 256 -i 3,spi,Wed 29 May 2024 01:42:33 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI300X_A1/sysinfo.csv index 163e311c46..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SPI/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SPI,./tests/vcopy -n 1048576 -b 256 -i 3,spi,Wed 29 May 2024 12:05:35 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI100/sysinfo.csv index e7f9eb171c..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ,./tests/vcopy -n 1048576 -b 256 -i 3,sq,Thu 21 Mar 2024 03:54:33 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI200/sysinfo.csv index bfb16a2601..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ,./tests/vcopy -n 1048576 -b 256 -i 3,sq|roofline,Thu 21 Mar 2024 04:38:11 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI300A_A1/sysinfo.csv index 43356d7b12..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ,./tests/vcopy -n 1048576 -b 256 -i 3,sq,Wed 29 May 2024 01:40:01 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI300X_A1/sysinfo.csv index d75de2ff8f..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ,./tests/vcopy -n 1048576 -b 256 -i 3,sq,Wed 29 May 2024 12:03:33 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI100/sysinfo.csv index bd54e30e7e..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQC,./tests/vcopy -n 1048576 -b 256 -i 3,sqc,Thu 21 Mar 2024 03:53:41 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI200/sysinfo.csv index 094bc74263..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQC,./tests/vcopy -n 1048576 -b 256 -i 3,sqc|roofline,Thu 21 Mar 2024 04:29:10 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI300A_A1/sysinfo.csv index bda035de64..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQC,./tests/vcopy -n 1048576 -b 256 -i 3,sqc,Wed 29 May 2024 01:37:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI300X_A1/sysinfo.csv index 28015acbe2..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQC/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQC,./tests/vcopy -n 1048576 -b 256 -i 3,sqc,Wed 29 May 2024 12:02:07 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI100/sysinfo.csv index e4b0aff7f9..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_CPC,./tests/vcopy -n 1048576 -b 256 -i 3,sq|cpc,Thu 21 Mar 2024 03:54:41 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI200/sysinfo.csv index c82264ede6..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_CPC,./tests/vcopy -n 1048576 -b 256 -i 3,sq|cpc|roofline,Thu 21 Mar 2024 04:39:52 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI300A_A1/sysinfo.csv index bb29c43a78..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_CPC,./tests/vcopy -n 1048576 -b 256 -i 3,sq|cpc,Wed 29 May 2024 01:40:28 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI300X_A1/sysinfo.csv index 216eb6362b..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_CPC/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_CPC,./tests/vcopy -n 1048576 -b 256 -i 3,sq|cpc,Wed 29 May 2024 12:03:51 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI100/sysinfo.csv index 098c81b6e3..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_SPI,./tests/vcopy -n 1048576 -b 256 -i 3,sq|spi,Thu 21 Mar 2024 03:52:25 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI200/sysinfo.csv index f472fa54e2..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_SPI,./tests/vcopy -n 1048576 -b 256 -i 3,sq|spi|roofline,Thu 21 Mar 2024 04:18:32 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI300A_A1/sysinfo.csv index 9539ecf94a..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_SPI,./tests/vcopy -n 1048576 -b 256 -i 3,sq|spi,Wed 29 May 2024 01:34:33 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI300X_A1/sysinfo.csv index 30bd8163c8..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_SPI,./tests/vcopy -n 1048576 -b 256 -i 3,sq|spi,Wed 29 May 2024 11:59:57 AM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI100/sysinfo.csv index 2d58d3bb3a..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_SPI_TA_TCC_CPF,./tests/vcopy -n 1048576 -b 256 -i 3,sq|spi|ta|tcc|cpf,Thu 21 Mar 2024 03:51:28 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI200/sysinfo.csv index c8b7277582..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_SPI_TA_TCC_CPF,./tests/vcopy -n 1048576 -b 256 -i 3,sq|spi|ta|tcc|cpf|roofline,Thu 21 Mar 2024 04:11:22 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI300A_A1/sysinfo.csv index 184ffd9f90..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_SPI_TA_TCC_CPF,./tests/vcopy -n 1048576 -b 256 -i 3,sq|spi|ta|tcc|cpf,Wed 29 May 2024 01:31:58 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI300X_A1/sysinfo.csv index ae3d84ac8b..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SPI_TA_TCC_CPF/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_SPI_TA_TCC_CPF,./tests/vcopy -n 1048576 -b 256 -i 3,sq|spi|ta|tcc|cpf,Wed 29 May 2024 11:58:14 AM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI100/sysinfo.csv index 8c68f6d235..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_SQC_TCP_CPC,./tests/vcopy -n 1048576 -b 256 -i 3,sq|sqc|tcp|cpc,Thu 21 Mar 2024 03:51:50 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI200/sysinfo.csv index 5c97c3ca98..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_SQC_TCP_CPC,./tests/vcopy -n 1048576 -b 256 -i 3,sq|sqc|tcp|cpc|roofline,Thu 21 Mar 2024 04:14:50 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI300A_A1/sysinfo.csv index fb4f3b9b2a..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_SQC_TCP_CPC,./tests/vcopy -n 1048576 -b 256 -i 3,sq|sqc|tcp|cpc,Wed 29 May 2024 01:32:59 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI300X_A1/sysinfo.csv index 56b9feb8ae..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_SQC_TCP_CPC/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_SQC_TCP_CPC,./tests/vcopy -n 1048576 -b 256 -i 3,sq|sqc|tcp|cpc,Wed 29 May 2024 11:58:54 AM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI100/sysinfo.csv index 798fb70553..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_TA,./tests/vcopy -n 1048576 -b 256 -i 3,sq|ta,Thu 21 Mar 2024 03:51:20 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI200/sysinfo.csv index b48885be2b..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_TA,./tests/vcopy -n 1048576 -b 256 -i 3,sq|ta|roofline,Thu 21 Mar 2024 04:09:40 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI300A_A1/sysinfo.csv index e7e5150aed..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_TA,./tests/vcopy -n 1048576 -b 256 -i 3,sq|ta,Wed 29 May 2024 01:31:31 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI300X_A1/sysinfo.csv index 4d2493cdd3..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_SQ_TA/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_SQ_TA,./tests/vcopy -n 1048576 -b 256 -i 3,sq|ta,Wed 29 May 2024 11:57:57 AM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI100/sysinfo.csv index 186d2cdfd1..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TA,./tests/vcopy -n 1048576 -b 256 -i 3,ta,Thu 21 Mar 2024 03:54:49 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI200/sysinfo.csv index dc817c94ff..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TA,./tests/vcopy -n 1048576 -b 256 -i 3,ta|roofline,Thu 21 Mar 2024 04:41:34 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI300A_A1/sysinfo.csv index c8d0617047..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TA,./tests/vcopy -n 1048576 -b 256 -i 3,ta,Wed 29 May 2024 01:40:55 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI300X_A1/sysinfo.csv index 74a5783762..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TA/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TA,./tests/vcopy -n 1048576 -b 256 -i 3,ta,Wed 29 May 2024 12:04:09 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI100/sysinfo.csv index 7947c06dab..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TCC,./tests/vcopy -n 1048576 -b 256 -i 3,tcc,Thu 21 Mar 2024 03:50:39 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI200/sysinfo.csv index 197b7a9acb..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TCC,./tests/vcopy -n 1048576 -b 256 -i 3,tcc|roofline,Thu 21 Mar 2024 04:01:15 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI300A_A1/sysinfo.csv index 9c60fbf620..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TCC,./tests/vcopy -n 1048576 -b 256 -i 3,tcc,Wed 29 May 2024 01:29:53 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI300X_A1/sysinfo.csv index 2812d02766..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCC/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TCC,./tests/vcopy -n 1048576 -b 256 -i 3,tcc,Wed 29 May 2024 11:56:51 AM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI100/sysinfo.csv index bc00696c3c..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TCP,./tests/vcopy -n 1048576 -b 256 -i 3,tcp,Thu 21 Mar 2024 03:51:00 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI200/sysinfo.csv index 83e24f9bc5..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TCP,./tests/vcopy -n 1048576 -b 256 -i 3,tcp|roofline,Thu 21 Mar 2024 04:04:39 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI300A_A1/sysinfo.csv index a97497a0ef..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TCP,./tests/vcopy -n 1048576 -b 256 -i 3,tcp,Wed 29 May 2024 01:30:41 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI300X_A1/sysinfo.csv index b11dc04254..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TCP/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TCP,./tests/vcopy -n 1048576 -b 256 -i 3,tcp,Wed 29 May 2024 11:57:23 AM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI100/sysinfo.csv index d2937b20cc..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TD,./tests/vcopy -n 1048576 -b 256 -i 3,td,Thu 21 Mar 2024 03:54:54 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI200/sysinfo.csv index 01297e11e6..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TD,./tests/vcopy -n 1048576 -b 256 -i 3,td|roofline,Thu 21 Mar 2024 04:43:11 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI300A_A1/sysinfo.csv index 7c1fc793f7..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TD,./tests/vcopy -n 1048576 -b 256 -i 3,td,Wed 29 May 2024 01:41:08 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI300X_A1/sysinfo.csv index 41fdfccb00..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/ipblocks_TD/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -ipblocks_TD,./tests/vcopy -n 1048576 -b 256 -i 3,td,Wed 29 May 2024 12:04:17 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI100/sysinfo.csv index 01041b7128..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -join_type_grid,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:51:37 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI200/sysinfo.csv index 975adc5e90..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -join_type_grid,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:13:03 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI300A_A1/sysinfo.csv index b681dcbbb1..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -join_type_grid,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:32:25 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI300X_A1/sysinfo.csv index dac86af145..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/join_type_grid/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -join_type_grid,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 11:58:32 AM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI100/sysinfo.csv index 97e3890573..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -join_type_kernel,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:51:07 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI200/sysinfo.csv index 9fd5a9a343..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -join_type_kernel,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:07:54 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI300A_A1/sysinfo.csv index 9f2958e717..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -join_type_kernel,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:30:58 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI300X_A1/sysinfo.csv index 3343f02299..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/join_type_kernel/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -join_type_kernel,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 11:57:34 AM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel/MI100/sysinfo.csv index e9151330ba..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 05:07:54 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel/MI200/sysinfo.csv index d52c86c1f4..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 05:04:59 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/kernel/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/kernel/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel/MI300A_A1/sysinfo.csv index 28264aef5b..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:41:56 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/kernel/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/kernel/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel/MI300X_A1/sysinfo.csv index 444ccf388c..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 12:04:49 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI100/sysinfo.csv index 3654a9c34f..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel_inv_int,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:51:59 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI200/sysinfo.csv index 012c9eecce..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel_inv_int,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:32 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI300A_A1/sysinfo.csv index 57fc3fc879..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel_inv_int,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:33:25 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI300X_A1/sysinfo.csv index b550e8c0f1..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel_inv_int/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel_inv_int,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 11:59:12 AM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI100/sysinfo.csv index 89d7986234..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel_inv_str,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:54:05 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI200/sysinfo.csv index 932bf8d601..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel_inv_str,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:35:42 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI300A_A1/sysinfo.csv index f2a815bfd8..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel_inv_str,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:38:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI300X_A1/sysinfo.csv index 5a67519e08..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel_inv_str/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel_inv_str,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 12:02:47 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_names/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel_names/MI200/sysinfo.csv index 3408a5bd12..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel_names/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel_names/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel_names,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:25:47 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI100/sysinfo.csv index 5e1c91244f..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel_substr,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:33 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI200/sysinfo.csv index 0b43aab07b..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel_substr,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:20:15 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI300A_A1/sysinfo.csv index d5cb6e86ca..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel_substr,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:35:00 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI300X_A1/sysinfo.csv index 2f8050c9db..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/kernel_substr/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -kernel_substr,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 12:00:15 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/mem_levels_HBM/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/mem_levels_HBM/MI200/sysinfo.csv index c6803fddd3..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/mem_levels_HBM/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/mem_levels_HBM/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -mem_levels_HBM,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:49:51 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/mem_levels_HBM_LDS/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/mem_levels_HBM_LDS/MI200/sysinfo.csv index ce5fcd40ab..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/mem_levels_HBM_LDS/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/mem_levels_HBM_LDS/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -mem_levels_HBM_LDS,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 03:58:02 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/mem_levels_L2/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/mem_levels_L2/MI200/sysinfo.csv index 57584dd5ab..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/mem_levels_L2/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/mem_levels_L2/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -mem_levels_L2,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:46:23 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/mem_levels_L2_vL1d_LDS/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/mem_levels_L2_vL1d_LDS/MI200/sysinfo.csv index e5d95bedca..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/mem_levels_L2_vL1d_LDS/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/mem_levels_L2_vL1d_LDS/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -mem_levels_L2_vL1d_LDS,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:48:13 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/mem_levels_LDS/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/mem_levels_LDS/MI200/sysinfo.csv index 0bc8912cba..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/mem_levels_LDS/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/mem_levels_LDS/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -mem_levels_LDS,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:44:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/mem_levels_vL1D/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/mem_levels_vL1D/MI200/sysinfo.csv index 8009e0d1f6..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/mem_levels_vL1D/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/mem_levels_vL1D/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -mem_levels_vL1D,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 03:59:39 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/mem_levels_vL1d_LDS/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/mem_levels_vL1d_LDS/MI200/sysinfo.csv index 36d409baaf..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/mem_levels_vL1d_LDS/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/mem_levels_vL1d_LDS/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -mem_levels_vL1d_LDS,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:51:27 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI100/sysinfo.csv index 8a6148ab1d..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/no_roof/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -no_roof,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:55:21 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI200/sysinfo.csv index 1b5f2167ea..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/no_roof/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -no_roof,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 04:54:41 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI300A_A1/sysinfo.csv index acc13ccce0..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/no_roof/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -no_roof,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:42:47 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI300X_A1/sysinfo.csv index e6f960db2b..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/no_roof/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -no_roof,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 12:05:44 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/SQ_IFETCH_LEVEL.csv new file mode 100644 index 0000000000..c32def855c --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/SQ_IFETCH_LEVEL.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,CPC_ME1_BUSY_FOR_PACKET_DECODE,CPC_SYNC_WRREQ_FIFO_BUSY,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_BUSY,GRBM_GUI_ACTIVE,SPI_CS0_WAVE,SPI_CS1_WAVE,SPI_CS2_WAVE,SPI_CS3_WAVE,SQC_DCACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQ_IFETCH_LEVEL,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_VMEM_WR_TA_DATA_FIFO_FULL,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TCC_EA0_RDREQ[0],TCC_EA0_RDREQ[10],TCC_EA0_RDREQ[11],TCC_EA0_RDREQ[12],TCC_EA0_RDREQ[13],TCC_EA0_RDREQ[14],TCC_EA0_RDREQ[15],TCC_EA0_RDREQ[16],TCC_EA0_RDREQ[17],TCC_EA0_RDREQ[18],TCC_EA0_RDREQ[19],TCC_EA0_RDREQ[1],TCC_EA0_RDREQ[20],TCC_EA0_RDREQ[21],TCC_EA0_RDREQ[22],TCC_EA0_RDREQ[23],TCC_EA0_RDREQ[25],TCC_EA0_RDREQ[26],TCC_EA0_RDREQ[27],TCC_EA0_RDREQ[28],TCC_EA0_RDREQ[29],TCC_EA0_RDREQ[2],TCC_EA0_RDREQ[30],TCC_EA0_RDREQ[31],TCC_EA0_RDREQ[32],TCC_EA0_RDREQ[33],TCC_EA0_RDREQ[34],TCC_EA0_RDREQ[35],TCC_EA0_RDREQ[36],TCC_EA0_RDREQ[37],TCC_EA0_RDREQ[38],TCC_EA0_RDREQ[39],TCC_EA0_RDREQ[3],TCC_EA0_RDREQ[40],TCC_EA0_RDREQ[41],TCC_EA0_RDREQ[42],TCC_EA0_RDREQ[43],TCC_EA0_RDREQ[45],TCC_EA0_RDREQ[46],TCC_EA0_RDREQ[47],TCC_EA0_RDREQ[48],TCC_EA0_RDREQ[49],TCC_EA0_RDREQ[50],TCC_EA0_RDREQ[51],TCC_EA0_RDREQ[52],TCC_EA0_RDREQ[53],TCC_EA0_RDREQ[54],TCC_EA0_RDREQ[55],TCC_EA0_RDREQ[56],TCC_EA0_RDREQ[57],TCC_EA0_RDREQ[58],TCC_EA0_RDREQ[59],TCC_EA0_RDREQ[5],TCC_EA0_RDREQ[60],TCC_EA0_RDREQ[61],TCC_EA0_RDREQ[62],TCC_EA0_RDREQ[63],TCC_EA0_RDREQ[6],TCC_EA0_RDREQ[7],TCC_EA0_RDREQ[8],TCC_EA0_RDREQ[9],TCC_EA0_WRREQ_LEVEL[0],TCC_EA0_WRREQ_LEVEL[10],TCC_EA0_WRREQ_LEVEL[11],TCC_EA0_WRREQ_LEVEL[12],TCC_EA0_WRREQ_LEVEL[13],TCC_EA0_WRREQ_LEVEL[14],TCC_EA0_WRREQ_LEVEL[15],TCC_EA0_WRREQ_LEVEL[16],TCC_EA0_WRREQ_LEVEL[17],TCC_EA0_WRREQ_LEVEL[18],TCC_EA0_WRREQ_LEVEL[19],TCC_EA0_WRREQ_LEVEL[1],TCC_EA0_WRREQ_LEVEL[20],TCC_EA0_WRREQ_LEVEL[21],TCC_EA0_WRREQ_LEVEL[22],TCC_EA0_WRREQ_LEVEL[23],TCC_EA0_WRREQ_LEVEL[25],TCC_EA0_WRREQ_LEVEL[26],TCC_EA0_WRREQ_LEVEL[27],TCC_EA0_WRREQ_LEVEL[28],TCC_EA0_WRREQ_LEVEL[29],TCC_EA0_WRREQ_LEVEL[2],TCC_EA0_WRREQ_LEVEL[30],TCC_EA0_WRREQ_LEVEL[31],TCC_EA0_WRREQ_LEVEL[32],TCC_EA0_WRREQ_LEVEL[33],TCC_EA0_WRREQ_LEVEL[34],TCC_EA0_WRREQ_LEVEL[35],TCC_EA0_WRREQ_LEVEL[36],TCC_EA0_WRREQ_LEVEL[37],TCC_EA0_WRREQ_LEVEL[38],TCC_EA0_WRREQ_LEVEL[39],TCC_EA0_WRREQ_LEVEL[3],TCC_EA0_WRREQ_LEVEL[40],TCC_EA0_WRREQ_LEVEL[41],TCC_EA0_WRREQ_LEVEL[42],TCC_EA0_WRREQ_LEVEL[43],TCC_EA0_WRREQ_LEVEL[45],TCC_EA0_WRREQ_LEVEL[46],TCC_EA0_WRREQ_LEVEL[47],TCC_EA0_WRREQ_LEVEL[48],TCC_EA0_WRREQ_LEVEL[49],TCC_EA0_WRREQ_LEVEL[50],TCC_EA0_WRREQ_LEVEL[51],TCC_EA0_WRREQ_LEVEL[52],TCC_EA0_WRREQ_LEVEL[53],TCC_EA0_WRREQ_LEVEL[54],TCC_EA0_WRREQ_LEVEL[55],TCC_EA0_WRREQ_LEVEL[56],TCC_EA0_WRREQ_LEVEL[57],TCC_EA0_WRREQ_LEVEL[58],TCC_EA0_WRREQ_LEVEL[59],TCC_EA0_WRREQ_LEVEL[5],TCC_EA0_WRREQ_LEVEL[60],TCC_EA0_WRREQ_LEVEL[61],TCC_EA0_WRREQ_LEVEL[62],TCC_EA0_WRREQ_LEVEL[63],TCC_EA0_WRREQ_LEVEL[6],TCC_EA0_WRREQ_LEVEL[7],TCC_EA0_WRREQ_LEVEL[8],TCC_EA0_WRREQ_LEVEL[9],TCC_NC_REQ_sum,TCC_REQ[0],TCC_REQ[10],TCC_REQ[11],TCC_REQ[12],TCC_REQ[13],TCC_REQ[14],TCC_REQ[15],TCC_REQ[16],TCC_REQ[17],TCC_REQ[18],TCC_REQ[19],TCC_REQ[1],TCC_REQ[20],TCC_REQ[21],TCC_REQ[22],TCC_REQ[23],TCC_REQ[25],TCC_REQ[26],TCC_REQ[27],TCC_REQ[28],TCC_REQ[29],TCC_REQ[2],TCC_REQ[30],TCC_REQ[31],TCC_REQ[32],TCC_REQ[33],TCC_REQ[34],TCC_REQ[35],TCC_REQ[36],TCC_REQ[37],TCC_REQ[38],TCC_REQ[39],TCC_REQ[3],TCC_REQ[40],TCC_REQ[41],TCC_REQ[42],TCC_REQ[43],TCC_REQ[45],TCC_REQ[46],TCC_REQ[47],TCC_REQ[48],TCC_REQ[49],TCC_REQ[50],TCC_REQ[51],TCC_REQ[52],TCC_REQ[53],TCC_REQ[54],TCC_REQ[55],TCC_REQ[56],TCC_REQ[57],TCC_REQ[58],TCC_REQ[59],TCC_REQ[5],TCC_REQ[60],TCC_REQ[61],TCC_REQ[62],TCC_REQ[63],TCC_REQ[6],TCC_REQ[7],TCC_REQ[8],TCC_REQ[9],TCP_GATE_EN1_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_TOTAL_WRITE_sum,TD_ATOMIC_WAVEFRONT_sum,TD_TC_STALL_sum +0,0,1,15737,15737,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, 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diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/SQ_INST_LEVEL_LDS.csv new file mode 100644 index 0000000000..f69137167f --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/SQ_INST_LEVEL_LDS.csv @@ -0,0 +1,4 @@ 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diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/SQ_INST_LEVEL_VMEM.csv new file mode 100644 index 0000000000..2d78689306 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/SQ_INST_LEVEL_VMEM.csv @@ -0,0 +1,4 @@ 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diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/SQ_LEVEL_WAVES.csv new file mode 100644 index 0000000000..bbf437cf1b --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/SQ_LEVEL_WAVES.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,CPC_CPC_TCIU_IDLE,CPC_TG_SEND,CPF_CPF_TCIU_IDLE,SPI_CS0_BUSY,SPI_CS1_BUSY,SPI_CS2_BUSY,SPI_CS3_BUSY,SQ_INSTS_LDS,SQ_INSTS_LDS_LOAD_BANDWIDTH,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_FMA_F16,SQ_LDS_IDX_ACTIVE,SQ_LEVEL_WAVES,SQ_WAVE_CYCLES,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_BUBBLE_sum,TCC_EA0_ATOMIC_LEVEL[0],TCC_EA0_ATOMIC_LEVEL[11],TCC_EA0_ATOMIC_LEVEL[12],TCC_EA0_ATOMIC_LEVEL[13],TCC_EA0_ATOMIC_LEVEL[14],TCC_EA0_ATOMIC_LEVEL[16],TCC_EA0_ATOMIC_LEVEL[17],TCC_EA0_ATOMIC_LEVEL[18],TCC_EA0_ATOMIC_LEVEL[19],TCC_EA0_ATOMIC_LEVEL[1],TCC_EA0_ATOMIC_LEVEL[22],TCC_EA0_ATOMIC_LEVEL[23],TCC_EA0_ATOMIC_LEVEL[24],TCC_EA0_ATOMIC_LEVEL[25],TCC_EA0_ATOMIC_LEVEL[27],TCC_EA0_ATOMIC_LEVEL[28],TCC_EA0_ATOMIC_LEVEL[29],TCC_EA0_ATOMIC_LEVEL[2],TCC_EA0_ATOMIC_LEVEL[30],TCC_EA0_ATOMIC_LEVEL[32],TCC_EA0_ATOMIC_LEVEL[33],TCC_EA0_ATOMIC_LEVEL[34],TCC_EA0_ATOMIC_LEVEL[35],TCC_EA0_ATOMIC_LEVEL[37],TCC_EA0_ATOMIC_LEVEL[38],TCC_EA0_ATOMIC_LEVEL[39],TCC_EA0_ATOMIC_LEVEL[3],TCC_EA0_ATOMIC_LEVEL[40],TCC_EA0_ATOMIC_LEVEL[43],TCC_EA0_ATOMIC_LEVEL[44],TCC_EA0_ATOMIC_LEVEL[45],TCC_EA0_ATOMIC_LEVEL[46],TCC_EA0_ATOMIC_LEVEL[48],TCC_EA0_ATOMIC_LEVEL[49],TCC_EA0_ATOMIC_LEVEL[4],TCC_EA0_ATOMIC_LEVEL[50],TCC_EA0_ATOMIC_LEVEL[51],TCC_EA0_ATOMIC_LEVEL[53],TCC_EA0_ATOMIC_LEVEL[54],TCC_EA0_ATOMIC_LEVEL[55],TCC_EA0_ATOMIC_LEVEL[56],TCC_EA0_ATOMIC_LEVEL[58],TCC_EA0_ATOMIC_LEVEL[59],TCC_EA0_ATOMIC_LEVEL[60],TCC_EA0_ATOMIC_LEVEL[61],TCC_EA0_ATOMIC_LEVEL[6],TCC_EA0_ATOMIC_LEVEL[7],TCC_EA0_ATOMIC_LEVEL[8],TCC_EA0_ATOMIC_LEVEL[9],TCC_EA0_RDREQ_LEVEL[0],TCC_EA0_RDREQ_LEVEL[11],TCC_EA0_RDREQ_LEVEL[12],TCC_EA0_RDREQ_LEVEL[13],TCC_EA0_RDREQ_LEVEL[14],TCC_EA0_RDREQ_LEVEL[16],TCC_EA0_RDREQ_LEVEL[17],TCC_EA0_RDREQ_LEVEL[18],TCC_EA0_RDREQ_LEVEL[19],TCC_EA0_RDREQ_LEVEL[1],TCC_EA0_RDREQ_LEVEL[22],TCC_EA0_RDREQ_LEVEL[23],TCC_EA0_RDREQ_LEVEL[24],TCC_EA0_RDREQ_LEVEL[25],TCC_EA0_RDREQ_LEVEL[27],TCC_EA0_RDREQ_LEVEL[28],TCC_EA0_RDREQ_LEVEL[29],TCC_EA0_RDREQ_LEVEL[2],TCC_EA0_RDREQ_LEVEL[30],TCC_EA0_RDREQ_LEVEL[32],TCC_EA0_RDREQ_LEVEL[33],TCC_EA0_RDREQ_LEVEL[34],TCC_EA0_RDREQ_LEVEL[35],TCC_EA0_RDREQ_LEVEL[37],TCC_EA0_RDREQ_LEVEL[38],TCC_EA0_RDREQ_LEVEL[39],TCC_EA0_RDREQ_LEVEL[3],TCC_EA0_RDREQ_LEVEL[40],TCC_EA0_RDREQ_LEVEL[43],TCC_EA0_RDREQ_LEVEL[44],TCC_EA0_RDREQ_LEVEL[45],TCC_EA0_RDREQ_LEVEL[46],TCC_EA0_RDREQ_LEVEL[48],TCC_EA0_RDREQ_LEVEL[49],TCC_EA0_RDREQ_LEVEL[4],TCC_EA0_RDREQ_LEVEL[50],TCC_EA0_RDREQ_LEVEL[51],TCC_EA0_RDREQ_LEVEL[53],TCC_EA0_RDREQ_LEVEL[54],TCC_EA0_RDREQ_LEVEL[55],TCC_EA0_RDREQ_LEVEL[56],TCC_EA0_RDREQ_LEVEL[58],TCC_EA0_RDREQ_LEVEL[59],TCC_EA0_RDREQ_LEVEL[60],TCC_EA0_RDREQ_LEVEL[61],TCC_EA0_RDREQ_LEVEL[6],TCC_EA0_RDREQ_LEVEL[7],TCC_EA0_RDREQ_LEVEL[8],TCC_EA0_RDREQ_LEVEL[9],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_TOO_MANY_EA_WRREQS_STALL[32],TCC_TOO_MANY_EA_WRREQS_STALL[33],TCC_TOO_MANY_EA_WRREQS_STALL[34],TCC_TOO_MANY_EA_WRREQS_STALL[35],TCC_TOO_MANY_EA_WRREQS_STALL[37],TCC_TOO_MANY_EA_WRREQS_STALL[38],TCC_TOO_MANY_EA_WRREQS_STALL[39],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_TOO_MANY_EA_WRREQS_STALL[40],TCC_TOO_MANY_EA_WRREQS_STALL[43],TCC_TOO_MANY_EA_WRREQS_STALL[44],TCC_TOO_MANY_EA_WRREQS_STALL[45],TCC_TOO_MANY_EA_WRREQS_STALL[46],TCC_TOO_MANY_EA_WRREQS_STALL[48],TCC_TOO_MANY_EA_WRREQS_STALL[49],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_TOO_MANY_EA_WRREQS_STALL[50],TCC_TOO_MANY_EA_WRREQS_STALL[51],TCC_TOO_MANY_EA_WRREQS_STALL[53],TCC_TOO_MANY_EA_WRREQS_STALL[54],TCC_TOO_MANY_EA_WRREQS_STALL[55],TCC_TOO_MANY_EA_WRREQS_STALL[56],TCC_TOO_MANY_EA_WRREQS_STALL[58],TCC_TOO_MANY_EA_WRREQS_STALL[59],TCC_TOO_MANY_EA_WRREQS_STALL[60],TCC_TOO_MANY_EA_WRREQS_STALL[61],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCP_GATE_EN2_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TD_TD_BUSY_sum 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diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/log.txt b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/log.txt new file mode 100644 index 0000000000..7cde2f83bc --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/log.txt @@ -0,0 +1,195 @@ +[profiling] pre-processing using rocprofv3 profiler +[gen_sysinfo] +Incomplete class definition for gfx950. Expecting populated max_mclk but detected None. +Incomplete class definition for gfx950. Expecting populated cur_mclk but detected None. +Missing specs fields for gfx950 +starting "run_profiling" and about to start rocprof's workload +[profiling] performing profiling using rocprofv3 profiler +Rocprofiler-Compute version: 3.1.0 +Profiler choice: rocprofv3 +Path: /app/workloads/vcopy/MI350 +Target: MI350 +Command: tests/vcopy -n 1048576 -b 256 -i 3 +Kernel Selection: None +Dispatch Selection: None +Hardware Blocks: [] +Report Sections: [] + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Collecting Performance Counters +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.txt +pmc file: SQ_IFETCH_LEVEL.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.yaml -i /app/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] W20250328 22:43:59.475907 140180820113408 tool.cpp:930] Unable to find all counters for agent 1 (gpu-0, gfx950) in [CPC_ME1_BUSY_FOR_PACKET_DECODE, CPC_SYNC_WRREQ_FIFO_BUSY, CPF_CMP_UTCL1_STALL_ON_TRANSLATION, CPF_CPF_STAT_BUSY, GRBM_GUI_ACTIVE, SPI_CS0_WAVE, SPI_CS1_WAVE, SPI_CS2_WAVE, SPI_CS3_WAVE, SQC_DCACHE_HITS, SQC_ICACHE_MISSES, SQC_ICACHE_MISSES_DUPLICATE, SQ_IFETCH_LEVEL, SQ_IFETCH_LEVEL_ACCUM, SQ_INSTS_VALU_FMA_F64, SQ_INSTS_VALU_MFMA_MOPS_I8, SQ_VMEM_WR_TA_DATA_FIFO_FULL, TA_ADDR_STALLED_BY_TC_CYCLES_sum, TA_FLAT_WAVEFRONTS_sum, TCC_EA0_RDREQ[0], TCC_EA0_RDREQ[100], TCC_EA0_RDREQ[101], TCC_EA0_RDREQ[102], TCC_EA0_RDREQ[103], TCC_EA0_RDREQ[104], TCC_EA0_RDREQ[105], TCC_EA0_RDREQ[106], TCC_EA0_RDREQ[107], TCC_EA0_RDREQ[108], TCC_EA0_RDREQ[109], TCC_EA0_RDREQ[10], TCC_EA0_RDREQ[110], TCC_EA0_RDREQ[111], TCC_EA0_RDREQ[112], TCC_EA0_RDREQ[113], TCC_EA0_RDREQ[114], TCC_EA0_RDREQ[115], TCC_EA0_RDREQ[116], TCC_EA0_RDREQ[117], TCC_EA0_RDREQ[118], TCC_EA0_RDREQ[119], TCC_EA0_RDREQ[11], TCC_EA0_RDREQ[120], TCC_EA0_RDREQ[121], TCC_EA0_RDREQ[122], TCC_EA0_RDREQ[123], TCC_EA0_RDREQ[124], TCC_EA0_RDREQ[125], TCC_EA0_RDREQ[126], TCC_EA0_RDREQ[127], TCC_EA0_RDREQ[12], TCC_EA0_RDREQ[13], TCC_EA0_RDREQ[14], TCC_EA0_RDREQ[15], TCC_EA0_RDREQ[16], TCC_EA0_RDREQ[17], TCC_EA0_RDREQ[18], TCC_EA0_RDREQ[19], TCC_EA0_RDREQ[1], TCC_EA0_RDREQ[20], TCC_EA0_RDREQ[21], TCC_EA0_RDREQ[22], TCC_EA0_RDREQ[23], TCC_EA0_RDREQ[24], TCC_EA0_RDREQ[25], TCC_EA0_RDREQ[26], TCC_EA0_RDREQ[27], TCC_EA0_RDREQ[28], TCC_EA0_RDREQ[29], TCC_EA0_RDREQ[2], TCC_EA0_RDREQ[30], TCC_EA0_RDREQ[31], TCC_EA0_RDREQ[32], TCC_EA0_RDREQ[33], TCC_EA0_RDREQ[34], TCC_EA0_RDREQ[35], TCC_EA0_RDREQ[36], TCC_EA0_RDREQ[37], TCC_EA0_RDREQ[38], TCC_EA0_RDREQ[39], TCC_EA0_RDREQ[3], TCC_EA0_RDREQ[40], TCC_EA0_RDREQ[41], TCC_EA0_RDREQ[42], TCC_EA0_RDREQ[43], TCC_EA0_RDREQ[44], TCC_EA0_RDREQ[45], TCC_EA0_RDREQ[46], TCC_EA0_RDREQ[47], TCC_EA0_RDREQ[48], TCC_EA0_RDREQ[49], TCC_EA0_RDREQ[4], TCC_EA0_RDREQ[50], TCC_EA0_RDREQ[51], TCC_EA0_RDREQ[52], TCC_EA0_RDREQ[53], TCC_EA0_RDREQ[54], TCC_EA0_RDREQ[55], TCC_EA0_RDREQ[56], TCC_EA0_RDREQ[57], TCC_EA0_RDREQ[58], TCC_EA0_RDREQ[59], TCC_EA0_RDREQ[5], TCC_EA0_RDREQ[60], TCC_EA0_RDREQ[61], TCC_EA0_RDREQ[62], TCC_EA0_RDREQ[63], TCC_EA0_RDREQ[64], TCC_EA0_RDREQ[65], TCC_EA0_RDREQ[66], TCC_EA0_RDREQ[67], TCC_EA0_RDREQ[68], TCC_EA0_RDREQ[69], TCC_EA0_RDREQ[6], TCC_EA0_RDREQ[70], TCC_EA0_RDREQ[71], TCC_EA0_RDREQ[72], TCC_EA0_RDREQ[73], TCC_EA0_RDREQ[74], TCC_EA0_RDREQ[75], TCC_EA0_RDREQ[76], TCC_EA0_RDREQ[77], TCC_EA0_RDREQ[78], TCC_EA0_RDREQ[79], TCC_EA0_RDREQ[7], TCC_EA0_RDREQ[80], TCC_EA0_RDREQ[81], TCC_EA0_RDREQ[82], TCC_EA0_RDREQ[83], TCC_EA0_RDREQ[84], TCC_EA0_RDREQ[85], TCC_EA0_RDREQ[86], TCC_EA0_RDREQ[87], TCC_EA0_RDREQ[88], TCC_EA0_RDREQ[89], TCC_EA0_RDREQ[8], TCC_EA0_RDREQ[90], TCC_EA0_RDREQ[91], TCC_EA0_RDREQ[92], TCC_EA0_RDREQ[93], TCC_EA0_RDREQ[94], TCC_EA0_RDREQ[95], TCC_EA0_RDREQ[96], TCC_EA0_RDREQ[97], TCC_EA0_RDREQ[98], TCC_EA0_RDREQ[99], TCC_EA0_RDREQ[9], TCC_EA0_WRREQ_LEVEL[0], TCC_EA0_WRREQ_LEVEL[100], TCC_EA0_WRREQ_LEVEL[101], TCC_EA0_WRREQ_LEVEL[102], TCC_EA0_WRREQ_LEVEL[103], TCC_EA0_WRREQ_LEVEL[104], TCC_EA0_WRREQ_LEVEL[105], TCC_EA0_WRREQ_LEVEL[106], TCC_EA0_WRREQ_LEVEL[107], TCC_EA0_WRREQ_LEVEL[108], TCC_EA0_WRREQ_LEVEL[109], TCC_EA0_WRREQ_LEVEL[10], TCC_EA0_WRREQ_LEVEL[110], TCC_EA0_WRREQ_LEVEL[111], TCC_EA0_WRREQ_LEVEL[112], TCC_EA0_WRREQ_LEVEL[113], TCC_EA0_WRREQ_LEVEL[114], TCC_EA0_WRREQ_LEVEL[115], TCC_EA0_WRREQ_LEVEL[116], TCC_EA0_WRREQ_LEVEL[117], TCC_EA0_WRREQ_LEVEL[118], TCC_EA0_WRREQ_LEVEL[119], TCC_EA0_WRREQ_LEVEL[11], TCC_EA0_WRREQ_LEVEL[120], TCC_EA0_WRREQ_LEVEL[121], TCC_EA0_WRREQ_LEVEL[122], TCC_EA0_WRREQ_LEVEL[123], TCC_EA0_WRREQ_LEVEL[124], TCC_EA0_WRREQ_LEVEL[125], TCC_EA0_WRREQ_LEVEL[126], TCC_EA0_WRREQ_LEVEL[127], TCC_EA0_WRREQ_LEVEL[12], TCC_EA0_WRREQ_LEVEL[13], TCC_EA0_WRREQ_LEVEL[14], TCC_EA0_WRREQ_LEVEL[15], TCC_EA0_WRREQ_LEVEL[16], TCC_EA0_WRREQ_LEVEL[17], TCC_EA0_WRREQ_LEVEL[18], TCC_EA0_WRREQ_LEVEL[19], TCC_EA0_WRREQ_LEVEL[1], TCC_EA0_WRREQ_LEVEL[20], TCC_EA0_WRREQ_LEVEL[21], TCC_EA0_WRREQ_LEVEL[22], TCC_EA0_WRREQ_LEVEL[23], TCC_EA0_WRREQ_LEVEL[24], TCC_EA0_WRREQ_LEVEL[25], TCC_EA0_WRREQ_LEVEL[26], TCC_EA0_WRREQ_LEVEL[27], TCC_EA0_WRREQ_LEVEL[28], TCC_EA0_WRREQ_LEVEL[29], TCC_EA0_WRREQ_LEVEL[2], TCC_EA0_WRREQ_LEVEL[30], TCC_EA0_WRREQ_LEVEL[31], TCC_EA0_WRREQ_LEVEL[32], TCC_EA0_WRREQ_LEVEL[33], TCC_EA0_WRREQ_LEVEL[34], TCC_EA0_WRREQ_LEVEL[35], TCC_EA0_WRREQ_LEVEL[36], TCC_EA0_WRREQ_LEVEL[37], TCC_EA0_WRREQ_LEVEL[38], TCC_EA0_WRREQ_LEVEL[39], TCC_EA0_WRREQ_LEVEL[3], TCC_EA0_WRREQ_LEVEL[40], TCC_EA0_WRREQ_LEVEL[41], TCC_EA0_WRREQ_LEVEL[42], TCC_EA0_WRREQ_LEVEL[43], TCC_EA0_WRREQ_LEVEL[44], TCC_EA0_WRREQ_LEVEL[45], TCC_EA0_WRREQ_LEVEL[46], TCC_EA0_WRREQ_LEVEL[47], TCC_EA0_WRREQ_LEVEL[48], TCC_EA0_WRREQ_LEVEL[49], TCC_EA0_WRREQ_LEVEL[4], TCC_EA0_WRREQ_LEVEL[50], TCC_EA0_WRREQ_LEVEL[51], TCC_EA0_WRREQ_LEVEL[52], TCC_EA0_WRREQ_LEVEL[53], TCC_EA0_WRREQ_LEVEL[54], TCC_EA0_WRREQ_LEVEL[55], TCC_EA0_WRREQ_LEVEL[56], TCC_EA0_WRREQ_LEVEL[57], TCC_EA0_WRREQ_LEVEL[58], TCC_EA0_WRREQ_LEVEL[59], TCC_EA0_WRREQ_LEVEL[5], TCC_EA0_WRREQ_LEVEL[60], TCC_EA0_WRREQ_LEVEL[61], TCC_EA0_WRREQ_LEVEL[62], TCC_EA0_WRREQ_LEVEL[63], TCC_EA0_WRREQ_LEVEL[64], TCC_EA0_WRREQ_LEVEL[65], TCC_EA0_WRREQ_LEVEL[66], TCC_EA0_WRREQ_LEVEL[67], TCC_EA0_WRREQ_LEVEL[68], TCC_EA0_WRREQ_LEVEL[69], TCC_EA0_WRREQ_LEVEL[6], TCC_EA0_WRREQ_LEVEL[70], TCC_EA0_WRREQ_LEVEL[71], TCC_EA0_WRREQ_LEVEL[72], TCC_EA0_WRREQ_LEVEL[73], TCC_EA0_WRREQ_LEVEL[74], TCC_EA0_WRREQ_LEVEL[75], TCC_EA0_WRREQ_LEVEL[76], TCC_EA0_WRREQ_LEVEL[77], TCC_EA0_WRREQ_LEVEL[78], TCC_EA0_WRREQ_LEVEL[79], TCC_EA0_WRREQ_LEVEL[7], TCC_EA0_WRREQ_LEVEL[80], TCC_EA0_WRREQ_LEVEL[81], TCC_EA0_WRREQ_LEVEL[82], TCC_EA0_WRREQ_LEVEL[83], TCC_EA0_WRREQ_LEVEL[84], TCC_EA0_WRREQ_LEVEL[85], TCC_EA0_WRREQ_LEVEL[86], TCC_EA0_WRREQ_LEVEL[87], TCC_EA0_WRREQ_LEVEL[88], TCC_EA0_WRREQ_LEVEL[89], TCC_EA0_WRREQ_LEVEL[8], TCC_EA0_WRREQ_LEVEL[90], TCC_EA0_WRREQ_LEVEL[91], TCC_EA0_WRREQ_LEVEL[92], TCC_EA0_WRREQ_LEVEL[93], TCC_EA0_WRREQ_LEVEL[94], TCC_EA0_WRREQ_LEVEL[95], TCC_EA0_WRREQ_LEVEL[96], TCC_EA0_WRREQ_LEVEL[97], TCC_EA0_WRREQ_LEVEL[98], TCC_EA0_WRREQ_LEVEL[99], TCC_EA0_WRREQ_LEVEL[9], TCC_NC_REQ_sum, TCC_REQ[0], TCC_REQ[100], TCC_REQ[101], TCC_REQ[102], TCC_REQ[103], TCC_REQ[104], TCC_REQ[105], TCC_REQ[106], TCC_REQ[107], TCC_REQ[108], TCC_REQ[109], TCC_REQ[10], TCC_REQ[110], TCC_REQ[111], TCC_REQ[112], TCC_REQ[113], TCC_REQ[114], TCC_REQ[115], TCC_REQ[116], TCC_REQ[117], TCC_REQ[118], TCC_REQ[119], TCC_REQ[11], TCC_REQ[120], TCC_REQ[121], TCC_REQ[122], TCC_REQ[123], TCC_REQ[124], TCC_REQ[125], TCC_REQ[126], TCC_REQ[127], TCC_REQ[12], TCC_REQ[13], TCC_REQ[14], TCC_REQ[15], TCC_REQ[16], TCC_REQ[17], TCC_REQ[18], TCC_REQ[19], TCC_REQ[1], TCC_REQ[20], TCC_REQ[21], TCC_REQ[22], TCC_REQ[23], TCC_REQ[24], TCC_REQ[25], TCC_REQ[26], TCC_REQ[27], TCC_REQ[28], TCC_REQ[29], TCC_REQ[2], TCC_REQ[30], TCC_REQ[31], TCC_REQ[32], TCC_REQ[33], TCC_REQ[34], TCC_REQ[35], TCC_REQ[36], TCC_REQ[37], TCC_REQ[38], TCC_REQ[39], TCC_REQ[3], TCC_REQ[40], TCC_REQ[41], TCC_REQ[42], TCC_REQ[43], TCC_REQ[44], TCC_REQ[45], TCC_REQ[46], TCC_REQ[47], TCC_REQ[48], TCC_REQ[49], TCC_REQ[4], TCC_REQ[50], TCC_REQ[51], TCC_REQ[52], TCC_REQ[53], TCC_REQ[54], TCC_REQ[55], TCC_REQ[56], TCC_REQ[57], TCC_REQ[58], TCC_REQ[59], TCC_REQ[5], TCC_REQ[60], TCC_REQ[61], TCC_REQ[62], TCC_REQ[63], TCC_REQ[64], TCC_REQ[65], TCC_REQ[66], TCC_REQ[67], TCC_REQ[68], TCC_REQ[69], TCC_REQ[6], TCC_REQ[70], TCC_REQ[71], TCC_REQ[72], TCC_REQ[73], TCC_REQ[74], TCC_REQ[75], TCC_REQ[76], TCC_REQ[77], TCC_REQ[78], TCC_REQ[79], TCC_REQ[7], TCC_REQ[80], TCC_REQ[81], TCC_REQ[82], TCC_REQ[83], TCC_REQ[84], TCC_REQ[85], TCC_REQ[86], TCC_REQ[87], TCC_REQ[88], TCC_REQ[89], TCC_REQ[8], TCC_REQ[90], TCC_REQ[91], TCC_REQ[92], TCC_REQ[93], TCC_REQ[94], TCC_REQ[95], TCC_REQ[96], TCC_REQ[97], TCC_REQ[98], TCC_REQ[99], TCC_REQ[9], TCP_GATE_EN1_sum, TCP_TCC_NC_ATOMIC_REQ_sum, TCP_TCC_RW_ATOMIC_REQ_sum, TCP_TOTAL_WRITE_sum, TD_ATOMIC_WAVEFRONT_sum, TD_TC_STALL_sum]. Found: [CPC_ME1_BUSY_FOR_PACKET_DECODE, CPC_SYNC_WRREQ_FIFO_BUSY, CPF_CMP_UTCL1_STALL_ON_TRANSLATION, CPF_CPF_STAT_BUSY, GRBM_GUI_ACTIVE, SPI_CS0_WAVE, SPI_CS1_WAVE, SPI_CS2_WAVE, SPI_CS3_WAVE, SQC_DCACHE_HITS, SQC_ICACHE_MISSES, SQC_ICACHE_MISSES_DUPLICATE, SQ_IFETCH_LEVEL, SQ_INSTS_VALU_FMA_F64, SQ_INSTS_VALU_MFMA_MOPS_I8, SQ_VMEM_WR_TA_DATA_FIFO_FULL, TA_ADDR_STALLED_BY_TC_CYCLES_sum, TA_FLAT_WAVEFRONTS_sum, TCC_EA0_RDREQ[0], TCC_EA0_RDREQ[100], TCC_EA0_RDREQ[101], TCC_EA0_RDREQ[102], TCC_EA0_RDREQ[103], TCC_EA0_RDREQ[104], TCC_EA0_RDREQ[105], TCC_EA0_RDREQ[106], TCC_EA0_RDREQ[107], TCC_EA0_RDREQ[108], TCC_EA0_RDREQ[109], TCC_EA0_RDREQ[10], TCC_EA0_RDREQ[110], TCC_EA0_RDREQ[111], TCC_EA0_RDREQ[112], TCC_EA0_RDREQ[113], TCC_EA0_RDREQ[114], TCC_EA0_RDREQ[115], TCC_EA0_RDREQ[116], TCC_EA0_RDREQ[117], TCC_EA0_RDREQ[118], TCC_EA0_RDREQ[119], TCC_EA0_RDREQ[11], TCC_EA0_RDREQ[120], TCC_EA0_RDREQ[121], TCC_EA0_RDREQ[122], TCC_EA0_RDREQ[123], TCC_EA0_RDREQ[124], TCC_EA0_RDREQ[125], TCC_EA0_RDREQ[126], TCC_EA0_RDREQ[127], TCC_EA0_RDREQ[12], TCC_EA0_RDREQ[13], TCC_EA0_RDREQ[14], TCC_EA0_RDREQ[15], TCC_EA0_RDREQ[16], TCC_EA0_RDREQ[17], TCC_EA0_RDREQ[18], TCC_EA0_RDREQ[19], TCC_EA0_RDREQ[1], TCC_EA0_RDREQ[20], TCC_EA0_RDREQ[21], TCC_EA0_RDREQ[22], TCC_EA0_RDREQ[23], TCC_EA0_RDREQ[24], TCC_EA0_RDREQ[25], TCC_EA0_RDREQ[26], TCC_EA0_RDREQ[27], TCC_EA0_RDREQ[28], TCC_EA0_RDREQ[29], TCC_EA0_RDREQ[2], TCC_EA0_RDREQ[30], TCC_EA0_RDREQ[31], TCC_EA0_RDREQ[32], TCC_EA0_RDREQ[33], TCC_EA0_RDREQ[34], TCC_EA0_RDREQ[35], TCC_EA0_RDREQ[36], TCC_EA0_RDREQ[37], TCC_EA0_RDREQ[38], TCC_EA0_RDREQ[39], TCC_EA0_RDREQ[3], TCC_EA0_RDREQ[40], TCC_EA0_RDREQ[41], TCC_EA0_RDREQ[42], TCC_EA0_RDREQ[43], TCC_EA0_RDREQ[44], TCC_EA0_RDREQ[45], TCC_EA0_RDREQ[46], TCC_EA0_RDREQ[47], TCC_EA0_RDREQ[48], TCC_EA0_RDREQ[49], TCC_EA0_RDREQ[4], TCC_EA0_RDREQ[50], TCC_EA0_RDREQ[51], TCC_EA0_RDREQ[52], TCC_EA0_RDREQ[53], TCC_EA0_RDREQ[54], TCC_EA0_RDREQ[55], TCC_EA0_RDREQ[56], TCC_EA0_RDREQ[57], TCC_EA0_RDREQ[58], TCC_EA0_RDREQ[59], TCC_EA0_RDREQ[5], TCC_EA0_RDREQ[60], TCC_EA0_RDREQ[61], TCC_EA0_RDREQ[62], TCC_EA0_RDREQ[63], TCC_EA0_RDREQ[64], TCC_EA0_RDREQ[65], TCC_EA0_RDREQ[66], TCC_EA0_RDREQ[67], TCC_EA0_RDREQ[68], TCC_EA0_RDREQ[69], TCC_EA0_RDREQ[6], TCC_EA0_RDREQ[70], TCC_EA0_RDREQ[71], TCC_EA0_RDREQ[72], TCC_EA0_RDREQ[73], TCC_EA0_RDREQ[74], TCC_EA0_RDREQ[75], TCC_EA0_RDREQ[76], TCC_EA0_RDREQ[77], TCC_EA0_RDREQ[78], TCC_EA0_RDREQ[79], TCC_EA0_RDREQ[7], TCC_EA0_RDREQ[80], TCC_EA0_RDREQ[81], TCC_EA0_RDREQ[82], TCC_EA0_RDREQ[83], TCC_EA0_RDREQ[84], TCC_EA0_RDREQ[85], TCC_EA0_RDREQ[86], TCC_EA0_RDREQ[87], TCC_EA0_RDREQ[88], TCC_EA0_RDREQ[89], TCC_EA0_RDREQ[8], TCC_EA0_RDREQ[90], TCC_EA0_RDREQ[91], TCC_EA0_RDREQ[92], TCC_EA0_RDREQ[93], TCC_EA0_RDREQ[94], TCC_EA0_RDREQ[95], TCC_EA0_RDREQ[96], TCC_EA0_RDREQ[97], TCC_EA0_RDREQ[98], TCC_EA0_RDREQ[99], TCC_EA0_RDREQ[9], TCC_EA0_WRREQ_LEVEL[0], TCC_EA0_WRREQ_LEVEL[100], TCC_EA0_WRREQ_LEVEL[101], TCC_EA0_WRREQ_LEVEL[102], TCC_EA0_WRREQ_LEVEL[103], TCC_EA0_WRREQ_LEVEL[104], TCC_EA0_WRREQ_LEVEL[105], TCC_EA0_WRREQ_LEVEL[106], TCC_EA0_WRREQ_LEVEL[107], TCC_EA0_WRREQ_LEVEL[108], TCC_EA0_WRREQ_LEVEL[109], TCC_EA0_WRREQ_LEVEL[10], TCC_EA0_WRREQ_LEVEL[110], TCC_EA0_WRREQ_LEVEL[111], TCC_EA0_WRREQ_LEVEL[112], TCC_EA0_WRREQ_LEVEL[113], TCC_EA0_WRREQ_LEVEL[114], TCC_EA0_WRREQ_LEVEL[115], TCC_EA0_WRREQ_LEVEL[116], TCC_EA0_WRREQ_LEVEL[117], TCC_EA0_WRREQ_LEVEL[118], TCC_EA0_WRREQ_LEVEL[119], TCC_EA0_WRREQ_LEVEL[11], TCC_EA0_WRREQ_LEVEL[120], TCC_EA0_WRREQ_LEVEL[121], TCC_EA0_WRREQ_LEVEL[122], TCC_EA0_WRREQ_LEVEL[123], TCC_EA0_WRREQ_LEVEL[124], TCC_EA0_WRREQ_LEVEL[125], TCC_EA0_WRREQ_LEVEL[126], TCC_EA0_WRREQ_LEVEL[127], TCC_EA0_WRREQ_LEVEL[12], TCC_EA0_WRREQ_LEVEL[13], TCC_EA0_WRREQ_LEVEL[14], TCC_EA0_WRREQ_LEVEL[15], TCC_EA0_WRREQ_LEVEL[16], TCC_EA0_WRREQ_LEVEL[17], TCC_EA0_WRREQ_LEVEL[18], TCC_EA0_WRREQ_LEVEL[19], TCC_EA0_WRREQ_LEVEL[1], TCC_EA0_WRREQ_LEVEL[20], TCC_EA0_WRREQ_LEVEL[21], TCC_EA0_WRREQ_LEVEL[22], TCC_EA0_WRREQ_LEVEL[23], TCC_EA0_WRREQ_LEVEL[24], TCC_EA0_WRREQ_LEVEL[25], TCC_EA0_WRREQ_LEVEL[26], TCC_EA0_WRREQ_LEVEL[27], TCC_EA0_WRREQ_LEVEL[28], TCC_EA0_WRREQ_LEVEL[29], TCC_EA0_WRREQ_LEVEL[2], TCC_EA0_WRREQ_LEVEL[30], TCC_EA0_WRREQ_LEVEL[31], TCC_EA0_WRREQ_LEVEL[32], TCC_EA0_WRREQ_LEVEL[33], TCC_EA0_WRREQ_LEVEL[34], TCC_EA0_WRREQ_LEVEL[35], TCC_EA0_WRREQ_LEVEL[36], TCC_EA0_WRREQ_LEVEL[37], TCC_EA0_WRREQ_LEVEL[38], TCC_EA0_WRREQ_LEVEL[39], TCC_EA0_WRREQ_LEVEL[3], TCC_EA0_WRREQ_LEVEL[40], TCC_EA0_WRREQ_LEVEL[41], TCC_EA0_WRREQ_LEVEL[42], TCC_EA0_WRREQ_LEVEL[43], TCC_EA0_WRREQ_LEVEL[44], TCC_EA0_WRREQ_LEVEL[45], TCC_EA0_WRREQ_LEVEL[46], TCC_EA0_WRREQ_LEVEL[47], TCC_EA0_WRREQ_LEVEL[48], TCC_EA0_WRREQ_LEVEL[49], TCC_EA0_WRREQ_LEVEL[4], TCC_EA0_WRREQ_LEVEL[50], TCC_EA0_WRREQ_LEVEL[51], TCC_EA0_WRREQ_LEVEL[52], TCC_EA0_WRREQ_LEVEL[53], TCC_EA0_WRREQ_LEVEL[54], TCC_EA0_WRREQ_LEVEL[55], TCC_EA0_WRREQ_LEVEL[56], TCC_EA0_WRREQ_LEVEL[57], TCC_EA0_WRREQ_LEVEL[58], TCC_EA0_WRREQ_LEVEL[59], TCC_EA0_WRREQ_LEVEL[5], TCC_EA0_WRREQ_LEVEL[60], TCC_EA0_WRREQ_LEVEL[61], TCC_EA0_WRREQ_LEVEL[62], TCC_EA0_WRREQ_LEVEL[63], TCC_EA0_WRREQ_LEVEL[64], TCC_EA0_WRREQ_LEVEL[65], TCC_EA0_WRREQ_LEVEL[66], TCC_EA0_WRREQ_LEVEL[67], TCC_EA0_WRREQ_LEVEL[68], TCC_EA0_WRREQ_LEVEL[69], TCC_EA0_WRREQ_LEVEL[6], TCC_EA0_WRREQ_LEVEL[70], TCC_EA0_WRREQ_LEVEL[71], TCC_EA0_WRREQ_LEVEL[72], TCC_EA0_WRREQ_LEVEL[73], TCC_EA0_WRREQ_LEVEL[74], TCC_EA0_WRREQ_LEVEL[75], TCC_EA0_WRREQ_LEVEL[76], TCC_EA0_WRREQ_LEVEL[77], TCC_EA0_WRREQ_LEVEL[78], TCC_EA0_WRREQ_LEVEL[79], TCC_EA0_WRREQ_LEVEL[7], TCC_EA0_WRREQ_LEVEL[80], TCC_EA0_WRREQ_LEVEL[81], TCC_EA0_WRREQ_LEVEL[82], TCC_EA0_WRREQ_LEVEL[83], TCC_EA0_WRREQ_LEVEL[84], TCC_EA0_WRREQ_LEVEL[85], TCC_EA0_WRREQ_LEVEL[86], TCC_EA0_WRREQ_LEVEL[87], TCC_EA0_WRREQ_LEVEL[88], TCC_EA0_WRREQ_LEVEL[89], TCC_EA0_WRREQ_LEVEL[8], TCC_EA0_WRREQ_LEVEL[90], TCC_EA0_WRREQ_LEVEL[91], TCC_EA0_WRREQ_LEVEL[92], TCC_EA0_WRREQ_LEVEL[93], TCC_EA0_WRREQ_LEVEL[94], TCC_EA0_WRREQ_LEVEL[95], TCC_EA0_WRREQ_LEVEL[96], TCC_EA0_WRREQ_LEVEL[97], TCC_EA0_WRREQ_LEVEL[98], TCC_EA0_WRREQ_LEVEL[99], TCC_EA0_WRREQ_LEVEL[9], TCC_NC_REQ_sum, TCC_REQ[0], TCC_REQ[100], TCC_REQ[101], TCC_REQ[102], TCC_REQ[103], TCC_REQ[104], TCC_REQ[105], TCC_REQ[106], TCC_REQ[107], TCC_REQ[108], TCC_REQ[109], TCC_REQ[10], TCC_REQ[110], TCC_REQ[111], TCC_REQ[112], TCC_REQ[113], TCC_REQ[114], TCC_REQ[115], TCC_REQ[116], TCC_REQ[117], TCC_REQ[118], TCC_REQ[119], TCC_REQ[11], TCC_REQ[120], TCC_REQ[121], TCC_REQ[122], TCC_REQ[123], TCC_REQ[124], TCC_REQ[125], TCC_REQ[126], TCC_REQ[127], TCC_REQ[12], TCC_REQ[13], TCC_REQ[14], TCC_REQ[15], TCC_REQ[16], TCC_REQ[17], TCC_REQ[18], TCC_REQ[19], TCC_REQ[1], TCC_REQ[20], TCC_REQ[21], TCC_REQ[22], TCC_REQ[23], TCC_REQ[24], TCC_REQ[25], TCC_REQ[26], TCC_REQ[27], TCC_REQ[28], TCC_REQ[29], TCC_REQ[2], TCC_REQ[30], TCC_REQ[31], TCC_REQ[32], TCC_REQ[33], TCC_REQ[34], TCC_REQ[35], TCC_REQ[36], TCC_REQ[37], TCC_REQ[38], TCC_REQ[39], TCC_REQ[3], TCC_REQ[40], TCC_REQ[41], TCC_REQ[42], TCC_REQ[43], TCC_REQ[44], TCC_REQ[45], TCC_REQ[46], TCC_REQ[47], TCC_REQ[48], TCC_REQ[49], TCC_REQ[4], TCC_REQ[50], TCC_REQ[51], TCC_REQ[52], TCC_REQ[53], TCC_REQ[54], TCC_REQ[55], TCC_REQ[56], TCC_REQ[57], TCC_REQ[58], TCC_REQ[59], TCC_REQ[5], TCC_REQ[60], TCC_REQ[61], TCC_REQ[62], TCC_REQ[63], TCC_REQ[64], TCC_REQ[65], TCC_REQ[66], TCC_REQ[67], TCC_REQ[68], TCC_REQ[69], TCC_REQ[6], TCC_REQ[70], TCC_REQ[71], TCC_REQ[72], TCC_REQ[73], TCC_REQ[74], TCC_REQ[75], TCC_REQ[76], TCC_REQ[77], TCC_REQ[78], TCC_REQ[79], TCC_REQ[7], TCC_REQ[80], TCC_REQ[81], TCC_REQ[82], TCC_REQ[83], TCC_REQ[84], TCC_REQ[85], TCC_REQ[86], TCC_REQ[87], TCC_REQ[88], TCC_REQ[89], TCC_REQ[8], TCC_REQ[90], TCC_REQ[91], TCC_REQ[92], TCC_REQ[93], TCC_REQ[94], TCC_REQ[95], TCC_REQ[96], TCC_REQ[97], TCC_REQ[98], TCC_REQ[99], TCC_REQ[9], TCP_GATE_EN1_sum, TCP_TCC_NC_ATOMIC_REQ_sum, TCP_TCC_RW_ATOMIC_REQ_sum, TCP_TOTAL_WRITE_sum, TD_ATOMIC_WAVEFRONT_sum, TD_TC_STALL_sum] + |-> [rocprofv3] E20250328 22:43:59.489465 140180820113408 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15737_kernel_trace.csv + |-> [rocprofv3] E20250328 22:43:59.496185 140180820113408 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15737_counter_collection.csv + |-> [rocprofv3] E20250328 22:43:59.499819 140180820113408 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15737_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.txt, the time it takes was 0 m 0.5342490673065186 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.txt is 0 m 0.5495765209197998 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.txt +pmc file: SQ_INST_LEVEL_LDS.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.yaml -i /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] W20250328 22:44:00.019005 139673533200384 tool.cpp:930] Unable to find all counters for agent 1 (gpu-0, gfx950) in [CPC_CPC_TCIU_BUSY, CPC_ME1_DC0_SPI_BUSY, SPI_RA_REQ_NO_ALLOC_CSN, SPI_VWC0_VDATA_VALID_WR, SQC_DCACHE_ATOMIC, SQC_DCACHE_MISSES, SQC_ICACHE_REQ, SQC_TC_STALL, SQ_INSTS_VALU_MUL_F16, SQ_INST_LEVEL_LDS, SQ_INST_LEVEL_LDS_ACCUM, SQ_WAVES_SAVED, TA_BUFFER_WRITE_WAVEFRONTS_sum, TA_TA_BUSY_sum, TCC_ATOMIC_sum, TCC_EA0_ATOMIC_LEVEL_sum, TCC_EA0_WRREQ_sum, TCC_TOO_MANY_EA_WRREQS_STALL_sum, TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum, TCP_TCC_ATOMIC_WITH_RET_REQ_sum, TCP_TOTAL_WRITEBACK_INVALIDATES_sum, TCP_UTCL1_REQUEST_sum]. Found: [CPC_CPC_TCIU_BUSY, CPC_ME1_DC0_SPI_BUSY, SPI_RA_REQ_NO_ALLOC_CSN, SPI_VWC0_VDATA_VALID_WR, SQC_DCACHE_ATOMIC, SQC_DCACHE_MISSES, SQC_ICACHE_REQ, SQC_TC_STALL, SQ_INSTS_VALU_MUL_F16, SQ_INST_LEVEL_LDS, SQ_WAVES_SAVED, TA_BUFFER_WRITE_WAVEFRONTS_sum, TA_TA_BUSY_sum, TCC_ATOMIC_sum, TCC_EA0_ATOMIC_LEVEL_sum, TCC_EA0_WRREQ_sum, TCC_TOO_MANY_EA_WRREQS_STALL_sum, TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum, TCP_TCC_ATOMIC_WITH_RET_REQ_sum, TCP_TOTAL_WRITEBACK_INVALIDATES_sum, TCP_UTCL1_REQUEST_sum] + |-> [rocprofv3] E20250328 22:44:00.029844 139673533200384 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15744_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:00.036337 139673533200384 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15744_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:00.039437 139673533200384 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15744_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.txt, the time it takes was 0 m 0.5213537216186523 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.txt is 0 m 0.530348539352417 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt +pmc file: SQ_INST_LEVEL_SMEM.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.yaml -i /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] W20250328 22:44:00.560194 140472799942656 tool.cpp:930] Unable to find all counters for agent 1 (gpu-0, gfx950) in [CPC_CPC_STAT_BUSY, CPC_CPC_STAT_IDLE, CPF_CPF_STAT_IDLE, CPF_CPF_STAT_STALL, SPI_CSQ_P0_OCCUPANCY, SPI_CSQ_P1_OCCUPANCY, SPI_CSQ_P2_OCCUPANCY, SPI_CSQ_P3_OCCUPANCY, SPI_RA_SGPR_SIMD_FULL_CSN, SQC_DCACHE_REQ_READ_16, SQ_BUSY_CU_CYCLES, SQ_INSTS_LDS_LOAD, SQ_INSTS_LDS_STORE, SQ_INSTS_VALU_MUL_F64, SQ_INST_LEVEL_SMEM, SQ_INST_LEVEL_SMEM_ACCUM, SQ_LDS_CMD_FIFO_FULL, TA_BUFFER_TOTAL_CYCLES_sum, TA_FLAT_READ_WAVEFRONTS_sum, TCC_ATOMIC[0], TCC_ATOMIC[100], TCC_ATOMIC[101], TCC_ATOMIC[102], TCC_ATOMIC[103], TCC_ATOMIC[104], TCC_ATOMIC[105], TCC_ATOMIC[106], TCC_ATOMIC[107], TCC_ATOMIC[108], TCC_ATOMIC[109], TCC_ATOMIC[10], TCC_ATOMIC[110], TCC_ATOMIC[111], TCC_ATOMIC[112], TCC_ATOMIC[113], TCC_ATOMIC[114], TCC_ATOMIC[115], TCC_ATOMIC[116], TCC_ATOMIC[117], TCC_ATOMIC[118], TCC_ATOMIC[119], TCC_ATOMIC[11], TCC_ATOMIC[120], TCC_ATOMIC[121], TCC_ATOMIC[122], TCC_ATOMIC[123], TCC_ATOMIC[124], TCC_ATOMIC[125], TCC_ATOMIC[126], TCC_ATOMIC[127], TCC_ATOMIC[12], TCC_ATOMIC[13], TCC_ATOMIC[14], TCC_ATOMIC[15], TCC_ATOMIC[16], TCC_ATOMIC[17], TCC_ATOMIC[18], TCC_ATOMIC[19], TCC_ATOMIC[1], TCC_ATOMIC[20], TCC_ATOMIC[21], TCC_ATOMIC[22], TCC_ATOMIC[23], TCC_ATOMIC[24], TCC_ATOMIC[25], TCC_ATOMIC[26], TCC_ATOMIC[27], TCC_ATOMIC[28], TCC_ATOMIC[29], TCC_ATOMIC[2], TCC_ATOMIC[30], TCC_ATOMIC[31], TCC_ATOMIC[32], TCC_ATOMIC[33], TCC_ATOMIC[34], TCC_ATOMIC[35], TCC_ATOMIC[36], TCC_ATOMIC[37], TCC_ATOMIC[38], TCC_ATOMIC[39], TCC_ATOMIC[3], TCC_ATOMIC[40], TCC_ATOMIC[41], TCC_ATOMIC[42], TCC_ATOMIC[43], TCC_ATOMIC[44], TCC_ATOMIC[45], TCC_ATOMIC[46], TCC_ATOMIC[47], TCC_ATOMIC[48], TCC_ATOMIC[49], TCC_ATOMIC[4], TCC_ATOMIC[50], TCC_ATOMIC[51], TCC_ATOMIC[52], TCC_ATOMIC[53], TCC_ATOMIC[54], TCC_ATOMIC[55], TCC_ATOMIC[56], TCC_ATOMIC[57], TCC_ATOMIC[58], TCC_ATOMIC[59], TCC_ATOMIC[5], TCC_ATOMIC[60], TCC_ATOMIC[61], TCC_ATOMIC[62], TCC_ATOMIC[63], TCC_ATOMIC[64], TCC_ATOMIC[65], TCC_ATOMIC[66], TCC_ATOMIC[67], TCC_ATOMIC[68], TCC_ATOMIC[69], TCC_ATOMIC[6], TCC_ATOMIC[70], TCC_ATOMIC[71], TCC_ATOMIC[72], TCC_ATOMIC[73], TCC_ATOMIC[74], TCC_ATOMIC[75], TCC_ATOMIC[76], TCC_ATOMIC[77], TCC_ATOMIC[78], TCC_ATOMIC[79], TCC_ATOMIC[7], TCC_ATOMIC[80], TCC_ATOMIC[81], TCC_ATOMIC[82], TCC_ATOMIC[83], TCC_ATOMIC[84], TCC_ATOMIC[85], TCC_ATOMIC[86], TCC_ATOMIC[87], TCC_ATOMIC[88], TCC_ATOMIC[89], TCC_ATOMIC[8], TCC_ATOMIC[90], TCC_ATOMIC[91], TCC_ATOMIC[92], TCC_ATOMIC[93], TCC_ATOMIC[94], TCC_ATOMIC[95], TCC_ATOMIC[96], TCC_ATOMIC[97], TCC_ATOMIC[98], TCC_ATOMIC[99], TCC_ATOMIC[9], TCC_BUBBLE[0], TCC_BUBBLE[100], TCC_BUBBLE[101], TCC_BUBBLE[102], TCC_BUBBLE[103], TCC_BUBBLE[104], TCC_BUBBLE[105], TCC_BUBBLE[106], TCC_BUBBLE[107], TCC_BUBBLE[108], TCC_BUBBLE[109], TCC_BUBBLE[10], TCC_BUBBLE[110], TCC_BUBBLE[111], TCC_BUBBLE[112], TCC_BUBBLE[113], TCC_BUBBLE[114], TCC_BUBBLE[115], TCC_BUBBLE[116], TCC_BUBBLE[117], TCC_BUBBLE[118], TCC_BUBBLE[119], TCC_BUBBLE[11], TCC_BUBBLE[120], TCC_BUBBLE[121], TCC_BUBBLE[122], TCC_BUBBLE[123], TCC_BUBBLE[124], TCC_BUBBLE[125], TCC_BUBBLE[126], TCC_BUBBLE[127], TCC_BUBBLE[12], TCC_BUBBLE[13], TCC_BUBBLE[14], TCC_BUBBLE[15], TCC_BUBBLE[16], TCC_BUBBLE[17], TCC_BUBBLE[18], TCC_BUBBLE[19], TCC_BUBBLE[1], TCC_BUBBLE[20], TCC_BUBBLE[21], TCC_BUBBLE[22], TCC_BUBBLE[23], TCC_BUBBLE[24], TCC_BUBBLE[25], TCC_BUBBLE[26], TCC_BUBBLE[27], TCC_BUBBLE[28], TCC_BUBBLE[29], TCC_BUBBLE[2], TCC_BUBBLE[30], TCC_BUBBLE[31], TCC_BUBBLE[32], TCC_BUBBLE[33], TCC_BUBBLE[34], TCC_BUBBLE[35], TCC_BUBBLE[36], TCC_BUBBLE[37], TCC_BUBBLE[38], TCC_BUBBLE[39], TCC_BUBBLE[3], TCC_BUBBLE[40], TCC_BUBBLE[41], TCC_BUBBLE[42], TCC_BUBBLE[43], TCC_BUBBLE[44], TCC_BUBBLE[45], TCC_BUBBLE[46], TCC_BUBBLE[47], TCC_BUBBLE[48], TCC_BUBBLE[49], TCC_BUBBLE[4], TCC_BUBBLE[50], TCC_BUBBLE[51], TCC_BUBBLE[52], TCC_BUBBLE[53], TCC_BUBBLE[54], TCC_BUBBLE[55], TCC_BUBBLE[56], TCC_BUBBLE[57], TCC_BUBBLE[58], TCC_BUBBLE[59], TCC_BUBBLE[5], TCC_BUBBLE[60], TCC_BUBBLE[61], TCC_BUBBLE[62], TCC_BUBBLE[63], TCC_BUBBLE[64], TCC_BUBBLE[65], TCC_BUBBLE[66], TCC_BUBBLE[67], TCC_BUBBLE[68], TCC_BUBBLE[69], TCC_BUBBLE[6], TCC_BUBBLE[70], TCC_BUBBLE[71], TCC_BUBBLE[72], TCC_BUBBLE[73], TCC_BUBBLE[74], TCC_BUBBLE[75], TCC_BUBBLE[76], TCC_BUBBLE[77], TCC_BUBBLE[78], TCC_BUBBLE[79], TCC_BUBBLE[7], TCC_BUBBLE[80], TCC_BUBBLE[81], TCC_BUBBLE[82], TCC_BUBBLE[83], TCC_BUBBLE[84], TCC_BUBBLE[85], TCC_BUBBLE[86], TCC_BUBBLE[87], TCC_BUBBLE[88], TCC_BUBBLE[89], TCC_BUBBLE[8], TCC_BUBBLE[90], TCC_BUBBLE[91], TCC_BUBBLE[92], TCC_BUBBLE[93], TCC_BUBBLE[94], TCC_BUBBLE[95], TCC_BUBBLE[96], TCC_BUBBLE[97], TCC_BUBBLE[98], TCC_BUBBLE[99], TCC_BUBBLE[9], TCC_EA0_ATOMIC[0], TCC_EA0_ATOMIC[100], TCC_EA0_ATOMIC[101], TCC_EA0_ATOMIC[102], TCC_EA0_ATOMIC[103], TCC_EA0_ATOMIC[104], TCC_EA0_ATOMIC[105], TCC_EA0_ATOMIC[106], TCC_EA0_ATOMIC[107], TCC_EA0_ATOMIC[108], TCC_EA0_ATOMIC[109], TCC_EA0_ATOMIC[10], TCC_EA0_ATOMIC[110], TCC_EA0_ATOMIC[111], TCC_EA0_ATOMIC[112], TCC_EA0_ATOMIC[113], TCC_EA0_ATOMIC[114], TCC_EA0_ATOMIC[115], TCC_EA0_ATOMIC[116], TCC_EA0_ATOMIC[117], TCC_EA0_ATOMIC[118], TCC_EA0_ATOMIC[119], TCC_EA0_ATOMIC[11], TCC_EA0_ATOMIC[120], TCC_EA0_ATOMIC[121], TCC_EA0_ATOMIC[122], TCC_EA0_ATOMIC[123], TCC_EA0_ATOMIC[124], TCC_EA0_ATOMIC[125], TCC_EA0_ATOMIC[126], TCC_EA0_ATOMIC[127], TCC_EA0_ATOMIC[12], TCC_EA0_ATOMIC[13], TCC_EA0_ATOMIC[14], TCC_EA0_ATOMIC[15], TCC_EA0_ATOMIC[16], TCC_EA0_ATOMIC[17], TCC_EA0_ATOMIC[18], TCC_EA0_ATOMIC[19], TCC_EA0_ATOMIC[1], TCC_EA0_ATOMIC[20], TCC_EA0_ATOMIC[21], TCC_EA0_ATOMIC[22], TCC_EA0_ATOMIC[23], TCC_EA0_ATOMIC[24], TCC_EA0_ATOMIC[25], TCC_EA0_ATOMIC[26], TCC_EA0_ATOMIC[27], TCC_EA0_ATOMIC[28], TCC_EA0_ATOMIC[29], TCC_EA0_ATOMIC[2], TCC_EA0_ATOMIC[30], TCC_EA0_ATOMIC[31], TCC_EA0_ATOMIC[32], TCC_EA0_ATOMIC[33], TCC_EA0_ATOMIC[34], TCC_EA0_ATOMIC[35], TCC_EA0_ATOMIC[36], TCC_EA0_ATOMIC[37], TCC_EA0_ATOMIC[38], TCC_EA0_ATOMIC[39], TCC_EA0_ATOMIC[3], TCC_EA0_ATOMIC[40], TCC_EA0_ATOMIC[41], TCC_EA0_ATOMIC[42], TCC_EA0_ATOMIC[43], TCC_EA0_ATOMIC[44], TCC_EA0_ATOMIC[45], TCC_EA0_ATOMIC[46], TCC_EA0_ATOMIC[47], TCC_EA0_ATOMIC[48], TCC_EA0_ATOMIC[49], TCC_EA0_ATOMIC[4], TCC_EA0_ATOMIC[50], TCC_EA0_ATOMIC[51], TCC_EA0_ATOMIC[52], TCC_EA0_ATOMIC[53], TCC_EA0_ATOMIC[54], TCC_EA0_ATOMIC[55], TCC_EA0_ATOMIC[56], TCC_EA0_ATOMIC[57], TCC_EA0_ATOMIC[58], TCC_EA0_ATOMIC[59], TCC_EA0_ATOMIC[5], TCC_EA0_ATOMIC[60], TCC_EA0_ATOMIC[61], TCC_EA0_ATOMIC[62], TCC_EA0_ATOMIC[63], TCC_EA0_ATOMIC[64], TCC_EA0_ATOMIC[65], TCC_EA0_ATOMIC[66], TCC_EA0_ATOMIC[67], TCC_EA0_ATOMIC[68], TCC_EA0_ATOMIC[69], TCC_EA0_ATOMIC[6], TCC_EA0_ATOMIC[70], TCC_EA0_ATOMIC[71], TCC_EA0_ATOMIC[72], TCC_EA0_ATOMIC[73], TCC_EA0_ATOMIC[74], TCC_EA0_ATOMIC[75], TCC_EA0_ATOMIC[76], TCC_EA0_ATOMIC[77], TCC_EA0_ATOMIC[78], TCC_EA0_ATOMIC[79], TCC_EA0_ATOMIC[7], TCC_EA0_ATOMIC[80], TCC_EA0_ATOMIC[81], TCC_EA0_ATOMIC[82], TCC_EA0_ATOMIC[83], TCC_EA0_ATOMIC[84], TCC_EA0_ATOMIC[85], TCC_EA0_ATOMIC[86], TCC_EA0_ATOMIC[87], TCC_EA0_ATOMIC[88], TCC_EA0_ATOMIC[89], TCC_EA0_ATOMIC[8], TCC_EA0_ATOMIC[90], TCC_EA0_ATOMIC[91], TCC_EA0_ATOMIC[92], TCC_EA0_ATOMIC[93], TCC_EA0_ATOMIC[94], TCC_EA0_ATOMIC[95], TCC_EA0_ATOMIC[96], TCC_EA0_ATOMIC[97], TCC_EA0_ATOMIC[98], TCC_EA0_ATOMIC[99], TCC_EA0_ATOMIC[9], TCC_HIT[0], TCC_HIT[100], TCC_HIT[101], TCC_HIT[102], TCC_HIT[103], TCC_HIT[104], TCC_HIT[105], TCC_HIT[106], TCC_HIT[107], TCC_HIT[108], TCC_HIT[109], TCC_HIT[10], TCC_HIT[110], TCC_HIT[111], TCC_HIT[112], TCC_HIT[113], TCC_HIT[114], TCC_HIT[115], TCC_HIT[116], TCC_HIT[117], TCC_HIT[118], TCC_HIT[119], TCC_HIT[11], TCC_HIT[120], TCC_HIT[121], TCC_HIT[122], TCC_HIT[123], TCC_HIT[124], TCC_HIT[125], TCC_HIT[126], TCC_HIT[127], TCC_HIT[12], TCC_HIT[13], TCC_HIT[14], TCC_HIT[15], TCC_HIT[16], TCC_HIT[17], TCC_HIT[18], TCC_HIT[19], TCC_HIT[1], TCC_HIT[20], TCC_HIT[21], TCC_HIT[22], TCC_HIT[23], TCC_HIT[24], TCC_HIT[25], TCC_HIT[26], TCC_HIT[27], TCC_HIT[28], TCC_HIT[29], TCC_HIT[2], TCC_HIT[30], TCC_HIT[31], TCC_HIT[32], TCC_HIT[33], TCC_HIT[34], TCC_HIT[35], TCC_HIT[36], TCC_HIT[37], TCC_HIT[38], TCC_HIT[39], TCC_HIT[3], TCC_HIT[40], TCC_HIT[41], TCC_HIT[42], TCC_HIT[43], TCC_HIT[44], TCC_HIT[45], TCC_HIT[46], TCC_HIT[47], TCC_HIT[48], TCC_HIT[49], TCC_HIT[4], TCC_HIT[50], TCC_HIT[51], TCC_HIT[52], TCC_HIT[53], TCC_HIT[54], TCC_HIT[55], TCC_HIT[56], TCC_HIT[57], TCC_HIT[58], TCC_HIT[59], TCC_HIT[5], TCC_HIT[60], TCC_HIT[61], TCC_HIT[62], TCC_HIT[63], TCC_HIT[64], TCC_HIT[65], TCC_HIT[66], TCC_HIT[67], TCC_HIT[68], TCC_HIT[69], TCC_HIT[6], TCC_HIT[70], TCC_HIT[71], TCC_HIT[72], TCC_HIT[73], TCC_HIT[74], TCC_HIT[75], TCC_HIT[76], TCC_HIT[77], TCC_HIT[78], TCC_HIT[79], TCC_HIT[7], TCC_HIT[80], TCC_HIT[81], TCC_HIT[82], TCC_HIT[83], TCC_HIT[84], TCC_HIT[85], TCC_HIT[86], TCC_HIT[87], TCC_HIT[88], TCC_HIT[89], TCC_HIT[8], TCC_HIT[90], TCC_HIT[91], TCC_HIT[92], TCC_HIT[93], TCC_HIT[94], TCC_HIT[95], TCC_HIT[96], TCC_HIT[97], TCC_HIT[98], TCC_HIT[99], TCC_HIT[9], TCP_TA_TCP_STATE_READ_sum, TCP_TCC_UC_READ_REQ_sum, TCP_TOTAL_ATOMIC_WITH_RET_sum, TCP_UTCL1_TRANSLATION_HIT_sum, TD_LOAD_WAVEFRONT_sum, TD_STORE_WAVEFRONT_sum]. Found: [CPC_CPC_STAT_BUSY, CPC_CPC_STAT_IDLE, CPF_CPF_STAT_IDLE, CPF_CPF_STAT_STALL, SPI_CSQ_P0_OCCUPANCY, SPI_CSQ_P1_OCCUPANCY, SPI_CSQ_P2_OCCUPANCY, SPI_CSQ_P3_OCCUPANCY, SPI_RA_SGPR_SIMD_FULL_CSN, SQC_DCACHE_REQ_READ_16, SQ_BUSY_CU_CYCLES, SQ_INSTS_LDS_LOAD, SQ_INSTS_LDS_STORE, SQ_INSTS_VALU_MUL_F64, SQ_INST_LEVEL_SMEM, SQ_LDS_CMD_FIFO_FULL, TA_BUFFER_TOTAL_CYCLES_sum, TA_FLAT_READ_WAVEFRONTS_sum, TCC_ATOMIC[0], TCC_ATOMIC[100], TCC_ATOMIC[101], TCC_ATOMIC[102], TCC_ATOMIC[103], TCC_ATOMIC[104], TCC_ATOMIC[105], TCC_ATOMIC[106], TCC_ATOMIC[107], TCC_ATOMIC[108], TCC_ATOMIC[109], TCC_ATOMIC[10], TCC_ATOMIC[110], TCC_ATOMIC[111], TCC_ATOMIC[112], TCC_ATOMIC[113], TCC_ATOMIC[114], TCC_ATOMIC[115], TCC_ATOMIC[116], TCC_ATOMIC[117], TCC_ATOMIC[118], TCC_ATOMIC[119], TCC_ATOMIC[11], TCC_ATOMIC[120], TCC_ATOMIC[121], TCC_ATOMIC[122], TCC_ATOMIC[123], TCC_ATOMIC[124], TCC_ATOMIC[125], TCC_ATOMIC[126], TCC_ATOMIC[127], TCC_ATOMIC[12], TCC_ATOMIC[13], TCC_ATOMIC[14], TCC_ATOMIC[15], TCC_ATOMIC[16], TCC_ATOMIC[17], TCC_ATOMIC[18], TCC_ATOMIC[19], TCC_ATOMIC[1], TCC_ATOMIC[20], TCC_ATOMIC[21], TCC_ATOMIC[22], TCC_ATOMIC[23], TCC_ATOMIC[24], TCC_ATOMIC[25], TCC_ATOMIC[26], TCC_ATOMIC[27], TCC_ATOMIC[28], TCC_ATOMIC[29], TCC_ATOMIC[2], TCC_ATOMIC[30], TCC_ATOMIC[31], TCC_ATOMIC[32], TCC_ATOMIC[33], TCC_ATOMIC[34], TCC_ATOMIC[35], TCC_ATOMIC[36], TCC_ATOMIC[37], TCC_ATOMIC[38], TCC_ATOMIC[39], TCC_ATOMIC[3], TCC_ATOMIC[40], TCC_ATOMIC[41], TCC_ATOMIC[42], TCC_ATOMIC[43], TCC_ATOMIC[44], TCC_ATOMIC[45], TCC_ATOMIC[46], TCC_ATOMIC[47], TCC_ATOMIC[48], TCC_ATOMIC[49], TCC_ATOMIC[4], TCC_ATOMIC[50], TCC_ATOMIC[51], TCC_ATOMIC[52], TCC_ATOMIC[53], TCC_ATOMIC[54], TCC_ATOMIC[55], TCC_ATOMIC[56], TCC_ATOMIC[57], TCC_ATOMIC[58], TCC_ATOMIC[59], TCC_ATOMIC[5], TCC_ATOMIC[60], TCC_ATOMIC[61], TCC_ATOMIC[62], TCC_ATOMIC[63], TCC_ATOMIC[64], TCC_ATOMIC[65], TCC_ATOMIC[66], TCC_ATOMIC[67], TCC_ATOMIC[68], TCC_ATOMIC[69], TCC_ATOMIC[6], TCC_ATOMIC[70], TCC_ATOMIC[71], TCC_ATOMIC[72], TCC_ATOMIC[73], TCC_ATOMIC[74], TCC_ATOMIC[75], TCC_ATOMIC[76], TCC_ATOMIC[77], TCC_ATOMIC[78], TCC_ATOMIC[79], TCC_ATOMIC[7], TCC_ATOMIC[80], TCC_ATOMIC[81], TCC_ATOMIC[82], TCC_ATOMIC[83], TCC_ATOMIC[84], TCC_ATOMIC[85], TCC_ATOMIC[86], TCC_ATOMIC[87], TCC_ATOMIC[88], TCC_ATOMIC[89], TCC_ATOMIC[8], TCC_ATOMIC[90], TCC_ATOMIC[91], TCC_ATOMIC[92], TCC_ATOMIC[93], TCC_ATOMIC[94], TCC_ATOMIC[95], TCC_ATOMIC[96], TCC_ATOMIC[97], TCC_ATOMIC[98], TCC_ATOMIC[99], TCC_ATOMIC[9], TCC_BUBBLE[0], TCC_BUBBLE[100], TCC_BUBBLE[101], TCC_BUBBLE[102], TCC_BUBBLE[103], TCC_BUBBLE[104], TCC_BUBBLE[105], TCC_BUBBLE[106], TCC_BUBBLE[107], TCC_BUBBLE[108], TCC_BUBBLE[109], TCC_BUBBLE[10], TCC_BUBBLE[110], TCC_BUBBLE[111], TCC_BUBBLE[112], TCC_BUBBLE[113], TCC_BUBBLE[114], TCC_BUBBLE[115], TCC_BUBBLE[116], TCC_BUBBLE[117], TCC_BUBBLE[118], TCC_BUBBLE[119], TCC_BUBBLE[11], TCC_BUBBLE[120], TCC_BUBBLE[121], TCC_BUBBLE[122], TCC_BUBBLE[123], TCC_BUBBLE[124], TCC_BUBBLE[125], TCC_BUBBLE[126], TCC_BUBBLE[127], TCC_BUBBLE[12], TCC_BUBBLE[13], TCC_BUBBLE[14], TCC_BUBBLE[15], TCC_BUBBLE[16], TCC_BUBBLE[17], TCC_BUBBLE[18], TCC_BUBBLE[19], TCC_BUBBLE[1], TCC_BUBBLE[20], TCC_BUBBLE[21], TCC_BUBBLE[22], TCC_BUBBLE[23], TCC_BUBBLE[24], TCC_BUBBLE[25], TCC_BUBBLE[26], TCC_BUBBLE[27], TCC_BUBBLE[28], TCC_BUBBLE[29], TCC_BUBBLE[2], TCC_BUBBLE[30], TCC_BUBBLE[31], TCC_BUBBLE[32], TCC_BUBBLE[33], TCC_BUBBLE[34], TCC_BUBBLE[35], TCC_BUBBLE[36], TCC_BUBBLE[37], TCC_BUBBLE[38], TCC_BUBBLE[39], TCC_BUBBLE[3], TCC_BUBBLE[40], TCC_BUBBLE[41], TCC_BUBBLE[42], TCC_BUBBLE[43], TCC_BUBBLE[44], TCC_BUBBLE[45], TCC_BUBBLE[46], TCC_BUBBLE[47], TCC_BUBBLE[48], TCC_BUBBLE[49], TCC_BUBBLE[4], TCC_BUBBLE[50], TCC_BUBBLE[51], TCC_BUBBLE[52], TCC_BUBBLE[53], TCC_BUBBLE[54], TCC_BUBBLE[55], TCC_BUBBLE[56], TCC_BUBBLE[57], TCC_BUBBLE[58], TCC_BUBBLE[59], TCC_BUBBLE[5], TCC_BUBBLE[60], TCC_BUBBLE[61], TCC_BUBBLE[62], TCC_BUBBLE[63], TCC_BUBBLE[64], TCC_BUBBLE[65], TCC_BUBBLE[66], TCC_BUBBLE[67], TCC_BUBBLE[68], TCC_BUBBLE[69], TCC_BUBBLE[6], TCC_BUBBLE[70], TCC_BUBBLE[71], TCC_BUBBLE[72], TCC_BUBBLE[73], TCC_BUBBLE[74], TCC_BUBBLE[75], TCC_BUBBLE[76], TCC_BUBBLE[77], TCC_BUBBLE[78], TCC_BUBBLE[79], TCC_BUBBLE[7], TCC_BUBBLE[80], TCC_BUBBLE[81], TCC_BUBBLE[82], TCC_BUBBLE[83], TCC_BUBBLE[84], TCC_BUBBLE[85], TCC_BUBBLE[86], TCC_BUBBLE[87], TCC_BUBBLE[88], TCC_BUBBLE[89], TCC_BUBBLE[8], TCC_BUBBLE[90], TCC_BUBBLE[91], TCC_BUBBLE[92], TCC_BUBBLE[93], TCC_BUBBLE[94], TCC_BUBBLE[95], TCC_BUBBLE[96], TCC_BUBBLE[97], TCC_BUBBLE[98], TCC_BUBBLE[99], TCC_BUBBLE[9], TCC_EA0_ATOMIC[0], TCC_EA0_ATOMIC[100], TCC_EA0_ATOMIC[101], TCC_EA0_ATOMIC[102], TCC_EA0_ATOMIC[103], TCC_EA0_ATOMIC[104], TCC_EA0_ATOMIC[105], TCC_EA0_ATOMIC[106], TCC_EA0_ATOMIC[107], TCC_EA0_ATOMIC[108], TCC_EA0_ATOMIC[109], TCC_EA0_ATOMIC[10], TCC_EA0_ATOMIC[110], TCC_EA0_ATOMIC[111], TCC_EA0_ATOMIC[112], TCC_EA0_ATOMIC[113], TCC_EA0_ATOMIC[114], TCC_EA0_ATOMIC[115], TCC_EA0_ATOMIC[116], TCC_EA0_ATOMIC[117], TCC_EA0_ATOMIC[118], TCC_EA0_ATOMIC[119], TCC_EA0_ATOMIC[11], TCC_EA0_ATOMIC[120], TCC_EA0_ATOMIC[121], TCC_EA0_ATOMIC[122], TCC_EA0_ATOMIC[123], TCC_EA0_ATOMIC[124], TCC_EA0_ATOMIC[125], TCC_EA0_ATOMIC[126], TCC_EA0_ATOMIC[127], TCC_EA0_ATOMIC[12], TCC_EA0_ATOMIC[13], TCC_EA0_ATOMIC[14], TCC_EA0_ATOMIC[15], TCC_EA0_ATOMIC[16], TCC_EA0_ATOMIC[17], TCC_EA0_ATOMIC[18], TCC_EA0_ATOMIC[19], TCC_EA0_ATOMIC[1], TCC_EA0_ATOMIC[20], TCC_EA0_ATOMIC[21], TCC_EA0_ATOMIC[22], TCC_EA0_ATOMIC[23], TCC_EA0_ATOMIC[24], TCC_EA0_ATOMIC[25], TCC_EA0_ATOMIC[26], TCC_EA0_ATOMIC[27], TCC_EA0_ATOMIC[28], TCC_EA0_ATOMIC[29], TCC_EA0_ATOMIC[2], TCC_EA0_ATOMIC[30], TCC_EA0_ATOMIC[31], TCC_EA0_ATOMIC[32], TCC_EA0_ATOMIC[33], TCC_EA0_ATOMIC[34], TCC_EA0_ATOMIC[35], TCC_EA0_ATOMIC[36], TCC_EA0_ATOMIC[37], TCC_EA0_ATOMIC[38], TCC_EA0_ATOMIC[39], TCC_EA0_ATOMIC[3], TCC_EA0_ATOMIC[40], TCC_EA0_ATOMIC[41], TCC_EA0_ATOMIC[42], TCC_EA0_ATOMIC[43], TCC_EA0_ATOMIC[44], TCC_EA0_ATOMIC[45], TCC_EA0_ATOMIC[46], TCC_EA0_ATOMIC[47], TCC_EA0_ATOMIC[48], TCC_EA0_ATOMIC[49], TCC_EA0_ATOMIC[4], TCC_EA0_ATOMIC[50], TCC_EA0_ATOMIC[51], TCC_EA0_ATOMIC[52], TCC_EA0_ATOMIC[53], TCC_EA0_ATOMIC[54], TCC_EA0_ATOMIC[55], TCC_EA0_ATOMIC[56], TCC_EA0_ATOMIC[57], TCC_EA0_ATOMIC[58], TCC_EA0_ATOMIC[59], TCC_EA0_ATOMIC[5], TCC_EA0_ATOMIC[60], TCC_EA0_ATOMIC[61], TCC_EA0_ATOMIC[62], TCC_EA0_ATOMIC[63], TCC_EA0_ATOMIC[64], TCC_EA0_ATOMIC[65], TCC_EA0_ATOMIC[66], TCC_EA0_ATOMIC[67], TCC_EA0_ATOMIC[68], TCC_EA0_ATOMIC[69], TCC_EA0_ATOMIC[6], TCC_EA0_ATOMIC[70], TCC_EA0_ATOMIC[71], TCC_EA0_ATOMIC[72], TCC_EA0_ATOMIC[73], TCC_EA0_ATOMIC[74], TCC_EA0_ATOMIC[75], TCC_EA0_ATOMIC[76], TCC_EA0_ATOMIC[77], TCC_EA0_ATOMIC[78], TCC_EA0_ATOMIC[79], TCC_EA0_ATOMIC[7], TCC_EA0_ATOMIC[80], TCC_EA0_ATOMIC[81], TCC_EA0_ATOMIC[82], TCC_EA0_ATOMIC[83], TCC_EA0_ATOMIC[84], TCC_EA0_ATOMIC[85], TCC_EA0_ATOMIC[86], TCC_EA0_ATOMIC[87], TCC_EA0_ATOMIC[88], TCC_EA0_ATOMIC[89], TCC_EA0_ATOMIC[8], TCC_EA0_ATOMIC[90], TCC_EA0_ATOMIC[91], TCC_EA0_ATOMIC[92], TCC_EA0_ATOMIC[93], TCC_EA0_ATOMIC[94], TCC_EA0_ATOMIC[95], TCC_EA0_ATOMIC[96], TCC_EA0_ATOMIC[97], TCC_EA0_ATOMIC[98], TCC_EA0_ATOMIC[99], TCC_EA0_ATOMIC[9], TCC_HIT[0], TCC_HIT[100], TCC_HIT[101], TCC_HIT[102], TCC_HIT[103], TCC_HIT[104], TCC_HIT[105], TCC_HIT[106], TCC_HIT[107], TCC_HIT[108], TCC_HIT[109], TCC_HIT[10], TCC_HIT[110], TCC_HIT[111], TCC_HIT[112], TCC_HIT[113], TCC_HIT[114], TCC_HIT[115], TCC_HIT[116], TCC_HIT[117], TCC_HIT[118], TCC_HIT[119], TCC_HIT[11], TCC_HIT[120], TCC_HIT[121], TCC_HIT[122], TCC_HIT[123], TCC_HIT[124], TCC_HIT[125], TCC_HIT[126], TCC_HIT[127], TCC_HIT[12], TCC_HIT[13], TCC_HIT[14], TCC_HIT[15], TCC_HIT[16], TCC_HIT[17], TCC_HIT[18], TCC_HIT[19], TCC_HIT[1], TCC_HIT[20], TCC_HIT[21], TCC_HIT[22], TCC_HIT[23], TCC_HIT[24], TCC_HIT[25], TCC_HIT[26], TCC_HIT[27], TCC_HIT[28], TCC_HIT[29], TCC_HIT[2], TCC_HIT[30], TCC_HIT[31], TCC_HIT[32], TCC_HIT[33], TCC_HIT[34], TCC_HIT[35], TCC_HIT[36], TCC_HIT[37], TCC_HIT[38], TCC_HIT[39], TCC_HIT[3], TCC_HIT[40], TCC_HIT[41], TCC_HIT[42], TCC_HIT[43], TCC_HIT[44], TCC_HIT[45], TCC_HIT[46], TCC_HIT[47], TCC_HIT[48], TCC_HIT[49], TCC_HIT[4], TCC_HIT[50], TCC_HIT[51], TCC_HIT[52], TCC_HIT[53], TCC_HIT[54], TCC_HIT[55], TCC_HIT[56], TCC_HIT[57], TCC_HIT[58], TCC_HIT[59], TCC_HIT[5], TCC_HIT[60], TCC_HIT[61], TCC_HIT[62], TCC_HIT[63], TCC_HIT[64], TCC_HIT[65], TCC_HIT[66], TCC_HIT[67], TCC_HIT[68], TCC_HIT[69], TCC_HIT[6], TCC_HIT[70], TCC_HIT[71], TCC_HIT[72], TCC_HIT[73], TCC_HIT[74], TCC_HIT[75], TCC_HIT[76], TCC_HIT[77], TCC_HIT[78], TCC_HIT[79], TCC_HIT[7], TCC_HIT[80], TCC_HIT[81], TCC_HIT[82], TCC_HIT[83], TCC_HIT[84], TCC_HIT[85], TCC_HIT[86], TCC_HIT[87], TCC_HIT[88], TCC_HIT[89], TCC_HIT[8], TCC_HIT[90], TCC_HIT[91], TCC_HIT[92], TCC_HIT[93], TCC_HIT[94], TCC_HIT[95], TCC_HIT[96], TCC_HIT[97], TCC_HIT[98], TCC_HIT[99], TCC_HIT[9], TCP_TA_TCP_STATE_READ_sum, TCP_TCC_UC_READ_REQ_sum, TCP_TOTAL_ATOMIC_WITH_RET_sum, TCP_UTCL1_TRANSLATION_HIT_sum, TD_LOAD_WAVEFRONT_sum, TD_STORE_WAVEFRONT_sum] + |-> [rocprofv3] E20250328 22:44:00.574379 140472799942656 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15751_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:00.580668 140472799942656 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15751_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:00.584250 140472799942656 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15751_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt, the time it takes was 0 m 0.5386278629302979 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt is 0 m 0.5522944927215576 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt +pmc file: SQ_INST_LEVEL_VMEM.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.yaml -i /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] W20250328 22:44:01.114627 140613229746176 tool.cpp:930] Unable to find all counters for agent 1 (gpu-0, gfx950) in [CPC_CANE_STALL, CPC_CPC_STAT_STALL, CPF_CPF_TCIU_BUSY, CPF_CPF_TCIU_STALL, GRBM_COUNT, GRBM_SPI_BUSY, SPI_CS0_CRAWLER_STALL, SPI_CS1_CRAWLER_STALL, SPI_CS2_CRAWLER_STALL, SPI_CS3_CRAWLER_STALL, SQ_ACTIVE_INST_VMEM, SQ_INSTS_GDS, SQ_INSTS_LDS_ATOMIC, SQ_INSTS_VALU_MFMA_F16, SQ_INSTS_VALU_MFMA_MOPS_F32, SQ_INSTS_VSKIPPED, SQ_INST_LEVEL_VMEM, SQ_INST_LEVEL_VMEM_ACCUM, TA_ADDR_STALLED_BY_TD_CYCLES_sum, TA_BUFFER_COALESCED_READ_CYCLES_sum, TCC_EA0_WRREQ[0], TCC_EA0_WRREQ[100], TCC_EA0_WRREQ[101], TCC_EA0_WRREQ[102], TCC_EA0_WRREQ[103], TCC_EA0_WRREQ[104], TCC_EA0_WRREQ[105], TCC_EA0_WRREQ[106], TCC_EA0_WRREQ[107], TCC_EA0_WRREQ[108], TCC_EA0_WRREQ[109], TCC_EA0_WRREQ[10], TCC_EA0_WRREQ[110], TCC_EA0_WRREQ[111], TCC_EA0_WRREQ[112], TCC_EA0_WRREQ[113], TCC_EA0_WRREQ[114], TCC_EA0_WRREQ[115], TCC_EA0_WRREQ[116], TCC_EA0_WRREQ[117], TCC_EA0_WRREQ[118], TCC_EA0_WRREQ[119], TCC_EA0_WRREQ[11], TCC_EA0_WRREQ[120], TCC_EA0_WRREQ[121], TCC_EA0_WRREQ[122], TCC_EA0_WRREQ[123], TCC_EA0_WRREQ[124], TCC_EA0_WRREQ[125], TCC_EA0_WRREQ[126], TCC_EA0_WRREQ[127], TCC_EA0_WRREQ[12], TCC_EA0_WRREQ[13], TCC_EA0_WRREQ[14], TCC_EA0_WRREQ[15], TCC_EA0_WRREQ[16], TCC_EA0_WRREQ[17], TCC_EA0_WRREQ[18], TCC_EA0_WRREQ[19], TCC_EA0_WRREQ[1], TCC_EA0_WRREQ[20], TCC_EA0_WRREQ[21], TCC_EA0_WRREQ[22], TCC_EA0_WRREQ[23], TCC_EA0_WRREQ[24], TCC_EA0_WRREQ[25], TCC_EA0_WRREQ[26], TCC_EA0_WRREQ[27], TCC_EA0_WRREQ[28], TCC_EA0_WRREQ[29], TCC_EA0_WRREQ[2], TCC_EA0_WRREQ[30], TCC_EA0_WRREQ[31], TCC_EA0_WRREQ[32], TCC_EA0_WRREQ[33], TCC_EA0_WRREQ[34], TCC_EA0_WRREQ[35], TCC_EA0_WRREQ[36], TCC_EA0_WRREQ[37], TCC_EA0_WRREQ[38], TCC_EA0_WRREQ[39], TCC_EA0_WRREQ[3], TCC_EA0_WRREQ[40], TCC_EA0_WRREQ[41], TCC_EA0_WRREQ[42], TCC_EA0_WRREQ[43], TCC_EA0_WRREQ[44], TCC_EA0_WRREQ[45], TCC_EA0_WRREQ[46], TCC_EA0_WRREQ[47], TCC_EA0_WRREQ[48], TCC_EA0_WRREQ[49], TCC_EA0_WRREQ[4], TCC_EA0_WRREQ[50], TCC_EA0_WRREQ[51], TCC_EA0_WRREQ[52], TCC_EA0_WRREQ[53], TCC_EA0_WRREQ[54], TCC_EA0_WRREQ[55], TCC_EA0_WRREQ[56], TCC_EA0_WRREQ[57], TCC_EA0_WRREQ[58], TCC_EA0_WRREQ[59], TCC_EA0_WRREQ[5], TCC_EA0_WRREQ[60], TCC_EA0_WRREQ[61], TCC_EA0_WRREQ[62], TCC_EA0_WRREQ[63], TCC_EA0_WRREQ[64], TCC_EA0_WRREQ[65], TCC_EA0_WRREQ[66], TCC_EA0_WRREQ[67], TCC_EA0_WRREQ[68], TCC_EA0_WRREQ[69], TCC_EA0_WRREQ[6], TCC_EA0_WRREQ[70], TCC_EA0_WRREQ[71], TCC_EA0_WRREQ[72], TCC_EA0_WRREQ[73], TCC_EA0_WRREQ[74], TCC_EA0_WRREQ[75], TCC_EA0_WRREQ[76], TCC_EA0_WRREQ[77], TCC_EA0_WRREQ[78], TCC_EA0_WRREQ[79], TCC_EA0_WRREQ[7], TCC_EA0_WRREQ[80], TCC_EA0_WRREQ[81], TCC_EA0_WRREQ[82], TCC_EA0_WRREQ[83], TCC_EA0_WRREQ[84], TCC_EA0_WRREQ[85], TCC_EA0_WRREQ[86], TCC_EA0_WRREQ[87], TCC_EA0_WRREQ[88], TCC_EA0_WRREQ[89], TCC_EA0_WRREQ[8], TCC_EA0_WRREQ[90], TCC_EA0_WRREQ[91], TCC_EA0_WRREQ[92], TCC_EA0_WRREQ[93], TCC_EA0_WRREQ[94], TCC_EA0_WRREQ[95], TCC_EA0_WRREQ[96], TCC_EA0_WRREQ[97], TCC_EA0_WRREQ[98], TCC_EA0_WRREQ[99], TCC_EA0_WRREQ[9], TCC_MISS[0], TCC_MISS[100], TCC_MISS[101], TCC_MISS[102], TCC_MISS[103], TCC_MISS[104], TCC_MISS[105], TCC_MISS[106], TCC_MISS[107], TCC_MISS[108], TCC_MISS[109], TCC_MISS[10], TCC_MISS[110], TCC_MISS[111], TCC_MISS[112], TCC_MISS[113], TCC_MISS[114], TCC_MISS[115], TCC_MISS[116], TCC_MISS[117], TCC_MISS[118], TCC_MISS[119], TCC_MISS[11], TCC_MISS[120], TCC_MISS[121], TCC_MISS[122], TCC_MISS[123], TCC_MISS[124], TCC_MISS[125], TCC_MISS[126], TCC_MISS[127], TCC_MISS[12], TCC_MISS[13], TCC_MISS[14], TCC_MISS[15], TCC_MISS[16], TCC_MISS[17], TCC_MISS[18], TCC_MISS[19], TCC_MISS[1], TCC_MISS[20], TCC_MISS[21], TCC_MISS[22], TCC_MISS[23], TCC_MISS[24], TCC_MISS[25], TCC_MISS[26], TCC_MISS[27], TCC_MISS[28], TCC_MISS[29], TCC_MISS[2], TCC_MISS[30], TCC_MISS[31], TCC_MISS[32], TCC_MISS[33], TCC_MISS[34], TCC_MISS[35], TCC_MISS[36], TCC_MISS[37], TCC_MISS[38], TCC_MISS[39], TCC_MISS[3], TCC_MISS[40], TCC_MISS[41], TCC_MISS[42], TCC_MISS[43], TCC_MISS[44], TCC_MISS[45], TCC_MISS[46], TCC_MISS[47], TCC_MISS[48], TCC_MISS[49], TCC_MISS[4], TCC_MISS[50], TCC_MISS[51], TCC_MISS[52], TCC_MISS[53], TCC_MISS[54], TCC_MISS[55], TCC_MISS[56], TCC_MISS[57], TCC_MISS[58], TCC_MISS[59], TCC_MISS[5], TCC_MISS[60], TCC_MISS[61], TCC_MISS[62], TCC_MISS[63], TCC_MISS[64], TCC_MISS[65], TCC_MISS[66], TCC_MISS[67], TCC_MISS[68], TCC_MISS[69], TCC_MISS[6], TCC_MISS[70], TCC_MISS[71], TCC_MISS[72], TCC_MISS[73], TCC_MISS[74], TCC_MISS[75], TCC_MISS[76], TCC_MISS[77], TCC_MISS[78], TCC_MISS[79], TCC_MISS[7], TCC_MISS[80], TCC_MISS[81], TCC_MISS[82], TCC_MISS[83], TCC_MISS[84], TCC_MISS[85], TCC_MISS[86], TCC_MISS[87], TCC_MISS[88], TCC_MISS[89], TCC_MISS[8], TCC_MISS[90], TCC_MISS[91], TCC_MISS[92], TCC_MISS[93], TCC_MISS[94], TCC_MISS[95], TCC_MISS[96], TCC_MISS[97], TCC_MISS[98], TCC_MISS[99], TCC_MISS[9], TCC_READ[0], TCC_READ[100], TCC_READ[101], TCC_READ[102], TCC_READ[103], TCC_READ[104], TCC_READ[105], TCC_READ[106], TCC_READ[107], TCC_READ[108], TCC_READ[109], TCC_READ[10], TCC_READ[110], TCC_READ[111], TCC_READ[112], TCC_READ[113], TCC_READ[114], TCC_READ[115], TCC_READ[116], TCC_READ[117], TCC_READ[118], TCC_READ[119], TCC_READ[11], TCC_READ[120], TCC_READ[121], TCC_READ[122], TCC_READ[123], TCC_READ[124], TCC_READ[125], TCC_READ[126], TCC_READ[127], TCC_READ[12], TCC_READ[13], TCC_READ[14], TCC_READ[15], TCC_READ[16], TCC_READ[17], TCC_READ[18], TCC_READ[19], TCC_READ[1], TCC_READ[20], TCC_READ[21], TCC_READ[22], TCC_READ[23], TCC_READ[24], TCC_READ[25], TCC_READ[26], TCC_READ[27], TCC_READ[28], TCC_READ[29], TCC_READ[2], TCC_READ[30], TCC_READ[31], TCC_READ[32], TCC_READ[33], TCC_READ[34], TCC_READ[35], TCC_READ[36], TCC_READ[37], TCC_READ[38], TCC_READ[39], TCC_READ[3], TCC_READ[40], TCC_READ[41], TCC_READ[42], TCC_READ[43], TCC_READ[44], TCC_READ[45], TCC_READ[46], TCC_READ[47], TCC_READ[48], TCC_READ[49], TCC_READ[4], TCC_READ[50], TCC_READ[51], TCC_READ[52], TCC_READ[53], TCC_READ[54], TCC_READ[55], TCC_READ[56], TCC_READ[57], TCC_READ[58], TCC_READ[59], TCC_READ[5], TCC_READ[60], TCC_READ[61], TCC_READ[62], TCC_READ[63], TCC_READ[64], TCC_READ[65], TCC_READ[66], TCC_READ[67], TCC_READ[68], TCC_READ[69], TCC_READ[6], TCC_READ[70], TCC_READ[71], TCC_READ[72], TCC_READ[73], TCC_READ[74], TCC_READ[75], TCC_READ[76], TCC_READ[77], TCC_READ[78], TCC_READ[79], TCC_READ[7], TCC_READ[80], TCC_READ[81], TCC_READ[82], TCC_READ[83], TCC_READ[84], TCC_READ[85], TCC_READ[86], TCC_READ[87], TCC_READ[88], TCC_READ[89], TCC_READ[8], TCC_READ[90], TCC_READ[91], TCC_READ[92], TCC_READ[93], TCC_READ[94], TCC_READ[95], TCC_READ[96], TCC_READ[97], TCC_READ[98], TCC_READ[99], TCC_READ[9], TCC_WRITE[0], TCC_WRITE[100], TCC_WRITE[101], TCC_WRITE[102], TCC_WRITE[103], TCC_WRITE[104], TCC_WRITE[105], TCC_WRITE[106], TCC_WRITE[107], TCC_WRITE[108], TCC_WRITE[109], TCC_WRITE[10], TCC_WRITE[110], TCC_WRITE[111], TCC_WRITE[112], TCC_WRITE[113], TCC_WRITE[114], TCC_WRITE[115], TCC_WRITE[116], TCC_WRITE[117], TCC_WRITE[118], TCC_WRITE[119], TCC_WRITE[11], TCC_WRITE[120], TCC_WRITE[121], TCC_WRITE[122], TCC_WRITE[123], TCC_WRITE[124], TCC_WRITE[125], TCC_WRITE[126], TCC_WRITE[127], TCC_WRITE[12], TCC_WRITE[13], TCC_WRITE[14], TCC_WRITE[15], TCC_WRITE[16], TCC_WRITE[17], TCC_WRITE[18], TCC_WRITE[19], TCC_WRITE[1], TCC_WRITE[20], TCC_WRITE[21], TCC_WRITE[22], TCC_WRITE[23], TCC_WRITE[24], TCC_WRITE[25], TCC_WRITE[26], TCC_WRITE[27], TCC_WRITE[28], TCC_WRITE[29], TCC_WRITE[2], TCC_WRITE[30], TCC_WRITE[31], TCC_WRITE[32], TCC_WRITE[33], TCC_WRITE[34], TCC_WRITE[35], TCC_WRITE[36], TCC_WRITE[37], TCC_WRITE[38], TCC_WRITE[39], TCC_WRITE[3], TCC_WRITE[40], TCC_WRITE[41], TCC_WRITE[42], TCC_WRITE[43], TCC_WRITE[44], TCC_WRITE[45], TCC_WRITE[46], TCC_WRITE[47], TCC_WRITE[48], TCC_WRITE[49], TCC_WRITE[4], TCC_WRITE[50], TCC_WRITE[51], TCC_WRITE[52], TCC_WRITE[53], TCC_WRITE[54], TCC_WRITE[55], TCC_WRITE[56], TCC_WRITE[57], TCC_WRITE[58], TCC_WRITE[59], TCC_WRITE[5], TCC_WRITE[60], TCC_WRITE[61], TCC_WRITE[62], TCC_WRITE[63], TCC_WRITE[64], TCC_WRITE[65], TCC_WRITE[66], TCC_WRITE[67], TCC_WRITE[68], TCC_WRITE[69], TCC_WRITE[6], TCC_WRITE[70], TCC_WRITE[71], TCC_WRITE[72], TCC_WRITE[73], TCC_WRITE[74], TCC_WRITE[75], TCC_WRITE[76], TCC_WRITE[77], TCC_WRITE[78], TCC_WRITE[79], TCC_WRITE[7], TCC_WRITE[80], TCC_WRITE[81], TCC_WRITE[82], TCC_WRITE[83], TCC_WRITE[84], TCC_WRITE[85], TCC_WRITE[86], TCC_WRITE[87], TCC_WRITE[88], TCC_WRITE[89], TCC_WRITE[8], TCC_WRITE[90], TCC_WRITE[91], TCC_WRITE[92], TCC_WRITE[93], TCC_WRITE[94], TCC_WRITE[95], TCC_WRITE[96], TCC_WRITE[97], TCC_WRITE[98], TCC_WRITE[99], TCC_WRITE[9], TCP_READ_TAGCONFLICT_STALL_CYCLES_sum, TCP_TCC_NC_WRITE_REQ_sum, TCP_TCC_RW_READ_REQ_sum, TCP_TCP_LATENCY_sum, TD_COALESCABLE_WAVEFRONT_sum, TD_SPI_STALL_sum]. Found: [CPC_CANE_STALL, CPC_CPC_STAT_STALL, CPF_CPF_TCIU_BUSY, CPF_CPF_TCIU_STALL, GRBM_COUNT, GRBM_SPI_BUSY, SPI_CS0_CRAWLER_STALL, SPI_CS1_CRAWLER_STALL, SPI_CS2_CRAWLER_STALL, SPI_CS3_CRAWLER_STALL, SQ_ACTIVE_INST_VMEM, SQ_INSTS_GDS, SQ_INSTS_LDS_ATOMIC, SQ_INSTS_VALU_MFMA_F16, SQ_INSTS_VALU_MFMA_MOPS_F32, SQ_INSTS_VSKIPPED, SQ_INST_LEVEL_VMEM, TA_ADDR_STALLED_BY_TD_CYCLES_sum, TA_BUFFER_COALESCED_READ_CYCLES_sum, TCC_EA0_WRREQ[0], TCC_EA0_WRREQ[100], TCC_EA0_WRREQ[101], TCC_EA0_WRREQ[102], TCC_EA0_WRREQ[103], TCC_EA0_WRREQ[104], TCC_EA0_WRREQ[105], TCC_EA0_WRREQ[106], TCC_EA0_WRREQ[107], TCC_EA0_WRREQ[108], TCC_EA0_WRREQ[109], TCC_EA0_WRREQ[10], TCC_EA0_WRREQ[110], TCC_EA0_WRREQ[111], TCC_EA0_WRREQ[112], TCC_EA0_WRREQ[113], TCC_EA0_WRREQ[114], TCC_EA0_WRREQ[115], TCC_EA0_WRREQ[116], TCC_EA0_WRREQ[117], TCC_EA0_WRREQ[118], TCC_EA0_WRREQ[119], TCC_EA0_WRREQ[11], TCC_EA0_WRREQ[120], TCC_EA0_WRREQ[121], TCC_EA0_WRREQ[122], TCC_EA0_WRREQ[123], TCC_EA0_WRREQ[124], TCC_EA0_WRREQ[125], TCC_EA0_WRREQ[126], TCC_EA0_WRREQ[127], TCC_EA0_WRREQ[12], TCC_EA0_WRREQ[13], TCC_EA0_WRREQ[14], TCC_EA0_WRREQ[15], TCC_EA0_WRREQ[16], TCC_EA0_WRREQ[17], TCC_EA0_WRREQ[18], TCC_EA0_WRREQ[19], TCC_EA0_WRREQ[1], TCC_EA0_WRREQ[20], TCC_EA0_WRREQ[21], TCC_EA0_WRREQ[22], TCC_EA0_WRREQ[23], TCC_EA0_WRREQ[24], TCC_EA0_WRREQ[25], TCC_EA0_WRREQ[26], TCC_EA0_WRREQ[27], TCC_EA0_WRREQ[28], TCC_EA0_WRREQ[29], TCC_EA0_WRREQ[2], TCC_EA0_WRREQ[30], TCC_EA0_WRREQ[31], TCC_EA0_WRREQ[32], TCC_EA0_WRREQ[33], TCC_EA0_WRREQ[34], TCC_EA0_WRREQ[35], TCC_EA0_WRREQ[36], TCC_EA0_WRREQ[37], TCC_EA0_WRREQ[38], TCC_EA0_WRREQ[39], TCC_EA0_WRREQ[3], TCC_EA0_WRREQ[40], TCC_EA0_WRREQ[41], TCC_EA0_WRREQ[42], TCC_EA0_WRREQ[43], TCC_EA0_WRREQ[44], TCC_EA0_WRREQ[45], TCC_EA0_WRREQ[46], TCC_EA0_WRREQ[47], TCC_EA0_WRREQ[48], TCC_EA0_WRREQ[49], TCC_EA0_WRREQ[4], TCC_EA0_WRREQ[50], TCC_EA0_WRREQ[51], TCC_EA0_WRREQ[52], TCC_EA0_WRREQ[53], TCC_EA0_WRREQ[54], TCC_EA0_WRREQ[55], TCC_EA0_WRREQ[56], TCC_EA0_WRREQ[57], TCC_EA0_WRREQ[58], TCC_EA0_WRREQ[59], TCC_EA0_WRREQ[5], TCC_EA0_WRREQ[60], TCC_EA0_WRREQ[61], TCC_EA0_WRREQ[62], TCC_EA0_WRREQ[63], TCC_EA0_WRREQ[64], TCC_EA0_WRREQ[65], TCC_EA0_WRREQ[66], TCC_EA0_WRREQ[67], TCC_EA0_WRREQ[68], TCC_EA0_WRREQ[69], TCC_EA0_WRREQ[6], TCC_EA0_WRREQ[70], TCC_EA0_WRREQ[71], TCC_EA0_WRREQ[72], TCC_EA0_WRREQ[73], TCC_EA0_WRREQ[74], TCC_EA0_WRREQ[75], TCC_EA0_WRREQ[76], TCC_EA0_WRREQ[77], TCC_EA0_WRREQ[78], TCC_EA0_WRREQ[79], TCC_EA0_WRREQ[7], TCC_EA0_WRREQ[80], TCC_EA0_WRREQ[81], TCC_EA0_WRREQ[82], TCC_EA0_WRREQ[83], TCC_EA0_WRREQ[84], TCC_EA0_WRREQ[85], TCC_EA0_WRREQ[86], TCC_EA0_WRREQ[87], TCC_EA0_WRREQ[88], TCC_EA0_WRREQ[89], TCC_EA0_WRREQ[8], TCC_EA0_WRREQ[90], TCC_EA0_WRREQ[91], TCC_EA0_WRREQ[92], TCC_EA0_WRREQ[93], TCC_EA0_WRREQ[94], TCC_EA0_WRREQ[95], TCC_EA0_WRREQ[96], TCC_EA0_WRREQ[97], TCC_EA0_WRREQ[98], TCC_EA0_WRREQ[99], TCC_EA0_WRREQ[9], TCC_MISS[0], TCC_MISS[100], TCC_MISS[101], TCC_MISS[102], TCC_MISS[103], TCC_MISS[104], TCC_MISS[105], TCC_MISS[106], TCC_MISS[107], TCC_MISS[108], TCC_MISS[109], TCC_MISS[10], TCC_MISS[110], TCC_MISS[111], TCC_MISS[112], TCC_MISS[113], TCC_MISS[114], TCC_MISS[115], TCC_MISS[116], TCC_MISS[117], TCC_MISS[118], TCC_MISS[119], TCC_MISS[11], TCC_MISS[120], TCC_MISS[121], TCC_MISS[122], TCC_MISS[123], TCC_MISS[124], TCC_MISS[125], TCC_MISS[126], TCC_MISS[127], TCC_MISS[12], TCC_MISS[13], TCC_MISS[14], TCC_MISS[15], TCC_MISS[16], TCC_MISS[17], TCC_MISS[18], TCC_MISS[19], TCC_MISS[1], TCC_MISS[20], TCC_MISS[21], TCC_MISS[22], TCC_MISS[23], TCC_MISS[24], TCC_MISS[25], TCC_MISS[26], TCC_MISS[27], TCC_MISS[28], TCC_MISS[29], TCC_MISS[2], TCC_MISS[30], TCC_MISS[31], TCC_MISS[32], TCC_MISS[33], TCC_MISS[34], TCC_MISS[35], TCC_MISS[36], TCC_MISS[37], TCC_MISS[38], TCC_MISS[39], TCC_MISS[3], TCC_MISS[40], TCC_MISS[41], TCC_MISS[42], TCC_MISS[43], TCC_MISS[44], TCC_MISS[45], TCC_MISS[46], TCC_MISS[47], TCC_MISS[48], TCC_MISS[49], TCC_MISS[4], TCC_MISS[50], TCC_MISS[51], TCC_MISS[52], TCC_MISS[53], TCC_MISS[54], TCC_MISS[55], TCC_MISS[56], TCC_MISS[57], TCC_MISS[58], TCC_MISS[59], TCC_MISS[5], TCC_MISS[60], TCC_MISS[61], TCC_MISS[62], TCC_MISS[63], TCC_MISS[64], TCC_MISS[65], TCC_MISS[66], TCC_MISS[67], TCC_MISS[68], TCC_MISS[69], TCC_MISS[6], TCC_MISS[70], TCC_MISS[71], TCC_MISS[72], TCC_MISS[73], TCC_MISS[74], TCC_MISS[75], TCC_MISS[76], TCC_MISS[77], TCC_MISS[78], TCC_MISS[79], TCC_MISS[7], TCC_MISS[80], TCC_MISS[81], TCC_MISS[82], TCC_MISS[83], TCC_MISS[84], TCC_MISS[85], TCC_MISS[86], TCC_MISS[87], TCC_MISS[88], TCC_MISS[89], TCC_MISS[8], TCC_MISS[90], TCC_MISS[91], TCC_MISS[92], TCC_MISS[93], TCC_MISS[94], TCC_MISS[95], TCC_MISS[96], TCC_MISS[97], TCC_MISS[98], TCC_MISS[99], TCC_MISS[9], TCC_READ[0], TCC_READ[100], TCC_READ[101], TCC_READ[102], TCC_READ[103], TCC_READ[104], TCC_READ[105], TCC_READ[106], TCC_READ[107], TCC_READ[108], TCC_READ[109], TCC_READ[10], TCC_READ[110], TCC_READ[111], TCC_READ[112], TCC_READ[113], TCC_READ[114], TCC_READ[115], TCC_READ[116], TCC_READ[117], TCC_READ[118], TCC_READ[119], TCC_READ[11], TCC_READ[120], TCC_READ[121], TCC_READ[122], TCC_READ[123], TCC_READ[124], TCC_READ[125], TCC_READ[126], TCC_READ[127], TCC_READ[12], TCC_READ[13], TCC_READ[14], TCC_READ[15], TCC_READ[16], TCC_READ[17], TCC_READ[18], TCC_READ[19], TCC_READ[1], TCC_READ[20], TCC_READ[21], TCC_READ[22], TCC_READ[23], TCC_READ[24], TCC_READ[25], TCC_READ[26], TCC_READ[27], TCC_READ[28], TCC_READ[29], TCC_READ[2], TCC_READ[30], TCC_READ[31], TCC_READ[32], TCC_READ[33], TCC_READ[34], TCC_READ[35], TCC_READ[36], TCC_READ[37], TCC_READ[38], TCC_READ[39], TCC_READ[3], TCC_READ[40], TCC_READ[41], TCC_READ[42], TCC_READ[43], TCC_READ[44], TCC_READ[45], TCC_READ[46], TCC_READ[47], TCC_READ[48], TCC_READ[49], TCC_READ[4], TCC_READ[50], TCC_READ[51], TCC_READ[52], TCC_READ[53], TCC_READ[54], TCC_READ[55], TCC_READ[56], TCC_READ[57], TCC_READ[58], TCC_READ[59], TCC_READ[5], TCC_READ[60], TCC_READ[61], TCC_READ[62], TCC_READ[63], TCC_READ[64], TCC_READ[65], TCC_READ[66], TCC_READ[67], TCC_READ[68], TCC_READ[69], TCC_READ[6], TCC_READ[70], TCC_READ[71], TCC_READ[72], TCC_READ[73], TCC_READ[74], TCC_READ[75], TCC_READ[76], TCC_READ[77], TCC_READ[78], TCC_READ[79], TCC_READ[7], TCC_READ[80], TCC_READ[81], TCC_READ[82], TCC_READ[83], TCC_READ[84], TCC_READ[85], TCC_READ[86], TCC_READ[87], TCC_READ[88], TCC_READ[89], TCC_READ[8], TCC_READ[90], TCC_READ[91], TCC_READ[92], TCC_READ[93], TCC_READ[94], TCC_READ[95], TCC_READ[96], TCC_READ[97], TCC_READ[98], TCC_READ[99], TCC_READ[9], TCC_WRITE[0], TCC_WRITE[100], TCC_WRITE[101], TCC_WRITE[102], TCC_WRITE[103], TCC_WRITE[104], TCC_WRITE[105], TCC_WRITE[106], TCC_WRITE[107], TCC_WRITE[108], TCC_WRITE[109], TCC_WRITE[10], TCC_WRITE[110], TCC_WRITE[111], TCC_WRITE[112], TCC_WRITE[113], TCC_WRITE[114], TCC_WRITE[115], TCC_WRITE[116], TCC_WRITE[117], TCC_WRITE[118], TCC_WRITE[119], TCC_WRITE[11], TCC_WRITE[120], TCC_WRITE[121], TCC_WRITE[122], TCC_WRITE[123], TCC_WRITE[124], TCC_WRITE[125], TCC_WRITE[126], TCC_WRITE[127], TCC_WRITE[12], TCC_WRITE[13], TCC_WRITE[14], TCC_WRITE[15], TCC_WRITE[16], TCC_WRITE[17], TCC_WRITE[18], TCC_WRITE[19], TCC_WRITE[1], TCC_WRITE[20], TCC_WRITE[21], TCC_WRITE[22], TCC_WRITE[23], TCC_WRITE[24], TCC_WRITE[25], TCC_WRITE[26], TCC_WRITE[27], TCC_WRITE[28], TCC_WRITE[29], TCC_WRITE[2], TCC_WRITE[30], TCC_WRITE[31], TCC_WRITE[32], TCC_WRITE[33], TCC_WRITE[34], TCC_WRITE[35], TCC_WRITE[36], TCC_WRITE[37], TCC_WRITE[38], TCC_WRITE[39], TCC_WRITE[3], TCC_WRITE[40], TCC_WRITE[41], TCC_WRITE[42], TCC_WRITE[43], TCC_WRITE[44], TCC_WRITE[45], TCC_WRITE[46], TCC_WRITE[47], TCC_WRITE[48], TCC_WRITE[49], TCC_WRITE[4], TCC_WRITE[50], TCC_WRITE[51], TCC_WRITE[52], TCC_WRITE[53], TCC_WRITE[54], TCC_WRITE[55], TCC_WRITE[56], TCC_WRITE[57], TCC_WRITE[58], TCC_WRITE[59], TCC_WRITE[5], TCC_WRITE[60], TCC_WRITE[61], TCC_WRITE[62], TCC_WRITE[63], TCC_WRITE[64], TCC_WRITE[65], TCC_WRITE[66], TCC_WRITE[67], TCC_WRITE[68], TCC_WRITE[69], TCC_WRITE[6], TCC_WRITE[70], TCC_WRITE[71], TCC_WRITE[72], TCC_WRITE[73], TCC_WRITE[74], TCC_WRITE[75], TCC_WRITE[76], TCC_WRITE[77], TCC_WRITE[78], TCC_WRITE[79], TCC_WRITE[7], TCC_WRITE[80], TCC_WRITE[81], TCC_WRITE[82], TCC_WRITE[83], TCC_WRITE[84], TCC_WRITE[85], TCC_WRITE[86], TCC_WRITE[87], TCC_WRITE[88], TCC_WRITE[89], TCC_WRITE[8], TCC_WRITE[90], TCC_WRITE[91], TCC_WRITE[92], TCC_WRITE[93], TCC_WRITE[94], TCC_WRITE[95], TCC_WRITE[96], TCC_WRITE[97], TCC_WRITE[98], TCC_WRITE[99], TCC_WRITE[9], TCP_READ_TAGCONFLICT_STALL_CYCLES_sum, TCP_TCC_NC_WRITE_REQ_sum, TCP_TCC_RW_READ_REQ_sum, TCP_TCP_LATENCY_sum, TD_COALESCABLE_WAVEFRONT_sum, TD_SPI_STALL_sum] + |-> [rocprofv3] E20250328 22:44:01.129009 140613229746176 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15758_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:01.135559 140613229746176 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15758_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:01.139250 140613229746176 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15758_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt, the time it takes was 0 m 0.5387754440307617 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt is 0 m 0.5530288219451904 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.txt +pmc file: SQ_LEVEL_WAVES.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.yaml -i /app/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] W20250328 22:44:01.669645 139667039954944 tool.cpp:930] Unable to find all counters for agent 1 (gpu-0, gfx950) in [CPC_CPC_TCIU_IDLE, CPC_TG_SEND, CPF_CPF_TCIU_IDLE, SPI_CS0_BUSY, SPI_CS1_BUSY, SPI_CS2_BUSY, SPI_CS3_BUSY, SQ_INSTS_LDS, SQ_INSTS_LDS_LOAD_BANDWIDTH, SQ_INSTS_VALU_ADD_F16, SQ_INSTS_VALU_FMA_F16, SQ_LDS_IDX_ACTIVE, SQ_LEVEL_WAVES, SQ_LEVEL_WAVES_ACCUM, SQ_WAVE_CYCLES, TA_BUFFER_ATOMIC_WAVEFRONTS_sum, TA_FLAT_ATOMIC_WAVEFRONTS_sum, TCC_BUBBLE_sum, TCC_EA0_ATOMIC_LEVEL[0], TCC_EA0_ATOMIC_LEVEL[100], TCC_EA0_ATOMIC_LEVEL[101], TCC_EA0_ATOMIC_LEVEL[102], TCC_EA0_ATOMIC_LEVEL[103], TCC_EA0_ATOMIC_LEVEL[104], TCC_EA0_ATOMIC_LEVEL[105], TCC_EA0_ATOMIC_LEVEL[106], TCC_EA0_ATOMIC_LEVEL[107], TCC_EA0_ATOMIC_LEVEL[108], TCC_EA0_ATOMIC_LEVEL[109], TCC_EA0_ATOMIC_LEVEL[10], TCC_EA0_ATOMIC_LEVEL[110], TCC_EA0_ATOMIC_LEVEL[111], TCC_EA0_ATOMIC_LEVEL[112], TCC_EA0_ATOMIC_LEVEL[113], TCC_EA0_ATOMIC_LEVEL[114], TCC_EA0_ATOMIC_LEVEL[115], TCC_EA0_ATOMIC_LEVEL[116], TCC_EA0_ATOMIC_LEVEL[117], TCC_EA0_ATOMIC_LEVEL[118], TCC_EA0_ATOMIC_LEVEL[119], TCC_EA0_ATOMIC_LEVEL[11], TCC_EA0_ATOMIC_LEVEL[120], TCC_EA0_ATOMIC_LEVEL[121], TCC_EA0_ATOMIC_LEVEL[122], TCC_EA0_ATOMIC_LEVEL[123], TCC_EA0_ATOMIC_LEVEL[124], TCC_EA0_ATOMIC_LEVEL[125], TCC_EA0_ATOMIC_LEVEL[126], TCC_EA0_ATOMIC_LEVEL[127], TCC_EA0_ATOMIC_LEVEL[12], TCC_EA0_ATOMIC_LEVEL[13], TCC_EA0_ATOMIC_LEVEL[14], TCC_EA0_ATOMIC_LEVEL[15], TCC_EA0_ATOMIC_LEVEL[16], TCC_EA0_ATOMIC_LEVEL[17], TCC_EA0_ATOMIC_LEVEL[18], TCC_EA0_ATOMIC_LEVEL[19], TCC_EA0_ATOMIC_LEVEL[1], TCC_EA0_ATOMIC_LEVEL[20], TCC_EA0_ATOMIC_LEVEL[21], TCC_EA0_ATOMIC_LEVEL[22], TCC_EA0_ATOMIC_LEVEL[23], TCC_EA0_ATOMIC_LEVEL[24], TCC_EA0_ATOMIC_LEVEL[25], TCC_EA0_ATOMIC_LEVEL[26], TCC_EA0_ATOMIC_LEVEL[27], TCC_EA0_ATOMIC_LEVEL[28], TCC_EA0_ATOMIC_LEVEL[29], TCC_EA0_ATOMIC_LEVEL[2], TCC_EA0_ATOMIC_LEVEL[30], TCC_EA0_ATOMIC_LEVEL[31], TCC_EA0_ATOMIC_LEVEL[32], TCC_EA0_ATOMIC_LEVEL[33], TCC_EA0_ATOMIC_LEVEL[34], TCC_EA0_ATOMIC_LEVEL[35], TCC_EA0_ATOMIC_LEVEL[36], TCC_EA0_ATOMIC_LEVEL[37], TCC_EA0_ATOMIC_LEVEL[38], TCC_EA0_ATOMIC_LEVEL[39], TCC_EA0_ATOMIC_LEVEL[3], TCC_EA0_ATOMIC_LEVEL[40], TCC_EA0_ATOMIC_LEVEL[41], TCC_EA0_ATOMIC_LEVEL[42], TCC_EA0_ATOMIC_LEVEL[43], TCC_EA0_ATOMIC_LEVEL[44], TCC_EA0_ATOMIC_LEVEL[45], TCC_EA0_ATOMIC_LEVEL[46], TCC_EA0_ATOMIC_LEVEL[47], TCC_EA0_ATOMIC_LEVEL[48], TCC_EA0_ATOMIC_LEVEL[49], TCC_EA0_ATOMIC_LEVEL[4], TCC_EA0_ATOMIC_LEVEL[50], TCC_EA0_ATOMIC_LEVEL[51], TCC_EA0_ATOMIC_LEVEL[52], TCC_EA0_ATOMIC_LEVEL[53], TCC_EA0_ATOMIC_LEVEL[54], TCC_EA0_ATOMIC_LEVEL[55], TCC_EA0_ATOMIC_LEVEL[56], TCC_EA0_ATOMIC_LEVEL[57], TCC_EA0_ATOMIC_LEVEL[58], TCC_EA0_ATOMIC_LEVEL[59], TCC_EA0_ATOMIC_LEVEL[5], TCC_EA0_ATOMIC_LEVEL[60], TCC_EA0_ATOMIC_LEVEL[61], TCC_EA0_ATOMIC_LEVEL[62], TCC_EA0_ATOMIC_LEVEL[63], TCC_EA0_ATOMIC_LEVEL[64], TCC_EA0_ATOMIC_LEVEL[65], TCC_EA0_ATOMIC_LEVEL[66], TCC_EA0_ATOMIC_LEVEL[67], TCC_EA0_ATOMIC_LEVEL[68], TCC_EA0_ATOMIC_LEVEL[69], TCC_EA0_ATOMIC_LEVEL[6], TCC_EA0_ATOMIC_LEVEL[70], TCC_EA0_ATOMIC_LEVEL[71], TCC_EA0_ATOMIC_LEVEL[72], TCC_EA0_ATOMIC_LEVEL[73], TCC_EA0_ATOMIC_LEVEL[74], TCC_EA0_ATOMIC_LEVEL[75], TCC_EA0_ATOMIC_LEVEL[76], TCC_EA0_ATOMIC_LEVEL[77], TCC_EA0_ATOMIC_LEVEL[78], TCC_EA0_ATOMIC_LEVEL[79], TCC_EA0_ATOMIC_LEVEL[7], TCC_EA0_ATOMIC_LEVEL[80], TCC_EA0_ATOMIC_LEVEL[81], TCC_EA0_ATOMIC_LEVEL[82], TCC_EA0_ATOMIC_LEVEL[83], TCC_EA0_ATOMIC_LEVEL[84], TCC_EA0_ATOMIC_LEVEL[85], TCC_EA0_ATOMIC_LEVEL[86], TCC_EA0_ATOMIC_LEVEL[87], TCC_EA0_ATOMIC_LEVEL[88], TCC_EA0_ATOMIC_LEVEL[89], TCC_EA0_ATOMIC_LEVEL[8], TCC_EA0_ATOMIC_LEVEL[90], TCC_EA0_ATOMIC_LEVEL[91], TCC_EA0_ATOMIC_LEVEL[92], TCC_EA0_ATOMIC_LEVEL[93], TCC_EA0_ATOMIC_LEVEL[94], TCC_EA0_ATOMIC_LEVEL[95], TCC_EA0_ATOMIC_LEVEL[96], TCC_EA0_ATOMIC_LEVEL[97], TCC_EA0_ATOMIC_LEVEL[98], TCC_EA0_ATOMIC_LEVEL[99], TCC_EA0_ATOMIC_LEVEL[9], TCC_EA0_RDREQ_LEVEL[0], TCC_EA0_RDREQ_LEVEL[100], TCC_EA0_RDREQ_LEVEL[101], TCC_EA0_RDREQ_LEVEL[102], TCC_EA0_RDREQ_LEVEL[103], TCC_EA0_RDREQ_LEVEL[104], TCC_EA0_RDREQ_LEVEL[105], TCC_EA0_RDREQ_LEVEL[106], TCC_EA0_RDREQ_LEVEL[107], TCC_EA0_RDREQ_LEVEL[108], TCC_EA0_RDREQ_LEVEL[109], TCC_EA0_RDREQ_LEVEL[10], TCC_EA0_RDREQ_LEVEL[110], TCC_EA0_RDREQ_LEVEL[111], TCC_EA0_RDREQ_LEVEL[112], TCC_EA0_RDREQ_LEVEL[113], TCC_EA0_RDREQ_LEVEL[114], TCC_EA0_RDREQ_LEVEL[115], TCC_EA0_RDREQ_LEVEL[116], TCC_EA0_RDREQ_LEVEL[117], TCC_EA0_RDREQ_LEVEL[118], TCC_EA0_RDREQ_LEVEL[119], TCC_EA0_RDREQ_LEVEL[11], TCC_EA0_RDREQ_LEVEL[120], TCC_EA0_RDREQ_LEVEL[121], TCC_EA0_RDREQ_LEVEL[122], TCC_EA0_RDREQ_LEVEL[123], TCC_EA0_RDREQ_LEVEL[124], TCC_EA0_RDREQ_LEVEL[125], TCC_EA0_RDREQ_LEVEL[126], TCC_EA0_RDREQ_LEVEL[127], TCC_EA0_RDREQ_LEVEL[12], TCC_EA0_RDREQ_LEVEL[13], TCC_EA0_RDREQ_LEVEL[14], TCC_EA0_RDREQ_LEVEL[15], TCC_EA0_RDREQ_LEVEL[16], TCC_EA0_RDREQ_LEVEL[17], TCC_EA0_RDREQ_LEVEL[18], TCC_EA0_RDREQ_LEVEL[19], TCC_EA0_RDREQ_LEVEL[1], TCC_EA0_RDREQ_LEVEL[20], TCC_EA0_RDREQ_LEVEL[21], TCC_EA0_RDREQ_LEVEL[22], TCC_EA0_RDREQ_LEVEL[23], TCC_EA0_RDREQ_LEVEL[24], TCC_EA0_RDREQ_LEVEL[25], TCC_EA0_RDREQ_LEVEL[26], TCC_EA0_RDREQ_LEVEL[27], TCC_EA0_RDREQ_LEVEL[28], TCC_EA0_RDREQ_LEVEL[29], TCC_EA0_RDREQ_LEVEL[2], TCC_EA0_RDREQ_LEVEL[30], TCC_EA0_RDREQ_LEVEL[31], TCC_EA0_RDREQ_LEVEL[32], TCC_EA0_RDREQ_LEVEL[33], TCC_EA0_RDREQ_LEVEL[34], TCC_EA0_RDREQ_LEVEL[35], TCC_EA0_RDREQ_LEVEL[36], TCC_EA0_RDREQ_LEVEL[37], TCC_EA0_RDREQ_LEVEL[38], TCC_EA0_RDREQ_LEVEL[39], TCC_EA0_RDREQ_LEVEL[3], TCC_EA0_RDREQ_LEVEL[40], TCC_EA0_RDREQ_LEVEL[41], TCC_EA0_RDREQ_LEVEL[42], TCC_EA0_RDREQ_LEVEL[43], TCC_EA0_RDREQ_LEVEL[44], TCC_EA0_RDREQ_LEVEL[45], TCC_EA0_RDREQ_LEVEL[46], TCC_EA0_RDREQ_LEVEL[47], TCC_EA0_RDREQ_LEVEL[48], TCC_EA0_RDREQ_LEVEL[49], TCC_EA0_RDREQ_LEVEL[4], TCC_EA0_RDREQ_LEVEL[50], TCC_EA0_RDREQ_LEVEL[51], TCC_EA0_RDREQ_LEVEL[52], TCC_EA0_RDREQ_LEVEL[53], TCC_EA0_RDREQ_LEVEL[54], TCC_EA0_RDREQ_LEVEL[55], TCC_EA0_RDREQ_LEVEL[56], TCC_EA0_RDREQ_LEVEL[57], TCC_EA0_RDREQ_LEVEL[58], TCC_EA0_RDREQ_LEVEL[59], TCC_EA0_RDREQ_LEVEL[5], TCC_EA0_RDREQ_LEVEL[60], TCC_EA0_RDREQ_LEVEL[61], TCC_EA0_RDREQ_LEVEL[62], TCC_EA0_RDREQ_LEVEL[63], TCC_EA0_RDREQ_LEVEL[64], TCC_EA0_RDREQ_LEVEL[65], TCC_EA0_RDREQ_LEVEL[66], TCC_EA0_RDREQ_LEVEL[67], TCC_EA0_RDREQ_LEVEL[68], TCC_EA0_RDREQ_LEVEL[69], TCC_EA0_RDREQ_LEVEL[6], TCC_EA0_RDREQ_LEVEL[70], TCC_EA0_RDREQ_LEVEL[71], TCC_EA0_RDREQ_LEVEL[72], TCC_EA0_RDREQ_LEVEL[73], TCC_EA0_RDREQ_LEVEL[74], TCC_EA0_RDREQ_LEVEL[75], TCC_EA0_RDREQ_LEVEL[76], TCC_EA0_RDREQ_LEVEL[77], TCC_EA0_RDREQ_LEVEL[78], TCC_EA0_RDREQ_LEVEL[79], TCC_EA0_RDREQ_LEVEL[7], TCC_EA0_RDREQ_LEVEL[80], TCC_EA0_RDREQ_LEVEL[81], TCC_EA0_RDREQ_LEVEL[82], TCC_EA0_RDREQ_LEVEL[83], TCC_EA0_RDREQ_LEVEL[84], TCC_EA0_RDREQ_LEVEL[85], TCC_EA0_RDREQ_LEVEL[86], TCC_EA0_RDREQ_LEVEL[87], TCC_EA0_RDREQ_LEVEL[88], TCC_EA0_RDREQ_LEVEL[89], TCC_EA0_RDREQ_LEVEL[8], TCC_EA0_RDREQ_LEVEL[90], TCC_EA0_RDREQ_LEVEL[91], TCC_EA0_RDREQ_LEVEL[92], TCC_EA0_RDREQ_LEVEL[93], TCC_EA0_RDREQ_LEVEL[94], TCC_EA0_RDREQ_LEVEL[95], TCC_EA0_RDREQ_LEVEL[96], TCC_EA0_RDREQ_LEVEL[97], TCC_EA0_RDREQ_LEVEL[98], TCC_EA0_RDREQ_LEVEL[99], TCC_EA0_RDREQ_LEVEL[9], TCC_TOO_MANY_EA_WRREQS_STALL[0], TCC_TOO_MANY_EA_WRREQS_STALL[100], TCC_TOO_MANY_EA_WRREQS_STALL[101], TCC_TOO_MANY_EA_WRREQS_STALL[102], TCC_TOO_MANY_EA_WRREQS_STALL[103], TCC_TOO_MANY_EA_WRREQS_STALL[104], TCC_TOO_MANY_EA_WRREQS_STALL[105], TCC_TOO_MANY_EA_WRREQS_STALL[106], TCC_TOO_MANY_EA_WRREQS_STALL[107], TCC_TOO_MANY_EA_WRREQS_STALL[108], TCC_TOO_MANY_EA_WRREQS_STALL[109], TCC_TOO_MANY_EA_WRREQS_STALL[10], TCC_TOO_MANY_EA_WRREQS_STALL[110], TCC_TOO_MANY_EA_WRREQS_STALL[111], TCC_TOO_MANY_EA_WRREQS_STALL[112], TCC_TOO_MANY_EA_WRREQS_STALL[113], TCC_TOO_MANY_EA_WRREQS_STALL[114], TCC_TOO_MANY_EA_WRREQS_STALL[115], TCC_TOO_MANY_EA_WRREQS_STALL[116], TCC_TOO_MANY_EA_WRREQS_STALL[117], TCC_TOO_MANY_EA_WRREQS_STALL[118], TCC_TOO_MANY_EA_WRREQS_STALL[119], TCC_TOO_MANY_EA_WRREQS_STALL[11], TCC_TOO_MANY_EA_WRREQS_STALL[120], TCC_TOO_MANY_EA_WRREQS_STALL[121], TCC_TOO_MANY_EA_WRREQS_STALL[122], TCC_TOO_MANY_EA_WRREQS_STALL[123], TCC_TOO_MANY_EA_WRREQS_STALL[124], TCC_TOO_MANY_EA_WRREQS_STALL[125], TCC_TOO_MANY_EA_WRREQS_STALL[126], TCC_TOO_MANY_EA_WRREQS_STALL[127], TCC_TOO_MANY_EA_WRREQS_STALL[12], TCC_TOO_MANY_EA_WRREQS_STALL[13], TCC_TOO_MANY_EA_WRREQS_STALL[14], TCC_TOO_MANY_EA_WRREQS_STALL[15], TCC_TOO_MANY_EA_WRREQS_STALL[16], TCC_TOO_MANY_EA_WRREQS_STALL[17], TCC_TOO_MANY_EA_WRREQS_STALL[18], TCC_TOO_MANY_EA_WRREQS_STALL[19], TCC_TOO_MANY_EA_WRREQS_STALL[1], TCC_TOO_MANY_EA_WRREQS_STALL[20], TCC_TOO_MANY_EA_WRREQS_STALL[21], TCC_TOO_MANY_EA_WRREQS_STALL[22], TCC_TOO_MANY_EA_WRREQS_STALL[23], TCC_TOO_MANY_EA_WRREQS_STALL[24], TCC_TOO_MANY_EA_WRREQS_STALL[25], TCC_TOO_MANY_EA_WRREQS_STALL[26], TCC_TOO_MANY_EA_WRREQS_STALL[27], TCC_TOO_MANY_EA_WRREQS_STALL[28], TCC_TOO_MANY_EA_WRREQS_STALL[29], TCC_TOO_MANY_EA_WRREQS_STALL[2], TCC_TOO_MANY_EA_WRREQS_STALL[30], TCC_TOO_MANY_EA_WRREQS_STALL[31], TCC_TOO_MANY_EA_WRREQS_STALL[32], TCC_TOO_MANY_EA_WRREQS_STALL[33], TCC_TOO_MANY_EA_WRREQS_STALL[34], TCC_TOO_MANY_EA_WRREQS_STALL[35], TCC_TOO_MANY_EA_WRREQS_STALL[36], TCC_TOO_MANY_EA_WRREQS_STALL[37], TCC_TOO_MANY_EA_WRREQS_STALL[38], TCC_TOO_MANY_EA_WRREQS_STALL[39], TCC_TOO_MANY_EA_WRREQS_STALL[3], TCC_TOO_MANY_EA_WRREQS_STALL[40], TCC_TOO_MANY_EA_WRREQS_STALL[41], TCC_TOO_MANY_EA_WRREQS_STALL[42], TCC_TOO_MANY_EA_WRREQS_STALL[43], TCC_TOO_MANY_EA_WRREQS_STALL[44], TCC_TOO_MANY_EA_WRREQS_STALL[45], TCC_TOO_MANY_EA_WRREQS_STALL[46], TCC_TOO_MANY_EA_WRREQS_STALL[47], TCC_TOO_MANY_EA_WRREQS_STALL[48], TCC_TOO_MANY_EA_WRREQS_STALL[49], TCC_TOO_MANY_EA_WRREQS_STALL[4], TCC_TOO_MANY_EA_WRREQS_STALL[50], TCC_TOO_MANY_EA_WRREQS_STALL[51], TCC_TOO_MANY_EA_WRREQS_STALL[52], TCC_TOO_MANY_EA_WRREQS_STALL[53], TCC_TOO_MANY_EA_WRREQS_STALL[54], TCC_TOO_MANY_EA_WRREQS_STALL[55], TCC_TOO_MANY_EA_WRREQS_STALL[56], TCC_TOO_MANY_EA_WRREQS_STALL[57], TCC_TOO_MANY_EA_WRREQS_STALL[58], TCC_TOO_MANY_EA_WRREQS_STALL[59], TCC_TOO_MANY_EA_WRREQS_STALL[5], TCC_TOO_MANY_EA_WRREQS_STALL[60], TCC_TOO_MANY_EA_WRREQS_STALL[61], TCC_TOO_MANY_EA_WRREQS_STALL[62], TCC_TOO_MANY_EA_WRREQS_STALL[63], TCC_TOO_MANY_EA_WRREQS_STALL[64], TCC_TOO_MANY_EA_WRREQS_STALL[65], TCC_TOO_MANY_EA_WRREQS_STALL[66], TCC_TOO_MANY_EA_WRREQS_STALL[67], TCC_TOO_MANY_EA_WRREQS_STALL[68], TCC_TOO_MANY_EA_WRREQS_STALL[69], TCC_TOO_MANY_EA_WRREQS_STALL[6], TCC_TOO_MANY_EA_WRREQS_STALL[70], TCC_TOO_MANY_EA_WRREQS_STALL[71], TCC_TOO_MANY_EA_WRREQS_STALL[72], TCC_TOO_MANY_EA_WRREQS_STALL[73], TCC_TOO_MANY_EA_WRREQS_STALL[74], TCC_TOO_MANY_EA_WRREQS_STALL[75], TCC_TOO_MANY_EA_WRREQS_STALL[76], TCC_TOO_MANY_EA_WRREQS_STALL[77], TCC_TOO_MANY_EA_WRREQS_STALL[78], TCC_TOO_MANY_EA_WRREQS_STALL[79], TCC_TOO_MANY_EA_WRREQS_STALL[7], TCC_TOO_MANY_EA_WRREQS_STALL[80], TCC_TOO_MANY_EA_WRREQS_STALL[81], TCC_TOO_MANY_EA_WRREQS_STALL[82], TCC_TOO_MANY_EA_WRREQS_STALL[83], TCC_TOO_MANY_EA_WRREQS_STALL[84], TCC_TOO_MANY_EA_WRREQS_STALL[85], TCC_TOO_MANY_EA_WRREQS_STALL[86], TCC_TOO_MANY_EA_WRREQS_STALL[87], TCC_TOO_MANY_EA_WRREQS_STALL[88], TCC_TOO_MANY_EA_WRREQS_STALL[89], TCC_TOO_MANY_EA_WRREQS_STALL[8], TCC_TOO_MANY_EA_WRREQS_STALL[90], TCC_TOO_MANY_EA_WRREQS_STALL[91], TCC_TOO_MANY_EA_WRREQS_STALL[92], TCC_TOO_MANY_EA_WRREQS_STALL[93], TCC_TOO_MANY_EA_WRREQS_STALL[94], TCC_TOO_MANY_EA_WRREQS_STALL[95], TCC_TOO_MANY_EA_WRREQS_STALL[96], TCC_TOO_MANY_EA_WRREQS_STALL[97], TCC_TOO_MANY_EA_WRREQS_STALL[98], TCC_TOO_MANY_EA_WRREQS_STALL[99], TCC_TOO_MANY_EA_WRREQS_STALL[9], TCP_GATE_EN2_sum, TCP_TCC_RW_WRITE_REQ_sum, TCP_TCC_UC_ATOMIC_REQ_sum, TCP_TOTAL_CACHE_ACCESSES_sum, TD_TD_BUSY_sum]. Found: [CPC_CPC_TCIU_IDLE, CPC_TG_SEND, CPF_CPF_TCIU_IDLE, SPI_CS0_BUSY, SPI_CS1_BUSY, SPI_CS2_BUSY, SPI_CS3_BUSY, SQ_INSTS_LDS, SQ_INSTS_LDS_LOAD_BANDWIDTH, SQ_INSTS_VALU_ADD_F16, SQ_INSTS_VALU_FMA_F16, SQ_LDS_IDX_ACTIVE, SQ_LEVEL_WAVES, SQ_WAVE_CYCLES, TA_BUFFER_ATOMIC_WAVEFRONTS_sum, TA_FLAT_ATOMIC_WAVEFRONTS_sum, TCC_BUBBLE_sum, TCC_EA0_ATOMIC_LEVEL[0], TCC_EA0_ATOMIC_LEVEL[100], TCC_EA0_ATOMIC_LEVEL[101], TCC_EA0_ATOMIC_LEVEL[102], TCC_EA0_ATOMIC_LEVEL[103], TCC_EA0_ATOMIC_LEVEL[104], TCC_EA0_ATOMIC_LEVEL[105], TCC_EA0_ATOMIC_LEVEL[106], TCC_EA0_ATOMIC_LEVEL[107], TCC_EA0_ATOMIC_LEVEL[108], TCC_EA0_ATOMIC_LEVEL[109], TCC_EA0_ATOMIC_LEVEL[10], TCC_EA0_ATOMIC_LEVEL[110], TCC_EA0_ATOMIC_LEVEL[111], TCC_EA0_ATOMIC_LEVEL[112], TCC_EA0_ATOMIC_LEVEL[113], TCC_EA0_ATOMIC_LEVEL[114], TCC_EA0_ATOMIC_LEVEL[115], TCC_EA0_ATOMIC_LEVEL[116], TCC_EA0_ATOMIC_LEVEL[117], TCC_EA0_ATOMIC_LEVEL[118], TCC_EA0_ATOMIC_LEVEL[119], TCC_EA0_ATOMIC_LEVEL[11], TCC_EA0_ATOMIC_LEVEL[120], TCC_EA0_ATOMIC_LEVEL[121], TCC_EA0_ATOMIC_LEVEL[122], TCC_EA0_ATOMIC_LEVEL[123], TCC_EA0_ATOMIC_LEVEL[124], TCC_EA0_ATOMIC_LEVEL[125], TCC_EA0_ATOMIC_LEVEL[126], TCC_EA0_ATOMIC_LEVEL[127], TCC_EA0_ATOMIC_LEVEL[12], TCC_EA0_ATOMIC_LEVEL[13], TCC_EA0_ATOMIC_LEVEL[14], TCC_EA0_ATOMIC_LEVEL[15], TCC_EA0_ATOMIC_LEVEL[16], TCC_EA0_ATOMIC_LEVEL[17], TCC_EA0_ATOMIC_LEVEL[18], TCC_EA0_ATOMIC_LEVEL[19], TCC_EA0_ATOMIC_LEVEL[1], TCC_EA0_ATOMIC_LEVEL[20], TCC_EA0_ATOMIC_LEVEL[21], TCC_EA0_ATOMIC_LEVEL[22], TCC_EA0_ATOMIC_LEVEL[23], TCC_EA0_ATOMIC_LEVEL[24], TCC_EA0_ATOMIC_LEVEL[25], TCC_EA0_ATOMIC_LEVEL[26], TCC_EA0_ATOMIC_LEVEL[27], TCC_EA0_ATOMIC_LEVEL[28], TCC_EA0_ATOMIC_LEVEL[29], TCC_EA0_ATOMIC_LEVEL[2], TCC_EA0_ATOMIC_LEVEL[30], TCC_EA0_ATOMIC_LEVEL[31], TCC_EA0_ATOMIC_LEVEL[32], TCC_EA0_ATOMIC_LEVEL[33], TCC_EA0_ATOMIC_LEVEL[34], TCC_EA0_ATOMIC_LEVEL[35], TCC_EA0_ATOMIC_LEVEL[36], TCC_EA0_ATOMIC_LEVEL[37], TCC_EA0_ATOMIC_LEVEL[38], TCC_EA0_ATOMIC_LEVEL[39], TCC_EA0_ATOMIC_LEVEL[3], TCC_EA0_ATOMIC_LEVEL[40], TCC_EA0_ATOMIC_LEVEL[41], TCC_EA0_ATOMIC_LEVEL[42], TCC_EA0_ATOMIC_LEVEL[43], TCC_EA0_ATOMIC_LEVEL[44], TCC_EA0_ATOMIC_LEVEL[45], TCC_EA0_ATOMIC_LEVEL[46], TCC_EA0_ATOMIC_LEVEL[47], TCC_EA0_ATOMIC_LEVEL[48], TCC_EA0_ATOMIC_LEVEL[49], TCC_EA0_ATOMIC_LEVEL[4], TCC_EA0_ATOMIC_LEVEL[50], TCC_EA0_ATOMIC_LEVEL[51], TCC_EA0_ATOMIC_LEVEL[52], TCC_EA0_ATOMIC_LEVEL[53], TCC_EA0_ATOMIC_LEVEL[54], TCC_EA0_ATOMIC_LEVEL[55], TCC_EA0_ATOMIC_LEVEL[56], TCC_EA0_ATOMIC_LEVEL[57], TCC_EA0_ATOMIC_LEVEL[58], TCC_EA0_ATOMIC_LEVEL[59], TCC_EA0_ATOMIC_LEVEL[5], TCC_EA0_ATOMIC_LEVEL[60], TCC_EA0_ATOMIC_LEVEL[61], TCC_EA0_ATOMIC_LEVEL[62], TCC_EA0_ATOMIC_LEVEL[63], TCC_EA0_ATOMIC_LEVEL[64], TCC_EA0_ATOMIC_LEVEL[65], TCC_EA0_ATOMIC_LEVEL[66], TCC_EA0_ATOMIC_LEVEL[67], TCC_EA0_ATOMIC_LEVEL[68], TCC_EA0_ATOMIC_LEVEL[69], TCC_EA0_ATOMIC_LEVEL[6], TCC_EA0_ATOMIC_LEVEL[70], TCC_EA0_ATOMIC_LEVEL[71], TCC_EA0_ATOMIC_LEVEL[72], TCC_EA0_ATOMIC_LEVEL[73], TCC_EA0_ATOMIC_LEVEL[74], TCC_EA0_ATOMIC_LEVEL[75], TCC_EA0_ATOMIC_LEVEL[76], TCC_EA0_ATOMIC_LEVEL[77], TCC_EA0_ATOMIC_LEVEL[78], TCC_EA0_ATOMIC_LEVEL[79], TCC_EA0_ATOMIC_LEVEL[7], TCC_EA0_ATOMIC_LEVEL[80], TCC_EA0_ATOMIC_LEVEL[81], TCC_EA0_ATOMIC_LEVEL[82], TCC_EA0_ATOMIC_LEVEL[83], TCC_EA0_ATOMIC_LEVEL[84], TCC_EA0_ATOMIC_LEVEL[85], TCC_EA0_ATOMIC_LEVEL[86], TCC_EA0_ATOMIC_LEVEL[87], TCC_EA0_ATOMIC_LEVEL[88], TCC_EA0_ATOMIC_LEVEL[89], TCC_EA0_ATOMIC_LEVEL[8], TCC_EA0_ATOMIC_LEVEL[90], TCC_EA0_ATOMIC_LEVEL[91], TCC_EA0_ATOMIC_LEVEL[92], TCC_EA0_ATOMIC_LEVEL[93], TCC_EA0_ATOMIC_LEVEL[94], TCC_EA0_ATOMIC_LEVEL[95], TCC_EA0_ATOMIC_LEVEL[96], TCC_EA0_ATOMIC_LEVEL[97], TCC_EA0_ATOMIC_LEVEL[98], TCC_EA0_ATOMIC_LEVEL[99], TCC_EA0_ATOMIC_LEVEL[9], TCC_EA0_RDREQ_LEVEL[0], TCC_EA0_RDREQ_LEVEL[100], TCC_EA0_RDREQ_LEVEL[101], TCC_EA0_RDREQ_LEVEL[102], TCC_EA0_RDREQ_LEVEL[103], TCC_EA0_RDREQ_LEVEL[104], TCC_EA0_RDREQ_LEVEL[105], TCC_EA0_RDREQ_LEVEL[106], TCC_EA0_RDREQ_LEVEL[107], TCC_EA0_RDREQ_LEVEL[108], TCC_EA0_RDREQ_LEVEL[109], TCC_EA0_RDREQ_LEVEL[10], TCC_EA0_RDREQ_LEVEL[110], TCC_EA0_RDREQ_LEVEL[111], TCC_EA0_RDREQ_LEVEL[112], TCC_EA0_RDREQ_LEVEL[113], TCC_EA0_RDREQ_LEVEL[114], TCC_EA0_RDREQ_LEVEL[115], TCC_EA0_RDREQ_LEVEL[116], TCC_EA0_RDREQ_LEVEL[117], TCC_EA0_RDREQ_LEVEL[118], TCC_EA0_RDREQ_LEVEL[119], TCC_EA0_RDREQ_LEVEL[11], TCC_EA0_RDREQ_LEVEL[120], TCC_EA0_RDREQ_LEVEL[121], TCC_EA0_RDREQ_LEVEL[122], TCC_EA0_RDREQ_LEVEL[123], TCC_EA0_RDREQ_LEVEL[124], TCC_EA0_RDREQ_LEVEL[125], TCC_EA0_RDREQ_LEVEL[126], TCC_EA0_RDREQ_LEVEL[127], TCC_EA0_RDREQ_LEVEL[12], TCC_EA0_RDREQ_LEVEL[13], TCC_EA0_RDREQ_LEVEL[14], TCC_EA0_RDREQ_LEVEL[15], TCC_EA0_RDREQ_LEVEL[16], TCC_EA0_RDREQ_LEVEL[17], TCC_EA0_RDREQ_LEVEL[18], TCC_EA0_RDREQ_LEVEL[19], TCC_EA0_RDREQ_LEVEL[1], TCC_EA0_RDREQ_LEVEL[20], TCC_EA0_RDREQ_LEVEL[21], TCC_EA0_RDREQ_LEVEL[22], TCC_EA0_RDREQ_LEVEL[23], TCC_EA0_RDREQ_LEVEL[24], TCC_EA0_RDREQ_LEVEL[25], TCC_EA0_RDREQ_LEVEL[26], TCC_EA0_RDREQ_LEVEL[27], TCC_EA0_RDREQ_LEVEL[28], TCC_EA0_RDREQ_LEVEL[29], TCC_EA0_RDREQ_LEVEL[2], TCC_EA0_RDREQ_LEVEL[30], TCC_EA0_RDREQ_LEVEL[31], TCC_EA0_RDREQ_LEVEL[32], TCC_EA0_RDREQ_LEVEL[33], TCC_EA0_RDREQ_LEVEL[34], TCC_EA0_RDREQ_LEVEL[35], TCC_EA0_RDREQ_LEVEL[36], TCC_EA0_RDREQ_LEVEL[37], TCC_EA0_RDREQ_LEVEL[38], TCC_EA0_RDREQ_LEVEL[39], TCC_EA0_RDREQ_LEVEL[3], TCC_EA0_RDREQ_LEVEL[40], TCC_EA0_RDREQ_LEVEL[41], TCC_EA0_RDREQ_LEVEL[42], TCC_EA0_RDREQ_LEVEL[43], TCC_EA0_RDREQ_LEVEL[44], TCC_EA0_RDREQ_LEVEL[45], TCC_EA0_RDREQ_LEVEL[46], TCC_EA0_RDREQ_LEVEL[47], TCC_EA0_RDREQ_LEVEL[48], TCC_EA0_RDREQ_LEVEL[49], TCC_EA0_RDREQ_LEVEL[4], TCC_EA0_RDREQ_LEVEL[50], TCC_EA0_RDREQ_LEVEL[51], TCC_EA0_RDREQ_LEVEL[52], TCC_EA0_RDREQ_LEVEL[53], TCC_EA0_RDREQ_LEVEL[54], TCC_EA0_RDREQ_LEVEL[55], TCC_EA0_RDREQ_LEVEL[56], TCC_EA0_RDREQ_LEVEL[57], TCC_EA0_RDREQ_LEVEL[58], TCC_EA0_RDREQ_LEVEL[59], TCC_EA0_RDREQ_LEVEL[5], TCC_EA0_RDREQ_LEVEL[60], TCC_EA0_RDREQ_LEVEL[61], TCC_EA0_RDREQ_LEVEL[62], TCC_EA0_RDREQ_LEVEL[63], TCC_EA0_RDREQ_LEVEL[64], TCC_EA0_RDREQ_LEVEL[65], TCC_EA0_RDREQ_LEVEL[66], TCC_EA0_RDREQ_LEVEL[67], TCC_EA0_RDREQ_LEVEL[68], TCC_EA0_RDREQ_LEVEL[69], TCC_EA0_RDREQ_LEVEL[6], TCC_EA0_RDREQ_LEVEL[70], TCC_EA0_RDREQ_LEVEL[71], TCC_EA0_RDREQ_LEVEL[72], TCC_EA0_RDREQ_LEVEL[73], TCC_EA0_RDREQ_LEVEL[74], TCC_EA0_RDREQ_LEVEL[75], TCC_EA0_RDREQ_LEVEL[76], TCC_EA0_RDREQ_LEVEL[77], TCC_EA0_RDREQ_LEVEL[78], TCC_EA0_RDREQ_LEVEL[79], TCC_EA0_RDREQ_LEVEL[7], TCC_EA0_RDREQ_LEVEL[80], TCC_EA0_RDREQ_LEVEL[81], TCC_EA0_RDREQ_LEVEL[82], TCC_EA0_RDREQ_LEVEL[83], TCC_EA0_RDREQ_LEVEL[84], TCC_EA0_RDREQ_LEVEL[85], TCC_EA0_RDREQ_LEVEL[86], TCC_EA0_RDREQ_LEVEL[87], TCC_EA0_RDREQ_LEVEL[88], TCC_EA0_RDREQ_LEVEL[89], TCC_EA0_RDREQ_LEVEL[8], TCC_EA0_RDREQ_LEVEL[90], TCC_EA0_RDREQ_LEVEL[91], TCC_EA0_RDREQ_LEVEL[92], TCC_EA0_RDREQ_LEVEL[93], TCC_EA0_RDREQ_LEVEL[94], TCC_EA0_RDREQ_LEVEL[95], TCC_EA0_RDREQ_LEVEL[96], TCC_EA0_RDREQ_LEVEL[97], TCC_EA0_RDREQ_LEVEL[98], TCC_EA0_RDREQ_LEVEL[99], TCC_EA0_RDREQ_LEVEL[9], TCC_TOO_MANY_EA_WRREQS_STALL[0], TCC_TOO_MANY_EA_WRREQS_STALL[100], TCC_TOO_MANY_EA_WRREQS_STALL[101], TCC_TOO_MANY_EA_WRREQS_STALL[102], TCC_TOO_MANY_EA_WRREQS_STALL[103], TCC_TOO_MANY_EA_WRREQS_STALL[104], TCC_TOO_MANY_EA_WRREQS_STALL[105], TCC_TOO_MANY_EA_WRREQS_STALL[106], TCC_TOO_MANY_EA_WRREQS_STALL[107], TCC_TOO_MANY_EA_WRREQS_STALL[108], TCC_TOO_MANY_EA_WRREQS_STALL[109], TCC_TOO_MANY_EA_WRREQS_STALL[10], TCC_TOO_MANY_EA_WRREQS_STALL[110], TCC_TOO_MANY_EA_WRREQS_STALL[111], TCC_TOO_MANY_EA_WRREQS_STALL[112], TCC_TOO_MANY_EA_WRREQS_STALL[113], TCC_TOO_MANY_EA_WRREQS_STALL[114], TCC_TOO_MANY_EA_WRREQS_STALL[115], TCC_TOO_MANY_EA_WRREQS_STALL[116], TCC_TOO_MANY_EA_WRREQS_STALL[117], TCC_TOO_MANY_EA_WRREQS_STALL[118], TCC_TOO_MANY_EA_WRREQS_STALL[119], TCC_TOO_MANY_EA_WRREQS_STALL[11], TCC_TOO_MANY_EA_WRREQS_STALL[120], TCC_TOO_MANY_EA_WRREQS_STALL[121], TCC_TOO_MANY_EA_WRREQS_STALL[122], TCC_TOO_MANY_EA_WRREQS_STALL[123], TCC_TOO_MANY_EA_WRREQS_STALL[124], TCC_TOO_MANY_EA_WRREQS_STALL[125], TCC_TOO_MANY_EA_WRREQS_STALL[126], TCC_TOO_MANY_EA_WRREQS_STALL[127], TCC_TOO_MANY_EA_WRREQS_STALL[12], TCC_TOO_MANY_EA_WRREQS_STALL[13], TCC_TOO_MANY_EA_WRREQS_STALL[14], TCC_TOO_MANY_EA_WRREQS_STALL[15], TCC_TOO_MANY_EA_WRREQS_STALL[16], TCC_TOO_MANY_EA_WRREQS_STALL[17], TCC_TOO_MANY_EA_WRREQS_STALL[18], TCC_TOO_MANY_EA_WRREQS_STALL[19], TCC_TOO_MANY_EA_WRREQS_STALL[1], TCC_TOO_MANY_EA_WRREQS_STALL[20], TCC_TOO_MANY_EA_WRREQS_STALL[21], TCC_TOO_MANY_EA_WRREQS_STALL[22], TCC_TOO_MANY_EA_WRREQS_STALL[23], TCC_TOO_MANY_EA_WRREQS_STALL[24], TCC_TOO_MANY_EA_WRREQS_STALL[25], TCC_TOO_MANY_EA_WRREQS_STALL[26], TCC_TOO_MANY_EA_WRREQS_STALL[27], TCC_TOO_MANY_EA_WRREQS_STALL[28], TCC_TOO_MANY_EA_WRREQS_STALL[29], TCC_TOO_MANY_EA_WRREQS_STALL[2], TCC_TOO_MANY_EA_WRREQS_STALL[30], TCC_TOO_MANY_EA_WRREQS_STALL[31], TCC_TOO_MANY_EA_WRREQS_STALL[32], TCC_TOO_MANY_EA_WRREQS_STALL[33], TCC_TOO_MANY_EA_WRREQS_STALL[34], TCC_TOO_MANY_EA_WRREQS_STALL[35], TCC_TOO_MANY_EA_WRREQS_STALL[36], TCC_TOO_MANY_EA_WRREQS_STALL[37], TCC_TOO_MANY_EA_WRREQS_STALL[38], TCC_TOO_MANY_EA_WRREQS_STALL[39], TCC_TOO_MANY_EA_WRREQS_STALL[3], TCC_TOO_MANY_EA_WRREQS_STALL[40], TCC_TOO_MANY_EA_WRREQS_STALL[41], TCC_TOO_MANY_EA_WRREQS_STALL[42], TCC_TOO_MANY_EA_WRREQS_STALL[43], TCC_TOO_MANY_EA_WRREQS_STALL[44], TCC_TOO_MANY_EA_WRREQS_STALL[45], TCC_TOO_MANY_EA_WRREQS_STALL[46], TCC_TOO_MANY_EA_WRREQS_STALL[47], TCC_TOO_MANY_EA_WRREQS_STALL[48], TCC_TOO_MANY_EA_WRREQS_STALL[49], TCC_TOO_MANY_EA_WRREQS_STALL[4], TCC_TOO_MANY_EA_WRREQS_STALL[50], TCC_TOO_MANY_EA_WRREQS_STALL[51], TCC_TOO_MANY_EA_WRREQS_STALL[52], TCC_TOO_MANY_EA_WRREQS_STALL[53], TCC_TOO_MANY_EA_WRREQS_STALL[54], TCC_TOO_MANY_EA_WRREQS_STALL[55], TCC_TOO_MANY_EA_WRREQS_STALL[56], TCC_TOO_MANY_EA_WRREQS_STALL[57], TCC_TOO_MANY_EA_WRREQS_STALL[58], TCC_TOO_MANY_EA_WRREQS_STALL[59], TCC_TOO_MANY_EA_WRREQS_STALL[5], TCC_TOO_MANY_EA_WRREQS_STALL[60], TCC_TOO_MANY_EA_WRREQS_STALL[61], TCC_TOO_MANY_EA_WRREQS_STALL[62], TCC_TOO_MANY_EA_WRREQS_STALL[63], TCC_TOO_MANY_EA_WRREQS_STALL[64], TCC_TOO_MANY_EA_WRREQS_STALL[65], TCC_TOO_MANY_EA_WRREQS_STALL[66], TCC_TOO_MANY_EA_WRREQS_STALL[67], TCC_TOO_MANY_EA_WRREQS_STALL[68], TCC_TOO_MANY_EA_WRREQS_STALL[69], TCC_TOO_MANY_EA_WRREQS_STALL[6], TCC_TOO_MANY_EA_WRREQS_STALL[70], TCC_TOO_MANY_EA_WRREQS_STALL[71], TCC_TOO_MANY_EA_WRREQS_STALL[72], TCC_TOO_MANY_EA_WRREQS_STALL[73], TCC_TOO_MANY_EA_WRREQS_STALL[74], TCC_TOO_MANY_EA_WRREQS_STALL[75], TCC_TOO_MANY_EA_WRREQS_STALL[76], TCC_TOO_MANY_EA_WRREQS_STALL[77], TCC_TOO_MANY_EA_WRREQS_STALL[78], TCC_TOO_MANY_EA_WRREQS_STALL[79], TCC_TOO_MANY_EA_WRREQS_STALL[7], TCC_TOO_MANY_EA_WRREQS_STALL[80], TCC_TOO_MANY_EA_WRREQS_STALL[81], TCC_TOO_MANY_EA_WRREQS_STALL[82], TCC_TOO_MANY_EA_WRREQS_STALL[83], TCC_TOO_MANY_EA_WRREQS_STALL[84], TCC_TOO_MANY_EA_WRREQS_STALL[85], TCC_TOO_MANY_EA_WRREQS_STALL[86], TCC_TOO_MANY_EA_WRREQS_STALL[87], TCC_TOO_MANY_EA_WRREQS_STALL[88], TCC_TOO_MANY_EA_WRREQS_STALL[89], TCC_TOO_MANY_EA_WRREQS_STALL[8], TCC_TOO_MANY_EA_WRREQS_STALL[90], TCC_TOO_MANY_EA_WRREQS_STALL[91], TCC_TOO_MANY_EA_WRREQS_STALL[92], TCC_TOO_MANY_EA_WRREQS_STALL[93], TCC_TOO_MANY_EA_WRREQS_STALL[94], TCC_TOO_MANY_EA_WRREQS_STALL[95], TCC_TOO_MANY_EA_WRREQS_STALL[96], TCC_TOO_MANY_EA_WRREQS_STALL[97], TCC_TOO_MANY_EA_WRREQS_STALL[98], TCC_TOO_MANY_EA_WRREQS_STALL[99], TCC_TOO_MANY_EA_WRREQS_STALL[9], TCP_GATE_EN2_sum, TCP_TCC_RW_WRITE_REQ_sum, TCP_TCC_UC_ATOMIC_REQ_sum, TCP_TOTAL_CACHE_ACCESSES_sum, TD_TD_BUSY_sum] + |-> [rocprofv3] E20250328 22:44:01.683144 139667039954944 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15765_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:01.689887 139667039954944 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15765_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:01.693434 139667039954944 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15765_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.txt, the time it takes was 0 m 0.5417661666870117 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.txt is 0 m 0.580467700958252 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_0.txt +pmc file: pmc_perf_0.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_0.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_0.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_0.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_0.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:02.244642 140133276805120 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15772_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:02.251155 140133276805120 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15772_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:02.254238 140133276805120 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15772_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_0.txt, the time it takes was 0 m 0.520763635635376 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_0.txt is 0 m 0.5509796142578125 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_1.txt +pmc file: pmc_perf_1.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_1.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_1.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_1.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_1.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:02.774198 139877934254080 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15779_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:02.780803 139877934254080 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15779_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:02.783965 139877934254080 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15779_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_1.txt, the time it takes was 0 m 0.49741554260253906 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_1.txt is 0 m 0.5275735855102539 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_2.txt +pmc file: pmc_perf_2.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_2.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_2.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_2.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_2.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:03.328143 140410203478016 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15786_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:03.334680 140410203478016 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15786_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:03.337819 140410203478016 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15786_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_2.txt, the time it takes was 0 m 0.5256781578063965 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_2.txt is 0 m 0.5558264255523682 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_3.txt +pmc file: pmc_perf_3.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_3.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_3.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_3.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_3.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:03.877474 139773391017984 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15793_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:03.884064 139773391017984 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15793_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:03.887175 139773391017984 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15793_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_3.txt, the time it takes was 0 m 0.5174272060394287 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_3.txt is 0 m 0.5471975803375244 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_4.txt +pmc file: pmc_perf_4.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_4.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_4.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_4.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_4.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:04.425381 139659083270144 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15800_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:04.431890 139659083270144 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15800_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:04.434992 139659083270144 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15800_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_4.txt, the time it takes was 0 m 0.5173399448394775 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_4.txt is 0 m 0.5455985069274902 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_5.txt +pmc file: pmc_perf_5.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_5.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_5.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_5.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_5.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:04.975746 139690974885888 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15807_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:04.982230 139690974885888 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15807_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:04.985304 139690974885888 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15807_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_5.txt, the time it takes was 0 m 0.5242176055908203 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_5.txt is 0 m 0.5536882877349854 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_6.txt +pmc file: pmc_perf_6.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_6.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_6.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_6.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_6.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:05.528937 139905476130816 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15814_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:05.535486 139905476130816 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15814_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:05.538574 139905476130816 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15814_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_6.txt, the time it takes was 0 m 0.5223171710968018 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_6.txt is 0 m 0.5513536930084229 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_7.txt +pmc file: pmc_perf_7.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_7.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_7.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_7.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_7.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:06.078683 140554574170112 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15821_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:06.085252 140554574170112 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15821_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:06.088343 140554574170112 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15821_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_7.txt, the time it takes was 0 m 0.5185859203338623 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_7.txt is 0 m 0.5476455688476562 sec +finished "run_profiling" and finished rocprof's workload, time taken was 0 m 7.149999380111694 sec +[profiling] performing post-processing using rocprofv3 profiler +Successfully joined GPU_ID in pmc_perf.csv +Successfully joined Grid_Size in pmc_perf.csv +Successfully joined Workgroup_Size in pmc_perf.csv +Successfully joined LDS_Per_Workgroup in pmc_perf.csv +Successfully joined Scratch_Per_Workitem in pmc_perf.csv +Successfully joined SGPR in pmc_perf.csv +Successfully joined Arch_VGPR in pmc_perf.csv +Successfully joined Accum_VGPR in pmc_perf.csv +time taken for "post_processing" was 0 seconds +[profiling] perform SoC post processing for gfx950 +[roofline] Skipping roofline diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_IFETCH_LEVEL.txt b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_IFETCH_LEVEL.txt new file mode 100644 index 0000000000..93204ab025 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_IFETCH_LEVEL.txt @@ -0,0 +1,5 @@ +pmc: SQ_IFETCH_LEVEL SQ_IFETCH_LEVEL_ACCUM SQ_VMEM_WR_TA_DATA_FIFO_FULL SQC_ICACHE_MISSES_DUPLICATE SQC_ICACHE_MISSES SQ_INSTS_VALU_MFMA_MOPS_I8 SQC_DCACHE_HITS SQ_INSTS_VALU_FMA_F64 TA_ADDR_STALLED_BY_TC_CYCLES_sum TA_FLAT_WAVEFRONTS_sum TD_TC_STALL_sum TD_ATOMIC_WAVEFRONT_sum TCP_TCC_RW_ATOMIC_REQ_sum TCP_TOTAL_WRITE_sum TCP_GATE_EN1_sum TCP_TCC_NC_ATOMIC_REQ_sum TCC_EA0_RDREQ[36] TCC_EA0_WRREQ_LEVEL[59] TCC_NC_REQ_sum TCC_EA0_RDREQ[4] TCC_REQ[106] TCC_REQ[95] TCC_EA0_RDREQ[105] TCC_REQ[4] TCC_EA0_RDREQ[71] TCC_REQ[58] TCC_EA0_WRREQ_LEVEL[4] TCC_EA0_WRREQ_LEVEL[30] TCC_EA0_WRREQ_LEVEL[11] TCC_EA0_WRREQ_LEVEL[87] TCC_EA0_WRREQ_LEVEL[121] TCC_REQ[45] TCC_EA0_RDREQ[76] TCC_EA0_WRREQ_LEVEL[79] TCC_EA0_RDREQ[92] TCC_EA0_WRREQ_LEVEL[31] TCC_EA0_RDREQ[102] TCC_REQ[43] TCC_EA0_WRREQ_LEVEL[91] TCC_REQ[51] TCC_REQ[114] TCC_EA0_RDREQ[40] TCC_EA0_RDREQ[49] TCC_REQ[116] TCC_EA0_WRREQ_LEVEL[113] TCC_EA0_WRREQ_LEVEL[48] TCC_EA0_WRREQ_LEVEL[60] TCC_EA0_WRREQ_LEVEL[50] TCC_EA0_WRREQ_LEVEL[19] TCC_REQ[57] TCC_EA0_RDREQ[5] TCC_REQ[16] TCC_REQ[54] TCC_EA0_WRREQ_LEVEL[63] TCC_REQ[78] TCC_REQ[81] TCC_EA0_RDREQ[39] TCC_EA0_RDREQ[19] TCC_EA0_RDREQ[91] TCC_REQ[98] TCC_REQ[34] TCC_EA0_WRREQ_LEVEL[5] TCC_EA0_RDREQ[28] TCC_REQ[70] TCC_REQ[105] TCC_EA0_RDREQ[125] TCC_EA0_WRREQ_LEVEL[3] TCC_EA0_RDREQ[0] TCC_EA0_RDREQ[79] TCC_EA0_RDREQ[60] TCC_EA0_RDREQ[78] TCC_EA0_RDREQ[17] TCC_EA0_RDREQ[48] TCC_EA0_RDREQ[1] TCC_EA0_WRREQ_LEVEL[7] TCC_EA0_WRREQ_LEVEL[61] TCC_EA0_WRREQ_LEVEL[116] TCC_EA0_WRREQ_LEVEL[107] TCC_REQ[111] TCC_REQ[9] TCC_EA0_WRREQ_LEVEL[65] TCC_EA0_RDREQ[88] TCC_REQ[2] TCC_EA0_RDREQ[101] TCC_REQ[69] TCC_REQ[22] TCC_REQ[24] TCC_EA0_WRREQ_LEVEL[100] TCC_EA0_WRREQ_LEVEL[29] TCC_EA0_WRREQ_LEVEL[27] TCC_EA0_RDREQ[20] TCC_EA0_WRREQ_LEVEL[37] TCC_EA0_RDREQ[30] TCC_EA0_RDREQ[127] TCC_EA0_WRREQ_LEVEL[17] TCC_EA0_WRREQ_LEVEL[28] TCC_EA0_WRREQ_LEVEL[67] TCC_REQ[59] TCC_EA0_RDREQ[121] TCC_REQ[40] TCC_EA0_RDREQ[73] TCC_EA0_WRREQ_LEVEL[76] TCC_EA0_RDREQ[98] TCC_REQ[38] TCC_EA0_WRREQ_LEVEL[118] TCC_EA0_WRREQ_LEVEL[122] TCC_EA0_WRREQ_LEVEL[77] TCC_EA0_RDREQ[68] TCC_REQ[85] TCC_EA0_WRREQ_LEVEL[127] TCC_EA0_RDREQ[37] TCC_REQ[66] TCC_REQ[28] TCC_EA0_WRREQ_LEVEL[97] TCC_EA0_WRREQ_LEVEL[90] TCC_REQ[1] TCC_REQ[39] TCC_EA0_WRREQ_LEVEL[25] TCC_EA0_WRREQ_LEVEL[45] TCC_EA0_WRREQ_LEVEL[38] TCC_EA0_RDREQ[32] TCC_EA0_RDREQ[25] TCC_EA0_RDREQ[97] TCC_EA0_RDREQ[42] TCC_REQ[108] TCC_EA0_RDREQ[67] TCC_EA0_WRREQ_LEVEL[39] TCC_EA0_WRREQ_LEVEL[16] TCC_EA0_WRREQ_LEVEL[2] TCC_REQ[112] TCC_EA0_RDREQ[111] TCC_EA0_WRREQ_LEVEL[36] TCC_EA0_RDREQ[47] TCC_REQ[93] TCC_REQ[17] TCC_EA0_RDREQ[122] TCC_EA0_WRREQ_LEVEL[35] TCC_EA0_RDREQ[126] TCC_REQ[8] TCC_EA0_WRREQ_LEVEL[86] TCC_REQ[90] TCC_EA0_WRREQ_LEVEL[66] TCC_EA0_WRREQ_LEVEL[26] TCC_EA0_RDREQ[2] TCC_REQ[109] TCC_EA0_RDREQ[64] TCC_EA0_WRREQ_LEVEL[92] TCC_EA0_RDREQ[75] TCC_EA0_RDREQ[124] TCC_EA0_RDREQ[58] TCC_REQ[126] TCC_REQ[123] TCC_EA0_RDREQ[80] TCC_REQ[32] TCC_EA0_RDREQ[65] TCC_REQ[62] TCC_REQ[10] TCC_EA0_RDREQ[56] TCC_REQ[0] TCC_EA0_RDREQ[103] TCC_REQ[67] TCC_EA0_WRREQ_LEVEL[114] TCC_EA0_WRREQ_LEVEL[18] TCC_EA0_WRREQ_LEVEL[117] TCC_EA0_RDREQ[12] TCC_EA0_WRREQ_LEVEL[98] TCC_EA0_WRREQ_LEVEL[21] TCC_REQ[47] TCC_EA0_RDREQ[13] TCC_EA0_RDREQ[66] TCC_REQ[61] TCC_EA0_WRREQ_LEVEL[69] TCC_EA0_RDREQ[35] TCC_EA0_RDREQ[123] TCC_REQ[35] TCC_EA0_RDREQ[34] TCC_REQ[83] TCC_EA0_RDREQ[44] TCC_REQ[88] TCC_EA0_WRREQ_LEVEL[20] TCC_REQ[53] TCC_REQ[52] TCC_REQ[19] TCC_EA0_RDREQ[100] TCC_REQ[7] TCC_REQ[72] TCC_REQ[87] TCC_REQ[44] TCC_EA0_WRREQ_LEVEL[34] TCC_EA0_WRREQ_LEVEL[9] TCC_REQ[80] TCC_EA0_RDREQ[11] TCC_EA0_RDREQ[6] TCC_EA0_RDREQ[113] TCC_EA0_RDREQ[110] TCC_EA0_WRREQ_LEVEL[101] TCC_EA0_RDREQ[24] TCC_REQ[103] TCC_REQ[101] TCC_REQ[11] TCC_REQ[6] TCC_REQ[37] TCC_EA0_WRREQ_LEVEL[51] TCC_EA0_RDREQ[93] TCC_EA0_WRREQ_LEVEL[73] TCC_EA0_RDREQ[90] TCC_REQ[42] TCC_EA0_WRREQ_LEVEL[75] TCC_EA0_RDREQ[9] TCC_REQ[115] TCC_EA0_WRREQ_LEVEL[10] TCC_EA0_WRREQ_LEVEL[103] TCC_REQ[124] TCC_EA0_RDREQ[84] TCC_REQ[50] TCC_REQ[25] TCC_EA0_RDREQ[74] TCC_REQ[122] TCC_REQ[125] TCC_REQ[55] TCC_REQ[48] TCC_REQ[18] TCC_EA0_RDREQ[61] TCC_EA0_RDREQ[99] TCC_REQ[94] TCC_EA0_RDREQ[54] TCC_EA0_RDREQ[10] TCC_EA0_RDREQ[45] TCC_EA0_WRREQ_LEVEL[72] TCC_EA0_RDREQ[85] TCC_EA0_RDREQ[62] TCC_REQ[120] TCC_EA0_RDREQ[21] TCC_REQ[56] TCC_REQ[31] TCC_EA0_RDREQ[86] TCC_EA0_WRREQ_LEVEL[78] TCC_REQ[60] TCC_EA0_WRREQ_LEVEL[23] TCC_EA0_WRREQ_LEVEL[42] TCC_EA0_WRREQ_LEVEL[125] TCC_EA0_WRREQ_LEVEL[56] TCC_REQ[86] TCC_EA0_WRREQ_LEVEL[14] TCC_EA0_WRREQ_LEVEL[126] TCC_EA0_WRREQ_LEVEL[57] TCC_EA0_WRREQ_LEVEL[120] TCC_EA0_WRREQ_LEVEL[81] TCC_EA0_RDREQ[83] TCC_EA0_RDREQ[26] TCC_REQ[41] TCC_REQ[12] TCC_REQ[15] TCC_REQ[13] TCC_EA0_WRREQ_LEVEL[119] TCC_EA0_WRREQ_LEVEL[12] TCC_REQ[23] TCC_REQ[127] TCC_EA0_WRREQ_LEVEL[64] TCC_REQ[121] TCC_EA0_RDREQ[118] TCC_EA0_WRREQ_LEVEL[96] TCC_REQ[71] TCC_EA0_RDREQ[106] TCC_EA0_WRREQ_LEVEL[41] TCC_EA0_RDREQ[112] TCC_REQ[91] TCC_REQ[107] TCC_EA0_WRREQ_LEVEL[106] TCC_EA0_WRREQ_LEVEL[6] TCC_REQ[74] TCC_REQ[46] TCC_EA0_WRREQ_LEVEL[74] TCC_EA0_RDREQ[38] TCC_EA0_WRREQ_LEVEL[33] TCC_EA0_WRREQ_LEVEL[54] TCC_EA0_WRREQ_LEVEL[112] TCC_REQ[73] TCC_EA0_WRREQ_LEVEL[53] TCC_REQ[110] TCC_REQ[82] TCC_EA0_WRREQ_LEVEL[93] TCC_EA0_RDREQ[69] TCC_REQ[63] TCC_EA0_RDREQ[119] TCC_EA0_RDREQ[33] TCC_EA0_WRREQ_LEVEL[102] TCC_EA0_WRREQ_LEVEL[105] TCC_REQ[117] TCC_EA0_WRREQ_LEVEL[104] TCC_EA0_RDREQ[107] TCC_EA0_WRREQ_LEVEL[47] TCC_EA0_WRREQ_LEVEL[15] TCC_EA0_WRREQ_LEVEL[22] TCC_EA0_WRREQ_LEVEL[108] TCC_EA0_WRREQ_LEVEL[13] TCC_EA0_WRREQ_LEVEL[80] TCC_EA0_WRREQ_LEVEL[1] TCC_REQ[76] TCC_EA0_WRREQ_LEVEL[110] TCC_EA0_WRREQ_LEVEL[109] TCC_EA0_RDREQ[57] TCC_EA0_WRREQ_LEVEL[111] TCC_EA0_WRREQ_LEVEL[88] TCC_EA0_WRREQ_LEVEL[83] TCC_EA0_RDREQ[116] TCC_REQ[3] TCC_EA0_RDREQ[114] TCC_EA0_RDREQ[22] TCC_REQ[49] TCC_REQ[27] TCC_EA0_RDREQ[70] TCC_REQ[33] TCC_EA0_WRREQ_LEVEL[82] TCC_EA0_RDREQ[94] TCC_EA0_WRREQ_LEVEL[8] TCC_REQ[92] TCC_EA0_WRREQ_LEVEL[94] TCC_EA0_RDREQ[72] TCC_REQ[102] TCC_REQ[118] TCC_EA0_WRREQ_LEVEL[95] TCC_EA0_RDREQ[18] TCC_EA0_RDREQ[46] TCC_EA0_WRREQ_LEVEL[55] TCC_REQ[30] TCC_EA0_WRREQ_LEVEL[52] TCC_EA0_RDREQ[120] TCC_EA0_RDREQ[63] TCC_EA0_RDREQ[81] TCC_EA0_RDREQ[15] TCC_REQ[29] TCC_EA0_RDREQ[7] TCC_REQ[64] TCC_REQ[97] TCC_EA0_WRREQ_LEVEL[84] TCC_EA0_RDREQ[95] TCC_REQ[100] TCC_EA0_RDREQ[23] TCC_EA0_RDREQ[53] TCC_EA0_WRREQ_LEVEL[85] TCC_EA0_RDREQ[59] TCC_EA0_RDREQ[96] TCC_REQ[119] TCC_REQ[5] TCC_REQ[65] TCC_EA0_WRREQ_LEVEL[24] TCC_EA0_WRREQ_LEVEL[115] TCC_EA0_WRREQ_LEVEL[71] TCC_EA0_RDREQ[16] TCC_EA0_WRREQ_LEVEL[0] TCC_EA0_WRREQ_LEVEL[99] TCC_REQ[21] TCC_EA0_WRREQ_LEVEL[44] TCC_EA0_RDREQ[29] TCC_EA0_WRREQ_LEVEL[124] TCC_REQ[14] TCC_EA0_RDREQ[31] TCC_EA0_RDREQ[43] TCC_REQ[89] TCC_EA0_RDREQ[104] TCC_EA0_RDREQ[82] TCC_REQ[104] TCC_EA0_RDREQ[8] TCC_EA0_WRREQ_LEVEL[46] TCC_EA0_RDREQ[89] TCC_EA0_RDREQ[115] TCC_EA0_WRREQ_LEVEL[58] TCC_REQ[99] TCC_REQ[113] TCC_EA0_WRREQ_LEVEL[40] TCC_EA0_WRREQ_LEVEL[43] TCC_REQ[36] TCC_REQ[77] TCC_EA0_WRREQ_LEVEL[32] TCC_EA0_RDREQ[51] TCC_REQ[75] TCC_EA0_RDREQ[109] TCC_EA0_RDREQ[117] TCC_EA0_RDREQ[41] TCC_REQ[79] TCC_EA0_RDREQ[55] TCC_EA0_WRREQ_LEVEL[89] TCC_EA0_RDREQ[87] TCC_EA0_RDREQ[77] TCC_EA0_WRREQ_LEVEL[49] TCC_REQ[20] TCC_EA0_RDREQ[3] TCC_EA0_RDREQ[14] TCC_REQ[68] TCC_REQ[26] TCC_REQ[96] TCC_EA0_RDREQ[52] TCC_EA0_WRREQ_LEVEL[62] TCC_EA0_RDREQ[108] TCC_EA0_WRREQ_LEVEL[68] TCC_EA0_WRREQ_LEVEL[123] TCC_EA0_RDREQ[27] TCC_EA0_RDREQ[50] TCC_EA0_WRREQ_LEVEL[70] TCC_REQ[84] CPC_SYNC_WRREQ_FIFO_BUSY CPC_ME1_BUSY_FOR_PACKET_DECODE CPF_CPF_STAT_BUSY CPF_CMP_UTCL1_STALL_ON_TRANSLATION SPI_CS2_WAVE SPI_CS0_WAVE SPI_CS1_WAVE SPI_CS3_WAVE GRBM_GUI_ACTIVE + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_IFETCH_LEVEL.yaml b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_IFETCH_LEVEL.yaml new file mode 100644 index 0000000000..ad757566f9 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_IFETCH_LEVEL.yaml @@ -0,0 +1,1925 @@ +SQ_IFETCH_LEVEL_ACCUM: + architectures: + gfx942/gfx941/gfx940/gfx90a: + expression: accumulate(SQ_IFETCH_LEVEL, HIGH_RES) + description: SQ_IFETCH_LEVEL accumulation +TCC_EA0_RDREQ[0]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 0th XCC and 0th channel +TCC_EA0_RDREQ[100]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 6th XCC and 4th channel +TCC_EA0_RDREQ[101]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 6th XCC and 5th channel +TCC_EA0_RDREQ[102]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 6th XCC and 6th channel +TCC_EA0_RDREQ[103]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 6th XCC and 7th channel +TCC_EA0_RDREQ[104]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 6th XCC and 8th channel +TCC_EA0_RDREQ[105]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 6th XCC and 9th channel +TCC_EA0_RDREQ[106]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 6th XCC and 10th channel +TCC_EA0_RDREQ[107]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 6th XCC and 11th channel +TCC_EA0_RDREQ[108]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 6th XCC and 12th channel +TCC_EA0_RDREQ[109]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 6th XCC and 13th channel +TCC_EA0_RDREQ[10]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 0th XCC and 10th channel +TCC_EA0_RDREQ[110]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 6th XCC and 14th channel +TCC_EA0_RDREQ[111]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 6th XCC and 15th channel +TCC_EA0_RDREQ[112]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 7th XCC and 0th channel +TCC_EA0_RDREQ[113]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 7th XCC and 1th channel +TCC_EA0_RDREQ[114]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 7th XCC and 2th channel +TCC_EA0_RDREQ[115]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 7th XCC and 3th channel +TCC_EA0_RDREQ[116]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 7th XCC and 4th channel +TCC_EA0_RDREQ[117]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 7th XCC and 5th channel +TCC_EA0_RDREQ[118]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 7th XCC and 6th channel +TCC_EA0_RDREQ[119]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 7th XCC and 7th channel +TCC_EA0_RDREQ[11]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 0th XCC and 11th channel +TCC_EA0_RDREQ[120]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 7th XCC and 8th channel +TCC_EA0_RDREQ[121]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 7th XCC and 9th channel +TCC_EA0_RDREQ[122]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 7th XCC and 10th channel +TCC_EA0_RDREQ[123]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 7th XCC and 11th channel +TCC_EA0_RDREQ[124]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 7th XCC and 12th channel +TCC_EA0_RDREQ[125]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 7th XCC and 13th channel +TCC_EA0_RDREQ[126]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 7th XCC and 14th channel +TCC_EA0_RDREQ[127]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 7th XCC and 15th channel +TCC_EA0_RDREQ[12]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 0th XCC and 12th channel +TCC_EA0_RDREQ[13]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 0th XCC and 13th channel +TCC_EA0_RDREQ[14]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 0th XCC and 14th channel +TCC_EA0_RDREQ[15]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 0th XCC and 15th channel +TCC_EA0_RDREQ[16]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 1th XCC and 0th channel +TCC_EA0_RDREQ[17]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 1th XCC and 1th channel +TCC_EA0_RDREQ[18]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 1th XCC and 2th channel +TCC_EA0_RDREQ[19]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 1th XCC and 3th channel +TCC_EA0_RDREQ[1]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 0th XCC and 1th channel +TCC_EA0_RDREQ[20]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 1th XCC and 4th channel +TCC_EA0_RDREQ[21]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 1th XCC and 5th channel +TCC_EA0_RDREQ[22]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 1th XCC and 6th channel +TCC_EA0_RDREQ[23]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 1th XCC and 7th channel +TCC_EA0_RDREQ[24]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 1th XCC and 8th channel +TCC_EA0_RDREQ[25]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 1th XCC and 9th channel +TCC_EA0_RDREQ[26]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 1th XCC and 10th channel +TCC_EA0_RDREQ[27]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 1th XCC and 11th channel +TCC_EA0_RDREQ[28]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 1th XCC and 12th channel +TCC_EA0_RDREQ[29]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 1th XCC and 13th channel +TCC_EA0_RDREQ[2]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 0th XCC and 2th channel +TCC_EA0_RDREQ[30]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 1th XCC and 14th channel +TCC_EA0_RDREQ[31]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 1th XCC and 15th channel +TCC_EA0_RDREQ[32]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 2th XCC and 0th channel +TCC_EA0_RDREQ[33]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 2th XCC and 1th channel +TCC_EA0_RDREQ[34]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 2th XCC and 2th channel +TCC_EA0_RDREQ[35]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 2th XCC and 3th channel +TCC_EA0_RDREQ[36]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 2th XCC and 4th channel +TCC_EA0_RDREQ[37]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 2th XCC and 5th channel +TCC_EA0_RDREQ[38]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 2th XCC and 6th channel +TCC_EA0_RDREQ[39]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 2th XCC and 7th channel +TCC_EA0_RDREQ[3]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 0th XCC and 3th channel +TCC_EA0_RDREQ[40]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 2th XCC and 8th channel +TCC_EA0_RDREQ[41]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 2th XCC and 9th channel +TCC_EA0_RDREQ[42]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 2th XCC and 10th channel +TCC_EA0_RDREQ[43]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 2th XCC and 11th channel +TCC_EA0_RDREQ[44]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 2th XCC and 12th channel +TCC_EA0_RDREQ[45]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 2th XCC and 13th channel +TCC_EA0_RDREQ[46]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 2th XCC and 14th channel +TCC_EA0_RDREQ[47]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 2th XCC and 15th channel +TCC_EA0_RDREQ[48]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 3th XCC and 0th channel +TCC_EA0_RDREQ[49]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 3th XCC and 1th channel +TCC_EA0_RDREQ[4]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 0th XCC and 4th channel +TCC_EA0_RDREQ[50]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 3th XCC and 2th channel +TCC_EA0_RDREQ[51]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 3th XCC and 3th channel +TCC_EA0_RDREQ[52]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 3th XCC and 4th channel +TCC_EA0_RDREQ[53]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 3th XCC and 5th channel +TCC_EA0_RDREQ[54]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 3th XCC and 6th channel +TCC_EA0_RDREQ[55]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 3th XCC and 7th channel +TCC_EA0_RDREQ[56]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 3th XCC and 8th channel +TCC_EA0_RDREQ[57]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 3th XCC and 9th channel +TCC_EA0_RDREQ[58]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 3th XCC and 10th channel +TCC_EA0_RDREQ[59]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 3th XCC and 11th channel +TCC_EA0_RDREQ[5]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 0th XCC and 5th channel +TCC_EA0_RDREQ[60]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 3th XCC and 12th channel +TCC_EA0_RDREQ[61]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 3th XCC and 13th channel +TCC_EA0_RDREQ[62]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 3th XCC and 14th channel +TCC_EA0_RDREQ[63]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 3th XCC and 15th channel +TCC_EA0_RDREQ[64]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 4th XCC and 0th channel +TCC_EA0_RDREQ[65]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 4th XCC and 1th channel +TCC_EA0_RDREQ[66]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 4th XCC and 2th channel +TCC_EA0_RDREQ[67]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 4th XCC and 3th channel +TCC_EA0_RDREQ[68]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 4th XCC and 4th channel +TCC_EA0_RDREQ[69]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 4th XCC and 5th channel +TCC_EA0_RDREQ[6]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 0th XCC and 6th channel +TCC_EA0_RDREQ[70]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 4th XCC and 6th channel +TCC_EA0_RDREQ[71]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 4th XCC and 7th channel +TCC_EA0_RDREQ[72]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 4th XCC and 8th channel +TCC_EA0_RDREQ[73]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 4th XCC and 9th channel +TCC_EA0_RDREQ[74]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 4th XCC and 10th channel +TCC_EA0_RDREQ[75]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 4th XCC and 11th channel +TCC_EA0_RDREQ[76]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 4th XCC and 12th channel +TCC_EA0_RDREQ[77]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 4th XCC and 13th channel +TCC_EA0_RDREQ[78]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 4th XCC and 14th channel +TCC_EA0_RDREQ[79]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 4th XCC and 15th channel +TCC_EA0_RDREQ[7]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 0th XCC and 7th channel +TCC_EA0_RDREQ[80]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 5th XCC and 0th channel +TCC_EA0_RDREQ[81]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 5th XCC and 1th channel +TCC_EA0_RDREQ[82]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 5th XCC and 2th channel +TCC_EA0_RDREQ[83]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 5th XCC and 3th channel +TCC_EA0_RDREQ[84]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 5th XCC and 4th channel +TCC_EA0_RDREQ[85]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 5th XCC and 5th channel +TCC_EA0_RDREQ[86]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 5th XCC and 6th channel +TCC_EA0_RDREQ[87]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 5th XCC and 7th channel +TCC_EA0_RDREQ[88]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 5th XCC and 8th channel +TCC_EA0_RDREQ[89]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 5th XCC and 9th channel +TCC_EA0_RDREQ[8]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 0th XCC and 8th channel +TCC_EA0_RDREQ[90]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 5th XCC and 10th channel +TCC_EA0_RDREQ[91]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 5th XCC and 11th channel +TCC_EA0_RDREQ[92]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 5th XCC and 12th channel +TCC_EA0_RDREQ[93]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 5th XCC and 13th channel +TCC_EA0_RDREQ[94]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 5th XCC and 14th channel +TCC_EA0_RDREQ[95]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 5th XCC and 15th channel +TCC_EA0_RDREQ[96]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 6th XCC and 0th channel +TCC_EA0_RDREQ[97]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 6th XCC and 1th channel +TCC_EA0_RDREQ[98]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 6th XCC and 2th channel +TCC_EA0_RDREQ[99]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 6th XCC and 3th channel +TCC_EA0_RDREQ[9]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 0th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[0]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[100]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[101]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[102]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[103]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[104]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[105]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[106]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[107]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[108]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[109]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[10]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[110]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[111]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[112]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[113]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[114]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[115]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[116]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[117]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[118]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[119]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[11]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[120]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[121]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[122]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[123]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[124]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[125]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[126]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[127]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[12]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[13]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[14]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[15]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[16]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[17]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[18]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[19]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[1]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[20]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[21]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[22]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[23]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[24]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[25]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[26]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[27]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[28]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[29]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[2]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[30]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[31]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[32]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[33]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[34]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[35]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[36]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[37]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[38]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[39]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[3]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[40]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[41]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[42]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[43]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[44]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[45]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[46]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[47]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[48]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[49]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[4]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[50]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[51]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[52]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[53]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[54]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[55]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[56]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[57]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[58]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[59]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[5]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[60]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[61]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[62]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[63]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[64]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[65]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[66]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[67]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[68]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[69]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[6]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[70]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[71]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[72]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[73]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[74]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[75]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[76]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[77]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[78]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[79]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[7]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[80]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[81]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[82]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[83]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[84]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[85]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[86]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[87]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[88]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[89]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[8]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[90]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[91]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[92]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[93]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[94]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[95]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[96]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[97]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[98]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[99]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[9]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 9th channel +TCC_REQ[0]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 0th XCC and 0th channel +TCC_REQ[100]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 6th XCC and 4th channel +TCC_REQ[101]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 6th XCC and 5th channel +TCC_REQ[102]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 6th XCC and 6th channel +TCC_REQ[103]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 6th XCC and 7th channel +TCC_REQ[104]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 6th XCC and 8th channel +TCC_REQ[105]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 6th XCC and 9th channel +TCC_REQ[106]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 6th XCC and 10th channel +TCC_REQ[107]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 6th XCC and 11th channel +TCC_REQ[108]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 6th XCC and 12th channel +TCC_REQ[109]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 6th XCC and 13th channel +TCC_REQ[10]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 0th XCC and 10th channel +TCC_REQ[110]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 6th XCC and 14th channel +TCC_REQ[111]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 6th XCC and 15th channel +TCC_REQ[112]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 7th XCC and 0th channel +TCC_REQ[113]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 7th XCC and 1th channel +TCC_REQ[114]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 7th XCC and 2th channel +TCC_REQ[115]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 7th XCC and 3th channel +TCC_REQ[116]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 7th XCC and 4th channel +TCC_REQ[117]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 7th XCC and 5th channel +TCC_REQ[118]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 7th XCC and 6th channel +TCC_REQ[119]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 7th XCC and 7th channel +TCC_REQ[11]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 0th XCC and 11th channel +TCC_REQ[120]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 7th XCC and 8th channel +TCC_REQ[121]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 7th XCC and 9th channel +TCC_REQ[122]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 7th XCC and 10th channel +TCC_REQ[123]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 7th XCC and 11th channel +TCC_REQ[124]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 7th XCC and 12th channel +TCC_REQ[125]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 7th XCC and 13th channel +TCC_REQ[126]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 7th XCC and 14th channel +TCC_REQ[127]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 7th XCC and 15th channel +TCC_REQ[12]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 0th XCC and 12th channel +TCC_REQ[13]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 0th XCC and 13th channel +TCC_REQ[14]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 0th XCC and 14th channel +TCC_REQ[15]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 0th XCC and 15th channel +TCC_REQ[16]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 1th XCC and 0th channel +TCC_REQ[17]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 1th XCC and 1th channel +TCC_REQ[18]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 1th XCC and 2th channel +TCC_REQ[19]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 1th XCC and 3th channel +TCC_REQ[1]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 0th XCC and 1th channel +TCC_REQ[20]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 1th XCC and 4th channel +TCC_REQ[21]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 1th XCC and 5th channel +TCC_REQ[22]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 1th XCC and 6th channel +TCC_REQ[23]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 1th XCC and 7th channel +TCC_REQ[24]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 1th XCC and 8th channel +TCC_REQ[25]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 1th XCC and 9th channel +TCC_REQ[26]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 1th XCC and 10th channel +TCC_REQ[27]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 1th XCC and 11th channel +TCC_REQ[28]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 1th XCC and 12th channel +TCC_REQ[29]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 1th XCC and 13th channel +TCC_REQ[2]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 0th XCC and 2th channel +TCC_REQ[30]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 1th XCC and 14th channel +TCC_REQ[31]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 1th XCC and 15th channel +TCC_REQ[32]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 2th XCC and 0th channel +TCC_REQ[33]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 2th XCC and 1th channel +TCC_REQ[34]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 2th XCC and 2th channel +TCC_REQ[35]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 2th XCC and 3th channel +TCC_REQ[36]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 2th XCC and 4th channel +TCC_REQ[37]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 2th XCC and 5th channel +TCC_REQ[38]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 2th XCC and 6th channel +TCC_REQ[39]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 2th XCC and 7th channel +TCC_REQ[3]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 0th XCC and 3th channel +TCC_REQ[40]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 2th XCC and 8th channel +TCC_REQ[41]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 2th XCC and 9th channel +TCC_REQ[42]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 2th XCC and 10th channel +TCC_REQ[43]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 2th XCC and 11th channel +TCC_REQ[44]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 2th XCC and 12th channel +TCC_REQ[45]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 2th XCC and 13th channel +TCC_REQ[46]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 2th XCC and 14th channel +TCC_REQ[47]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 2th XCC and 15th channel +TCC_REQ[48]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 3th XCC and 0th channel +TCC_REQ[49]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 3th XCC and 1th channel +TCC_REQ[4]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 0th XCC and 4th channel +TCC_REQ[50]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 3th XCC and 2th channel +TCC_REQ[51]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 3th XCC and 3th channel +TCC_REQ[52]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 3th XCC and 4th channel +TCC_REQ[53]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 3th XCC and 5th channel +TCC_REQ[54]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 3th XCC and 6th channel +TCC_REQ[55]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 3th XCC and 7th channel +TCC_REQ[56]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 3th XCC and 8th channel +TCC_REQ[57]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 3th XCC and 9th channel +TCC_REQ[58]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 3th XCC and 10th channel +TCC_REQ[59]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 3th XCC and 11th channel +TCC_REQ[5]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 0th XCC and 5th channel +TCC_REQ[60]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 3th XCC and 12th channel +TCC_REQ[61]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 3th XCC and 13th channel +TCC_REQ[62]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 3th XCC and 14th channel +TCC_REQ[63]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 3th XCC and 15th channel +TCC_REQ[64]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 4th XCC and 0th channel +TCC_REQ[65]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 4th XCC and 1th channel +TCC_REQ[66]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 4th XCC and 2th channel +TCC_REQ[67]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 4th XCC and 3th channel +TCC_REQ[68]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 4th XCC and 4th channel +TCC_REQ[69]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 4th XCC and 5th channel +TCC_REQ[6]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 0th XCC and 6th channel +TCC_REQ[70]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 4th XCC and 6th channel +TCC_REQ[71]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 4th XCC and 7th channel +TCC_REQ[72]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 4th XCC and 8th channel +TCC_REQ[73]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 4th XCC and 9th channel +TCC_REQ[74]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 4th XCC and 10th channel +TCC_REQ[75]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 4th XCC and 11th channel +TCC_REQ[76]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 4th XCC and 12th channel +TCC_REQ[77]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 4th XCC and 13th channel +TCC_REQ[78]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 4th XCC and 14th channel +TCC_REQ[79]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 4th XCC and 15th channel +TCC_REQ[7]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 0th XCC and 7th channel +TCC_REQ[80]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 5th XCC and 0th channel +TCC_REQ[81]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 5th XCC and 1th channel +TCC_REQ[82]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 5th XCC and 2th channel +TCC_REQ[83]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 5th XCC and 3th channel +TCC_REQ[84]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 5th XCC and 4th channel +TCC_REQ[85]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 5th XCC and 5th channel +TCC_REQ[86]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 5th XCC and 6th channel +TCC_REQ[87]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 5th XCC and 7th channel +TCC_REQ[88]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 5th XCC and 8th channel +TCC_REQ[89]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 5th XCC and 9th channel +TCC_REQ[8]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 0th XCC and 8th channel +TCC_REQ[90]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 5th XCC and 10th channel +TCC_REQ[91]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 5th XCC and 11th channel +TCC_REQ[92]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 5th XCC and 12th channel +TCC_REQ[93]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 5th XCC and 13th channel +TCC_REQ[94]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 5th XCC and 14th channel +TCC_REQ[95]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 5th XCC and 15th channel +TCC_REQ[96]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 6th XCC and 0th channel +TCC_REQ[97]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 6th XCC and 1th channel +TCC_REQ[98]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 6th XCC and 2th channel +TCC_REQ[99]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 6th XCC and 3th channel +TCC_REQ[9]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 0th XCC and 9th channel diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_LDS.txt b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_LDS.txt new file mode 100644 index 0000000000..68dad9e8a5 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_LDS.txt @@ -0,0 +1,5 @@ +pmc: SQ_INST_LEVEL_LDS SQ_INST_LEVEL_LDS_ACCUM SQC_DCACHE_ATOMIC SQC_TC_STALL SQC_ICACHE_REQ SQC_DCACHE_MISSES SQ_INSTS_VALU_MUL_F16 SQ_WAVES_SAVED TA_BUFFER_WRITE_WAVEFRONTS_sum TA_TA_BUSY_sum TCP_TCC_ATOMIC_WITH_RET_REQ_sum TCP_UTCL1_REQUEST_sum TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum TCP_TOTAL_WRITEBACK_INVALIDATES_sum TCC_EA0_WRREQ_sum TCC_TOO_MANY_EA_WRREQS_STALL_sum TCC_ATOMIC_sum TCC_EA0_ATOMIC_LEVEL_sum CPC_ME1_DC0_SPI_BUSY CPC_CPC_TCIU_BUSY SPI_VWC0_VDATA_VALID_WR SPI_RA_REQ_NO_ALLOC_CSN + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_LDS.yaml b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_LDS.yaml new file mode 100644 index 0000000000..7e20aab5a9 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_LDS.yaml @@ -0,0 +1,5 @@ +SQ_INST_LEVEL_LDS_ACCUM: + architectures: + gfx942/gfx941/gfx940/gfx90a: + expression: accumulate(SQ_INST_LEVEL_LDS, HIGH_RES) + description: SQ_INST_LEVEL_LDS accumulation diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt new file mode 100644 index 0000000000..07699d7d74 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt @@ -0,0 +1,5 @@ +pmc: SQ_INST_LEVEL_SMEM SQ_INST_LEVEL_SMEM_ACCUM SQ_INSTS_LDS_LOAD SQ_LDS_CMD_FIFO_FULL SQ_BUSY_CU_CYCLES SQ_INSTS_LDS_STORE SQC_DCACHE_REQ_READ_16 SQ_INSTS_VALU_MUL_F64 TA_FLAT_READ_WAVEFRONTS_sum TA_BUFFER_TOTAL_CYCLES_sum TD_STORE_WAVEFRONT_sum TD_LOAD_WAVEFRONT_sum TCP_UTCL1_TRANSLATION_HIT_sum TCP_TOTAL_ATOMIC_WITH_RET_sum TCP_TCC_UC_READ_REQ_sum TCP_TA_TCP_STATE_READ_sum TCC_HIT[110] TCC_ATOMIC[112] TCC_HIT[49] TCC_ATOMIC[54] TCC_EA0_ATOMIC[108] TCC_BUBBLE[121] TCC_HIT[33] TCC_HIT[87] TCC_EA0_ATOMIC[44] TCC_BUBBLE[75] TCC_HIT[5] TCC_EA0_ATOMIC[96] TCC_EA0_ATOMIC[121] TCC_ATOMIC[72] TCC_HIT[123] TCC_ATOMIC[26] TCC_ATOMIC[88] TCC_ATOMIC[69] TCC_EA0_ATOMIC[79] TCC_BUBBLE[107] TCC_ATOMIC[81] TCC_HIT[100] TCC_HIT[84] TCC_ATOMIC[28] TCC_BUBBLE[82] TCC_HIT[9] TCC_BUBBLE[36] TCC_HIT[78] TCC_HIT[4] TCC_EA0_ATOMIC[66] TCC_HIT[48] TCC_HIT[79] TCC_EA0_ATOMIC[19] TCC_ATOMIC[91] TCC_EA0_ATOMIC[103] TCC_BUBBLE[109] TCC_BUBBLE[122] TCC_ATOMIC[48] TCC_EA0_ATOMIC[10] TCC_BUBBLE[24] TCC_EA0_ATOMIC[64] TCC_ATOMIC[39] TCC_ATOMIC[38] TCC_BUBBLE[53] TCC_ATOMIC[20] TCC_BUBBLE[96] TCC_HIT[12] TCC_BUBBLE[67] TCC_BUBBLE[87] TCC_HIT[126] TCC_BUBBLE[5] TCC_EA0_ATOMIC[46] TCC_ATOMIC[25] TCC_EA0_ATOMIC[118] TCC_EA0_ATOMIC[107] TCC_EA0_ATOMIC[26] TCC_HIT[75] TCC_HIT[7] TCC_EA0_ATOMIC[50] TCC_HIT[32] TCC_BUBBLE[39] TCC_EA0_ATOMIC[23] TCC_EA0_ATOMIC[61] TCC_BUBBLE[12] TCC_EA0_ATOMIC[62] TCC_BUBBLE[76] TCC_BUBBLE[8] TCC_EA0_ATOMIC[76] TCC_ATOMIC[40] TCC_HIT[80] TCC_HIT[115] TCC_EA0_ATOMIC[38] TCC_ATOMIC[45] TCC_EA0_ATOMIC[8] TCC_EA0_ATOMIC[42] TCC_HIT[52] TCC_BUBBLE[31] TCC_HIT[56] TCC_BUBBLE[32] TCC_HIT[47] TCC_ATOMIC[36] TCC_BUBBLE[43] TCC_ATOMIC[35] TCC_BUBBLE[23] TCC_ATOMIC[51] TCC_HIT[29] TCC_HIT[15] TCC_HIT[35] TCC_EA0_ATOMIC[67] TCC_HIT[51] TCC_EA0_ATOMIC[30] TCC_HIT[104] TCC_ATOMIC[115] TCC_EA0_ATOMIC[21] TCC_BUBBLE[26] TCC_HIT[124] TCC_HIT[92] TCC_EA0_ATOMIC[1] TCC_EA0_ATOMIC[72] TCC_HIT[93] TCC_HIT[28] TCC_HIT[8] TCC_EA0_ATOMIC[52] TCC_EA0_ATOMIC[32] TCC_BUBBLE[14] TCC_ATOMIC[66] TCC_EA0_ATOMIC[97] TCC_HIT[101] TCC_HIT[89] TCC_BUBBLE[106] TCC_EA0_ATOMIC[28] TCC_BUBBLE[99] TCC_BUBBLE[55] TCC_BUBBLE[110] TCC_ATOMIC[2] TCC_EA0_ATOMIC[7] TCC_EA0_ATOMIC[82] TCC_HIT[38] TCC_ATOMIC[110] TCC_BUBBLE[64] TCC_HIT[77] TCC_ATOMIC[86] TCC_BUBBLE[68] TCC_ATOMIC[4] TCC_BUBBLE[127] TCC_EA0_ATOMIC[54] TCC_BUBBLE[9] TCC_BUBBLE[3] TCC_EA0_ATOMIC[20] TCC_HIT[26] TCC_ATOMIC[22] TCC_BUBBLE[54] TCC_ATOMIC[96] TCC_EA0_ATOMIC[35] TCC_EA0_ATOMIC[126] TCC_ATOMIC[33] TCC_HIT[118] TCC_HIT[31] TCC_ATOMIC[95] TCC_EA0_ATOMIC[90] TCC_BUBBLE[105] TCC_BUBBLE[22] TCC_HIT[97] TCC_ATOMIC[113] TCC_ATOMIC[98] TCC_ATOMIC[63] TCC_ATOMIC[99] TCC_EA0_ATOMIC[15] TCC_ATOMIC[106] TCC_EA0_ATOMIC[14] TCC_HIT[19] TCC_BUBBLE[11] TCC_EA0_ATOMIC[70] TCC_BUBBLE[88] TCC_ATOMIC[82] TCC_ATOMIC[50] TCC_EA0_ATOMIC[51] TCC_HIT[46] TCC_HIT[1] TCC_EA0_ATOMIC[111] TCC_HIT[73] TCC_ATOMIC[41] TCC_ATOMIC[78] TCC_BUBBLE[17] TCC_ATOMIC[61] TCC_HIT[114] TCC_ATOMIC[44] TCC_BUBBLE[13] TCC_ATOMIC[57] TCC_ATOMIC[101] TCC_EA0_ATOMIC[122] TCC_EA0_ATOMIC[40] TCC_ATOMIC[67] TCC_BUBBLE[97] TCC_EA0_ATOMIC[113] TCC_HIT[36] TCC_BUBBLE[63] TCC_EA0_ATOMIC[77] TCC_HIT[58] TCC_EA0_ATOMIC[99] TCC_ATOMIC[89] TCC_ATOMIC[97] TCC_EA0_ATOMIC[47] TCC_EA0_ATOMIC[63] TCC_HIT[98] TCC_HIT[10] TCC_EA0_ATOMIC[123] TCC_HIT[86] TCC_HIT[106] TCC_EA0_ATOMIC[58] TCC_HIT[67] TCC_HIT[91] TCC_ATOMIC[105] TCC_HIT[121] TCC_HIT[64] TCC_BUBBLE[41] TCC_ATOMIC[29] TCC_BUBBLE[79] TCC_BUBBLE[115] TCC_ATOMIC[107] TCC_EA0_ATOMIC[89] TCC_EA0_ATOMIC[36] TCC_BUBBLE[50] TCC_BUBBLE[92] TCC_BUBBLE[48] TCC_EA0_ATOMIC[27] TCC_BUBBLE[81] TCC_BUBBLE[113] TCC_ATOMIC[127] TCC_HIT[16] TCC_BUBBLE[103] TCC_EA0_ATOMIC[12] TCC_ATOMIC[90] TCC_ATOMIC[16] TCC_EA0_ATOMIC[22] TCC_EA0_ATOMIC[41] TCC_BUBBLE[72] TCC_HIT[60] TCC_BUBBLE[66] TCC_ATOMIC[77] TCC_HIT[61] TCC_HIT[88] TCC_EA0_ATOMIC[11] TCC_ATOMIC[9] TCC_EA0_ATOMIC[88] TCC_ATOMIC[103] TCC_BUBBLE[6] TCC_HIT[37] TCC_ATOMIC[18] TCC_HIT[14] TCC_BUBBLE[118] TCC_EA0_ATOMIC[65] TCC_ATOMIC[116] TCC_EA0_ATOMIC[125] TCC_ATOMIC[83] TCC_BUBBLE[117] TCC_EA0_ATOMIC[106] TCC_HIT[0] TCC_HIT[71] TCC_EA0_ATOMIC[31] TCC_BUBBLE[91] TCC_EA0_ATOMIC[100] TCC_ATOMIC[75] TCC_ATOMIC[6] TCC_HIT[39] TCC_BUBBLE[7] TCC_BUBBLE[40] TCC_EA0_ATOMIC[39] TCC_EA0_ATOMIC[55] TCC_EA0_ATOMIC[56] TCC_BUBBLE[34] TCC_BUBBLE[52] TCC_ATOMIC[125] TCC_EA0_ATOMIC[80] TCC_HIT[70] TCC_BUBBLE[49] TCC_BUBBLE[20] TCC_ATOMIC[62] TCC_BUBBLE[4] TCC_HIT[6] TCC_ATOMIC[10] TCC_EA0_ATOMIC[120] TCC_HIT[127] TCC_ATOMIC[124] TCC_HIT[3] TCC_ATOMIC[70] TCC_EA0_ATOMIC[34] TCC_EA0_ATOMIC[3] TCC_HIT[120] TCC_BUBBLE[27] TCC_EA0_ATOMIC[5] TCC_ATOMIC[8] TCC_HIT[54] TCC_BUBBLE[10] TCC_BUBBLE[101] TCC_BUBBLE[19] TCC_HIT[62] TCC_HIT[85] TCC_ATOMIC[119] TCC_ATOMIC[76] TCC_HIT[103] TCC_EA0_ATOMIC[75] TCC_BUBBLE[102] TCC_ATOMIC[87] TCC_BUBBLE[56] TCC_EA0_ATOMIC[104] TCC_HIT[25] TCC_BUBBLE[47] TCC_EA0_ATOMIC[87] TCC_ATOMIC[46] TCC_HIT[125] TCC_HIT[13] TCC_ATOMIC[100] TCC_HIT[43] TCC_BUBBLE[15] TCC_BUBBLE[59] TCC_ATOMIC[85] TCC_ATOMIC[93] TCC_ATOMIC[68] TCC_ATOMIC[84] TCC_EA0_ATOMIC[81] TCC_BUBBLE[124] TCC_BUBBLE[123] TCC_EA0_ATOMIC[98] TCC_ATOMIC[13] TCC_ATOMIC[60] TCC_BUBBLE[70] TCC_HIT[30] TCC_HIT[23] TCC_BUBBLE[60] TCC_ATOMIC[37] TCC_EA0_ATOMIC[101] TCC_EA0_ATOMIC[116] TCC_ATOMIC[1] TCC_ATOMIC[80] TCC_ATOMIC[7] TCC_EA0_ATOMIC[110] TCC_BUBBLE[93] TCC_BUBBLE[126] TCC_ATOMIC[12] TCC_ATOMIC[74] TCC_HIT[117] TCC_ATOMIC[31] TCC_HIT[22] TCC_HIT[76] TCC_BUBBLE[104] TCC_HIT[55] TCC_EA0_ATOMIC[105] TCC_HIT[18] TCC_HIT[119] TCC_BUBBLE[33] TCC_HIT[34] TCC_BUBBLE[125] TCC_EA0_ATOMIC[13] TCC_EA0_ATOMIC[2] TCC_EA0_ATOMIC[48] TCC_HIT[111] TCC_HIT[109] TCC_EA0_ATOMIC[109] TCC_BUBBLE[114] TCC_BUBBLE[45] TCC_HIT[102] TCC_ATOMIC[27] TCC_BUBBLE[61] TCC_HIT[96] TCC_EA0_ATOMIC[74] TCC_BUBBLE[111] TCC_HIT[82] TCC_ATOMIC[59] TCC_HIT[21] TCC_EA0_ATOMIC[124] TCC_BUBBLE[0] TCC_ATOMIC[24] TCC_EA0_ATOMIC[114] TCC_BUBBLE[94] TCC_BUBBLE[108] TCC_BUBBLE[83] TCC_BUBBLE[95] TCC_HIT[41] TCC_HIT[53] TCC_HIT[20] TCC_ATOMIC[3] TCC_ATOMIC[55] TCC_BUBBLE[16] TCC_HIT[95] TCC_EA0_ATOMIC[49] TCC_EA0_ATOMIC[9] TCC_EA0_ATOMIC[68] TCC_ATOMIC[34] TCC_HIT[24] TCC_BUBBLE[98] TCC_ATOMIC[117] TCC_BUBBLE[28] TCC_BUBBLE[80] TCC_ATOMIC[108] TCC_ATOMIC[122] TCC_ATOMIC[5] TCC_EA0_ATOMIC[119] TCC_BUBBLE[44] TCC_BUBBLE[116] TCC_EA0_ATOMIC[59] TCC_EA0_ATOMIC[78] TCC_ATOMIC[64] TCC_EA0_ATOMIC[0] TCC_BUBBLE[90] TCC_EA0_ATOMIC[43] TCC_HIT[11] TCC_ATOMIC[71] TCC_HIT[68] TCC_BUBBLE[77] TCC_EA0_ATOMIC[37] TCC_BUBBLE[21] TCC_BUBBLE[112] TCC_ATOMIC[14] TCC_BUBBLE[120] TCC_EA0_ATOMIC[17] TCC_ATOMIC[23] TCC_BUBBLE[51] TCC_BUBBLE[57] TCC_EA0_ATOMIC[53] TCC_EA0_ATOMIC[93] TCC_EA0_ATOMIC[115] TCC_ATOMIC[32] TCC_EA0_ATOMIC[94] TCC_EA0_ATOMIC[4] TCC_BUBBLE[84] TCC_EA0_ATOMIC[33] TCC_ATOMIC[94] TCC_HIT[44] TCC_ATOMIC[43] TCC_ATOMIC[111] TCC_BUBBLE[30] TCC_EA0_ATOMIC[57] TCC_BUBBLE[2] TCC_BUBBLE[73] TCC_HIT[90] TCC_ATOMIC[73] TCC_EA0_ATOMIC[84] TCC_EA0_ATOMIC[86] TCC_EA0_ATOMIC[91] TCC_EA0_ATOMIC[6] TCC_EA0_ATOMIC[117] TCC_ATOMIC[104] TCC_BUBBLE[46] TCC_ATOMIC[126] TCC_BUBBLE[62] TCC_HIT[81] TCC_HIT[2] TCC_EA0_ATOMIC[73] TCC_BUBBLE[69] TCC_ATOMIC[49] TCC_BUBBLE[71] TCC_ATOMIC[109] TCC_EA0_ATOMIC[85] TCC_BUBBLE[35] TCC_ATOMIC[118] TCC_BUBBLE[37] TCC_ATOMIC[79] TCC_HIT[66] TCC_HIT[63] TCC_HIT[107] TCC_ATOMIC[15] TCC_EA0_ATOMIC[24] TCC_EA0_ATOMIC[127] TCC_ATOMIC[102] TCC_ATOMIC[58] TCC_BUBBLE[74] TCC_ATOMIC[121] TCC_HIT[40] TCC_BUBBLE[65] TCC_EA0_ATOMIC[45] TCC_ATOMIC[42] TCC_HIT[108] TCC_ATOMIC[114] TCC_BUBBLE[89] TCC_EA0_ATOMIC[102] TCC_BUBBLE[42] TCC_BUBBLE[119] TCC_HIT[94] TCC_BUBBLE[78] TCC_BUBBLE[25] TCC_ATOMIC[52] TCC_ATOMIC[19] TCC_HIT[65] TCC_ATOMIC[30] TCC_ATOMIC[65] TCC_BUBBLE[38] TCC_HIT[17] TCC_BUBBLE[85] TCC_HIT[112] TCC_EA0_ATOMIC[29] TCC_EA0_ATOMIC[25] TCC_ATOMIC[17] TCC_EA0_ATOMIC[60] TCC_EA0_ATOMIC[83] TCC_BUBBLE[58] TCC_HIT[83] TCC_HIT[59] TCC_BUBBLE[100] TCC_ATOMIC[56] TCC_HIT[122] TCC_EA0_ATOMIC[16] TCC_ATOMIC[21] TCC_EA0_ATOMIC[92] TCC_HIT[42] TCC_EA0_ATOMIC[71] TCC_HIT[74] TCC_ATOMIC[53] TCC_HIT[45] TCC_EA0_ATOMIC[95] TCC_ATOMIC[123] TCC_ATOMIC[47] TCC_HIT[57] TCC_HIT[69] TCC_ATOMIC[120] TCC_EA0_ATOMIC[69] TCC_HIT[50] TCC_ATOMIC[92] TCC_EA0_ATOMIC[112] TCC_HIT[105] TCC_HIT[27] TCC_BUBBLE[1] TCC_EA0_ATOMIC[18] TCC_HIT[72] TCC_BUBBLE[86] TCC_ATOMIC[11] TCC_HIT[113] TCC_BUBBLE[18] TCC_HIT[99] TCC_ATOMIC[0] TCC_BUBBLE[29] TCC_HIT[116] CPC_CPC_STAT_IDLE CPC_CPC_STAT_BUSY CPF_CPF_STAT_STALL CPF_CPF_STAT_IDLE SPI_RA_SGPR_SIMD_FULL_CSN SPI_CSQ_P1_OCCUPANCY SPI_CSQ_P2_OCCUPANCY SPI_CSQ_P0_OCCUPANCY SPI_CSQ_P3_OCCUPANCY + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_SMEM.yaml b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_SMEM.yaml new file mode 100644 index 0000000000..a8c352b332 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_SMEM.yaml @@ -0,0 +1,2565 @@ +SQ_INST_LEVEL_SMEM_ACCUM: + architectures: + gfx942/gfx941/gfx940/gfx90a: + expression: accumulate(SQ_INST_LEVEL_SMEM, HIGH_RES) + description: SQ_INST_LEVEL_SMEM accumulation +TCC_ATOMIC[0]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 0th XCC and 0th channel +TCC_ATOMIC[100]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 6th XCC and 4th channel +TCC_ATOMIC[101]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 6th XCC and 5th channel +TCC_ATOMIC[102]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 6th XCC and 6th channel +TCC_ATOMIC[103]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 6th XCC and 7th channel +TCC_ATOMIC[104]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 6th XCC and 8th channel +TCC_ATOMIC[105]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 6th XCC and 9th channel +TCC_ATOMIC[106]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 6th XCC and 10th channel +TCC_ATOMIC[107]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 6th XCC and 11th channel +TCC_ATOMIC[108]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 6th XCC and 12th channel +TCC_ATOMIC[109]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 6th XCC and 13th channel +TCC_ATOMIC[10]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 0th XCC and 10th channel +TCC_ATOMIC[110]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 6th XCC and 14th channel +TCC_ATOMIC[111]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 6th XCC and 15th channel +TCC_ATOMIC[112]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 7th XCC and 0th channel +TCC_ATOMIC[113]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 7th XCC and 1th channel +TCC_ATOMIC[114]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 7th XCC and 2th channel +TCC_ATOMIC[115]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 7th XCC and 3th channel +TCC_ATOMIC[116]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 7th XCC and 4th channel +TCC_ATOMIC[117]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 7th XCC and 5th channel +TCC_ATOMIC[118]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 7th XCC and 6th channel +TCC_ATOMIC[119]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 7th XCC and 7th channel +TCC_ATOMIC[11]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 0th XCC and 11th channel +TCC_ATOMIC[120]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 7th XCC and 8th channel +TCC_ATOMIC[121]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 7th XCC and 9th channel +TCC_ATOMIC[122]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 7th XCC and 10th channel +TCC_ATOMIC[123]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 7th XCC and 11th channel +TCC_ATOMIC[124]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 7th XCC and 12th channel +TCC_ATOMIC[125]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 7th XCC and 13th channel +TCC_ATOMIC[126]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 7th XCC and 14th channel +TCC_ATOMIC[127]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 7th XCC and 15th channel +TCC_ATOMIC[12]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 0th XCC and 12th channel +TCC_ATOMIC[13]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 0th XCC and 13th channel +TCC_ATOMIC[14]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 0th XCC and 14th channel +TCC_ATOMIC[15]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 0th XCC and 15th channel +TCC_ATOMIC[16]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 1th XCC and 0th channel +TCC_ATOMIC[17]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 1th XCC and 1th channel +TCC_ATOMIC[18]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 1th XCC and 2th channel +TCC_ATOMIC[19]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 1th XCC and 3th channel +TCC_ATOMIC[1]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 0th XCC and 1th channel +TCC_ATOMIC[20]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 1th XCC and 4th channel +TCC_ATOMIC[21]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 1th XCC and 5th channel +TCC_ATOMIC[22]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 1th XCC and 6th channel +TCC_ATOMIC[23]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 1th XCC and 7th channel +TCC_ATOMIC[24]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 1th XCC and 8th channel +TCC_ATOMIC[25]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 1th XCC and 9th channel +TCC_ATOMIC[26]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 1th XCC and 10th channel +TCC_ATOMIC[27]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 1th XCC and 11th channel +TCC_ATOMIC[28]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 1th XCC and 12th channel +TCC_ATOMIC[29]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 1th XCC and 13th channel +TCC_ATOMIC[2]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 0th XCC and 2th channel +TCC_ATOMIC[30]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 1th XCC and 14th channel +TCC_ATOMIC[31]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 1th XCC and 15th channel +TCC_ATOMIC[32]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 2th XCC and 0th channel +TCC_ATOMIC[33]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 2th XCC and 1th channel +TCC_ATOMIC[34]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 2th XCC and 2th channel +TCC_ATOMIC[35]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 2th XCC and 3th channel +TCC_ATOMIC[36]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 2th XCC and 4th channel +TCC_ATOMIC[37]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 2th XCC and 5th channel +TCC_ATOMIC[38]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 2th XCC and 6th channel +TCC_ATOMIC[39]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 2th XCC and 7th channel +TCC_ATOMIC[3]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 0th XCC and 3th channel +TCC_ATOMIC[40]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 2th XCC and 8th channel +TCC_ATOMIC[41]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 2th XCC and 9th channel +TCC_ATOMIC[42]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 2th XCC and 10th channel +TCC_ATOMIC[43]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 2th XCC and 11th channel +TCC_ATOMIC[44]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 2th XCC and 12th channel +TCC_ATOMIC[45]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 2th XCC and 13th channel +TCC_ATOMIC[46]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 2th XCC and 14th channel +TCC_ATOMIC[47]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 2th XCC and 15th channel +TCC_ATOMIC[48]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 3th XCC and 0th channel +TCC_ATOMIC[49]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 3th XCC and 1th channel +TCC_ATOMIC[4]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 0th XCC and 4th channel +TCC_ATOMIC[50]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 3th XCC and 2th channel +TCC_ATOMIC[51]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 3th XCC and 3th channel +TCC_ATOMIC[52]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 3th XCC and 4th channel +TCC_ATOMIC[53]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 3th XCC and 5th channel +TCC_ATOMIC[54]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 3th XCC and 6th channel +TCC_ATOMIC[55]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 3th XCC and 7th channel +TCC_ATOMIC[56]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 3th XCC and 8th channel +TCC_ATOMIC[57]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 3th XCC and 9th channel +TCC_ATOMIC[58]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 3th XCC and 10th channel +TCC_ATOMIC[59]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 3th XCC and 11th channel +TCC_ATOMIC[5]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 0th XCC and 5th channel +TCC_ATOMIC[60]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 3th XCC and 12th channel +TCC_ATOMIC[61]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 3th XCC and 13th channel +TCC_ATOMIC[62]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 3th XCC and 14th channel +TCC_ATOMIC[63]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 3th XCC and 15th channel +TCC_ATOMIC[64]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 4th XCC and 0th channel +TCC_ATOMIC[65]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 4th XCC and 1th channel +TCC_ATOMIC[66]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 4th XCC and 2th channel +TCC_ATOMIC[67]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 4th XCC and 3th channel +TCC_ATOMIC[68]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 4th XCC and 4th channel +TCC_ATOMIC[69]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 4th XCC and 5th channel +TCC_ATOMIC[6]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 0th XCC and 6th channel +TCC_ATOMIC[70]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 4th XCC and 6th channel +TCC_ATOMIC[71]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 4th XCC and 7th channel +TCC_ATOMIC[72]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 4th XCC and 8th channel +TCC_ATOMIC[73]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 4th XCC and 9th channel +TCC_ATOMIC[74]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 4th XCC and 10th channel +TCC_ATOMIC[75]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 4th XCC and 11th channel +TCC_ATOMIC[76]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 4th XCC and 12th channel +TCC_ATOMIC[77]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 4th XCC and 13th channel +TCC_ATOMIC[78]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 4th XCC and 14th channel +TCC_ATOMIC[79]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 4th XCC and 15th channel +TCC_ATOMIC[7]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 0th XCC and 7th channel +TCC_ATOMIC[80]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 5th XCC and 0th channel +TCC_ATOMIC[81]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 5th XCC and 1th channel +TCC_ATOMIC[82]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 5th XCC and 2th channel +TCC_ATOMIC[83]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 5th XCC and 3th channel +TCC_ATOMIC[84]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 5th XCC and 4th channel +TCC_ATOMIC[85]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 5th XCC and 5th channel +TCC_ATOMIC[86]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 5th XCC and 6th channel +TCC_ATOMIC[87]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 5th XCC and 7th channel +TCC_ATOMIC[88]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 5th XCC and 8th channel +TCC_ATOMIC[89]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 5th XCC and 9th channel +TCC_ATOMIC[8]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 0th XCC and 8th channel +TCC_ATOMIC[90]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 5th XCC and 10th channel +TCC_ATOMIC[91]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 5th XCC and 11th channel +TCC_ATOMIC[92]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 5th XCC and 12th channel +TCC_ATOMIC[93]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 5th XCC and 13th channel +TCC_ATOMIC[94]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 5th XCC and 14th channel +TCC_ATOMIC[95]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 5th XCC and 15th channel +TCC_ATOMIC[96]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 6th XCC and 0th channel +TCC_ATOMIC[97]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 6th XCC and 1th channel +TCC_ATOMIC[98]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 6th XCC and 2th channel +TCC_ATOMIC[99]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 6th XCC and 3th channel +TCC_ATOMIC[9]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 0th XCC and 9th channel +TCC_BUBBLE[0]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 0th XCC and 0th channel +TCC_BUBBLE[100]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 6th XCC and 4th channel +TCC_BUBBLE[101]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 6th XCC and 5th channel +TCC_BUBBLE[102]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 6th XCC and 6th channel +TCC_BUBBLE[103]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 6th XCC and 7th channel +TCC_BUBBLE[104]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 6th XCC and 8th channel +TCC_BUBBLE[105]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 6th XCC and 9th channel +TCC_BUBBLE[106]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 6th XCC and 10th channel +TCC_BUBBLE[107]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 6th XCC and 11th channel +TCC_BUBBLE[108]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 6th XCC and 12th channel +TCC_BUBBLE[109]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 6th XCC and 13th channel +TCC_BUBBLE[10]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 0th XCC and 10th channel +TCC_BUBBLE[110]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 6th XCC and 14th channel +TCC_BUBBLE[111]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 6th XCC and 15th channel +TCC_BUBBLE[112]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 7th XCC and 0th channel +TCC_BUBBLE[113]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 7th XCC and 1th channel +TCC_BUBBLE[114]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 7th XCC and 2th channel +TCC_BUBBLE[115]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 7th XCC and 3th channel +TCC_BUBBLE[116]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 7th XCC and 4th channel +TCC_BUBBLE[117]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 7th XCC and 5th channel +TCC_BUBBLE[118]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 7th XCC and 6th channel +TCC_BUBBLE[119]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 7th XCC and 7th channel +TCC_BUBBLE[11]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 0th XCC and 11th channel +TCC_BUBBLE[120]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 7th XCC and 8th channel +TCC_BUBBLE[121]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 7th XCC and 9th channel +TCC_BUBBLE[122]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 7th XCC and 10th channel +TCC_BUBBLE[123]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 7th XCC and 11th channel +TCC_BUBBLE[124]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 7th XCC and 12th channel +TCC_BUBBLE[125]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 7th XCC and 13th channel +TCC_BUBBLE[126]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 7th XCC and 14th channel +TCC_BUBBLE[127]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 7th XCC and 15th channel +TCC_BUBBLE[12]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 0th XCC and 12th channel +TCC_BUBBLE[13]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 0th XCC and 13th channel +TCC_BUBBLE[14]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 0th XCC and 14th channel +TCC_BUBBLE[15]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 0th XCC and 15th channel +TCC_BUBBLE[16]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 1th XCC and 0th channel +TCC_BUBBLE[17]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 1th XCC and 1th channel +TCC_BUBBLE[18]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 1th XCC and 2th channel +TCC_BUBBLE[19]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 1th XCC and 3th channel +TCC_BUBBLE[1]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 0th XCC and 1th channel +TCC_BUBBLE[20]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 1th XCC and 4th channel +TCC_BUBBLE[21]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 1th XCC and 5th channel +TCC_BUBBLE[22]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 1th XCC and 6th channel +TCC_BUBBLE[23]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 1th XCC and 7th channel +TCC_BUBBLE[24]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 1th XCC and 8th channel +TCC_BUBBLE[25]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 1th XCC and 9th channel +TCC_BUBBLE[26]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 1th XCC and 10th channel +TCC_BUBBLE[27]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 1th XCC and 11th channel +TCC_BUBBLE[28]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 1th XCC and 12th channel +TCC_BUBBLE[29]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 1th XCC and 13th channel +TCC_BUBBLE[2]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 0th XCC and 2th channel +TCC_BUBBLE[30]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 1th XCC and 14th channel +TCC_BUBBLE[31]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 1th XCC and 15th channel +TCC_BUBBLE[32]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 2th XCC and 0th channel +TCC_BUBBLE[33]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 2th XCC and 1th channel +TCC_BUBBLE[34]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 2th XCC and 2th channel +TCC_BUBBLE[35]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 2th XCC and 3th channel +TCC_BUBBLE[36]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 2th XCC and 4th channel +TCC_BUBBLE[37]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 2th XCC and 5th channel +TCC_BUBBLE[38]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 2th XCC and 6th channel +TCC_BUBBLE[39]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 2th XCC and 7th channel +TCC_BUBBLE[3]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 0th XCC and 3th channel +TCC_BUBBLE[40]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 2th XCC and 8th channel +TCC_BUBBLE[41]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 2th XCC and 9th channel +TCC_BUBBLE[42]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 2th XCC and 10th channel +TCC_BUBBLE[43]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 2th XCC and 11th channel +TCC_BUBBLE[44]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 2th XCC and 12th channel +TCC_BUBBLE[45]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 2th XCC and 13th channel +TCC_BUBBLE[46]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 2th XCC and 14th channel +TCC_BUBBLE[47]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 2th XCC and 15th channel +TCC_BUBBLE[48]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 3th XCC and 0th channel +TCC_BUBBLE[49]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 3th XCC and 1th channel +TCC_BUBBLE[4]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 0th XCC and 4th channel +TCC_BUBBLE[50]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 3th XCC and 2th channel +TCC_BUBBLE[51]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 3th XCC and 3th channel +TCC_BUBBLE[52]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 3th XCC and 4th channel +TCC_BUBBLE[53]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 3th XCC and 5th channel +TCC_BUBBLE[54]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 3th XCC and 6th channel +TCC_BUBBLE[55]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 3th XCC and 7th channel +TCC_BUBBLE[56]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 3th XCC and 8th channel +TCC_BUBBLE[57]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 3th XCC and 9th channel +TCC_BUBBLE[58]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 3th XCC and 10th channel +TCC_BUBBLE[59]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 3th XCC and 11th channel +TCC_BUBBLE[5]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 0th XCC and 5th channel +TCC_BUBBLE[60]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 3th XCC and 12th channel +TCC_BUBBLE[61]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 3th XCC and 13th channel +TCC_BUBBLE[62]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 3th XCC and 14th channel +TCC_BUBBLE[63]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 3th XCC and 15th channel +TCC_BUBBLE[64]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 4th XCC and 0th channel +TCC_BUBBLE[65]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 4th XCC and 1th channel +TCC_BUBBLE[66]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 4th XCC and 2th channel +TCC_BUBBLE[67]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 4th XCC and 3th channel +TCC_BUBBLE[68]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 4th XCC and 4th channel +TCC_BUBBLE[69]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 4th XCC and 5th channel +TCC_BUBBLE[6]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 0th XCC and 6th channel +TCC_BUBBLE[70]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 4th XCC and 6th channel +TCC_BUBBLE[71]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 4th XCC and 7th channel +TCC_BUBBLE[72]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 4th XCC and 8th channel +TCC_BUBBLE[73]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 4th XCC and 9th channel +TCC_BUBBLE[74]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 4th XCC and 10th channel +TCC_BUBBLE[75]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 4th XCC and 11th channel +TCC_BUBBLE[76]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 4th XCC and 12th channel +TCC_BUBBLE[77]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 4th XCC and 13th channel +TCC_BUBBLE[78]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 4th XCC and 14th channel +TCC_BUBBLE[79]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 4th XCC and 15th channel +TCC_BUBBLE[7]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 0th XCC and 7th channel +TCC_BUBBLE[80]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 5th XCC and 0th channel +TCC_BUBBLE[81]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 5th XCC and 1th channel +TCC_BUBBLE[82]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 5th XCC and 2th channel +TCC_BUBBLE[83]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 5th XCC and 3th channel +TCC_BUBBLE[84]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 5th XCC and 4th channel +TCC_BUBBLE[85]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 5th XCC and 5th channel +TCC_BUBBLE[86]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 5th XCC and 6th channel +TCC_BUBBLE[87]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 5th XCC and 7th channel +TCC_BUBBLE[88]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 5th XCC and 8th channel +TCC_BUBBLE[89]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 5th XCC and 9th channel +TCC_BUBBLE[8]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 0th XCC and 8th channel +TCC_BUBBLE[90]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 5th XCC and 10th channel +TCC_BUBBLE[91]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 5th XCC and 11th channel +TCC_BUBBLE[92]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 5th XCC and 12th channel +TCC_BUBBLE[93]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 5th XCC and 13th channel +TCC_BUBBLE[94]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 5th XCC and 14th channel +TCC_BUBBLE[95]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 5th XCC and 15th channel +TCC_BUBBLE[96]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 6th XCC and 0th channel +TCC_BUBBLE[97]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 6th XCC and 1th channel +TCC_BUBBLE[98]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 6th XCC and 2th channel +TCC_BUBBLE[99]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 6th XCC and 3th channel +TCC_BUBBLE[9]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 0th XCC and 9th channel +TCC_EA0_ATOMIC[0]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 0th XCC and 0th channel +TCC_EA0_ATOMIC[100]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 6th XCC and 4th channel +TCC_EA0_ATOMIC[101]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 6th XCC and 5th channel +TCC_EA0_ATOMIC[102]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 6th XCC and 6th channel +TCC_EA0_ATOMIC[103]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 6th XCC and 7th channel +TCC_EA0_ATOMIC[104]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 6th XCC and 8th channel +TCC_EA0_ATOMIC[105]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 6th XCC and 9th channel +TCC_EA0_ATOMIC[106]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 6th XCC and 10th channel +TCC_EA0_ATOMIC[107]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 6th XCC and 11th channel +TCC_EA0_ATOMIC[108]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 6th XCC and 12th channel +TCC_EA0_ATOMIC[109]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 6th XCC and 13th channel +TCC_EA0_ATOMIC[10]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 0th XCC and 10th channel +TCC_EA0_ATOMIC[110]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 6th XCC and 14th channel +TCC_EA0_ATOMIC[111]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 6th XCC and 15th channel +TCC_EA0_ATOMIC[112]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 7th XCC and 0th channel +TCC_EA0_ATOMIC[113]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 7th XCC and 1th channel +TCC_EA0_ATOMIC[114]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 7th XCC and 2th channel +TCC_EA0_ATOMIC[115]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 7th XCC and 3th channel +TCC_EA0_ATOMIC[116]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 7th XCC and 4th channel +TCC_EA0_ATOMIC[117]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 7th XCC and 5th channel +TCC_EA0_ATOMIC[118]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 7th XCC and 6th channel +TCC_EA0_ATOMIC[119]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 7th XCC and 7th channel +TCC_EA0_ATOMIC[11]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 0th XCC and 11th channel +TCC_EA0_ATOMIC[120]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 7th XCC and 8th channel +TCC_EA0_ATOMIC[121]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 7th XCC and 9th channel +TCC_EA0_ATOMIC[122]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 7th XCC and 10th channel +TCC_EA0_ATOMIC[123]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 7th XCC and 11th channel +TCC_EA0_ATOMIC[124]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 7th XCC and 12th channel +TCC_EA0_ATOMIC[125]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 7th XCC and 13th channel +TCC_EA0_ATOMIC[126]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 7th XCC and 14th channel +TCC_EA0_ATOMIC[127]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 7th XCC and 15th channel +TCC_EA0_ATOMIC[12]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 0th XCC and 12th channel +TCC_EA0_ATOMIC[13]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 0th XCC and 13th channel +TCC_EA0_ATOMIC[14]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 0th XCC and 14th channel +TCC_EA0_ATOMIC[15]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 0th XCC and 15th channel +TCC_EA0_ATOMIC[16]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 1th XCC and 0th channel +TCC_EA0_ATOMIC[17]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 1th XCC and 1th channel +TCC_EA0_ATOMIC[18]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 1th XCC and 2th channel +TCC_EA0_ATOMIC[19]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 1th XCC and 3th channel +TCC_EA0_ATOMIC[1]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 0th XCC and 1th channel +TCC_EA0_ATOMIC[20]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 1th XCC and 4th channel +TCC_EA0_ATOMIC[21]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 1th XCC and 5th channel +TCC_EA0_ATOMIC[22]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 1th XCC and 6th channel +TCC_EA0_ATOMIC[23]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 1th XCC and 7th channel +TCC_EA0_ATOMIC[24]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 1th XCC and 8th channel +TCC_EA0_ATOMIC[25]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 1th XCC and 9th channel +TCC_EA0_ATOMIC[26]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 1th XCC and 10th channel +TCC_EA0_ATOMIC[27]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 1th XCC and 11th channel +TCC_EA0_ATOMIC[28]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 1th XCC and 12th channel +TCC_EA0_ATOMIC[29]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 1th XCC and 13th channel +TCC_EA0_ATOMIC[2]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 0th XCC and 2th channel +TCC_EA0_ATOMIC[30]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 1th XCC and 14th channel +TCC_EA0_ATOMIC[31]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 1th XCC and 15th channel +TCC_EA0_ATOMIC[32]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 2th XCC and 0th channel +TCC_EA0_ATOMIC[33]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 2th XCC and 1th channel +TCC_EA0_ATOMIC[34]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 2th XCC and 2th channel +TCC_EA0_ATOMIC[35]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 2th XCC and 3th channel +TCC_EA0_ATOMIC[36]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 2th XCC and 4th channel +TCC_EA0_ATOMIC[37]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 2th XCC and 5th channel +TCC_EA0_ATOMIC[38]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 2th XCC and 6th channel +TCC_EA0_ATOMIC[39]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 2th XCC and 7th channel +TCC_EA0_ATOMIC[3]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 0th XCC and 3th channel +TCC_EA0_ATOMIC[40]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 2th XCC and 8th channel +TCC_EA0_ATOMIC[41]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 2th XCC and 9th channel +TCC_EA0_ATOMIC[42]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 2th XCC and 10th channel +TCC_EA0_ATOMIC[43]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 2th XCC and 11th channel +TCC_EA0_ATOMIC[44]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 2th XCC and 12th channel +TCC_EA0_ATOMIC[45]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 2th XCC and 13th channel +TCC_EA0_ATOMIC[46]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 2th XCC and 14th channel +TCC_EA0_ATOMIC[47]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 2th XCC and 15th channel +TCC_EA0_ATOMIC[48]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 3th XCC and 0th channel +TCC_EA0_ATOMIC[49]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 3th XCC and 1th channel +TCC_EA0_ATOMIC[4]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 0th XCC and 4th channel +TCC_EA0_ATOMIC[50]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 3th XCC and 2th channel +TCC_EA0_ATOMIC[51]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 3th XCC and 3th channel +TCC_EA0_ATOMIC[52]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 3th XCC and 4th channel +TCC_EA0_ATOMIC[53]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 3th XCC and 5th channel +TCC_EA0_ATOMIC[54]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 3th XCC and 6th channel +TCC_EA0_ATOMIC[55]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 3th XCC and 7th channel +TCC_EA0_ATOMIC[56]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 3th XCC and 8th channel +TCC_EA0_ATOMIC[57]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 3th XCC and 9th channel +TCC_EA0_ATOMIC[58]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 3th XCC and 10th channel +TCC_EA0_ATOMIC[59]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 3th XCC and 11th channel +TCC_EA0_ATOMIC[5]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 0th XCC and 5th channel +TCC_EA0_ATOMIC[60]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 3th XCC and 12th channel +TCC_EA0_ATOMIC[61]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 3th XCC and 13th channel +TCC_EA0_ATOMIC[62]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 3th XCC and 14th channel +TCC_EA0_ATOMIC[63]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 3th XCC and 15th channel +TCC_EA0_ATOMIC[64]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 4th XCC and 0th channel +TCC_EA0_ATOMIC[65]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 4th XCC and 1th channel +TCC_EA0_ATOMIC[66]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 4th XCC and 2th channel +TCC_EA0_ATOMIC[67]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 4th XCC and 3th channel +TCC_EA0_ATOMIC[68]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 4th XCC and 4th channel +TCC_EA0_ATOMIC[69]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 4th XCC and 5th channel +TCC_EA0_ATOMIC[6]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 0th XCC and 6th channel +TCC_EA0_ATOMIC[70]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 4th XCC and 6th channel +TCC_EA0_ATOMIC[71]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 4th XCC and 7th channel +TCC_EA0_ATOMIC[72]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 4th XCC and 8th channel +TCC_EA0_ATOMIC[73]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 4th XCC and 9th channel +TCC_EA0_ATOMIC[74]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 4th XCC and 10th channel +TCC_EA0_ATOMIC[75]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 4th XCC and 11th channel +TCC_EA0_ATOMIC[76]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 4th XCC and 12th channel +TCC_EA0_ATOMIC[77]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 4th XCC and 13th channel +TCC_EA0_ATOMIC[78]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 4th XCC and 14th channel +TCC_EA0_ATOMIC[79]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 4th XCC and 15th channel +TCC_EA0_ATOMIC[7]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 0th XCC and 7th channel +TCC_EA0_ATOMIC[80]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 5th XCC and 0th channel +TCC_EA0_ATOMIC[81]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 5th XCC and 1th channel +TCC_EA0_ATOMIC[82]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 5th XCC and 2th channel +TCC_EA0_ATOMIC[83]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 5th XCC and 3th channel +TCC_EA0_ATOMIC[84]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 5th XCC and 4th channel +TCC_EA0_ATOMIC[85]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 5th XCC and 5th channel +TCC_EA0_ATOMIC[86]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 5th XCC and 6th channel +TCC_EA0_ATOMIC[87]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 5th XCC and 7th channel +TCC_EA0_ATOMIC[88]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 5th XCC and 8th channel +TCC_EA0_ATOMIC[89]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 5th XCC and 9th channel +TCC_EA0_ATOMIC[8]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 0th XCC and 8th channel +TCC_EA0_ATOMIC[90]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 5th XCC and 10th channel +TCC_EA0_ATOMIC[91]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 5th XCC and 11th channel +TCC_EA0_ATOMIC[92]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 5th XCC and 12th channel +TCC_EA0_ATOMIC[93]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 5th XCC and 13th channel +TCC_EA0_ATOMIC[94]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 5th XCC and 14th channel +TCC_EA0_ATOMIC[95]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 5th XCC and 15th channel +TCC_EA0_ATOMIC[96]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 6th XCC and 0th channel +TCC_EA0_ATOMIC[97]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 6th XCC and 1th channel +TCC_EA0_ATOMIC[98]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 6th XCC and 2th channel +TCC_EA0_ATOMIC[99]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 6th XCC and 3th channel +TCC_EA0_ATOMIC[9]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 0th XCC and 9th channel +TCC_HIT[0]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 0th XCC and 0th channel +TCC_HIT[100]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 6th XCC and 4th channel +TCC_HIT[101]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 6th XCC and 5th channel +TCC_HIT[102]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 6th XCC and 6th channel +TCC_HIT[103]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 6th XCC and 7th channel +TCC_HIT[104]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 6th XCC and 8th channel +TCC_HIT[105]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 6th XCC and 9th channel +TCC_HIT[106]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 6th XCC and 10th channel +TCC_HIT[107]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 6th XCC and 11th channel +TCC_HIT[108]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 6th XCC and 12th channel +TCC_HIT[109]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 6th XCC and 13th channel +TCC_HIT[10]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 0th XCC and 10th channel +TCC_HIT[110]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 6th XCC and 14th channel +TCC_HIT[111]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 6th XCC and 15th channel +TCC_HIT[112]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 7th XCC and 0th channel +TCC_HIT[113]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 7th XCC and 1th channel +TCC_HIT[114]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 7th XCC and 2th channel +TCC_HIT[115]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 7th XCC and 3th channel +TCC_HIT[116]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 7th XCC and 4th channel +TCC_HIT[117]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 7th XCC and 5th channel +TCC_HIT[118]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 7th XCC and 6th channel +TCC_HIT[119]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 7th XCC and 7th channel +TCC_HIT[11]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 0th XCC and 11th channel +TCC_HIT[120]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 7th XCC and 8th channel +TCC_HIT[121]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 7th XCC and 9th channel +TCC_HIT[122]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 7th XCC and 10th channel +TCC_HIT[123]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 7th XCC and 11th channel +TCC_HIT[124]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 7th XCC and 12th channel +TCC_HIT[125]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 7th XCC and 13th channel +TCC_HIT[126]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 7th XCC and 14th channel +TCC_HIT[127]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 7th XCC and 15th channel +TCC_HIT[12]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 0th XCC and 12th channel +TCC_HIT[13]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 0th XCC and 13th channel +TCC_HIT[14]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 0th XCC and 14th channel +TCC_HIT[15]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 0th XCC and 15th channel +TCC_HIT[16]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 1th XCC and 0th channel +TCC_HIT[17]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 1th XCC and 1th channel +TCC_HIT[18]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 1th XCC and 2th channel +TCC_HIT[19]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 1th XCC and 3th channel +TCC_HIT[1]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 0th XCC and 1th channel +TCC_HIT[20]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 1th XCC and 4th channel +TCC_HIT[21]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 1th XCC and 5th channel +TCC_HIT[22]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 1th XCC and 6th channel +TCC_HIT[23]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 1th XCC and 7th channel +TCC_HIT[24]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 1th XCC and 8th channel +TCC_HIT[25]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 1th XCC and 9th channel +TCC_HIT[26]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 1th XCC and 10th channel +TCC_HIT[27]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 1th XCC and 11th channel +TCC_HIT[28]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 1th XCC and 12th channel +TCC_HIT[29]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 1th XCC and 13th channel +TCC_HIT[2]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 0th XCC and 2th channel +TCC_HIT[30]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 1th XCC and 14th channel +TCC_HIT[31]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 1th XCC and 15th channel +TCC_HIT[32]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 2th XCC and 0th channel +TCC_HIT[33]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 2th XCC and 1th channel +TCC_HIT[34]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 2th XCC and 2th channel +TCC_HIT[35]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 2th XCC and 3th channel +TCC_HIT[36]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 2th XCC and 4th channel +TCC_HIT[37]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 2th XCC and 5th channel +TCC_HIT[38]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 2th XCC and 6th channel +TCC_HIT[39]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 2th XCC and 7th channel +TCC_HIT[3]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 0th XCC and 3th channel +TCC_HIT[40]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 2th XCC and 8th channel +TCC_HIT[41]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 2th XCC and 9th channel +TCC_HIT[42]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 2th XCC and 10th channel +TCC_HIT[43]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 2th XCC and 11th channel +TCC_HIT[44]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 2th XCC and 12th channel +TCC_HIT[45]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 2th XCC and 13th channel +TCC_HIT[46]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 2th XCC and 14th channel +TCC_HIT[47]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 2th XCC and 15th channel +TCC_HIT[48]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 3th XCC and 0th channel +TCC_HIT[49]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 3th XCC and 1th channel +TCC_HIT[4]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 0th XCC and 4th channel +TCC_HIT[50]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 3th XCC and 2th channel +TCC_HIT[51]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 3th XCC and 3th channel +TCC_HIT[52]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 3th XCC and 4th channel +TCC_HIT[53]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 3th XCC and 5th channel +TCC_HIT[54]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 3th XCC and 6th channel +TCC_HIT[55]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 3th XCC and 7th channel +TCC_HIT[56]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 3th XCC and 8th channel +TCC_HIT[57]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 3th XCC and 9th channel +TCC_HIT[58]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 3th XCC and 10th channel +TCC_HIT[59]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 3th XCC and 11th channel +TCC_HIT[5]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 0th XCC and 5th channel +TCC_HIT[60]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 3th XCC and 12th channel +TCC_HIT[61]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 3th XCC and 13th channel +TCC_HIT[62]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 3th XCC and 14th channel +TCC_HIT[63]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 3th XCC and 15th channel +TCC_HIT[64]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 4th XCC and 0th channel +TCC_HIT[65]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 4th XCC and 1th channel +TCC_HIT[66]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 4th XCC and 2th channel +TCC_HIT[67]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 4th XCC and 3th channel +TCC_HIT[68]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 4th XCC and 4th channel +TCC_HIT[69]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 4th XCC and 5th channel +TCC_HIT[6]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 0th XCC and 6th channel +TCC_HIT[70]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 4th XCC and 6th channel +TCC_HIT[71]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 4th XCC and 7th channel +TCC_HIT[72]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 4th XCC and 8th channel +TCC_HIT[73]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 4th XCC and 9th channel +TCC_HIT[74]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 4th XCC and 10th channel +TCC_HIT[75]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 4th XCC and 11th channel +TCC_HIT[76]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 4th XCC and 12th channel +TCC_HIT[77]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 4th XCC and 13th channel +TCC_HIT[78]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 4th XCC and 14th channel +TCC_HIT[79]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 4th XCC and 15th channel +TCC_HIT[7]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 0th XCC and 7th channel +TCC_HIT[80]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 5th XCC and 0th channel +TCC_HIT[81]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 5th XCC and 1th channel +TCC_HIT[82]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 5th XCC and 2th channel +TCC_HIT[83]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 5th XCC and 3th channel +TCC_HIT[84]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 5th XCC and 4th channel +TCC_HIT[85]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 5th XCC and 5th channel +TCC_HIT[86]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 5th XCC and 6th channel +TCC_HIT[87]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 5th XCC and 7th channel +TCC_HIT[88]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 5th XCC and 8th channel +TCC_HIT[89]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 5th XCC and 9th channel +TCC_HIT[8]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 0th XCC and 8th channel +TCC_HIT[90]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 5th XCC and 10th channel +TCC_HIT[91]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 5th XCC and 11th channel +TCC_HIT[92]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 5th XCC and 12th channel +TCC_HIT[93]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 5th XCC and 13th channel +TCC_HIT[94]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 5th XCC and 14th channel +TCC_HIT[95]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 5th XCC and 15th channel +TCC_HIT[96]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 6th XCC and 0th channel +TCC_HIT[97]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 6th XCC and 1th channel +TCC_HIT[98]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 6th XCC and 2th channel +TCC_HIT[99]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 6th XCC and 3th channel +TCC_HIT[9]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 0th XCC and 9th channel diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt new file mode 100644 index 0000000000..7f8a7f6cd5 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt @@ -0,0 +1,5 @@ +pmc: SQ_INST_LEVEL_VMEM SQ_INST_LEVEL_VMEM_ACCUM SQ_INSTS_VSKIPPED SQ_INSTS_VALU_MFMA_MOPS_F32 SQ_INSTS_VALU_MFMA_F16 SQ_ACTIVE_INST_VMEM SQ_INSTS_LDS_ATOMIC SQ_INSTS_GDS TA_ADDR_STALLED_BY_TD_CYCLES_sum TA_BUFFER_COALESCED_READ_CYCLES_sum TD_SPI_STALL_sum TD_COALESCABLE_WAVEFRONT_sum TCP_READ_TAGCONFLICT_STALL_CYCLES_sum TCP_TCC_RW_READ_REQ_sum TCP_TCC_NC_WRITE_REQ_sum TCP_TCP_LATENCY_sum TCC_WRITE[52] TCC_READ[108] TCC_MISS[73] TCC_EA0_WRREQ[34] TCC_MISS[95] TCC_WRITE[12] TCC_READ[14] TCC_MISS[62] TCC_READ[21] TCC_READ[118] TCC_MISS[98] TCC_MISS[112] TCC_EA0_WRREQ[31] TCC_MISS[77] TCC_MISS[39] TCC_WRITE[33] TCC_WRITE[54] TCC_EA0_WRREQ[75] TCC_WRITE[89] TCC_EA0_WRREQ[37] TCC_READ[69] TCC_READ[53] TCC_MISS[59] TCC_WRITE[51] TCC_EA0_WRREQ[127] TCC_WRITE[38] TCC_EA0_WRREQ[117] TCC_EA0_WRREQ[0] TCC_EA0_WRREQ[64] TCC_EA0_WRREQ[93] TCC_EA0_WRREQ[57] TCC_READ[28] TCC_MISS[107] TCC_READ[24] TCC_WRITE[126] TCC_WRITE[69] TCC_EA0_WRREQ[102] TCC_EA0_WRREQ[25] TCC_EA0_WRREQ[32] TCC_EA0_WRREQ[26] TCC_MISS[84] TCC_WRITE[123] TCC_READ[110] TCC_READ[12] TCC_EA0_WRREQ[55] TCC_EA0_WRREQ[20] TCC_WRITE[6] TCC_READ[61] TCC_EA0_WRREQ[72] TCC_READ[57] TCC_WRITE[113] TCC_WRITE[118] TCC_EA0_WRREQ[114] TCC_WRITE[99] TCC_READ[49] TCC_WRITE[100] TCC_WRITE[106] TCC_READ[70] TCC_WRITE[28] TCC_MISS[60] TCC_WRITE[39] TCC_MISS[99] TCC_MISS[32] TCC_MISS[114] TCC_EA0_WRREQ[63] TCC_READ[121] TCC_WRITE[66] TCC_EA0_WRREQ[62] TCC_EA0_WRREQ[97] TCC_EA0_WRREQ[94] TCC_EA0_WRREQ[96] TCC_MISS[50] TCC_EA0_WRREQ[29] TCC_EA0_WRREQ[18] TCC_WRITE[85] TCC_EA0_WRREQ[7] TCC_READ[117] TCC_MISS[45] TCC_WRITE[62] TCC_MISS[37] TCC_READ[15] TCC_MISS[116] TCC_MISS[90] TCC_EA0_WRREQ[77] TCC_MISS[100] TCC_EA0_WRREQ[48] TCC_MISS[55] TCC_EA0_WRREQ[99] TCC_READ[35] TCC_WRITE[64] TCC_READ[59] TCC_EA0_WRREQ[126] TCC_READ[71] TCC_READ[122] TCC_MISS[127] TCC_READ[114] TCC_MISS[106] TCC_MISS[8] TCC_READ[6] TCC_WRITE[2] TCC_READ[73] TCC_MISS[103] TCC_READ[41] TCC_MISS[109] TCC_EA0_WRREQ[78] TCC_WRITE[24] TCC_EA0_WRREQ[58] TCC_MISS[83] TCC_MISS[18] TCC_MISS[91] TCC_READ[72] TCC_READ[101] TCC_MISS[80] TCC_MISS[58] TCC_MISS[67] TCC_MISS[93] TCC_MISS[122] TCC_MISS[74] TCC_WRITE[98] TCC_MISS[81] TCC_EA0_WRREQ[119] TCC_MISS[104] TCC_WRITE[121] TCC_WRITE[60] TCC_WRITE[53] TCC_EA0_WRREQ[85] TCC_EA0_WRREQ[4] TCC_READ[45] TCC_MISS[63] TCC_EA0_WRREQ[8] TCC_EA0_WRREQ[61] TCC_EA0_WRREQ[74] TCC_EA0_WRREQ[9] TCC_EA0_WRREQ[6] TCC_MISS[12] TCC_WRITE[83] TCC_MISS[71] TCC_WRITE[41] TCC_WRITE[124] TCC_MISS[4] TCC_READ[126] TCC_WRITE[8] TCC_READ[127] TCC_MISS[76] TCC_EA0_WRREQ[38] TCC_READ[56] TCC_WRITE[102] TCC_WRITE[72] TCC_READ[77] TCC_MISS[2] TCC_MISS[38] TCC_WRITE[90] TCC_MISS[10] TCC_WRITE[104] TCC_WRITE[4] TCC_READ[88] TCC_READ[9] TCC_WRITE[127] TCC_MISS[119] TCC_MISS[65] TCC_READ[96] TCC_MISS[14] TCC_WRITE[14] TCC_MISS[19] TCC_EA0_WRREQ[125] TCC_EA0_WRREQ[14] TCC_EA0_WRREQ[109] TCC_WRITE[48] TCC_EA0_WRREQ[52] TCC_MISS[54] TCC_READ[10] TCC_READ[63] TCC_WRITE[16] TCC_READ[87] TCC_MISS[89] TCC_EA0_WRREQ[53] TCC_EA0_WRREQ[49] TCC_WRITE[45] TCC_WRITE[76] TCC_READ[62] TCC_EA0_WRREQ[22] TCC_EA0_WRREQ[12] TCC_WRITE[36] TCC_EA0_WRREQ[11] TCC_READ[95] TCC_READ[113] TCC_READ[106] TCC_EA0_WRREQ[23] TCC_READ[120] TCC_MISS[92] TCC_WRITE[9] TCC_EA0_WRREQ[39] TCC_WRITE[18] TCC_MISS[20] TCC_MISS[82] TCC_READ[5] TCC_WRITE[0] TCC_WRITE[10] TCC_READ[36] TCC_MISS[26] TCC_WRITE[115] TCC_MISS[75] TCC_WRITE[81] TCC_WRITE[15] TCC_EA0_WRREQ[67] TCC_MISS[97] TCC_WRITE[3] TCC_WRITE[75] TCC_READ[13] TCC_WRITE[44] TCC_EA0_WRREQ[92] TCC_READ[76] TCC_WRITE[92] TCC_MISS[102] TCC_WRITE[57] TCC_EA0_WRREQ[121] TCC_WRITE[78] TCC_EA0_WRREQ[83] TCC_EA0_WRREQ[80] TCC_READ[91] TCC_WRITE[112] TCC_WRITE[120] TCC_MISS[41] TCC_READ[84] TCC_MISS[11] TCC_READ[39] TCC_WRITE[116] TCC_WRITE[71] TCC_EA0_WRREQ[115] TCC_MISS[111] TCC_EA0_WRREQ[59] TCC_READ[111] TCC_WRITE[50] TCC_MISS[124] TCC_MISS[66] TCC_READ[7] TCC_WRITE[119] TCC_READ[109] TCC_READ[80] TCC_WRITE[11] TCC_MISS[5] TCC_WRITE[37] TCC_WRITE[56] TCC_EA0_WRREQ[108] TCC_MISS[51] TCC_WRITE[19] TCC_WRITE[30] TCC_WRITE[117] TCC_MISS[126] TCC_READ[54] TCC_EA0_WRREQ[40] TCC_MISS[108] TCC_WRITE[43] TCC_MISS[7] TCC_WRITE[58] TCC_WRITE[67] TCC_READ[105] TCC_EA0_WRREQ[79] TCC_WRITE[91] TCC_EA0_WRREQ[111] TCC_WRITE[87] TCC_WRITE[34] TCC_READ[2] TCC_READ[116] TCC_WRITE[122] TCC_MISS[88] TCC_EA0_WRREQ[17] TCC_WRITE[96] TCC_READ[112] TCC_EA0_WRREQ[84] TCC_WRITE[17] TCC_MISS[23] TCC_EA0_WRREQ[86] TCC_WRITE[23] TCC_READ[11] TCC_MISS[27] TCC_READ[124] TCC_MISS[21] TCC_WRITE[46] TCC_EA0_WRREQ[82] TCC_WRITE[27] TCC_MISS[48] TCC_MISS[125] TCC_WRITE[7] TCC_READ[8] TCC_WRITE[101] TCC_EA0_WRREQ[71] TCC_READ[58] TCC_MISS[49] TCC_WRITE[95] TCC_READ[99] TCC_EA0_WRREQ[69] TCC_READ[119] TCC_READ[82] TCC_EA0_WRREQ[41] TCC_EA0_WRREQ[42] TCC_MISS[110] TCC_READ[66] TCC_MISS[70] TCC_MISS[17] TCC_MISS[120] TCC_MISS[31] TCC_MISS[28] TCC_EA0_WRREQ[45] TCC_WRITE[20] TCC_EA0_WRREQ[116] TCC_WRITE[109] TCC_WRITE[13] TCC_EA0_WRREQ[13] TCC_READ[85] TCC_READ[38] TCC_READ[34] TCC_EA0_WRREQ[87] TCC_EA0_WRREQ[30] TCC_MISS[86] TCC_READ[52] TCC_MISS[79] TCC_READ[22] TCC_EA0_WRREQ[66] TCC_WRITE[26] TCC_WRITE[32] TCC_MISS[115] TCC_MISS[13] TCC_MISS[15] TCC_WRITE[59] TCC_WRITE[97] TCC_READ[46] TCC_WRITE[65] TCC_EA0_WRREQ[16] TCC_WRITE[21] TCC_EA0_WRREQ[65] TCC_WRITE[108] TCC_EA0_WRREQ[76] TCC_WRITE[42] TCC_EA0_WRREQ[110] TCC_EA0_WRREQ[91] TCC_MISS[64] TCC_WRITE[73] TCC_WRITE[93] TCC_MISS[1] TCC_EA0_WRREQ[3] TCC_READ[29] TCC_WRITE[80] TCC_MISS[69] TCC_MISS[22] TCC_READ[92] TCC_EA0_WRREQ[56] TCC_EA0_WRREQ[68] TCC_EA0_WRREQ[98] TCC_MISS[118] TCC_READ[67] TCC_READ[86] TCC_MISS[24] TCC_READ[30] TCC_EA0_WRREQ[60] TCC_EA0_WRREQ[28] TCC_WRITE[82] TCC_EA0_WRREQ[54] TCC_WRITE[77] TCC_MISS[53] TCC_MISS[117] TCC_EA0_WRREQ[103] TCC_MISS[56] TCC_WRITE[1] TCC_READ[55] TCC_MISS[94] TCC_MISS[105] TCC_READ[123] TCC_EA0_WRREQ[19] TCC_READ[64] TCC_EA0_WRREQ[106] TCC_WRITE[35] TCC_READ[51] TCC_MISS[34] TCC_WRITE[88] TCC_READ[44] TCC_MISS[36] TCC_EA0_WRREQ[1] TCC_EA0_WRREQ[44] TCC_MISS[87] TCC_READ[103] TCC_WRITE[31] TCC_READ[90] TCC_READ[75] TCC_EA0_WRREQ[47] TCC_EA0_WRREQ[112] TCC_MISS[78] TCC_EA0_WRREQ[2] TCC_WRITE[5] TCC_READ[4] TCC_READ[16] TCC_WRITE[86] TCC_EA0_WRREQ[89] TCC_WRITE[68] TCC_READ[20] TCC_MISS[9] TCC_WRITE[63] TCC_MISS[35] TCC_READ[94] TCC_EA0_WRREQ[73] TCC_WRITE[29] TCC_MISS[57] TCC_MISS[85] TCC_EA0_WRREQ[5] TCC_MISS[43] TCC_READ[32] TCC_READ[65] TCC_READ[93] TCC_READ[100] TCC_WRITE[49] TCC_MISS[47] TCC_READ[98] TCC_EA0_WRREQ[95] TCC_READ[1] TCC_READ[79] TCC_EA0_WRREQ[70] TCC_EA0_WRREQ[120] TCC_READ[107] TCC_READ[81] TCC_MISS[0] TCC_READ[42] TCC_WRITE[25] TCC_EA0_WRREQ[122] TCC_WRITE[110] TCC_MISS[121] TCC_WRITE[79] TCC_READ[0] TCC_EA0_WRREQ[21] TCC_READ[104] TCC_MISS[52] TCC_READ[125] TCC_EA0_WRREQ[43] TCC_EA0_WRREQ[123] TCC_EA0_WRREQ[107] TCC_READ[18] TCC_WRITE[74] TCC_READ[83] TCC_WRITE[22] TCC_READ[68] TCC_MISS[61] TCC_MISS[30] TCC_READ[33] TCC_WRITE[55] TCC_EA0_WRREQ[50] TCC_WRITE[111] TCC_EA0_WRREQ[124] TCC_READ[48] TCC_MISS[123] TCC_READ[19] TCC_WRITE[84] TCC_WRITE[114] TCC_READ[26] TCC_EA0_WRREQ[36] TCC_READ[89] TCC_MISS[46] TCC_EA0_WRREQ[24] TCC_WRITE[105] TCC_EA0_WRREQ[101] TCC_READ[97] TCC_WRITE[61] TCC_WRITE[125] TCC_MISS[29] TCC_READ[17] TCC_MISS[33] TCC_WRITE[94] TCC_MISS[96] TCC_EA0_WRREQ[113] TCC_EA0_WRREQ[27] TCC_MISS[44] TCC_EA0_WRREQ[46] TCC_READ[23] TCC_READ[40] TCC_WRITE[107] TCC_EA0_WRREQ[35] TCC_EA0_WRREQ[81] TCC_EA0_WRREQ[51] TCC_MISS[40] TCC_READ[102] TCC_MISS[113] TCC_READ[115] TCC_READ[60] TCC_READ[3] TCC_EA0_WRREQ[88] TCC_READ[43] TCC_MISS[68] TCC_EA0_WRREQ[104] TCC_MISS[72] TCC_READ[47] TCC_EA0_WRREQ[105] TCC_EA0_WRREQ[33] TCC_READ[25] TCC_EA0_WRREQ[90] TCC_MISS[16] TCC_EA0_WRREQ[118] TCC_READ[31] TCC_WRITE[40] TCC_EA0_WRREQ[15] TCC_MISS[25] TCC_READ[50] TCC_READ[27] TCC_READ[74] TCC_MISS[101] TCC_MISS[3] TCC_WRITE[103] TCC_MISS[6] TCC_READ[37] TCC_WRITE[70] TCC_MISS[42] TCC_EA0_WRREQ[10] TCC_READ[78] TCC_EA0_WRREQ[100] TCC_WRITE[47] CPC_CANE_STALL CPC_CPC_STAT_STALL CPF_CPF_TCIU_STALL CPF_CPF_TCIU_BUSY SPI_CS1_CRAWLER_STALL SPI_CS0_CRAWLER_STALL SPI_CS3_CRAWLER_STALL SPI_CS2_CRAWLER_STALL GRBM_SPI_BUSY GRBM_COUNT + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_VMEM.yaml b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_VMEM.yaml new file mode 100644 index 0000000000..6f24742891 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_INST_LEVEL_VMEM.yaml @@ -0,0 +1,2565 @@ +SQ_INST_LEVEL_VMEM_ACCUM: + architectures: + gfx942/gfx941/gfx940/gfx90a: + expression: accumulate(SQ_INST_LEVEL_VMEM, HIGH_RES) + description: SQ_INST_LEVEL_VMEM accumulation +TCC_EA0_WRREQ[0]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 0th XCC and 0th channel +TCC_EA0_WRREQ[100]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 6th XCC and 4th channel +TCC_EA0_WRREQ[101]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 6th XCC and 5th channel +TCC_EA0_WRREQ[102]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 6th XCC and 6th channel +TCC_EA0_WRREQ[103]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 6th XCC and 7th channel +TCC_EA0_WRREQ[104]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 6th XCC and 8th channel +TCC_EA0_WRREQ[105]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 6th XCC and 9th channel +TCC_EA0_WRREQ[106]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 6th XCC and 10th channel +TCC_EA0_WRREQ[107]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 6th XCC and 11th channel +TCC_EA0_WRREQ[108]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 6th XCC and 12th channel +TCC_EA0_WRREQ[109]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 6th XCC and 13th channel +TCC_EA0_WRREQ[10]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 0th XCC and 10th channel +TCC_EA0_WRREQ[110]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 6th XCC and 14th channel +TCC_EA0_WRREQ[111]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 6th XCC and 15th channel +TCC_EA0_WRREQ[112]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 7th XCC and 0th channel +TCC_EA0_WRREQ[113]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 7th XCC and 1th channel +TCC_EA0_WRREQ[114]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 7th XCC and 2th channel +TCC_EA0_WRREQ[115]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 7th XCC and 3th channel +TCC_EA0_WRREQ[116]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 7th XCC and 4th channel +TCC_EA0_WRREQ[117]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 7th XCC and 5th channel +TCC_EA0_WRREQ[118]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 7th XCC and 6th channel +TCC_EA0_WRREQ[119]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 7th XCC and 7th channel +TCC_EA0_WRREQ[11]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 0th XCC and 11th channel +TCC_EA0_WRREQ[120]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 7th XCC and 8th channel +TCC_EA0_WRREQ[121]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 7th XCC and 9th channel +TCC_EA0_WRREQ[122]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 7th XCC and 10th channel +TCC_EA0_WRREQ[123]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 7th XCC and 11th channel +TCC_EA0_WRREQ[124]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 7th XCC and 12th channel +TCC_EA0_WRREQ[125]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 7th XCC and 13th channel +TCC_EA0_WRREQ[126]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 7th XCC and 14th channel +TCC_EA0_WRREQ[127]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 7th XCC and 15th channel +TCC_EA0_WRREQ[12]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 0th XCC and 12th channel +TCC_EA0_WRREQ[13]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 0th XCC and 13th channel +TCC_EA0_WRREQ[14]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 0th XCC and 14th channel +TCC_EA0_WRREQ[15]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 0th XCC and 15th channel +TCC_EA0_WRREQ[16]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 1th XCC and 0th channel +TCC_EA0_WRREQ[17]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 1th XCC and 1th channel +TCC_EA0_WRREQ[18]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 1th XCC and 2th channel +TCC_EA0_WRREQ[19]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 1th XCC and 3th channel +TCC_EA0_WRREQ[1]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 0th XCC and 1th channel +TCC_EA0_WRREQ[20]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 1th XCC and 4th channel +TCC_EA0_WRREQ[21]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 1th XCC and 5th channel +TCC_EA0_WRREQ[22]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 1th XCC and 6th channel +TCC_EA0_WRREQ[23]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 1th XCC and 7th channel +TCC_EA0_WRREQ[24]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 1th XCC and 8th channel +TCC_EA0_WRREQ[25]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 1th XCC and 9th channel +TCC_EA0_WRREQ[26]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 1th XCC and 10th channel +TCC_EA0_WRREQ[27]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 1th XCC and 11th channel +TCC_EA0_WRREQ[28]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 1th XCC and 12th channel +TCC_EA0_WRREQ[29]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 1th XCC and 13th channel +TCC_EA0_WRREQ[2]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 0th XCC and 2th channel +TCC_EA0_WRREQ[30]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 1th XCC and 14th channel +TCC_EA0_WRREQ[31]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 1th XCC and 15th channel +TCC_EA0_WRREQ[32]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 2th XCC and 0th channel +TCC_EA0_WRREQ[33]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 2th XCC and 1th channel +TCC_EA0_WRREQ[34]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 2th XCC and 2th channel +TCC_EA0_WRREQ[35]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 2th XCC and 3th channel +TCC_EA0_WRREQ[36]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 2th XCC and 4th channel +TCC_EA0_WRREQ[37]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 2th XCC and 5th channel +TCC_EA0_WRREQ[38]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 2th XCC and 6th channel +TCC_EA0_WRREQ[39]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 2th XCC and 7th channel +TCC_EA0_WRREQ[3]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 0th XCC and 3th channel +TCC_EA0_WRREQ[40]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 2th XCC and 8th channel +TCC_EA0_WRREQ[41]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 2th XCC and 9th channel +TCC_EA0_WRREQ[42]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 2th XCC and 10th channel +TCC_EA0_WRREQ[43]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 2th XCC and 11th channel +TCC_EA0_WRREQ[44]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 2th XCC and 12th channel +TCC_EA0_WRREQ[45]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 2th XCC and 13th channel +TCC_EA0_WRREQ[46]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 2th XCC and 14th channel +TCC_EA0_WRREQ[47]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 2th XCC and 15th channel +TCC_EA0_WRREQ[48]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 3th XCC and 0th channel +TCC_EA0_WRREQ[49]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 3th XCC and 1th channel +TCC_EA0_WRREQ[4]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 0th XCC and 4th channel +TCC_EA0_WRREQ[50]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 3th XCC and 2th channel +TCC_EA0_WRREQ[51]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 3th XCC and 3th channel +TCC_EA0_WRREQ[52]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 3th XCC and 4th channel +TCC_EA0_WRREQ[53]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 3th XCC and 5th channel +TCC_EA0_WRREQ[54]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 3th XCC and 6th channel +TCC_EA0_WRREQ[55]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 3th XCC and 7th channel +TCC_EA0_WRREQ[56]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 3th XCC and 8th channel +TCC_EA0_WRREQ[57]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 3th XCC and 9th channel +TCC_EA0_WRREQ[58]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 3th XCC and 10th channel +TCC_EA0_WRREQ[59]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 3th XCC and 11th channel +TCC_EA0_WRREQ[5]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 0th XCC and 5th channel +TCC_EA0_WRREQ[60]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 3th XCC and 12th channel +TCC_EA0_WRREQ[61]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 3th XCC and 13th channel +TCC_EA0_WRREQ[62]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 3th XCC and 14th channel +TCC_EA0_WRREQ[63]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 3th XCC and 15th channel +TCC_EA0_WRREQ[64]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 4th XCC and 0th channel +TCC_EA0_WRREQ[65]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 4th XCC and 1th channel +TCC_EA0_WRREQ[66]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 4th XCC and 2th channel +TCC_EA0_WRREQ[67]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 4th XCC and 3th channel +TCC_EA0_WRREQ[68]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 4th XCC and 4th channel +TCC_EA0_WRREQ[69]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 4th XCC and 5th channel +TCC_EA0_WRREQ[6]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 0th XCC and 6th channel +TCC_EA0_WRREQ[70]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 4th XCC and 6th channel +TCC_EA0_WRREQ[71]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 4th XCC and 7th channel +TCC_EA0_WRREQ[72]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 4th XCC and 8th channel +TCC_EA0_WRREQ[73]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 4th XCC and 9th channel +TCC_EA0_WRREQ[74]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 4th XCC and 10th channel +TCC_EA0_WRREQ[75]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 4th XCC and 11th channel +TCC_EA0_WRREQ[76]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 4th XCC and 12th channel +TCC_EA0_WRREQ[77]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 4th XCC and 13th channel +TCC_EA0_WRREQ[78]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 4th XCC and 14th channel +TCC_EA0_WRREQ[79]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 4th XCC and 15th channel +TCC_EA0_WRREQ[7]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 0th XCC and 7th channel +TCC_EA0_WRREQ[80]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 5th XCC and 0th channel +TCC_EA0_WRREQ[81]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 5th XCC and 1th channel +TCC_EA0_WRREQ[82]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 5th XCC and 2th channel +TCC_EA0_WRREQ[83]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 5th XCC and 3th channel +TCC_EA0_WRREQ[84]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 5th XCC and 4th channel +TCC_EA0_WRREQ[85]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 5th XCC and 5th channel +TCC_EA0_WRREQ[86]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 5th XCC and 6th channel +TCC_EA0_WRREQ[87]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 5th XCC and 7th channel +TCC_EA0_WRREQ[88]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 5th XCC and 8th channel +TCC_EA0_WRREQ[89]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 5th XCC and 9th channel +TCC_EA0_WRREQ[8]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 0th XCC and 8th channel +TCC_EA0_WRREQ[90]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 5th XCC and 10th channel +TCC_EA0_WRREQ[91]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 5th XCC and 11th channel +TCC_EA0_WRREQ[92]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 5th XCC and 12th channel +TCC_EA0_WRREQ[93]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 5th XCC and 13th channel +TCC_EA0_WRREQ[94]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 5th XCC and 14th channel +TCC_EA0_WRREQ[95]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 5th XCC and 15th channel +TCC_EA0_WRREQ[96]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 6th XCC and 0th channel +TCC_EA0_WRREQ[97]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 6th XCC and 1th channel +TCC_EA0_WRREQ[98]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 6th XCC and 2th channel +TCC_EA0_WRREQ[99]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 6th XCC and 3th channel +TCC_EA0_WRREQ[9]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 0th XCC and 9th channel +TCC_MISS[0]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 0th XCC and 0th channel +TCC_MISS[100]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 6th XCC and 4th channel +TCC_MISS[101]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 6th XCC and 5th channel +TCC_MISS[102]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 6th XCC and 6th channel +TCC_MISS[103]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 6th XCC and 7th channel +TCC_MISS[104]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 6th XCC and 8th channel +TCC_MISS[105]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 6th XCC and 9th channel +TCC_MISS[106]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 6th XCC and 10th channel +TCC_MISS[107]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 6th XCC and 11th channel +TCC_MISS[108]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 6th XCC and 12th channel +TCC_MISS[109]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 6th XCC and 13th channel +TCC_MISS[10]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 0th XCC and 10th channel +TCC_MISS[110]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 6th XCC and 14th channel +TCC_MISS[111]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 6th XCC and 15th channel +TCC_MISS[112]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 7th XCC and 0th channel +TCC_MISS[113]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 7th XCC and 1th channel +TCC_MISS[114]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 7th XCC and 2th channel +TCC_MISS[115]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 7th XCC and 3th channel +TCC_MISS[116]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 7th XCC and 4th channel +TCC_MISS[117]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 7th XCC and 5th channel +TCC_MISS[118]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 7th XCC and 6th channel +TCC_MISS[119]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 7th XCC and 7th channel +TCC_MISS[11]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 0th XCC and 11th channel +TCC_MISS[120]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 7th XCC and 8th channel +TCC_MISS[121]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 7th XCC and 9th channel +TCC_MISS[122]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 7th XCC and 10th channel +TCC_MISS[123]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 7th XCC and 11th channel +TCC_MISS[124]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 7th XCC and 12th channel +TCC_MISS[125]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 7th XCC and 13th channel +TCC_MISS[126]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 7th XCC and 14th channel +TCC_MISS[127]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 7th XCC and 15th channel +TCC_MISS[12]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 0th XCC and 12th channel +TCC_MISS[13]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 0th XCC and 13th channel +TCC_MISS[14]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 0th XCC and 14th channel +TCC_MISS[15]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 0th XCC and 15th channel +TCC_MISS[16]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 1th XCC and 0th channel +TCC_MISS[17]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 1th XCC and 1th channel +TCC_MISS[18]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 1th XCC and 2th channel +TCC_MISS[19]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 1th XCC and 3th channel +TCC_MISS[1]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 0th XCC and 1th channel +TCC_MISS[20]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 1th XCC and 4th channel +TCC_MISS[21]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 1th XCC and 5th channel +TCC_MISS[22]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 1th XCC and 6th channel +TCC_MISS[23]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 1th XCC and 7th channel +TCC_MISS[24]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 1th XCC and 8th channel +TCC_MISS[25]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 1th XCC and 9th channel +TCC_MISS[26]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 1th XCC and 10th channel +TCC_MISS[27]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 1th XCC and 11th channel +TCC_MISS[28]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 1th XCC and 12th channel +TCC_MISS[29]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 1th XCC and 13th channel +TCC_MISS[2]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 0th XCC and 2th channel +TCC_MISS[30]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 1th XCC and 14th channel +TCC_MISS[31]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 1th XCC and 15th channel +TCC_MISS[32]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 2th XCC and 0th channel +TCC_MISS[33]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 2th XCC and 1th channel +TCC_MISS[34]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 2th XCC and 2th channel +TCC_MISS[35]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 2th XCC and 3th channel +TCC_MISS[36]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 2th XCC and 4th channel +TCC_MISS[37]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 2th XCC and 5th channel +TCC_MISS[38]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 2th XCC and 6th channel +TCC_MISS[39]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 2th XCC and 7th channel +TCC_MISS[3]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 0th XCC and 3th channel +TCC_MISS[40]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 2th XCC and 8th channel +TCC_MISS[41]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 2th XCC and 9th channel +TCC_MISS[42]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 2th XCC and 10th channel +TCC_MISS[43]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 2th XCC and 11th channel +TCC_MISS[44]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 2th XCC and 12th channel +TCC_MISS[45]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 2th XCC and 13th channel +TCC_MISS[46]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 2th XCC and 14th channel +TCC_MISS[47]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 2th XCC and 15th channel +TCC_MISS[48]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 3th XCC and 0th channel +TCC_MISS[49]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 3th XCC and 1th channel +TCC_MISS[4]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 0th XCC and 4th channel +TCC_MISS[50]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 3th XCC and 2th channel +TCC_MISS[51]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 3th XCC and 3th channel +TCC_MISS[52]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 3th XCC and 4th channel +TCC_MISS[53]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 3th XCC and 5th channel +TCC_MISS[54]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 3th XCC and 6th channel +TCC_MISS[55]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 3th XCC and 7th channel +TCC_MISS[56]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 3th XCC and 8th channel +TCC_MISS[57]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 3th XCC and 9th channel +TCC_MISS[58]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 3th XCC and 10th channel +TCC_MISS[59]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 3th XCC and 11th channel +TCC_MISS[5]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 0th XCC and 5th channel +TCC_MISS[60]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 3th XCC and 12th channel +TCC_MISS[61]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 3th XCC and 13th channel +TCC_MISS[62]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 3th XCC and 14th channel +TCC_MISS[63]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 3th XCC and 15th channel +TCC_MISS[64]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 4th XCC and 0th channel +TCC_MISS[65]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 4th XCC and 1th channel +TCC_MISS[66]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 4th XCC and 2th channel +TCC_MISS[67]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 4th XCC and 3th channel +TCC_MISS[68]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 4th XCC and 4th channel +TCC_MISS[69]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 4th XCC and 5th channel +TCC_MISS[6]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 0th XCC and 6th channel +TCC_MISS[70]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 4th XCC and 6th channel +TCC_MISS[71]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 4th XCC and 7th channel +TCC_MISS[72]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 4th XCC and 8th channel +TCC_MISS[73]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 4th XCC and 9th channel +TCC_MISS[74]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 4th XCC and 10th channel +TCC_MISS[75]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 4th XCC and 11th channel +TCC_MISS[76]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 4th XCC and 12th channel +TCC_MISS[77]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 4th XCC and 13th channel +TCC_MISS[78]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 4th XCC and 14th channel +TCC_MISS[79]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 4th XCC and 15th channel +TCC_MISS[7]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 0th XCC and 7th channel +TCC_MISS[80]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 5th XCC and 0th channel +TCC_MISS[81]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 5th XCC and 1th channel +TCC_MISS[82]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 5th XCC and 2th channel +TCC_MISS[83]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 5th XCC and 3th channel +TCC_MISS[84]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 5th XCC and 4th channel +TCC_MISS[85]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 5th XCC and 5th channel +TCC_MISS[86]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 5th XCC and 6th channel +TCC_MISS[87]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 5th XCC and 7th channel +TCC_MISS[88]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 5th XCC and 8th channel +TCC_MISS[89]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 5th XCC and 9th channel +TCC_MISS[8]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 0th XCC and 8th channel +TCC_MISS[90]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 5th XCC and 10th channel +TCC_MISS[91]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 5th XCC and 11th channel +TCC_MISS[92]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 5th XCC and 12th channel +TCC_MISS[93]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 5th XCC and 13th channel +TCC_MISS[94]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 5th XCC and 14th channel +TCC_MISS[95]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 5th XCC and 15th channel +TCC_MISS[96]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 6th XCC and 0th channel +TCC_MISS[97]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 6th XCC and 1th channel +TCC_MISS[98]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 6th XCC and 2th channel +TCC_MISS[99]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 6th XCC and 3th channel +TCC_MISS[9]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 0th XCC and 9th channel +TCC_READ[0]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 0th XCC and 0th channel +TCC_READ[100]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 6th XCC and 4th channel +TCC_READ[101]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 6th XCC and 5th channel +TCC_READ[102]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 6th XCC and 6th channel +TCC_READ[103]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 6th XCC and 7th channel +TCC_READ[104]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 6th XCC and 8th channel +TCC_READ[105]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 6th XCC and 9th channel +TCC_READ[106]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 6th XCC and 10th channel +TCC_READ[107]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 6th XCC and 11th channel +TCC_READ[108]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 6th XCC and 12th channel +TCC_READ[109]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 6th XCC and 13th channel +TCC_READ[10]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 0th XCC and 10th channel +TCC_READ[110]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 6th XCC and 14th channel +TCC_READ[111]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 6th XCC and 15th channel +TCC_READ[112]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 7th XCC and 0th channel +TCC_READ[113]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 7th XCC and 1th channel +TCC_READ[114]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 7th XCC and 2th channel +TCC_READ[115]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 7th XCC and 3th channel +TCC_READ[116]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 7th XCC and 4th channel +TCC_READ[117]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 7th XCC and 5th channel +TCC_READ[118]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 7th XCC and 6th channel +TCC_READ[119]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 7th XCC and 7th channel +TCC_READ[11]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 0th XCC and 11th channel +TCC_READ[120]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 7th XCC and 8th channel +TCC_READ[121]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 7th XCC and 9th channel +TCC_READ[122]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 7th XCC and 10th channel +TCC_READ[123]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 7th XCC and 11th channel +TCC_READ[124]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 7th XCC and 12th channel +TCC_READ[125]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 7th XCC and 13th channel +TCC_READ[126]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 7th XCC and 14th channel +TCC_READ[127]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 7th XCC and 15th channel +TCC_READ[12]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 0th XCC and 12th channel +TCC_READ[13]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 0th XCC and 13th channel +TCC_READ[14]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 0th XCC and 14th channel +TCC_READ[15]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 0th XCC and 15th channel +TCC_READ[16]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 1th XCC and 0th channel +TCC_READ[17]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 1th XCC and 1th channel +TCC_READ[18]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 1th XCC and 2th channel +TCC_READ[19]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 1th XCC and 3th channel +TCC_READ[1]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 0th XCC and 1th channel +TCC_READ[20]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 1th XCC and 4th channel +TCC_READ[21]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 1th XCC and 5th channel +TCC_READ[22]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 1th XCC and 6th channel +TCC_READ[23]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 1th XCC and 7th channel +TCC_READ[24]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 1th XCC and 8th channel +TCC_READ[25]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 1th XCC and 9th channel +TCC_READ[26]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 1th XCC and 10th channel +TCC_READ[27]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 1th XCC and 11th channel +TCC_READ[28]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 1th XCC and 12th channel +TCC_READ[29]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 1th XCC and 13th channel +TCC_READ[2]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 0th XCC and 2th channel +TCC_READ[30]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 1th XCC and 14th channel +TCC_READ[31]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 1th XCC and 15th channel +TCC_READ[32]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 2th XCC and 0th channel +TCC_READ[33]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 2th XCC and 1th channel +TCC_READ[34]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 2th XCC and 2th channel +TCC_READ[35]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 2th XCC and 3th channel +TCC_READ[36]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 2th XCC and 4th channel +TCC_READ[37]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 2th XCC and 5th channel +TCC_READ[38]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 2th XCC and 6th channel +TCC_READ[39]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 2th XCC and 7th channel +TCC_READ[3]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 0th XCC and 3th channel +TCC_READ[40]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 2th XCC and 8th channel +TCC_READ[41]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 2th XCC and 9th channel +TCC_READ[42]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 2th XCC and 10th channel +TCC_READ[43]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 2th XCC and 11th channel +TCC_READ[44]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 2th XCC and 12th channel +TCC_READ[45]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 2th XCC and 13th channel +TCC_READ[46]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 2th XCC and 14th channel +TCC_READ[47]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 2th XCC and 15th channel +TCC_READ[48]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 3th XCC and 0th channel +TCC_READ[49]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 3th XCC and 1th channel +TCC_READ[4]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 0th XCC and 4th channel +TCC_READ[50]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 3th XCC and 2th channel +TCC_READ[51]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 3th XCC and 3th channel +TCC_READ[52]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 3th XCC and 4th channel +TCC_READ[53]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 3th XCC and 5th channel +TCC_READ[54]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 3th XCC and 6th channel +TCC_READ[55]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 3th XCC and 7th channel +TCC_READ[56]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 3th XCC and 8th channel +TCC_READ[57]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 3th XCC and 9th channel +TCC_READ[58]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 3th XCC and 10th channel +TCC_READ[59]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 3th XCC and 11th channel +TCC_READ[5]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 0th XCC and 5th channel +TCC_READ[60]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 3th XCC and 12th channel +TCC_READ[61]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 3th XCC and 13th channel +TCC_READ[62]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 3th XCC and 14th channel +TCC_READ[63]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 3th XCC and 15th channel +TCC_READ[64]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 4th XCC and 0th channel +TCC_READ[65]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 4th XCC and 1th channel +TCC_READ[66]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 4th XCC and 2th channel +TCC_READ[67]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 4th XCC and 3th channel +TCC_READ[68]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 4th XCC and 4th channel +TCC_READ[69]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 4th XCC and 5th channel +TCC_READ[6]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 0th XCC and 6th channel +TCC_READ[70]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 4th XCC and 6th channel +TCC_READ[71]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 4th XCC and 7th channel +TCC_READ[72]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 4th XCC and 8th channel +TCC_READ[73]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 4th XCC and 9th channel +TCC_READ[74]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 4th XCC and 10th channel +TCC_READ[75]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 4th XCC and 11th channel +TCC_READ[76]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 4th XCC and 12th channel +TCC_READ[77]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 4th XCC and 13th channel +TCC_READ[78]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 4th XCC and 14th channel +TCC_READ[79]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 4th XCC and 15th channel +TCC_READ[7]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 0th XCC and 7th channel +TCC_READ[80]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 5th XCC and 0th channel +TCC_READ[81]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 5th XCC and 1th channel +TCC_READ[82]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 5th XCC and 2th channel +TCC_READ[83]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 5th XCC and 3th channel +TCC_READ[84]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 5th XCC and 4th channel +TCC_READ[85]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 5th XCC and 5th channel +TCC_READ[86]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 5th XCC and 6th channel +TCC_READ[87]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 5th XCC and 7th channel +TCC_READ[88]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 5th XCC and 8th channel +TCC_READ[89]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 5th XCC and 9th channel +TCC_READ[8]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 0th XCC and 8th channel +TCC_READ[90]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 5th XCC and 10th channel +TCC_READ[91]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 5th XCC and 11th channel +TCC_READ[92]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 5th XCC and 12th channel +TCC_READ[93]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 5th XCC and 13th channel +TCC_READ[94]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 5th XCC and 14th channel +TCC_READ[95]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 5th XCC and 15th channel +TCC_READ[96]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 6th XCC and 0th channel +TCC_READ[97]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 6th XCC and 1th channel +TCC_READ[98]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 6th XCC and 2th channel +TCC_READ[99]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 6th XCC and 3th channel +TCC_READ[9]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 0th XCC and 9th channel +TCC_WRITE[0]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 0th XCC and 0th channel +TCC_WRITE[100]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 6th XCC and 4th channel +TCC_WRITE[101]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 6th XCC and 5th channel +TCC_WRITE[102]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 6th XCC and 6th channel +TCC_WRITE[103]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 6th XCC and 7th channel +TCC_WRITE[104]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 6th XCC and 8th channel +TCC_WRITE[105]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 6th XCC and 9th channel +TCC_WRITE[106]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 6th XCC and 10th channel +TCC_WRITE[107]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 6th XCC and 11th channel +TCC_WRITE[108]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 6th XCC and 12th channel +TCC_WRITE[109]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 6th XCC and 13th channel +TCC_WRITE[10]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 0th XCC and 10th channel +TCC_WRITE[110]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 6th XCC and 14th channel +TCC_WRITE[111]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 6th XCC and 15th channel +TCC_WRITE[112]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 7th XCC and 0th channel +TCC_WRITE[113]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 7th XCC and 1th channel +TCC_WRITE[114]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 7th XCC and 2th channel +TCC_WRITE[115]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 7th XCC and 3th channel +TCC_WRITE[116]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 7th XCC and 4th channel +TCC_WRITE[117]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 7th XCC and 5th channel +TCC_WRITE[118]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 7th XCC and 6th channel +TCC_WRITE[119]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 7th XCC and 7th channel +TCC_WRITE[11]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 0th XCC and 11th channel +TCC_WRITE[120]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 7th XCC and 8th channel +TCC_WRITE[121]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 7th XCC and 9th channel +TCC_WRITE[122]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 7th XCC and 10th channel +TCC_WRITE[123]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 7th XCC and 11th channel +TCC_WRITE[124]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 7th XCC and 12th channel +TCC_WRITE[125]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 7th XCC and 13th channel +TCC_WRITE[126]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 7th XCC and 14th channel +TCC_WRITE[127]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 7th XCC and 15th channel +TCC_WRITE[12]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 0th XCC and 12th channel +TCC_WRITE[13]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 0th XCC and 13th channel +TCC_WRITE[14]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 0th XCC and 14th channel +TCC_WRITE[15]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 0th XCC and 15th channel +TCC_WRITE[16]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 1th XCC and 0th channel +TCC_WRITE[17]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 1th XCC and 1th channel +TCC_WRITE[18]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 1th XCC and 2th channel +TCC_WRITE[19]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 1th XCC and 3th channel +TCC_WRITE[1]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 0th XCC and 1th channel +TCC_WRITE[20]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 1th XCC and 4th channel +TCC_WRITE[21]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 1th XCC and 5th channel +TCC_WRITE[22]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 1th XCC and 6th channel +TCC_WRITE[23]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 1th XCC and 7th channel +TCC_WRITE[24]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 1th XCC and 8th channel +TCC_WRITE[25]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 1th XCC and 9th channel +TCC_WRITE[26]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 1th XCC and 10th channel +TCC_WRITE[27]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 1th XCC and 11th channel +TCC_WRITE[28]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 1th XCC and 12th channel +TCC_WRITE[29]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 1th XCC and 13th channel +TCC_WRITE[2]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 0th XCC and 2th channel +TCC_WRITE[30]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 1th XCC and 14th channel +TCC_WRITE[31]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 1th XCC and 15th channel +TCC_WRITE[32]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 2th XCC and 0th channel +TCC_WRITE[33]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 2th XCC and 1th channel +TCC_WRITE[34]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 2th XCC and 2th channel +TCC_WRITE[35]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 2th XCC and 3th channel +TCC_WRITE[36]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 2th XCC and 4th channel +TCC_WRITE[37]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 2th XCC and 5th channel +TCC_WRITE[38]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 2th XCC and 6th channel +TCC_WRITE[39]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 2th XCC and 7th channel +TCC_WRITE[3]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 0th XCC and 3th channel +TCC_WRITE[40]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 2th XCC and 8th channel +TCC_WRITE[41]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 2th XCC and 9th channel +TCC_WRITE[42]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 2th XCC and 10th channel +TCC_WRITE[43]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 2th XCC and 11th channel +TCC_WRITE[44]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 2th XCC and 12th channel +TCC_WRITE[45]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 2th XCC and 13th channel +TCC_WRITE[46]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 2th XCC and 14th channel +TCC_WRITE[47]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 2th XCC and 15th channel +TCC_WRITE[48]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 3th XCC and 0th channel +TCC_WRITE[49]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 3th XCC and 1th channel +TCC_WRITE[4]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 0th XCC and 4th channel +TCC_WRITE[50]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 3th XCC and 2th channel +TCC_WRITE[51]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 3th XCC and 3th channel +TCC_WRITE[52]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 3th XCC and 4th channel +TCC_WRITE[53]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 3th XCC and 5th channel +TCC_WRITE[54]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 3th XCC and 6th channel +TCC_WRITE[55]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 3th XCC and 7th channel +TCC_WRITE[56]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 3th XCC and 8th channel +TCC_WRITE[57]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 3th XCC and 9th channel +TCC_WRITE[58]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 3th XCC and 10th channel +TCC_WRITE[59]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 3th XCC and 11th channel +TCC_WRITE[5]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 0th XCC and 5th channel +TCC_WRITE[60]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 3th XCC and 12th channel +TCC_WRITE[61]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 3th XCC and 13th channel +TCC_WRITE[62]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 3th XCC and 14th channel +TCC_WRITE[63]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 3th XCC and 15th channel +TCC_WRITE[64]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 4th XCC and 0th channel +TCC_WRITE[65]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 4th XCC and 1th channel +TCC_WRITE[66]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 4th XCC and 2th channel +TCC_WRITE[67]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 4th XCC and 3th channel +TCC_WRITE[68]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 4th XCC and 4th channel +TCC_WRITE[69]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 4th XCC and 5th channel +TCC_WRITE[6]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 0th XCC and 6th channel +TCC_WRITE[70]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 4th XCC and 6th channel +TCC_WRITE[71]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 4th XCC and 7th channel +TCC_WRITE[72]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 4th XCC and 8th channel +TCC_WRITE[73]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 4th XCC and 9th channel +TCC_WRITE[74]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 4th XCC and 10th channel +TCC_WRITE[75]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 4th XCC and 11th channel +TCC_WRITE[76]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 4th XCC and 12th channel +TCC_WRITE[77]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 4th XCC and 13th channel +TCC_WRITE[78]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 4th XCC and 14th channel +TCC_WRITE[79]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 4th XCC and 15th channel +TCC_WRITE[7]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 0th XCC and 7th channel +TCC_WRITE[80]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 5th XCC and 0th channel +TCC_WRITE[81]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 5th XCC and 1th channel +TCC_WRITE[82]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 5th XCC and 2th channel +TCC_WRITE[83]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 5th XCC and 3th channel +TCC_WRITE[84]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 5th XCC and 4th channel +TCC_WRITE[85]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 5th XCC and 5th channel +TCC_WRITE[86]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 5th XCC and 6th channel +TCC_WRITE[87]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 5th XCC and 7th channel +TCC_WRITE[88]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 5th XCC and 8th channel +TCC_WRITE[89]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 5th XCC and 9th channel +TCC_WRITE[8]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 0th XCC and 8th channel +TCC_WRITE[90]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 5th XCC and 10th channel +TCC_WRITE[91]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 5th XCC and 11th channel +TCC_WRITE[92]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 5th XCC and 12th channel +TCC_WRITE[93]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 5th XCC and 13th channel +TCC_WRITE[94]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 5th XCC and 14th channel +TCC_WRITE[95]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 5th XCC and 15th channel +TCC_WRITE[96]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 6th XCC and 0th channel +TCC_WRITE[97]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 6th XCC and 1th channel +TCC_WRITE[98]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 6th XCC and 2th channel +TCC_WRITE[99]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 6th XCC and 3th channel +TCC_WRITE[9]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 0th XCC and 9th channel diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_LEVEL_WAVES.txt b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_LEVEL_WAVES.txt new file mode 100644 index 0000000000..89a1f38eee --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_LEVEL_WAVES.txt @@ -0,0 +1,5 @@ +pmc: SQ_LEVEL_WAVES SQ_LEVEL_WAVES_ACCUM SQ_LDS_IDX_ACTIVE SQ_INSTS_VALU_FMA_F16 SQ_INSTS_VALU_ADD_F16 SQ_INSTS_LDS_LOAD_BANDWIDTH SQ_WAVE_CYCLES SQ_INSTS_LDS TA_FLAT_ATOMIC_WAVEFRONTS_sum TA_BUFFER_ATOMIC_WAVEFRONTS_sum TD_TD_BUSY_sum TCP_TCC_UC_ATOMIC_REQ_sum TCP_TOTAL_CACHE_ACCESSES_sum TCP_TCC_RW_WRITE_REQ_sum TCP_GATE_EN2_sum TCC_EA0_RDREQ_LEVEL[111] TCC_EA0_RDREQ_LEVEL[40] TCC_BUBBLE_sum TCC_TOO_MANY_EA_WRREQS_STALL[102] TCC_TOO_MANY_EA_WRREQS_STALL[50] TCC_EA0_RDREQ_LEVEL[83] TCC_EA0_ATOMIC_LEVEL[51] TCC_TOO_MANY_EA_WRREQS_STALL[114] TCC_EA0_RDREQ_LEVEL[18] TCC_TOO_MANY_EA_WRREQS_STALL[51] TCC_EA0_ATOMIC_LEVEL[112] TCC_TOO_MANY_EA_WRREQS_STALL[124] TCC_EA0_ATOMIC_LEVEL[82] TCC_EA0_ATOMIC_LEVEL[105] TCC_EA0_RDREQ_LEVEL[108] TCC_TOO_MANY_EA_WRREQS_STALL[115] TCC_EA0_ATOMIC_LEVEL[50] TCC_EA0_ATOMIC_LEVEL[49] TCC_EA0_RDREQ_LEVEL[90] TCC_EA0_RDREQ_LEVEL[14] TCC_EA0_RDREQ_LEVEL[101] TCC_EA0_RDREQ_LEVEL[66] TCC_EA0_ATOMIC_LEVEL[107] TCC_TOO_MANY_EA_WRREQS_STALL[55] TCC_TOO_MANY_EA_WRREQS_STALL[60] TCC_EA0_ATOMIC_LEVEL[54] TCC_TOO_MANY_EA_WRREQS_STALL[44] TCC_EA0_RDREQ_LEVEL[110] TCC_TOO_MANY_EA_WRREQS_STALL[104] TCC_EA0_ATOMIC_LEVEL[8] TCC_EA0_ATOMIC_LEVEL[27] TCC_EA0_RDREQ_LEVEL[50] TCC_EA0_RDREQ_LEVEL[49] TCC_TOO_MANY_EA_WRREQS_STALL[127] TCC_TOO_MANY_EA_WRREQS_STALL[27] TCC_TOO_MANY_EA_WRREQS_STALL[82] TCC_EA0_ATOMIC_LEVEL[77] TCC_TOO_MANY_EA_WRREQS_STALL[32] TCC_TOO_MANY_EA_WRREQS_STALL[108] TCC_EA0_RDREQ_LEVEL[69] TCC_TOO_MANY_EA_WRREQS_STALL[45] TCC_TOO_MANY_EA_WRREQS_STALL[63] TCC_EA0_ATOMIC_LEVEL[72] TCC_EA0_RDREQ_LEVEL[105] TCC_EA0_RDREQ_LEVEL[10] TCC_EA0_RDREQ_LEVEL[45] TCC_EA0_ATOMIC_LEVEL[7] TCC_EA0_ATOMIC_LEVEL[89] TCC_EA0_RDREQ_LEVEL[79] TCC_EA0_RDREQ_LEVEL[13] TCC_EA0_ATOMIC_LEVEL[14] TCC_EA0_ATOMIC_LEVEL[69] TCC_EA0_RDREQ_LEVEL[11] TCC_TOO_MANY_EA_WRREQS_STALL[31] TCC_TOO_MANY_EA_WRREQS_STALL[59] TCC_EA0_ATOMIC_LEVEL[92] TCC_TOO_MANY_EA_WRREQS_STALL[86] TCC_EA0_RDREQ_LEVEL[82] TCC_EA0_ATOMIC_LEVEL[66] TCC_EA0_ATOMIC_LEVEL[56] TCC_EA0_ATOMIC_LEVEL[101] TCC_EA0_RDREQ_LEVEL[61] TCC_EA0_ATOMIC_LEVEL[97] TCC_EA0_RDREQ_LEVEL[22] TCC_EA0_RDREQ_LEVEL[44] TCC_EA0_RDREQ_LEVEL[35] TCC_EA0_RDREQ_LEVEL[51] TCC_EA0_ATOMIC_LEVEL[96] TCC_TOO_MANY_EA_WRREQS_STALL[110] TCC_EA0_RDREQ_LEVEL[37] TCC_EA0_ATOMIC_LEVEL[74] TCC_EA0_ATOMIC_LEVEL[23] TCC_EA0_ATOMIC_LEVEL[71] TCC_EA0_ATOMIC_LEVEL[126] TCC_EA0_RDREQ_LEVEL[17] TCC_TOO_MANY_EA_WRREQS_STALL[28] TCC_TOO_MANY_EA_WRREQS_STALL[117] TCC_EA0_ATOMIC_LEVEL[86] TCC_EA0_ATOMIC_LEVEL[61] TCC_EA0_ATOMIC_LEVEL[102] TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_TOO_MANY_EA_WRREQS_STALL[24] TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_EA0_ATOMIC_LEVEL[16] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_EA0_ATOMIC_LEVEL[44] TCC_TOO_MANY_EA_WRREQS_STALL[52] TCC_EA0_RDREQ_LEVEL[70] TCC_EA0_ATOMIC_LEVEL[78] TCC_EA0_RDREQ_LEVEL[74] TCC_EA0_RDREQ_LEVEL[85] TCC_EA0_RDREQ_LEVEL[20] TCC_TOO_MANY_EA_WRREQS_STALL[53] TCC_EA0_RDREQ_LEVEL[123] TCC_EA0_ATOMIC_LEVEL[95] TCC_EA0_RDREQ_LEVEL[19] TCC_EA0_RDREQ_LEVEL[25] TCC_EA0_RDREQ_LEVEL[76] TCC_EA0_ATOMIC_LEVEL[65] TCC_EA0_ATOMIC_LEVEL[114] TCC_TOO_MANY_EA_WRREQS_STALL[122] TCC_EA0_RDREQ_LEVEL[125] TCC_TOO_MANY_EA_WRREQS_STALL[41] TCC_TOO_MANY_EA_WRREQS_STALL[49] TCC_EA0_ATOMIC_LEVEL[20] TCC_EA0_RDREQ_LEVEL[104] TCC_TOO_MANY_EA_WRREQS_STALL[70] TCC_EA0_ATOMIC_LEVEL[42] TCC_TOO_MANY_EA_WRREQS_STALL[74] TCC_EA0_RDREQ_LEVEL[95] TCC_EA0_RDREQ_LEVEL[56] TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_EA0_RDREQ_LEVEL[102] TCC_TOO_MANY_EA_WRREQS_STALL[68] TCC_TOO_MANY_EA_WRREQS_STALL[23] TCC_TOO_MANY_EA_WRREQS_STALL[111] TCC_EA0_RDREQ_LEVEL[3] TCC_EA0_RDREQ_LEVEL[32] TCC_EA0_ATOMIC_LEVEL[39] TCC_EA0_RDREQ_LEVEL[8] TCC_EA0_RDREQ_LEVEL[120] TCC_TOO_MANY_EA_WRREQS_STALL[116] TCC_TOO_MANY_EA_WRREQS_STALL[97] TCC_TOO_MANY_EA_WRREQS_STALL[106] TCC_EA0_ATOMIC_LEVEL[38] TCC_TOO_MANY_EA_WRREQS_STALL[98] TCC_EA0_RDREQ_LEVEL[34] TCC_EA0_ATOMIC_LEVEL[18] TCC_EA0_RDREQ_LEVEL[54] TCC_EA0_RDREQ_LEVEL[2] TCC_EA0_ATOMIC_LEVEL[43] TCC_EA0_ATOMIC_LEVEL[104] TCC_EA0_RDREQ_LEVEL[72] TCC_EA0_RDREQ_LEVEL[78] TCC_EA0_RDREQ_LEVEL[41] TCC_EA0_RDREQ_LEVEL[30] TCC_EA0_ATOMIC_LEVEL[40] TCC_TOO_MANY_EA_WRREQS_STALL[83] TCC_EA0_ATOMIC_LEVEL[111] TCC_EA0_RDREQ_LEVEL[53] TCC_TOO_MANY_EA_WRREQS_STALL[42] TCC_EA0_RDREQ_LEVEL[73] TCC_EA0_RDREQ_LEVEL[103] TCC_EA0_ATOMIC_LEVEL[59] TCC_EA0_RDREQ_LEVEL[100] TCC_EA0_RDREQ_LEVEL[67] TCC_EA0_ATOMIC_LEVEL[57] TCC_EA0_ATOMIC_LEVEL[22] TCC_TOO_MANY_EA_WRREQS_STALL[15] TCC_EA0_ATOMIC_LEVEL[9] TCC_EA0_ATOMIC_LEVEL[100] TCC_EA0_ATOMIC_LEVEL[70] TCC_EA0_ATOMIC_LEVEL[24] TCC_TOO_MANY_EA_WRREQS_STALL[123] TCC_EA0_ATOMIC_LEVEL[98] TCC_EA0_RDREQ_LEVEL[112] TCC_EA0_RDREQ_LEVEL[81] TCC_EA0_ATOMIC_LEVEL[36] TCC_EA0_RDREQ_LEVEL[89] TCC_EA0_RDREQ_LEVEL[126] TCC_EA0_RDREQ_LEVEL[62] TCC_EA0_ATOMIC_LEVEL[30] TCC_EA0_ATOMIC_LEVEL[41] TCC_TOO_MANY_EA_WRREQS_STALL[40] TCC_EA0_ATOMIC_LEVEL[53] TCC_EA0_ATOMIC_LEVEL[85] TCC_EA0_RDREQ_LEVEL[21] TCC_EA0_RDREQ_LEVEL[29] TCC_EA0_RDREQ_LEVEL[58] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_EA0_RDREQ_LEVEL[96] TCC_TOO_MANY_EA_WRREQS_STALL[92] TCC_TOO_MANY_EA_WRREQS_STALL[112] TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_EA0_RDREQ_LEVEL[42] TCC_EA0_RDREQ_LEVEL[12] TCC_EA0_RDREQ_LEVEL[46] TCC_EA0_RDREQ_LEVEL[88] TCC_EA0_ATOMIC_LEVEL[35] TCC_TOO_MANY_EA_WRREQS_STALL[120] TCC_EA0_ATOMIC_LEVEL[25] TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_TOO_MANY_EA_WRREQS_STALL[34] TCC_TOO_MANY_EA_WRREQS_STALL[37] TCC_EA0_RDREQ_LEVEL[75] TCC_EA0_ATOMIC_LEVEL[32] TCC_EA0_ATOMIC_LEVEL[108] TCC_EA0_ATOMIC_LEVEL[10] TCC_EA0_RDREQ_LEVEL[55] TCC_TOO_MANY_EA_WRREQS_STALL[65] TCC_EA0_RDREQ_LEVEL[99] TCC_TOO_MANY_EA_WRREQS_STALL[103] TCC_TOO_MANY_EA_WRREQS_STALL[80] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_TOO_MANY_EA_WRREQS_STALL[29] TCC_TOO_MANY_EA_WRREQS_STALL[87] TCC_TOO_MANY_EA_WRREQS_STALL[20] TCC_EA0_ATOMIC_LEVEL[79] TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_TOO_MANY_EA_WRREQS_STALL[76] TCC_TOO_MANY_EA_WRREQS_STALL[19] TCC_EA0_ATOMIC_LEVEL[17] TCC_EA0_RDREQ_LEVEL[113] TCC_EA0_ATOMIC_LEVEL[21] TCC_EA0_RDREQ_LEVEL[71] TCC_EA0_RDREQ_LEVEL[94] TCC_EA0_ATOMIC_LEVEL[125] TCC_EA0_RDREQ_LEVEL[36] TCC_EA0_ATOMIC_LEVEL[55] TCC_TOO_MANY_EA_WRREQS_STALL[119] TCC_EA0_ATOMIC_LEVEL[48] TCC_EA0_RDREQ_LEVEL[33] TCC_EA0_RDREQ_LEVEL[86] TCC_EA0_RDREQ_LEVEL[9] TCC_TOO_MANY_EA_WRREQS_STALL[16] TCC_TOO_MANY_EA_WRREQS_STALL[64] TCC_EA0_RDREQ_LEVEL[122] TCC_EA0_RDREQ_LEVEL[121] TCC_TOO_MANY_EA_WRREQS_STALL[101] TCC_EA0_ATOMIC_LEVEL[15] TCC_EA0_RDREQ_LEVEL[31] TCC_EA0_RDREQ_LEVEL[7] TCC_TOO_MANY_EA_WRREQS_STALL[57] TCC_EA0_ATOMIC_LEVEL[3] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_EA0_RDREQ_LEVEL[119] TCC_EA0_RDREQ_LEVEL[92] TCC_EA0_ATOMIC_LEVEL[103] TCC_TOO_MANY_EA_WRREQS_STALL[96] TCC_EA0_ATOMIC_LEVEL[88] TCC_TOO_MANY_EA_WRREQS_STALL[43] TCC_TOO_MANY_EA_WRREQS_STALL[91] TCC_TOO_MANY_EA_WRREQS_STALL[54] TCC_TOO_MANY_EA_WRREQS_STALL[94] TCC_EA0_RDREQ_LEVEL[64] TCC_TOO_MANY_EA_WRREQS_STALL[125] TCC_EA0_RDREQ_LEVEL[63] TCC_TOO_MANY_EA_WRREQS_STALL[72] TCC_TOO_MANY_EA_WRREQS_STALL[95] TCC_EA0_ATOMIC_LEVEL[113] TCC_EA0_ATOMIC_LEVEL[90] TCC_EA0_RDREQ_LEVEL[106] TCC_EA0_ATOMIC_LEVEL[87] TCC_EA0_RDREQ_LEVEL[0] TCC_EA0_ATOMIC_LEVEL[47] TCC_TOO_MANY_EA_WRREQS_STALL[99] TCC_TOO_MANY_EA_WRREQS_STALL[58] TCC_EA0_ATOMIC_LEVEL[122] TCC_EA0_ATOMIC_LEVEL[81] TCC_EA0_ATOMIC_LEVEL[6] TCC_EA0_RDREQ_LEVEL[4] TCC_TOO_MANY_EA_WRREQS_STALL[100] TCC_EA0_RDREQ_LEVEL[118] TCC_EA0_ATOMIC_LEVEL[110] TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_EA0_ATOMIC_LEVEL[109] TCC_EA0_RDREQ_LEVEL[23] TCC_EA0_RDREQ_LEVEL[68] TCC_EA0_ATOMIC_LEVEL[116] TCC_EA0_RDREQ_LEVEL[1] TCC_EA0_ATOMIC_LEVEL[12] TCC_EA0_ATOMIC_LEVEL[64] TCC_EA0_RDREQ_LEVEL[114] TCC_EA0_ATOMIC_LEVEL[91] TCC_EA0_RDREQ_LEVEL[65] TCC_EA0_RDREQ_LEVEL[77] TCC_EA0_ATOMIC_LEVEL[52] TCC_EA0_ATOMIC_LEVEL[80] TCC_EA0_ATOMIC_LEVEL[94] TCC_TOO_MANY_EA_WRREQS_STALL[35] TCC_TOO_MANY_EA_WRREQS_STALL[77] TCC_EA0_ATOMIC_LEVEL[67] TCC_EA0_ATOMIC_LEVEL[106] TCC_EA0_RDREQ_LEVEL[115] TCC_EA0_ATOMIC_LEVEL[28] TCC_EA0_ATOMIC_LEVEL[75] TCC_TOO_MANY_EA_WRREQS_STALL[25] TCC_TOO_MANY_EA_WRREQS_STALL[88] TCC_TOO_MANY_EA_WRREQS_STALL[61] TCC_TOO_MANY_EA_WRREQS_STALL[69] TCC_EA0_RDREQ_LEVEL[26] TCC_TOO_MANY_EA_WRREQS_STALL[67] TCC_EA0_ATOMIC_LEVEL[26] TCC_TOO_MANY_EA_WRREQS_STALL[62] TCC_TOO_MANY_EA_WRREQS_STALL[90] TCC_TOO_MANY_EA_WRREQS_STALL[47] TCC_EA0_RDREQ_LEVEL[60] TCC_EA0_ATOMIC_LEVEL[5] TCC_TOO_MANY_EA_WRREQS_STALL[26] TCC_EA0_RDREQ_LEVEL[84] TCC_TOO_MANY_EA_WRREQS_STALL[126] TCC_TOO_MANY_EA_WRREQS_STALL[93] TCC_EA0_ATOMIC_LEVEL[34] TCC_EA0_ATOMIC_LEVEL[2] TCC_EA0_ATOMIC_LEVEL[117] TCC_EA0_RDREQ_LEVEL[97] TCC_EA0_RDREQ_LEVEL[93] TCC_EA0_RDREQ_LEVEL[87] TCC_EA0_ATOMIC_LEVEL[31] TCC_TOO_MANY_EA_WRREQS_STALL[113] TCC_EA0_ATOMIC_LEVEL[121] TCC_EA0_ATOMIC_LEVEL[124] TCC_EA0_RDREQ_LEVEL[28] TCC_TOO_MANY_EA_WRREQS_STALL[73] TCC_EA0_RDREQ_LEVEL[127] TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_EA0_RDREQ_LEVEL[47] TCC_EA0_ATOMIC_LEVEL[62] TCC_EA0_RDREQ_LEVEL[116] TCC_TOO_MANY_EA_WRREQS_STALL[81] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_EA0_ATOMIC_LEVEL[127] TCC_EA0_RDREQ_LEVEL[124] TCC_EA0_RDREQ_LEVEL[107] TCC_TOO_MANY_EA_WRREQS_STALL[66] TCC_EA0_RDREQ_LEVEL[5] TCC_EA0_ATOMIC_LEVEL[0] TCC_EA0_ATOMIC_LEVEL[19] TCC_EA0_ATOMIC_LEVEL[37] TCC_TOO_MANY_EA_WRREQS_STALL[33] TCC_EA0_RDREQ_LEVEL[27] TCC_TOO_MANY_EA_WRREQS_STALL[21] TCC_EA0_ATOMIC_LEVEL[123] TCC_TOO_MANY_EA_WRREQS_STALL[75] TCC_EA0_RDREQ_LEVEL[98] TCC_TOO_MANY_EA_WRREQS_STALL[89] TCC_TOO_MANY_EA_WRREQS_STALL[71] TCC_TOO_MANY_EA_WRREQS_STALL[48] TCC_EA0_ATOMIC_LEVEL[83] TCC_EA0_ATOMIC_LEVEL[68] TCC_TOO_MANY_EA_WRREQS_STALL[107] TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_EA0_ATOMIC_LEVEL[29] TCC_TOO_MANY_EA_WRREQS_STALL[118] TCC_TOO_MANY_EA_WRREQS_STALL[56] TCC_EA0_RDREQ_LEVEL[48] TCC_EA0_RDREQ_LEVEL[15] TCC_EA0_ATOMIC_LEVEL[46] TCC_EA0_ATOMIC_LEVEL[11] TCC_EA0_ATOMIC_LEVEL[60] TCC_EA0_ATOMIC_LEVEL[63] TCC_EA0_RDREQ_LEVEL[80] TCC_EA0_ATOMIC_LEVEL[4] TCC_EA0_ATOMIC_LEVEL[1] TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_EA0_ATOMIC_LEVEL[115] TCC_EA0_ATOMIC_LEVEL[84] TCC_TOO_MANY_EA_WRREQS_STALL[121] TCC_EA0_RDREQ_LEVEL[43] TCC_TOO_MANY_EA_WRREQS_STALL[105] TCC_EA0_ATOMIC_LEVEL[33] TCC_TOO_MANY_EA_WRREQS_STALL[39] TCC_EA0_RDREQ_LEVEL[24] TCC_EA0_ATOMIC_LEVEL[45] TCC_EA0_RDREQ_LEVEL[38] TCC_TOO_MANY_EA_WRREQS_STALL[109] TCC_TOO_MANY_EA_WRREQS_STALL[18] TCC_EA0_ATOMIC_LEVEL[73] TCC_EA0_ATOMIC_LEVEL[120] TCC_TOO_MANY_EA_WRREQS_STALL[84] TCC_EA0_RDREQ_LEVEL[91] TCC_TOO_MANY_EA_WRREQS_STALL[38] TCC_EA0_RDREQ_LEVEL[6] TCC_TOO_MANY_EA_WRREQS_STALL[85] TCC_EA0_RDREQ_LEVEL[52] TCC_EA0_RDREQ_LEVEL[59] TCC_TOO_MANY_EA_WRREQS_STALL[17] TCC_EA0_ATOMIC_LEVEL[99] TCC_EA0_ATOMIC_LEVEL[118] TCC_TOO_MANY_EA_WRREQS_STALL[46] TCC_TOO_MANY_EA_WRREQS_STALL[30] TCC_TOO_MANY_EA_WRREQS_STALL[79] TCC_EA0_ATOMIC_LEVEL[76] TCC_EA0_ATOMIC_LEVEL[93] TCC_EA0_RDREQ_LEVEL[109] TCC_EA0_ATOMIC_LEVEL[58] TCC_EA0_RDREQ_LEVEL[117] TCC_TOO_MANY_EA_WRREQS_STALL[22] TCC_TOO_MANY_EA_WRREQS_STALL[78] TCC_EA0_RDREQ_LEVEL[57] TCC_EA0_RDREQ_LEVEL[16] TCC_EA0_RDREQ_LEVEL[39] TCC_EA0_ATOMIC_LEVEL[119] TCC_EA0_ATOMIC_LEVEL[13] TCC_TOO_MANY_EA_WRREQS_STALL[36] CPC_TG_SEND CPC_CPC_TCIU_IDLE CPF_CPF_TCIU_IDLE SPI_CS2_BUSY SPI_CS1_BUSY SPI_CS0_BUSY SPI_CS3_BUSY + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_LEVEL_WAVES.yaml b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_LEVEL_WAVES.yaml new file mode 100644 index 0000000000..0094f14e0e --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/SQ_LEVEL_WAVES.yaml @@ -0,0 +1,1925 @@ +SQ_LEVEL_WAVES_ACCUM: + architectures: + gfx942/gfx941/gfx940/gfx90a: + expression: accumulate(SQ_LEVEL_WAVES, HIGH_RES) + description: SQ_LEVEL_WAVES accumulation +TCC_EA0_ATOMIC_LEVEL[0]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[100]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[101]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[102]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[103]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[104]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[105]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 9th channel +TCC_EA0_ATOMIC_LEVEL[106]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[107]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[108]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[109]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[10]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[110]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[111]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[112]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[113]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[114]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[115]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[116]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[117]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[118]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[119]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[11]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[120]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[121]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 9th channel +TCC_EA0_ATOMIC_LEVEL[122]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[123]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[124]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[125]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[126]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[127]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[12]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[13]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[14]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[15]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[16]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[17]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[18]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[19]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[1]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[20]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[21]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[22]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[23]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[24]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[25]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 9th channel +TCC_EA0_ATOMIC_LEVEL[26]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[27]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[28]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[29]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[2]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[30]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[31]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[32]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[33]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[34]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[35]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[36]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[37]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[38]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[39]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[3]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[40]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[41]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 9th channel +TCC_EA0_ATOMIC_LEVEL[42]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[43]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[44]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[45]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[46]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[47]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[48]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[49]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[4]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[50]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[51]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[52]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[53]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[54]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[55]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[56]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[57]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 9th channel +TCC_EA0_ATOMIC_LEVEL[58]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[59]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[5]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[60]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[61]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[62]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[63]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[64]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[65]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[66]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[67]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[68]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[69]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[6]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[70]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[71]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[72]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[73]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 9th channel +TCC_EA0_ATOMIC_LEVEL[74]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[75]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[76]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[77]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[78]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[79]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[7]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[80]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[81]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[82]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[83]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[84]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[85]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[86]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[87]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[88]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[89]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 9th channel +TCC_EA0_ATOMIC_LEVEL[8]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[90]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[91]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[92]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[93]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[94]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[95]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[96]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[97]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[98]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[99]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[9]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[0]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[100]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[101]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[102]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[103]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[104]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[105]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[106]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[107]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[108]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[109]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[10]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[110]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[111]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[112]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[113]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[114]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[115]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[116]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[117]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[118]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[119]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[11]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[120]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[121]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[122]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[123]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[124]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[125]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[126]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[127]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[12]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[13]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[14]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[15]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[16]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[17]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[18]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[19]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[1]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[20]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[21]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[22]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[23]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[24]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[25]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[26]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[27]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[28]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[29]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[2]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[30]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[31]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[32]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[33]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[34]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[35]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[36]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[37]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[38]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[39]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[3]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[40]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[41]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[42]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[43]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[44]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[45]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[46]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[47]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[48]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[49]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[4]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[50]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[51]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[52]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[53]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[54]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[55]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[56]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[57]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[58]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[59]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[5]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[60]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[61]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[62]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[63]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[64]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[65]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[66]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[67]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[68]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[69]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[6]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[70]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[71]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[72]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[73]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[74]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[75]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[76]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[77]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[78]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[79]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[7]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[80]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[81]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[82]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[83]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[84]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[85]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[86]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[87]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[88]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[89]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[8]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[90]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[91]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[92]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[93]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[94]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[95]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[96]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[97]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[98]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[99]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[9]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[0]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[100]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[101]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[102]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[103]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[104]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[105]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[106]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[107]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[108]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[109]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[10]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[110]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[111]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[112]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[113]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[114]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[115]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[116]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[117]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[118]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[119]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[11]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[120]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[121]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[122]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[123]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[124]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[125]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[126]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[127]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[12]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[13]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[14]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[15]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[16]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[17]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[18]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[19]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[1]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[20]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[21]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[22]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[23]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[24]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[25]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[26]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[27]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[28]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[29]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[2]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[30]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[31]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[32]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[33]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[34]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[35]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[36]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[37]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[38]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[39]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[3]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[40]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[41]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[42]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[43]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[44]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[45]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[46]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[47]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[48]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[49]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[4]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[50]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[51]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[52]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[53]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[54]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[55]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[56]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[57]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[58]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[59]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[5]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[60]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[61]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[62]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[63]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[64]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[65]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[66]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[67]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[68]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[69]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[6]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[70]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[71]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[72]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[73]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[74]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[75]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[76]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[77]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[78]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[79]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[7]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[80]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[81]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[82]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[83]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[84]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[85]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[86]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[87]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[88]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[89]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[8]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[90]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[91]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[92]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[93]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[94]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[95]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[96]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[97]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[98]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[99]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[9]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 9th channel diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_0.txt b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_0.txt new file mode 100644 index 0000000000..6929e642c2 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_0.txt @@ -0,0 +1,5 @@ +pmc: SQ_INSTS_VALU_ADD_F64 SQ_ACTIVE_INST_VALU SQ_INSTS_SENDMSG SQ_VMEM_TA_CMD_FIFO_FULL SQC_DCACHE_REQ_READ_8 SQC_TC_DATA_ATOMIC_REQ SQ_LDS_BANK_CONFLICT SQ_BUSY_CYCLES TA_DATA_STALLED_BY_TC_CYCLES_sum TA_BUFFER_WAVEFRONTS_sum TCP_TCR_TCP_STALL_CYCLES_sum TCP_UTCL1_TRANSLATION_MISS_sum TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum TCP_TCC_READ_REQ_sum TCC_UC_REQ_sum TCC_ALL_TC_OP_INV_EVICT_sum TCC_ALL_TC_OP_WB_WRITEBACK_sum TCC_EA0_WRREQ_LEVEL_sum CPC_SYNC_FIFO_FULL CPC_CPC_UTCL2IU_BUSY SPI_CS2_NUM_THREADGROUPS SPI_CS3_NUM_THREADGROUPS SPI_CS1_NUM_THREADGROUPS SPI_CS0_NUM_THREADGROUPS + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_0.yaml b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_0.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_1.txt b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_1.txt new file mode 100644 index 0000000000..d484937f6f --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_1.txt @@ -0,0 +1,5 @@ +pmc: SQ_INSTS_VALU_MFMA_MOPS_F16 SQC_TC_DATA_READ_REQ SQ_INSTS_VMEM SQ_VALU_MFMA_BUSY_CYCLES SQ_INSTS_VALU_MFMA_MOPS_F6F4 SQ_INSTS_VALU_INT64 SQC_DCACHE_REQ_READ_4 SQ_INSTS_VALU_TRANS_F64 TA_FLAT_WRITE_WAVEFRONTS_sum TA_BUFFER_READ_WAVEFRONTS_sum TCP_PENDING_STALL_CYCLES_sum TCP_TCC_NC_READ_REQ_sum TCP_TCC_UC_WRITE_REQ_sum TCP_UTCL1_PERMISSION_MISS_sum TCC_EA0_RD_UNCACHED_32B_sum TCC_CC_REQ_sum TCC_EA0_RDREQ_LEVEL_sum TCC_RW_REQ_sum CPC_GD_BUSY CPC_CANE_BUSY SPI_RA_REQ_NO_ALLOC SPI_SWC_CSC_WR + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_1.yaml b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_1.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_2.txt b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_2.txt new file mode 100644 index 0000000000..713658c6cd --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_2.txt @@ -0,0 +1,5 @@ +pmc: SQ_THREAD_CYCLES_VALU SQC_DCACHE_MISSES_DUPLICATE SQ_INSTS_VALU_FMA_F32 SQ_INSTS_VALU_MFMA_MOPS_F8 SQ_INSTS_VALU_MFMA_F8 SQ_INSTS_SMEM SQ_INSTS_VALU_INT32 SQ_INSTS_VALU_TRANS_F32 TA_BUFFER_COALESCED_WRITE_CYCLES_sum TA_TOTAL_WAVEFRONTS_sum TCP_TCC_CC_READ_REQ_sum TCP_TCC_CC_ATOMIC_REQ_sum TCP_TCC_WRITE_REQ_sum TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum TCC_BUSY_sum TCC_HIT_sum TCC_NORMAL_WRITEBACK_sum TCC_READ_sum CPC_CPC_UTCL2IU_IDLE CPC_UTCL1_STALL_ON_TRANSLATION SPI_RA_RES_STALL_CSN SPI_RA_BAR_CU_FULL_CSN + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_2.yaml b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_2.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_3.txt b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_3.txt new file mode 100644 index 0000000000..14d59e51d2 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_3.txt @@ -0,0 +1,5 @@ +pmc: SQC_DCACHE_REQ_READ_2 SQ_INSTS_LDS_STORE_BANDWIDTH SQ_LDS_MEM_VIOLATIONS SQ_ACTIVE_INST_ANY SQ_LDS_ATOMIC_RETURN SQ_INSTS_BRANCH SQ_INSTS_VALU_CVT SQ_ACTIVE_INST_MISC TCP_TOTAL_ACCESSES_sum TCP_TOTAL_READ_sum TCP_TOTAL_ATOMIC_WITHOUT_RET_sum TCP_TCC_CC_WRITE_REQ_sum TCC_WRITEBACK_sum TCC_PROBE_sum TCC_MISS_sum TCC_REQ_sum SPI_VWC1_VDATA_VALID_WR SPI_RA_VGPR_SIMD_FULL_CSN + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_3.yaml b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_3.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_4.txt b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_4.txt new file mode 100644 index 0000000000..47fdf4f427 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_4.txt @@ -0,0 +1,5 @@ +pmc: SQ_WAVES_RESTORED SQ_WAVES SQ_LDS_DATA_FIFO_FULL SQC_TC_DATA_WRITE_REQ SQ_INSTS_VALU_MFMA_F64 SQ_INSTS_VALU_MFMA_BF16 SQ_ACTIVE_INST_LDS SQ_VMEM_TA_ADDR_FIFO_FULL TCC_EA0_WRREQ_64B_sum TCC_EA0_ATOMIC_sum TCC_EA0_RDREQ_DRAM_sum TCC_EA0_WRREQ_DRAM_sum SPI_CSC_WAVE_CNT_BUSY SPI_RA_WAVE_SIMD_FULL_CSN + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_4.yaml b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_4.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_5.txt b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_5.txt new file mode 100644 index 0000000000..6c6703231c --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_5.txt @@ -0,0 +1,5 @@ +pmc: SQ_LDS_ADDR_CONFLICT SQC_ICACHE_HITS SQ_INSTS_LDS_ATOMIC_BANDWIDTH SQ_INSTS_MFMA SQ_WAIT_INST_ANY SQ_INSTS_VALU_MFMA_F6F4 SQ_INSTS_VALU_MUL_F32 SQC_DCACHE_REQ_READ_1 TCC_STREAMING_REQ_sum TCC_EA0_RDREQ_32B_sum TCC_EA0_RDREQ_sum TCC_WRITE_sum SPI_RA_LDS_CU_FULL_CSN SPI_RA_TMP_STALL_CSN + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_5.yaml b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_5.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_6.txt b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_6.txt new file mode 100644 index 0000000000..57f5e105e2 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_6.txt @@ -0,0 +1,5 @@ +pmc: SQ_INSTS_VALU_MFMA_MOPS_F64 SQ_LDS_UNALIGNED_STALL SQ_INSTS_VALU_MFMA_I8 SQ_INSTS_VALU SQ_WAIT_ANY SQ_INSTS_VALU_TRANS_F16 SQ_INSTS_VALU_MFMA_MOPS_BF16 SQC_TC_INST_REQ TCC_EA0_WR_UNCACHED_32B_sum TCC_NORMAL_EVICT_sum SPI_RA_WVLIM_STALL_CSN SPI_RA_TGLIM_CU_FULL_CSN + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_6.yaml b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_6.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_7.txt b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_7.txt new file mode 100644 index 0000000000..875789310c --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_7.txt @@ -0,0 +1,5 @@ +pmc: SQC_DCACHE_REQ SQ_INSTS_SALU SQ_ACTIVE_INST_FLAT SQ_IFETCH SQ_ACTIVE_INST_SCA SQ_INSTS SQ_INSTS_VALU_MFMA_F32 SQ_INSTS_VALU_ADD_F32 + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_7.yaml b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/perfmon/pmc_perf_7.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_dispatch_info.csv new file mode 100644 index 0000000000..c65b416c9a --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int)",0 +1,"vecCopy(double*, double*, double*, int, int)",0 +2,"vecCopy(double*, double*, double*, int, int)",0 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf.csv new file mode 100644 index 0000000000..83f23a7a40 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Correlation_ID,Kernel_ID,CPC_CANE_BUSY,CPC_GD_BUSY,SPI_RA_REQ_NO_ALLOC,SPI_SWC_CSC_WR,SQC_DCACHE_REQ_READ_4,SQC_TC_DATA_READ_REQ,SQ_INSTS_VALU_INT64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_F6F4,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VMEM,SQ_VALU_MFMA_BUSY_CYCLES,TA_BUFFER_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TCC_CC_REQ_sum,TCC_EA0_RDREQ_LEVEL_sum,TCC_EA0_RD_UNCACHED_32B_sum,TCC_RW_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_UTCL1_PERMISSION_MISS_sum,Kernel_ID_1,CPC_CPC_UTCL2IU_BUSY,CPC_SYNC_FIFO_FULL,SPI_CS0_NUM_THREADGROUPS,SPI_CS1_NUM_THREADGROUPS,SPI_CS2_NUM_THREADGROUPS,SPI_CS3_NUM_THREADGROUPS,SQC_DCACHE_REQ_READ_8,SQC_TC_DATA_ATOMIC_REQ,SQ_ACTIVE_INST_VALU,SQ_BUSY_CYCLES,SQ_INSTS_SENDMSG,SQ_INSTS_VALU_ADD_F64,SQ_LDS_BANK_CONFLICT,SQ_VMEM_TA_CMD_FIFO_FULL,TA_BUFFER_WAVEFRONTS_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_EA0_WRREQ_LEVEL_sum,TCC_UC_REQ_sum,TCP_TCC_READ_REQ_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,Kernel_ID_2,SPI_RA_LDS_CU_FULL_CSN,SPI_RA_TMP_STALL_CSN,SQC_DCACHE_REQ_READ_1,SQC_ICACHE_HITS,SQ_INSTS_LDS_ATOMIC_BANDWIDTH,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_F6F4,SQ_INSTS_VALU_MUL_F32,SQ_LDS_ADDR_CONFLICT,SQ_WAIT_INST_ANY,TCC_EA0_RDREQ_32B_sum,TCC_EA0_RDREQ_sum,TCC_STREAMING_REQ_sum,TCC_WRITE_sum,Kernel_ID_3,SQC_DCACHE_REQ,SQ_ACTIVE_INST_FLAT,SQ_ACTIVE_INST_SCA,SQ_IFETCH,SQ_INSTS,SQ_INSTS_SALU,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MFMA_F32,Kernel_ID_4,SPI_RA_VGPR_SIMD_FULL_CSN,SPI_VWC1_VDATA_VALID_WR,SQC_DCACHE_REQ_READ_2,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_MISC,SQ_INSTS_BRANCH,SQ_INSTS_LDS_STORE_BANDWIDTH,SQ_INSTS_VALU_CVT,SQ_LDS_ATOMIC_RETURN,SQ_LDS_MEM_VIOLATIONS,TCC_MISS_sum,TCC_PROBE_sum,TCC_REQ_sum,TCC_WRITEBACK_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_READ_sum,Kernel_ID_5,CPC_CPC_UTCL2IU_IDLE,CPC_UTCL1_STALL_ON_TRANSLATION,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_RES_STALL_CSN,SQC_DCACHE_MISSES_DUPLICATE,SQ_INSTS_SMEM,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_MFMA_F8,SQ_INSTS_VALU_MFMA_MOPS_F8,SQ_INSTS_VALU_TRANS_F32,SQ_THREAD_CYCLES_VALU,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_BUSY_sum,TCC_HIT_sum,TCC_NORMAL_WRITEBACK_sum,TCC_READ_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,Kernel_ID_6,SPI_RA_TGLIM_CU_FULL_CSN,SPI_RA_WVLIM_STALL_CSN,SQC_TC_INST_REQ,SQ_INSTS_VALU,SQ_INSTS_VALU_MFMA_I8,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F64,SQ_INSTS_VALU_TRANS_F16,SQ_LDS_UNALIGNED_STALL,SQ_WAIT_ANY,TCC_EA0_WR_UNCACHED_32B_sum,TCC_NORMAL_EVICT_sum,Kernel_ID_7,SPI_CSC_WAVE_CNT_BUSY,SPI_RA_WAVE_SIMD_FULL_CSN,SQC_TC_DATA_WRITE_REQ,SQ_ACTIVE_INST_LDS,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F64,SQ_LDS_DATA_FIFO_FULL,SQ_VMEM_TA_ADDR_FIFO_FULL,SQ_WAVES,SQ_WAVES_RESTORED,TCC_EA0_ATOMIC_sum,TCC_EA0_RDREQ_DRAM_sum,TCC_EA0_WRREQ_64B_sum,TCC_EA0_WRREQ_DRAM_sum,Kernel_ID_8,CPC_CPC_TCIU_BUSY,CPC_ME1_DC0_SPI_BUSY,SPI_RA_REQ_NO_ALLOC_CSN,SPI_VWC0_VDATA_VALID_WR,SQC_DCACHE_ATOMIC,SQC_DCACHE_MISSES,SQC_ICACHE_REQ,SQC_TC_STALL,SQ_INSTS_VALU_MUL_F16,SQ_INST_LEVEL_LDS,SQ_WAVES_SAVED,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_TA_BUSY_sum,TCC_ATOMIC_sum,TCC_EA0_ATOMIC_LEVEL_sum,TCC_EA0_WRREQ_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_UTCL1_REQUEST_sum,Kernel_ID_9,CPC_CPC_TCIU_IDLE,CPC_TG_SEND,CPF_CPF_TCIU_IDLE,SPI_CS0_BUSY,SPI_CS1_BUSY,SPI_CS2_BUSY,SPI_CS3_BUSY,SQ_INSTS_LDS,SQ_INSTS_LDS_LOAD_BANDWIDTH,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_FMA_F16,SQ_LDS_IDX_ACTIVE,SQ_LEVEL_WAVES,SQ_WAVE_CYCLES,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_BUBBLE_sum,TCC_EA0_ATOMIC_LEVEL[0],TCC_EA0_ATOMIC_LEVEL[11],TCC_EA0_ATOMIC_LEVEL[12],TCC_EA0_ATOMIC_LEVEL[13],TCC_EA0_ATOMIC_LEVEL[14],TCC_EA0_ATOMIC_LEVEL[16],TCC_EA0_ATOMIC_LEVEL[17],TCC_EA0_ATOMIC_LEVEL[18],TCC_EA0_ATOMIC_LEVEL[19],TCC_EA0_ATOMIC_LEVEL[1],TCC_EA0_ATOMIC_LEVEL[22],TCC_EA0_ATOMIC_LEVEL[23],TCC_EA0_ATOMIC_LEVEL[24],TCC_EA0_ATOMIC_LEVEL[25],TCC_EA0_ATOMIC_LEVEL[27],TCC_EA0_ATOMIC_LEVEL[28],TCC_EA0_ATOMIC_LEVEL[29],TCC_EA0_ATOMIC_LEVEL[2],TCC_EA0_ATOMIC_LEVEL[30],TCC_EA0_ATOMIC_LEVEL[32],TCC_EA0_ATOMIC_LEVEL[33],TCC_EA0_ATOMIC_LEVEL[34],TCC_EA0_ATOMIC_LEVEL[35],TCC_EA0_ATOMIC_LEVEL[37],TCC_EA0_ATOMIC_LEVEL[38],TCC_EA0_ATOMIC_LEVEL[39],TCC_EA0_ATOMIC_LEVEL[3],TCC_EA0_ATOMIC_LEVEL[40],TCC_EA0_ATOMIC_LEVEL[43],TCC_EA0_ATOMIC_LEVEL[44],TCC_EA0_ATOMIC_LEVEL[45],TCC_EA0_ATOMIC_LEVEL[46],TCC_EA0_ATOMIC_LEVEL[48],TCC_EA0_ATOMIC_LEVEL[49],TCC_EA0_ATOMIC_LEVEL[4],TCC_EA0_ATOMIC_LEVEL[50],TCC_EA0_ATOMIC_LEVEL[51],TCC_EA0_ATOMIC_LEVEL[53],TCC_EA0_ATOMIC_LEVEL[54],TCC_EA0_ATOMIC_LEVEL[55],TCC_EA0_ATOMIC_LEVEL[56],TCC_EA0_ATOMIC_LEVEL[58],TCC_EA0_ATOMIC_LEVEL[59],TCC_EA0_ATOMIC_LEVEL[60],TCC_EA0_ATOMIC_LEVEL[61],TCC_EA0_ATOMIC_LEVEL[6],TCC_EA0_ATOMIC_LEVEL[7],TCC_EA0_ATOMIC_LEVEL[8],TCC_EA0_ATOMIC_LEVEL[9],TCC_EA0_RDREQ_LEVEL[0],TCC_EA0_RDREQ_LEVEL[11],TCC_EA0_RDREQ_LEVEL[12],TCC_EA0_RDREQ_LEVEL[13],TCC_EA0_RDREQ_LEVEL[14],TCC_EA0_RDREQ_LEVEL[16],TCC_EA0_RDREQ_LEVEL[17],TCC_EA0_RDREQ_LEVEL[18],TCC_EA0_RDREQ_LEVEL[19],TCC_EA0_RDREQ_LEVEL[1],TCC_EA0_RDREQ_LEVEL[22],TCC_EA0_RDREQ_LEVEL[23],TCC_EA0_RDREQ_LEVEL[24],TCC_EA0_RDREQ_LEVEL[25],TCC_EA0_RDREQ_LEVEL[27],TCC_EA0_RDREQ_LEVEL[28],TCC_EA0_RDREQ_LEVEL[29],TCC_EA0_RDREQ_LEVEL[2],TCC_EA0_RDREQ_LEVEL[30],TCC_EA0_RDREQ_LEVEL[32],TCC_EA0_RDREQ_LEVEL[33],TCC_EA0_RDREQ_LEVEL[34],TCC_EA0_RDREQ_LEVEL[35],TCC_EA0_RDREQ_LEVEL[37],TCC_EA0_RDREQ_LEVEL[38],TCC_EA0_RDREQ_LEVEL[39],TCC_EA0_RDREQ_LEVEL[3],TCC_EA0_RDREQ_LEVEL[40],TCC_EA0_RDREQ_LEVEL[43],TCC_EA0_RDREQ_LEVEL[44],TCC_EA0_RDREQ_LEVEL[45],TCC_EA0_RDREQ_LEVEL[46],TCC_EA0_RDREQ_LEVEL[48],TCC_EA0_RDREQ_LEVEL[49],TCC_EA0_RDREQ_LEVEL[4],TCC_EA0_RDREQ_LEVEL[50],TCC_EA0_RDREQ_LEVEL[51],TCC_EA0_RDREQ_LEVEL[53],TCC_EA0_RDREQ_LEVEL[54],TCC_EA0_RDREQ_LEVEL[55],TCC_EA0_RDREQ_LEVEL[56],TCC_EA0_RDREQ_LEVEL[58],TCC_EA0_RDREQ_LEVEL[59],TCC_EA0_RDREQ_LEVEL[60],TCC_EA0_RDREQ_LEVEL[61],TCC_EA0_RDREQ_LEVEL[6],TCC_EA0_RDREQ_LEVEL[7],TCC_EA0_RDREQ_LEVEL[8],TCC_EA0_RDREQ_LEVEL[9],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_TOO_MANY_EA_WRREQS_STALL[32],TCC_TOO_MANY_EA_WRREQS_STALL[33],TCC_TOO_MANY_EA_WRREQS_STALL[34],TCC_TOO_MANY_EA_WRREQS_STALL[35],TCC_TOO_MANY_EA_WRREQS_STALL[37],TCC_TOO_MANY_EA_WRREQS_STALL[38],TCC_TOO_MANY_EA_WRREQS_STALL[39],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_TOO_MANY_EA_WRREQS_STALL[40],TCC_TOO_MANY_EA_WRREQS_STALL[43],TCC_TOO_MANY_EA_WRREQS_STALL[44],TCC_TOO_MANY_EA_WRREQS_STALL[45],TCC_TOO_MANY_EA_WRREQS_STALL[46],TCC_TOO_MANY_EA_WRREQS_STALL[48],TCC_TOO_MANY_EA_WRREQS_STALL[49],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_TOO_MANY_EA_WRREQS_STALL[50],TCC_TOO_MANY_EA_WRREQS_STALL[51],TCC_TOO_MANY_EA_WRREQS_STALL[53],TCC_TOO_MANY_EA_WRREQS_STALL[54],TCC_TOO_MANY_EA_WRREQS_STALL[55],TCC_TOO_MANY_EA_WRREQS_STALL[56],TCC_TOO_MANY_EA_WRREQS_STALL[58],TCC_TOO_MANY_EA_WRREQS_STALL[59],TCC_TOO_MANY_EA_WRREQS_STALL[60],TCC_TOO_MANY_EA_WRREQS_STALL[61],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCP_GATE_EN2_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TD_TD_BUSY_sum,Kernel_ID_10,CPC_ME1_BUSY_FOR_PACKET_DECODE,CPC_SYNC_WRREQ_FIFO_BUSY,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_BUSY,GRBM_GUI_ACTIVE,SPI_CS0_WAVE,SPI_CS1_WAVE,SPI_CS2_WAVE,SPI_CS3_WAVE,SQC_DCACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQ_IFETCH_LEVEL,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_VMEM_WR_TA_DATA_FIFO_FULL,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TCC_EA0_RDREQ[0],TCC_EA0_RDREQ[10],TCC_EA0_RDREQ[11],TCC_EA0_RDREQ[12],TCC_EA0_RDREQ[13],TCC_EA0_RDREQ[14],TCC_EA0_RDREQ[15],TCC_EA0_RDREQ[16],TCC_EA0_RDREQ[17],TCC_EA0_RDREQ[18],TCC_EA0_RDREQ[19],TCC_EA0_RDREQ[1],TCC_EA0_RDREQ[20],TCC_EA0_RDREQ[21],TCC_EA0_RDREQ[22],TCC_EA0_RDREQ[23],TCC_EA0_RDREQ[25],TCC_EA0_RDREQ[26],TCC_EA0_RDREQ[27],TCC_EA0_RDREQ[28],TCC_EA0_RDREQ[29],TCC_EA0_RDREQ[2],TCC_EA0_RDREQ[30],TCC_EA0_RDREQ[31],TCC_EA0_RDREQ[32],TCC_EA0_RDREQ[33],TCC_EA0_RDREQ[34],TCC_EA0_RDREQ[35],TCC_EA0_RDREQ[36],TCC_EA0_RDREQ[37],TCC_EA0_RDREQ[38],TCC_EA0_RDREQ[39],TCC_EA0_RDREQ[3],TCC_EA0_RDREQ[40],TCC_EA0_RDREQ[41],TCC_EA0_RDREQ[42],TCC_EA0_RDREQ[43],TCC_EA0_RDREQ[45],TCC_EA0_RDREQ[46],TCC_EA0_RDREQ[47],TCC_EA0_RDREQ[48],TCC_EA0_RDREQ[49],TCC_EA0_RDREQ[50],TCC_EA0_RDREQ[51],TCC_EA0_RDREQ[52],TCC_EA0_RDREQ[53],TCC_EA0_RDREQ[54],TCC_EA0_RDREQ[55],TCC_EA0_RDREQ[56],TCC_EA0_RDREQ[57],TCC_EA0_RDREQ[58],TCC_EA0_RDREQ[59],TCC_EA0_RDREQ[5],TCC_EA0_RDREQ[60],TCC_EA0_RDREQ[61],TCC_EA0_RDREQ[62],TCC_EA0_RDREQ[63],TCC_EA0_RDREQ[6],TCC_EA0_RDREQ[7],TCC_EA0_RDREQ[8],TCC_EA0_RDREQ[9],TCC_EA0_WRREQ_LEVEL[0],TCC_EA0_WRREQ_LEVEL[10],TCC_EA0_WRREQ_LEVEL[11],TCC_EA0_WRREQ_LEVEL[12],TCC_EA0_WRREQ_LEVEL[13],TCC_EA0_WRREQ_LEVEL[14],TCC_EA0_WRREQ_LEVEL[15],TCC_EA0_WRREQ_LEVEL[16],TCC_EA0_WRREQ_LEVEL[17],TCC_EA0_WRREQ_LEVEL[18],TCC_EA0_WRREQ_LEVEL[19],TCC_EA0_WRREQ_LEVEL[1],TCC_EA0_WRREQ_LEVEL[20],TCC_EA0_WRREQ_LEVEL[21],TCC_EA0_WRREQ_LEVEL[22],TCC_EA0_WRREQ_LEVEL[23],TCC_EA0_WRREQ_LEVEL[25],TCC_EA0_WRREQ_LEVEL[26],TCC_EA0_WRREQ_LEVEL[27],TCC_EA0_WRREQ_LEVEL[28],TCC_EA0_WRREQ_LEVEL[29],TCC_EA0_WRREQ_LEVEL[2],TCC_EA0_WRREQ_LEVEL[30],TCC_EA0_WRREQ_LEVEL[31],TCC_EA0_WRREQ_LEVEL[32],TCC_EA0_WRREQ_LEVEL[33],TCC_EA0_WRREQ_LEVEL[34],TCC_EA0_WRREQ_LEVEL[35],TCC_EA0_WRREQ_LEVEL[36],TCC_EA0_WRREQ_LEVEL[37],TCC_EA0_WRREQ_LEVEL[38],TCC_EA0_WRREQ_LEVEL[39],TCC_EA0_WRREQ_LEVEL[3],TCC_EA0_WRREQ_LEVEL[40],TCC_EA0_WRREQ_LEVEL[41],TCC_EA0_WRREQ_LEVEL[42],TCC_EA0_WRREQ_LEVEL[43],TCC_EA0_WRREQ_LEVEL[45],TCC_EA0_WRREQ_LEVEL[46],TCC_EA0_WRREQ_LEVEL[47],TCC_EA0_WRREQ_LEVEL[48],TCC_EA0_WRREQ_LEVEL[49],TCC_EA0_WRREQ_LEVEL[50],TCC_EA0_WRREQ_LEVEL[51],TCC_EA0_WRREQ_LEVEL[52],TCC_EA0_WRREQ_LEVEL[53],TCC_EA0_WRREQ_LEVEL[54],TCC_EA0_WRREQ_LEVEL[55],TCC_EA0_WRREQ_LEVEL[56],TCC_EA0_WRREQ_LEVEL[57],TCC_EA0_WRREQ_LEVEL[58],TCC_EA0_WRREQ_LEVEL[59],TCC_EA0_WRREQ_LEVEL[5],TCC_EA0_WRREQ_LEVEL[60],TCC_EA0_WRREQ_LEVEL[61],TCC_EA0_WRREQ_LEVEL[62],TCC_EA0_WRREQ_LEVEL[63],TCC_EA0_WRREQ_LEVEL[6],TCC_EA0_WRREQ_LEVEL[7],TCC_EA0_WRREQ_LEVEL[8],TCC_EA0_WRREQ_LEVEL[9],TCC_NC_REQ_sum,TCC_REQ[0],TCC_REQ[10],TCC_REQ[11],TCC_REQ[12],TCC_REQ[13],TCC_REQ[14],TCC_REQ[15],TCC_REQ[16],TCC_REQ[17],TCC_REQ[18],TCC_REQ[19],TCC_REQ[1],TCC_REQ[20],TCC_REQ[21],TCC_REQ[22],TCC_REQ[23],TCC_REQ[25],TCC_REQ[26],TCC_REQ[27],TCC_REQ[28],TCC_REQ[29],TCC_REQ[2],TCC_REQ[30],TCC_REQ[31],TCC_REQ[32],TCC_REQ[33],TCC_REQ[34],TCC_REQ[35],TCC_REQ[36],TCC_REQ[37],TCC_REQ[38],TCC_REQ[39],TCC_REQ[3],TCC_REQ[40],TCC_REQ[41],TCC_REQ[42],TCC_REQ[43],TCC_REQ[45],TCC_REQ[46],TCC_REQ[47],TCC_REQ[48],TCC_REQ[49],TCC_REQ[50],TCC_REQ[51],TCC_REQ[52],TCC_REQ[53],TCC_REQ[54],TCC_REQ[55],TCC_REQ[56],TCC_REQ[57],TCC_REQ[58],TCC_REQ[59],TCC_REQ[5],TCC_REQ[60],TCC_REQ[61],TCC_REQ[62],TCC_REQ[63],TCC_REQ[6],TCC_REQ[7],TCC_REQ[8],TCC_REQ[9],TCP_GATE_EN1_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_TOTAL_WRITE_sum,TD_ATOMIC_WAVEFRONT_sum,TD_TC_STALL_sum,Kernel_ID_11,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_IDLE,CPF_CPF_STAT_STALL,SPI_CSQ_P0_OCCUPANCY,SPI_CSQ_P1_OCCUPANCY,SPI_CSQ_P2_OCCUPANCY,SPI_CSQ_P3_OCCUPANCY,SPI_RA_SGPR_SIMD_FULL_CSN,SQC_DCACHE_REQ_READ_16,SQ_BUSY_CU_CYCLES,SQ_INSTS_LDS_LOAD,SQ_INSTS_LDS_STORE,SQ_INSTS_VALU_MUL_F64,SQ_INST_LEVEL_SMEM,SQ_LDS_CMD_FIFO_FULL,TA_BUFFER_TOTAL_CYCLES_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_ATOMIC[10],TCC_ATOMIC[11],TCC_ATOMIC[12],TCC_ATOMIC[13],TCC_ATOMIC[15],TCC_ATOMIC[16],TCC_ATOMIC[17],TCC_ATOMIC[18],TCC_ATOMIC[19],TCC_ATOMIC[1],TCC_ATOMIC[21],TCC_ATOMIC[22],TCC_ATOMIC[23],TCC_ATOMIC[24],TCC_ATOMIC[26],TCC_ATOMIC[27],TCC_ATOMIC[28],TCC_ATOMIC[29],TCC_ATOMIC[2],TCC_ATOMIC[31],TCC_ATOMIC[32],TCC_ATOMIC[33],TCC_ATOMIC[34],TCC_ATOMIC[35],TCC_ATOMIC[37],TCC_ATOMIC[38],TCC_ATOMIC[39],TCC_ATOMIC[3],TCC_ATOMIC[40],TCC_ATOMIC[42],TCC_ATOMIC[43],TCC_ATOMIC[44],TCC_ATOMIC[45],TCC_ATOMIC[47],TCC_ATOMIC[48],TCC_ATOMIC[49],TCC_ATOMIC[50],TCC_ATOMIC[51],TCC_ATOMIC[53],TCC_ATOMIC[54],TCC_ATOMIC[55],TCC_ATOMIC[56],TCC_ATOMIC[58],TCC_ATOMIC[59],TCC_ATOMIC[5],TCC_ATOMIC[60],TCC_ATOMIC[61],TCC_ATOMIC[63],TCC_ATOMIC[6],TCC_ATOMIC[7],TCC_ATOMIC[8],TCC_BUBBLE[0],TCC_BUBBLE[10],TCC_BUBBLE[11],TCC_BUBBLE[12],TCC_BUBBLE[13],TCC_BUBBLE[15],TCC_BUBBLE[16],TCC_BUBBLE[17],TCC_BUBBLE[18],TCC_BUBBLE[19],TCC_BUBBLE[1],TCC_BUBBLE[21],TCC_BUBBLE[22],TCC_BUBBLE[23],TCC_BUBBLE[24],TCC_BUBBLE[26],TCC_BUBBLE[27],TCC_BUBBLE[28],TCC_BUBBLE[29],TCC_BUBBLE[2],TCC_BUBBLE[31],TCC_BUBBLE[32],TCC_BUBBLE[33],TCC_BUBBLE[34],TCC_BUBBLE[35],TCC_BUBBLE[37],TCC_BUBBLE[38],TCC_BUBBLE[39],TCC_BUBBLE[3],TCC_BUBBLE[40],TCC_BUBBLE[42],TCC_BUBBLE[43],TCC_BUBBLE[44],TCC_BUBBLE[45],TCC_BUBBLE[47],TCC_BUBBLE[48],TCC_BUBBLE[49],TCC_BUBBLE[50],TCC_BUBBLE[51],TCC_BUBBLE[53],TCC_BUBBLE[54],TCC_BUBBLE[55],TCC_BUBBLE[56],TCC_BUBBLE[58],TCC_BUBBLE[59],TCC_BUBBLE[5],TCC_BUBBLE[60],TCC_BUBBLE[61],TCC_BUBBLE[63],TCC_BUBBLE[6],TCC_BUBBLE[7],TCC_BUBBLE[8],TCC_EA0_ATOMIC[0],TCC_EA0_ATOMIC[10],TCC_EA0_ATOMIC[11],TCC_EA0_ATOMIC[12],TCC_EA0_ATOMIC[13],TCC_EA0_ATOMIC[15],TCC_EA0_ATOMIC[16],TCC_EA0_ATOMIC[17],TCC_EA0_ATOMIC[18],TCC_EA0_ATOMIC[19],TCC_EA0_ATOMIC[1],TCC_EA0_ATOMIC[21],TCC_EA0_ATOMIC[22],TCC_EA0_ATOMIC[23],TCC_EA0_ATOMIC[24],TCC_EA0_ATOMIC[26],TCC_EA0_ATOMIC[27],TCC_EA0_ATOMIC[28],TCC_EA0_ATOMIC[29],TCC_EA0_ATOMIC[2],TCC_EA0_ATOMIC[31],TCC_EA0_ATOMIC[32],TCC_EA0_ATOMIC[33],TCC_EA0_ATOMIC[34],TCC_EA0_ATOMIC[35],TCC_EA0_ATOMIC[37],TCC_EA0_ATOMIC[38],TCC_EA0_ATOMIC[39],TCC_EA0_ATOMIC[3],TCC_EA0_ATOMIC[40],TCC_EA0_ATOMIC[42],TCC_EA0_ATOMIC[43],TCC_EA0_ATOMIC[44],TCC_EA0_ATOMIC[45],TCC_EA0_ATOMIC[47],TCC_EA0_ATOMIC[48],TCC_EA0_ATOMIC[49],TCC_EA0_ATOMIC[50],TCC_EA0_ATOMIC[51],TCC_EA0_ATOMIC[53],TCC_EA0_ATOMIC[54],TCC_EA0_ATOMIC[55],TCC_EA0_ATOMIC[56],TCC_EA0_ATOMIC[58],TCC_EA0_ATOMIC[59],TCC_EA0_ATOMIC[5],TCC_EA0_ATOMIC[60],TCC_EA0_ATOMIC[61],TCC_EA0_ATOMIC[63],TCC_EA0_ATOMIC[6],TCC_EA0_ATOMIC[7],TCC_EA0_ATOMIC[8],TCC_HIT[0],TCC_HIT[10],TCC_HIT[11],TCC_HIT[12],TCC_HIT[13],TCC_HIT[15],TCC_HIT[16],TCC_HIT[17],TCC_HIT[18],TCC_HIT[19],TCC_HIT[1],TCC_HIT[21],TCC_HIT[22],TCC_HIT[23],TCC_HIT[24],TCC_HIT[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diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_0.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_0.csv new file mode 100644 index 0000000000..23ee498894 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_0.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,CPC_CPC_UTCL2IU_BUSY,CPC_SYNC_FIFO_FULL,SPI_CS0_NUM_THREADGROUPS,SPI_CS1_NUM_THREADGROUPS,SPI_CS2_NUM_THREADGROUPS,SPI_CS3_NUM_THREADGROUPS,SQC_DCACHE_REQ_READ_8,SQC_TC_DATA_ATOMIC_REQ,SQ_ACTIVE_INST_VALU,SQ_BUSY_CYCLES,SQ_INSTS_SENDMSG,SQ_INSTS_VALU_ADD_F64,SQ_LDS_BANK_CONFLICT,SQ_VMEM_TA_CMD_FIFO_FULL,TA_BUFFER_WAVEFRONTS_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_EA0_WRREQ_LEVEL_sum,TCC_UC_REQ_sum,TCP_TCC_READ_REQ_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum +0,0,1,15772,15772,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248227257271964,1248227257293723,1,13,389.0,0.0,4096.0,0.0,0.0,0.0,0.0,0.0,98304.0,126903.0,16384.0,0.0,0.0,0.0,0.0,154249.0,0.0,36146.0,9826410.0,26.0,65536.0,11.0,768.0,0.0 +1,0,1,15772,15772,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248227257962097,1248227257979016,2,13,0.0,0.0,4096.0,0.0,0.0,0.0,0.0,0.0,98304.0,96924.0,16384.0,0.0,0.0,0.0,0.0,103050.0,0.0,36209.0,10285296.0,8.0,65536.0,0.0,0.0,0.0 +2,0,1,15772,15772,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248227258551114,1248227258567914,3,13,0.0,0.0,4096.0,0.0,0.0,0.0,0.0,0.0,98304.0,96768.0,16384.0,0.0,0.0,0.0,0.0,100616.0,0.0,36239.0,10281734.0,0.0,65536.0,0.0,0.0,0.0 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_1.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_1.csv new file mode 100644 index 0000000000..269e6fbd13 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_1.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,CPC_CANE_BUSY,CPC_GD_BUSY,SPI_RA_REQ_NO_ALLOC,SPI_SWC_CSC_WR,SQC_DCACHE_REQ_READ_4,SQC_TC_DATA_READ_REQ,SQ_INSTS_VALU_INT64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_F6F4,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VMEM,SQ_VALU_MFMA_BUSY_CYCLES,TA_BUFFER_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TCC_CC_REQ_sum,TCC_EA0_RDREQ_LEVEL_sum,TCC_EA0_RD_UNCACHED_32B_sum,TCC_RW_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_UTCL1_PERMISSION_MISS_sum +0,0,1,15779,15779,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248227786612853,1248227786635252,1,13,630.0,30469.0,12744.0,32768.0,0.0,72.0,32768.0,0.0,0.0,0.0,32768.0,0.0,0.0,16384.0,0.0,22666001.0,58.0,197976.0,406733.0,0.0,0.0,0.0 +1,0,1,15779,15779,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248227787316865,1248227787333785,2,13,631.0,22019.0,4288.0,32768.0,0.0,72.0,32768.0,0.0,0.0,0.0,32768.0,0.0,0.0,16384.0,0.0,11922030.0,16.0,197976.0,289225.0,0.0,0.0,0.0 +2,0,1,15779,15779,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248227787897083,1248227787913762,3,13,630.0,21586.0,3860.0,32768.0,0.0,72.0,32768.0,0.0,0.0,0.0,32768.0,0.0,0.0,16384.0,0.0,11792534.0,0.0,197976.0,286818.0,0.0,0.0,0.0 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_2.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_2.csv new file mode 100644 index 0000000000..16fe385445 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_2.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,CPC_CPC_UTCL2IU_IDLE,CPC_UTCL1_STALL_ON_TRANSLATION,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_RES_STALL_CSN,SQC_DCACHE_MISSES_DUPLICATE,SQ_INSTS_SMEM,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_MFMA_F8,SQ_INSTS_VALU_MFMA_MOPS_F8,SQ_INSTS_VALU_TRANS_F32,SQ_THREAD_CYCLES_VALU,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_BUSY_sum,TCC_HIT_sum,TCC_NORMAL_WRITEBACK_sum,TCC_READ_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum +0,0,1,15786,15786,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248228340675080,1248228340696799,1,13,76981.0,399.0,0.0,9346.0,2160.0,65536.0,0.0,49152.0,0.0,0.0,0.0,6291456.0,0.0,32768.0,533130.0,66864.0,30395.0,66936.0,0.0,0.0,0.0,131072.0 +1,0,1,15786,15786,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248228341369934,1248228341386613,2,13,65633.0,0.0,0.0,3274.0,2160.0,65536.0,0.0,49152.0,0.0,0.0,0.0,6291456.0,0.0,32768.0,459164.0,66864.0,29343.0,66912.0,0.0,0.0,0.0,131072.0 +2,0,1,15786,15786,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248228341957512,1248228341974431,3,13,62962.0,0.0,0.0,3253.0,2160.0,65536.0,0.0,49152.0,0.0,0.0,0.0,6291456.0,0.0,32768.0,460697.0,66864.0,29330.0,66904.0,0.0,0.0,0.0,131072.0 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_3.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_3.csv new file mode 100644 index 0000000000..80a96c3e0d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_3.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,SPI_RA_VGPR_SIMD_FULL_CSN,SPI_VWC1_VDATA_VALID_WR,SQC_DCACHE_REQ_READ_2,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_MISC,SQ_INSTS_BRANCH,SQ_INSTS_LDS_STORE_BANDWIDTH,SQ_INSTS_VALU_CVT,SQ_LDS_ATOMIC_RETURN,SQ_LDS_MEM_VIOLATIONS,TCC_MISS_sum,TCC_PROBE_sum,TCC_REQ_sum,TCC_WRITEBACK_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_READ_sum +0,0,1,15793,15793,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248228890145284,1248228890166603,1,13,0.0,32768.0,32768.0,278528.0,32768.0,16384.0,0.0,0.0,0.0,0.0,131138.0,0.0,198002.0,65596.0,0.0,2097152.0,0.0,1048576.0 +1,0,1,15793,15793,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248228890710662,1248228890727781,2,13,0.0,32768.0,32768.0,278528.0,32768.0,16384.0,0.0,0.0,0.0,0.0,131120.0,0.0,197984.0,65596.0,0.0,2097152.0,0.0,1048576.0 +2,0,1,15793,15793,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248228891192003,1248228891208963,3,13,0.0,32768.0,32768.0,278528.0,32768.0,16384.0,0.0,0.0,0.0,0.0,131112.0,0.0,197976.0,65596.0,0.0,2097152.0,0.0,1048576.0 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_4.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_4.csv new file mode 100644 index 0000000000..78185bb32f --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_4.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,SPI_CSC_WAVE_CNT_BUSY,SPI_RA_WAVE_SIMD_FULL_CSN,SQC_TC_DATA_WRITE_REQ,SQ_ACTIVE_INST_LDS,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F64,SQ_LDS_DATA_FIFO_FULL,SQ_VMEM_TA_ADDR_FIFO_FULL,SQ_WAVES,SQ_WAVES_RESTORED,TCC_EA0_ATOMIC_sum,TCC_EA0_RDREQ_DRAM_sum,TCC_EA0_WRREQ_64B_sum,TCC_EA0_WRREQ_DRAM_sum +0,0,1,15800,15800,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248229438857357,1248229438879317,1,13,129716.0,279581.0,0.0,0.0,0.0,0.0,0.0,0.0,16384.0,0.0,0.0,65622.0,131072.0,131072.0 +1,0,1,15800,15800,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248229439181269,1248229439198349,2,13,97526.0,104638.0,0.0,0.0,0.0,0.0,0.0,0.0,16384.0,0.0,0.0,65612.0,131072.0,131072.0 +2,0,1,15800,15800,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248229439450184,1248229439467063,3,13,97380.0,103228.0,0.0,0.0,0.0,0.0,0.0,0.0,16384.0,0.0,0.0,65612.0,131072.0,131072.0 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_5.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_5.csv new file mode 100644 index 0000000000..45731a4561 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_5.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,SPI_RA_LDS_CU_FULL_CSN,SPI_RA_TMP_STALL_CSN,SQC_DCACHE_REQ_READ_1,SQC_ICACHE_HITS,SQ_INSTS_LDS_ATOMIC_BANDWIDTH,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_F6F4,SQ_INSTS_VALU_MUL_F32,SQ_LDS_ADDR_CONFLICT,SQ_WAIT_INST_ANY,TCC_EA0_RDREQ_32B_sum,TCC_EA0_RDREQ_sum,TCC_STREAMING_REQ_sum,TCC_WRITE_sum +0,0,1,15807,15807,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248229989191714,1248229989213393,1,13,0.0,0.0,32768.0,64005.0,0.0,0.0,0.0,0.0,0.0,656853.0,0.0,65640.0,0.0,131072.0 +1,0,1,15807,15807,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248229989539141,1248229989555860,2,13,0.0,0.0,32768.0,64262.0,0.0,0.0,0.0,0.0,0.0,95857.0,0.0,65612.0,0.0,131072.0 +2,0,1,15807,15807,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248229989799091,1248229989816011,3,13,0.0,0.0,32768.0,64364.0,0.0,0.0,0.0,0.0,0.0,120606.0,0.0,65612.0,0.0,131072.0 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_6.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_6.csv new file mode 100644 index 0000000000..0ca4acee02 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_6.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,SPI_RA_TGLIM_CU_FULL_CSN,SPI_RA_WVLIM_STALL_CSN,SQC_TC_INST_REQ,SQ_INSTS_VALU,SQ_INSTS_VALU_MFMA_I8,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F64,SQ_INSTS_VALU_TRANS_F16,SQ_LDS_UNALIGNED_STALL,SQ_WAIT_ANY,TCC_EA0_WR_UNCACHED_32B_sum,TCC_NORMAL_EVICT_sum +0,0,1,15814,15814,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248230542355535,1248230542376494,1,13,0.0,0.0,1296.0,98304.0,0.0,0.0,0.0,0.0,0.0,5300250.0,0.0,44.0 +1,0,1,15814,15814,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248230542613524,1248230542630444,2,13,0.0,0.0,1296.0,98304.0,0.0,0.0,0.0,0.0,0.0,4063067.0,0.0,44.0 +2,0,1,15814,15814,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248230542841396,1248230542858275,3,13,0.0,0.0,1296.0,98304.0,0.0,0.0,0.0,0.0,0.0,4109650.0,0.0,44.0 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_7.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_7.csv new file mode 100644 index 0000000000..6adbe9b90e --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/pmc_perf_7.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,SQC_DCACHE_REQ,SQ_ACTIVE_INST_FLAT,SQ_ACTIVE_INST_SCA,SQ_IFETCH,SQ_INSTS,SQ_INSTS_SALU,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MFMA_F32 +0,0,1,15821,15821,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248231092253037,1248231092274436,1,13,65536.0,32768.0,114688.0,65536.0,327680.0,49152.0,0.0,0.0 +1,0,1,15821,15821,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248231092448589,1248231092465748,2,13,65536.0,32768.0,114688.0,65536.0,327680.0,49152.0,0.0,0.0 +2,0,1,15821,15821,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248231092604703,1248231092621702,3,13,65536.0,32768.0,114688.0,65536.0,327680.0,49152.0,0.0,0.0 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/profiling_config.yaml b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/profiling_config.yaml new file mode 100644 index 0000000000..8182466e4b --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/profiling_config.yaml @@ -0,0 +1,39 @@ +config_dir: /app/src/rocprof_compute_soc/analysis_configs +device: -1 +dispatch: null +filter_blocks: {} +format_rocprof_output: csv +hip_trace: false +join_type: grid +kernel: null +kernel_names: false +kokkos_trace: false +list_metrics: null +loglevel: 10 +lucky: false +mem_level: ALL +mode: profile +name: vcopy +no_roof: true +path: /app/workloads/vcopy/MI350 +quiet: false +remaining: +- -- +- tests/vcopy +- -n +- '1048576' +- -b +- '256' +- -i +- '3' +roof_only: false +roofline_data_type: +- FP32 +sort: kernels +spatial_multiplexing: null +specs: false +subpath: gpu +summaries: false +target: null +use_rocscope: false +verbose: 1 diff --git a/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/sysinfo.csv new file mode 100644 index 0000000000..a30291968b --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/no_roof/MI350/sysinfo.csv @@ -0,0 +1,2 @@ +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_series,gpu_model,gpu_arch,gpu_chip_id,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Fri Mar 28 22:43:57 2025 (UTC),3,f77021840818,AMD Ryzen Threadripper PRO 7985WX 64-Cores,AMDVBS1052957N.FD,Ubuntu 22.04.5 LTS,5.15.0-70-generic,,527456116,,6.5.0-831,113-M3550101-100,SPX,NPS1,MI350,MI350,gfx950,30112,32,4096,128,4,16,64,1024,32,0,,0,,128,32,64,4,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/path/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/path/MI100/sysinfo.csv index 4278075525..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/path/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/path/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/path/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/path/MI200/sysinfo.csv index a382607e3d..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/path/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/path/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/path/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/path/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..7dd5abecf7 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/path/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",11995 diff --git a/projects/rocprofiler-compute/tests/workloads/path/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/path/MI300A_A1/sysinfo.csv index 92c9adfe9f..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/path/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/path/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:33:59 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/path/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/path/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..f02fc0193d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/path/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",60633 diff --git a/projects/rocprofiler-compute/tests/workloads/path/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/path/MI300X_A1/sysinfo.csv index 2830231d3c..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/path/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/path/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 11:59:34 AM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/sort_dispatches/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/sort_dispatches/MI200/sysinfo.csv index 7a9980829d..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/sort_dispatches/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/sort_dispatches/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -sort_dispatches,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:06:17 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/sort_kernels/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/sort_kernels/MI200/sysinfo.csv index 3cadeb5cc9..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/sort_kernels/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/sort_kernels/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -sort_kernels,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:36:34 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI100/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI100/sysinfo.csv index 4278075525..53463c7c0d 100644 --- a/projects/rocprofiler-compute/tests/workloads/vcopy/MI100/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI100/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 21 Mar 2024 03:52:12 PM (CDT),2,t007-001.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527651008,,6.0.2-115,113-D3431401-100,NA,NA,MI100,gfx908,16,8192,120,4,8,64,1024,40,1502,1200,1502,1200,32,32,64,4,1228.8,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI200/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI200/sysinfo.csv index a382607e3d..561b709077 100644 --- a/projects/rocprofiler-compute/tests/workloads/vcopy/MI200/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI200/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +path,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF|roofline,Thu 21 Mar 2024 04:16:46 PM (CDT),2,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,,527650760,,6.0.2-115,113-D67301-059,NA,NA,MI200,gfx90a,16,8192,104,4,8,64,1024,32,1700,1600,1700,1600,32,32,56,4,1638.4,1,32 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI300A_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI300A_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..ce2b03eb63 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI300A_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",2 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",2 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",2 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI300A_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI300A_A1/sysinfo.csv index 17ad2721f6..111a312780 100644 --- a/projects/rocprofiler-compute/tests/workloads/vcopy/MI300A_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI300A_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:09:51 PM (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6,96 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI300X_A1/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI300X_A1/pmc_dispatch_info.csv new file mode 100644 index 0000000000..ce2b03eb63 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI300X_A1/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int) (.kd)",2 +1,"vecCopy(double*, double*, double*, int, int) (.kd)",2 +2,"vecCopy(double*, double*, double*, int, int) (.kd)",2 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI300X_A1/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI300X_A1/sysinfo.csv index 5ec0030fd7..36a2277125 100644 --- a/projects/rocprofiler-compute/tests/workloads/vcopy/MI300X_A1/sysinfo.csv +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI300X_A1/sysinfo.csv @@ -1,2 +1,2 @@ -workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd -vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8 +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd,num_hbm_channels +vcopy,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Thu 30 May 2024 02:19:39 PM (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8,128 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/SQ_IFETCH_LEVEL.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/SQ_IFETCH_LEVEL.csv new file mode 100644 index 0000000000..c32def855c --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/SQ_IFETCH_LEVEL.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,CPC_ME1_BUSY_FOR_PACKET_DECODE,CPC_SYNC_WRREQ_FIFO_BUSY,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_BUSY,GRBM_GUI_ACTIVE,SPI_CS0_WAVE,SPI_CS1_WAVE,SPI_CS2_WAVE,SPI_CS3_WAVE,SQC_DCACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQ_IFETCH_LEVEL,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_VMEM_WR_TA_DATA_FIFO_FULL,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TCC_EA0_RDREQ[0],TCC_EA0_RDREQ[10],TCC_EA0_RDREQ[11],TCC_EA0_RDREQ[12],TCC_EA0_RDREQ[13],TCC_EA0_RDREQ[14],TCC_EA0_RDREQ[15],TCC_EA0_RDREQ[16],TCC_EA0_RDREQ[17],TCC_EA0_RDREQ[18],TCC_EA0_RDREQ[19],TCC_EA0_RDREQ[1],TCC_EA0_RDREQ[20],TCC_EA0_RDREQ[21],TCC_EA0_RDREQ[22],TCC_EA0_RDREQ[23],TCC_EA0_RDREQ[25],TCC_EA0_RDREQ[26],TCC_EA0_RDREQ[27],TCC_EA0_RDREQ[28],TCC_EA0_RDREQ[29],TCC_EA0_RDREQ[2],TCC_EA0_RDREQ[30],TCC_EA0_RDREQ[31],TCC_EA0_RDREQ[32],TCC_EA0_RDREQ[33],TCC_EA0_RDREQ[34],TCC_EA0_RDREQ[35],TCC_EA0_RDREQ[36],TCC_EA0_RDREQ[37],TCC_EA0_RDREQ[38],TCC_EA0_RDREQ[39],TCC_EA0_RDREQ[3],TCC_EA0_RDREQ[40],TCC_EA0_RDREQ[41],TCC_EA0_RDREQ[42],TCC_EA0_RDREQ[43],TCC_EA0_RDREQ[45],TCC_EA0_RDREQ[46],TCC_EA0_RDREQ[47],TCC_EA0_RDREQ[48],TCC_EA0_RDREQ[49],TCC_EA0_RDREQ[50],TCC_EA0_RDREQ[51],TCC_EA0_RDREQ[52],TCC_EA0_RDREQ[53],TCC_EA0_RDREQ[54],TCC_EA0_RDREQ[55],TCC_EA0_RDREQ[56],TCC_EA0_RDREQ[57],TCC_EA0_RDREQ[58],TCC_EA0_RDREQ[59],TCC_EA0_RDREQ[5],TCC_EA0_RDREQ[60],TCC_EA0_RDREQ[61],TCC_EA0_RDREQ[62],TCC_EA0_RDREQ[63],TCC_EA0_RDREQ[6],TCC_EA0_RDREQ[7],TCC_EA0_RDREQ[8],TCC_EA0_RDREQ[9],TCC_EA0_WRREQ_LEVEL[0],TCC_EA0_WRREQ_LEVEL[10],TCC_EA0_WRREQ_LEVEL[11],TCC_EA0_WRREQ_LEVEL[12],TCC_EA0_WRREQ_LEVEL[13],TCC_EA0_WRREQ_LEVEL[14],TCC_EA0_WRREQ_LEVEL[15],TCC_EA0_WRREQ_LEVEL[16],TCC_EA0_WRREQ_LEVEL[17],TCC_EA0_WRREQ_LEVEL[18],TCC_EA0_WRREQ_LEVEL[19],TCC_EA0_WRREQ_LEVEL[1],TCC_EA0_WRREQ_LEVEL[20],TCC_EA0_WRREQ_LEVEL[21],TCC_EA0_WRREQ_LEVEL[22],TCC_EA0_WRREQ_LEVEL[23],TCC_EA0_WRREQ_LEVEL[25],TCC_EA0_WRREQ_LEVEL[26],TCC_EA0_WRREQ_LEVEL[27],TCC_EA0_WRREQ_LEVEL[28],TCC_EA0_WRREQ_LEVEL[29],TCC_EA0_WRREQ_LEVEL[2],TCC_EA0_WRREQ_LEVEL[30],TCC_EA0_WRREQ_LEVEL[31],TCC_EA0_WRREQ_LEVEL[32],TCC_EA0_WRREQ_LEVEL[33],TCC_EA0_WRREQ_LEVEL[34],TCC_EA0_WRREQ_LEVEL[35],TCC_EA0_WRREQ_LEVEL[36],TCC_EA0_WRREQ_LEVEL[37],TCC_EA0_WRREQ_LEVEL[38],TCC_EA0_WRREQ_LEVEL[39],TCC_EA0_WRREQ_LEVEL[3],TCC_EA0_WRREQ_LEVEL[40],TCC_EA0_WRREQ_LEVEL[41],TCC_EA0_WRREQ_LEVEL[42],TCC_EA0_WRREQ_LEVEL[43],TCC_EA0_WRREQ_LEVEL[45],TCC_EA0_WRREQ_LEVEL[46],TCC_EA0_WRREQ_LEVEL[47],TCC_EA0_WRREQ_LEVEL[48],TCC_EA0_WRREQ_LEVEL[49],TCC_EA0_WRREQ_LEVEL[50],TCC_EA0_WRREQ_LEVEL[51],TCC_EA0_WRREQ_LEVEL[52],TCC_EA0_WRREQ_LEVEL[53],TCC_EA0_WRREQ_LEVEL[54],TCC_EA0_WRREQ_LEVEL[55],TCC_EA0_WRREQ_LEVEL[56],TCC_EA0_WRREQ_LEVEL[57],TCC_EA0_WRREQ_LEVEL[58],TCC_EA0_WRREQ_LEVEL[59],TCC_EA0_WRREQ_LEVEL[5],TCC_EA0_WRREQ_LEVEL[60],TCC_EA0_WRREQ_LEVEL[61],TCC_EA0_WRREQ_LEVEL[62],TCC_EA0_WRREQ_LEVEL[63],TCC_EA0_WRREQ_LEVEL[6],TCC_EA0_WRREQ_LEVEL[7],TCC_EA0_WRREQ_LEVEL[8],TCC_EA0_WRREQ_LEVEL[9],TCC_NC_REQ_sum,TCC_REQ[0],TCC_REQ[10],TCC_REQ[11],TCC_REQ[12],TCC_REQ[13],TCC_REQ[14],TCC_REQ[15],TCC_REQ[16],TCC_REQ[17],TCC_REQ[18],TCC_REQ[19],TCC_REQ[1],TCC_REQ[20],TCC_REQ[21],TCC_REQ[22],TCC_REQ[23],TCC_REQ[25],TCC_REQ[26],TCC_REQ[27],TCC_REQ[28],TCC_REQ[29],TCC_REQ[2],TCC_REQ[30],TCC_REQ[31],TCC_REQ[32],TCC_REQ[33],TCC_REQ[34],TCC_REQ[35],TCC_REQ[36],TCC_REQ[37],TCC_REQ[38],TCC_REQ[39],TCC_REQ[3],TCC_REQ[40],TCC_REQ[41],TCC_REQ[42],TCC_REQ[43],TCC_REQ[45],TCC_REQ[46],TCC_REQ[47],TCC_REQ[48],TCC_REQ[49],TCC_REQ[50],TCC_REQ[51],TCC_REQ[52],TCC_REQ[53],TCC_REQ[54],TCC_REQ[55],TCC_REQ[56],TCC_REQ[57],TCC_REQ[58],TCC_REQ[59],TCC_REQ[5],TCC_REQ[60],TCC_REQ[61],TCC_REQ[62],TCC_REQ[63],TCC_REQ[6],TCC_REQ[7],TCC_REQ[8],TCC_REQ[9],TCP_GATE_EN1_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_TOTAL_WRITE_sum,TD_ATOMIC_WAVEFRONT_sum,TD_TC_STALL_sum +0,0,1,15737,15737,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, 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diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/SQ_INST_LEVEL_LDS.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/SQ_INST_LEVEL_LDS.csv new file mode 100644 index 0000000000..f69137167f --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/SQ_INST_LEVEL_LDS.csv @@ -0,0 +1,4 @@ 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double*, int, int)",1248225043214988,1248225043231667,2,13,628.0,21899.0,17097.0,32768.0,0.0,72.0,65536.0,0.0,0.0,0.0,0.0,0.0,587815.0,0.0,0.0,131072.0,0.0,0.0,0.0,128.0,524288.0 +2,0,1,15744,15744,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248225043788046,1248225043804766,3,13,628.0,21865.0,17000.0,32768.0,0.0,72.0,65536.0,0.0,0.0,0.0,0.0,0.0,587705.0,0.0,0.0,131072.0,0.0,0.0,0.0,128.0,524288.0 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/SQ_INST_LEVEL_SMEM.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/SQ_INST_LEVEL_SMEM.csv new file mode 100644 index 0000000000..734bc63e92 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/SQ_INST_LEVEL_SMEM.csv @@ -0,0 +1,4 @@ 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diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/SQ_INST_LEVEL_VMEM.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/SQ_INST_LEVEL_VMEM.csv new file mode 100644 index 0000000000..2d78689306 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/SQ_INST_LEVEL_VMEM.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,CPC_CANE_STALL,CPC_CPC_STAT_STALL,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,GRBM_COUNT,GRBM_SPI_BUSY,SPI_CS0_CRAWLER_STALL,SPI_CS1_CRAWLER_STALL,SPI_CS2_CRAWLER_STALL,SPI_CS3_CRAWLER_STALL,SQ_ACTIVE_INST_VMEM,SQ_INSTS_GDS,SQ_INSTS_LDS_ATOMIC,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VSKIPPED,SQ_INST_LEVEL_VMEM,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TCC_EA0_WRREQ[0],TCC_EA0_WRREQ[10],TCC_EA0_WRREQ[11],TCC_EA0_WRREQ[12],TCC_EA0_WRREQ[14],TCC_EA0_WRREQ[15],TCC_EA0_WRREQ[16],TCC_EA0_WRREQ[17],TCC_EA0_WRREQ[18],TCC_EA0_WRREQ[19],TCC_EA0_WRREQ[1],TCC_EA0_WRREQ[21],TCC_EA0_WRREQ[22],TCC_EA0_WRREQ[23],TCC_EA0_WRREQ[24],TCC_EA0_WRREQ[25],TCC_EA0_WRREQ[26],TCC_EA0_WRREQ[27],TCC_EA0_WRREQ[28],TCC_EA0_WRREQ[2],TCC_EA0_WRREQ[30],TCC_EA0_WRREQ[31],TCC_EA0_WRREQ[32],TCC_EA0_WRREQ[33],TCC_EA0_WRREQ[34],TCC_EA0_WRREQ[35],TCC_EA0_WRREQ[36],TCC_EA0_WRREQ[37],TCC_EA0_WRREQ[38],TCC_EA0_WRREQ[39],TCC_EA0_WRREQ[3],TCC_EA0_WRREQ[41],TCC_EA0_WRREQ[42],TCC_EA0_WRREQ[43],TCC_EA0_WRREQ[44],TCC_EA0_WRREQ[45],TCC_EA0_WRREQ[46],TCC_EA0_WRREQ[47],TCC_EA0_WRREQ[48],TCC_EA0_WRREQ[49],TCC_EA0_WRREQ[50],TCC_EA0_WRREQ[51],TCC_EA0_WRREQ[52],TCC_EA0_WRREQ[53],TCC_EA0_WRREQ[54],TCC_EA0_WRREQ[55],TCC_EA0_WRREQ[57],TCC_EA0_WRREQ[58],TCC_EA0_WRREQ[59],TCC_EA0_WRREQ[5],TCC_EA0_WRREQ[60],TCC_EA0_WRREQ[61],TCC_EA0_WRREQ[62],TCC_EA0_WRREQ[63],TCC_EA0_WRREQ[6],TCC_EA0_WRREQ[7],TCC_EA0_WRREQ[8],TCC_EA0_WRREQ[9],TCC_MISS[0],TCC_MISS[10],TCC_MISS[11],TCC_MISS[12],TCC_MISS[14],TCC_MISS[15],TCC_MISS[16],TCC_MISS[17],TCC_MISS[18],TCC_MISS[19],TCC_MISS[1],TCC_MISS[21],TCC_MISS[22],TCC_MISS[23],TCC_MISS[24],TCC_MISS[25],TCC_MISS[26],TCC_MISS[27],TCC_MISS[28],TCC_MISS[2],TCC_MISS[30],TCC_MISS[31],TCC_MISS[32],TCC_MISS[33],TCC_MISS[34],TCC_MISS[35],TCC_MISS[36],TCC_MISS[37],TCC_MISS[38],TCC_MISS[39],TCC_MISS[3],TCC_MISS[41],TCC_MISS[42],TCC_MISS[43],TCC_MISS[44],TCC_MISS[45],TCC_MISS[46],TCC_MISS[47],TCC_MISS[48],TCC_MISS[49],TCC_MISS[50],TCC_MISS[51],TCC_MISS[52],TCC_MISS[53],TCC_MISS[54],TCC_MISS[55],TCC_MISS[57],TCC_MISS[58],TCC_MISS[59],TCC_MISS[5],TCC_MISS[60],TCC_MISS[61],TCC_MISS[62],TCC_MISS[63],TCC_MISS[6],TCC_MISS[7],TCC_MISS[8],TCC_MISS[9],TCC_READ[0],TCC_READ[10],TCC_READ[11],TCC_READ[12],TCC_READ[14],TCC_READ[15],TCC_READ[16],TCC_READ[17],TCC_READ[18],TCC_READ[19],TCC_READ[1],TCC_READ[21],TCC_READ[22],TCC_READ[23],TCC_READ[24],TCC_READ[25],TCC_READ[26],TCC_READ[27],TCC_READ[28],TCC_READ[2],TCC_READ[30],TCC_READ[31],TCC_READ[32],TCC_READ[33],TCC_READ[34],TCC_READ[35],TCC_READ[36],TCC_READ[37],TCC_READ[38],TCC_READ[39],TCC_READ[3],TCC_READ[41],TCC_READ[42],TCC_READ[43],TCC_READ[44],TCC_READ[45],TCC_READ[46],TCC_READ[47],TCC_READ[48],TCC_READ[49],TCC_READ[50],TCC_READ[51],TCC_READ[52],TCC_READ[53],TCC_READ[54],TCC_READ[55],TCC_READ[57],TCC_READ[58],TCC_READ[59],TCC_READ[5],TCC_READ[60],TCC_READ[61],TCC_READ[62],TCC_READ[63],TCC_READ[6],TCC_READ[7],TCC_READ[8],TCC_READ[9],TCC_WRITE[0],TCC_WRITE[10],TCC_WRITE[11],TCC_WRITE[12],TCC_WRITE[14],TCC_WRITE[15],TCC_WRITE[16],TCC_WRITE[17],TCC_WRITE[18],TCC_WRITE[19],TCC_WRITE[1],TCC_WRITE[21],TCC_WRITE[22],TCC_WRITE[23],TCC_WRITE[24],TCC_WRITE[25],TCC_WRITE[26],TCC_WRITE[27],TCC_WRITE[28],TCC_WRITE[2],TCC_WRITE[30],TCC_WRITE[31],TCC_WRITE[32],TCC_WRITE[33],TCC_WRITE[34],TCC_WRITE[35],TCC_WRITE[36],TCC_WRITE[37],TCC_WRITE[38],TCC_WRITE[39],TCC_WRITE[3],TCC_WRITE[41],TCC_WRITE[42],TCC_WRITE[43],TCC_WRITE[44],TCC_WRITE[45],TCC_WRITE[46],TCC_WRITE[47],TCC_WRITE[48],TCC_WRITE[49],TCC_WRITE[50],TCC_WRITE[51],TCC_WRITE[52],TCC_WRITE[53],TCC_WRITE[54],TCC_WRITE[55],TCC_WRITE[57],TCC_WRITE[58],TCC_WRITE[59],TCC_WRITE[5],TCC_WRITE[60],TCC_WRITE[61],TCC_WRITE[62],TCC_WRITE[63],TCC_WRITE[6],TCC_WRITE[7],TCC_WRITE[8],TCC_WRITE[9],TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCP_LATENCY_sum,TD_COALESCABLE_WAVEFRONT_sum,TD_SPI_STALL_sum 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diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/SQ_LEVEL_WAVES.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/SQ_LEVEL_WAVES.csv new file mode 100644 index 0000000000..bbf437cf1b --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/SQ_LEVEL_WAVES.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,CPC_CPC_TCIU_IDLE,CPC_TG_SEND,CPF_CPF_TCIU_IDLE,SPI_CS0_BUSY,SPI_CS1_BUSY,SPI_CS2_BUSY,SPI_CS3_BUSY,SQ_INSTS_LDS,SQ_INSTS_LDS_LOAD_BANDWIDTH,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_FMA_F16,SQ_LDS_IDX_ACTIVE,SQ_LEVEL_WAVES,SQ_WAVE_CYCLES,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_BUBBLE_sum,TCC_EA0_ATOMIC_LEVEL[0],TCC_EA0_ATOMIC_LEVEL[11],TCC_EA0_ATOMIC_LEVEL[12],TCC_EA0_ATOMIC_LEVEL[13],TCC_EA0_ATOMIC_LEVEL[14],TCC_EA0_ATOMIC_LEVEL[16],TCC_EA0_ATOMIC_LEVEL[17],TCC_EA0_ATOMIC_LEVEL[18],TCC_EA0_ATOMIC_LEVEL[19],TCC_EA0_ATOMIC_LEVEL[1],TCC_EA0_ATOMIC_LEVEL[22],TCC_EA0_ATOMIC_LEVEL[23],TCC_EA0_ATOMIC_LEVEL[24],TCC_EA0_ATOMIC_LEVEL[25],TCC_EA0_ATOMIC_LEVEL[27],TCC_EA0_ATOMIC_LEVEL[28],TCC_EA0_ATOMIC_LEVEL[29],TCC_EA0_ATOMIC_LEVEL[2],TCC_EA0_ATOMIC_LEVEL[30],TCC_EA0_ATOMIC_LEVEL[32],TCC_EA0_ATOMIC_LEVEL[33],TCC_EA0_ATOMIC_LEVEL[34],TCC_EA0_ATOMIC_LEVEL[35],TCC_EA0_ATOMIC_LEVEL[37],TCC_EA0_ATOMIC_LEVEL[38],TCC_EA0_ATOMIC_LEVEL[39],TCC_EA0_ATOMIC_LEVEL[3],TCC_EA0_ATOMIC_LEVEL[40],TCC_EA0_ATOMIC_LEVEL[43],TCC_EA0_ATOMIC_LEVEL[44],TCC_EA0_ATOMIC_LEVEL[45],TCC_EA0_ATOMIC_LEVEL[46],TCC_EA0_ATOMIC_LEVEL[48],TCC_EA0_ATOMIC_LEVEL[49],TCC_EA0_ATOMIC_LEVEL[4],TCC_EA0_ATOMIC_LEVEL[50],TCC_EA0_ATOMIC_LEVEL[51],TCC_EA0_ATOMIC_LEVEL[53],TCC_EA0_ATOMIC_LEVEL[54],TCC_EA0_ATOMIC_LEVEL[55],TCC_EA0_ATOMIC_LEVEL[56],TCC_EA0_ATOMIC_LEVEL[58],TCC_EA0_ATOMIC_LEVEL[59],TCC_EA0_ATOMIC_LEVEL[60],TCC_EA0_ATOMIC_LEVEL[61],TCC_EA0_ATOMIC_LEVEL[6],TCC_EA0_ATOMIC_LEVEL[7],TCC_EA0_ATOMIC_LEVEL[8],TCC_EA0_ATOMIC_LEVEL[9],TCC_EA0_RDREQ_LEVEL[0],TCC_EA0_RDREQ_LEVEL[11],TCC_EA0_RDREQ_LEVEL[12],TCC_EA0_RDREQ_LEVEL[13],TCC_EA0_RDREQ_LEVEL[14],TCC_EA0_RDREQ_LEVEL[16],TCC_EA0_RDREQ_LEVEL[17],TCC_EA0_RDREQ_LEVEL[18],TCC_EA0_RDREQ_LEVEL[19],TCC_EA0_RDREQ_LEVEL[1],TCC_EA0_RDREQ_LEVEL[22],TCC_EA0_RDREQ_LEVEL[23],TCC_EA0_RDREQ_LEVEL[24],TCC_EA0_RDREQ_LEVEL[25],TCC_EA0_RDREQ_LEVEL[27],TCC_EA0_RDREQ_LEVEL[28],TCC_EA0_RDREQ_LEVEL[29],TCC_EA0_RDREQ_LEVEL[2],TCC_EA0_RDREQ_LEVEL[30],TCC_EA0_RDREQ_LEVEL[32],TCC_EA0_RDREQ_LEVEL[33],TCC_EA0_RDREQ_LEVEL[34],TCC_EA0_RDREQ_LEVEL[35],TCC_EA0_RDREQ_LEVEL[37],TCC_EA0_RDREQ_LEVEL[38],TCC_EA0_RDREQ_LEVEL[39],TCC_EA0_RDREQ_LEVEL[3],TCC_EA0_RDREQ_LEVEL[40],TCC_EA0_RDREQ_LEVEL[43],TCC_EA0_RDREQ_LEVEL[44],TCC_EA0_RDREQ_LEVEL[45],TCC_EA0_RDREQ_LEVEL[46],TCC_EA0_RDREQ_LEVEL[48],TCC_EA0_RDREQ_LEVEL[49],TCC_EA0_RDREQ_LEVEL[4],TCC_EA0_RDREQ_LEVEL[50],TCC_EA0_RDREQ_LEVEL[51],TCC_EA0_RDREQ_LEVEL[53],TCC_EA0_RDREQ_LEVEL[54],TCC_EA0_RDREQ_LEVEL[55],TCC_EA0_RDREQ_LEVEL[56],TCC_EA0_RDREQ_LEVEL[58],TCC_EA0_RDREQ_LEVEL[59],TCC_EA0_RDREQ_LEVEL[60],TCC_EA0_RDREQ_LEVEL[61],TCC_EA0_RDREQ_LEVEL[6],TCC_EA0_RDREQ_LEVEL[7],TCC_EA0_RDREQ_LEVEL[8],TCC_EA0_RDREQ_LEVEL[9],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_TOO_MANY_EA_WRREQS_STALL[32],TCC_TOO_MANY_EA_WRREQS_STALL[33],TCC_TOO_MANY_EA_WRREQS_STALL[34],TCC_TOO_MANY_EA_WRREQS_STALL[35],TCC_TOO_MANY_EA_WRREQS_STALL[37],TCC_TOO_MANY_EA_WRREQS_STALL[38],TCC_TOO_MANY_EA_WRREQS_STALL[39],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_TOO_MANY_EA_WRREQS_STALL[40],TCC_TOO_MANY_EA_WRREQS_STALL[43],TCC_TOO_MANY_EA_WRREQS_STALL[44],TCC_TOO_MANY_EA_WRREQS_STALL[45],TCC_TOO_MANY_EA_WRREQS_STALL[46],TCC_TOO_MANY_EA_WRREQS_STALL[48],TCC_TOO_MANY_EA_WRREQS_STALL[49],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_TOO_MANY_EA_WRREQS_STALL[50],TCC_TOO_MANY_EA_WRREQS_STALL[51],TCC_TOO_MANY_EA_WRREQS_STALL[53],TCC_TOO_MANY_EA_WRREQS_STALL[54],TCC_TOO_MANY_EA_WRREQS_STALL[55],TCC_TOO_MANY_EA_WRREQS_STALL[56],TCC_TOO_MANY_EA_WRREQS_STALL[58],TCC_TOO_MANY_EA_WRREQS_STALL[59],TCC_TOO_MANY_EA_WRREQS_STALL[60],TCC_TOO_MANY_EA_WRREQS_STALL[61],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCP_GATE_EN2_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TD_TD_BUSY_sum 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int)",1248226695430472,1248226695452112,1,13,76230.0,4096.0,74700.0,146248.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,6406528.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,366347.0,357772.0,356963.0,349090.0,376766.0,737844.0,674665.0,709219.0,678639.0,690427.0,343990.0,324671.0,343293.0,346854.0,381616.0,358883.0,363344.0,703259.0,361957.0,743500.0,699149.0,680115.0,684746.0,338927.0,323941.0,341659.0,662566.0,341692.0,342216.0,362540.0,345698.0,325196.0,670504.0,706680.0,336552.0,689433.0,668474.0,338628.0,351132.0,343139.0,331632.0,367394.0,363667.0,344667.0,324349.0,343830.0,339430.0,345257.0,339020.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,823402.0,131072.0,0.0,524288.0,816209.0 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diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/log.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/log.txt new file mode 100644 index 0000000000..7cde2f83bc --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/log.txt @@ -0,0 +1,195 @@ +[profiling] pre-processing using rocprofv3 profiler +[gen_sysinfo] +Incomplete class definition for gfx950. Expecting populated max_mclk but detected None. +Incomplete class definition for gfx950. Expecting populated cur_mclk but detected None. +Missing specs fields for gfx950 +starting "run_profiling" and about to start rocprof's workload +[profiling] performing profiling using rocprofv3 profiler +Rocprofiler-Compute version: 3.1.0 +Profiler choice: rocprofv3 +Path: /app/workloads/vcopy/MI350 +Target: MI350 +Command: tests/vcopy -n 1048576 -b 256 -i 3 +Kernel Selection: None +Dispatch Selection: None +Hardware Blocks: [] +Report Sections: [] + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Collecting Performance Counters +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.txt +pmc file: SQ_IFETCH_LEVEL.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.yaml -i /app/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] W20250328 22:43:59.475907 140180820113408 tool.cpp:930] Unable to find all counters for agent 1 (gpu-0, gfx950) in [CPC_ME1_BUSY_FOR_PACKET_DECODE, CPC_SYNC_WRREQ_FIFO_BUSY, CPF_CMP_UTCL1_STALL_ON_TRANSLATION, CPF_CPF_STAT_BUSY, GRBM_GUI_ACTIVE, SPI_CS0_WAVE, SPI_CS1_WAVE, SPI_CS2_WAVE, SPI_CS3_WAVE, SQC_DCACHE_HITS, SQC_ICACHE_MISSES, SQC_ICACHE_MISSES_DUPLICATE, SQ_IFETCH_LEVEL, SQ_IFETCH_LEVEL_ACCUM, SQ_INSTS_VALU_FMA_F64, SQ_INSTS_VALU_MFMA_MOPS_I8, SQ_VMEM_WR_TA_DATA_FIFO_FULL, TA_ADDR_STALLED_BY_TC_CYCLES_sum, TA_FLAT_WAVEFRONTS_sum, TCC_EA0_RDREQ[0], TCC_EA0_RDREQ[100], TCC_EA0_RDREQ[101], TCC_EA0_RDREQ[102], TCC_EA0_RDREQ[103], TCC_EA0_RDREQ[104], TCC_EA0_RDREQ[105], TCC_EA0_RDREQ[106], TCC_EA0_RDREQ[107], TCC_EA0_RDREQ[108], TCC_EA0_RDREQ[109], TCC_EA0_RDREQ[10], TCC_EA0_RDREQ[110], TCC_EA0_RDREQ[111], TCC_EA0_RDREQ[112], TCC_EA0_RDREQ[113], TCC_EA0_RDREQ[114], TCC_EA0_RDREQ[115], TCC_EA0_RDREQ[116], TCC_EA0_RDREQ[117], TCC_EA0_RDREQ[118], TCC_EA0_RDREQ[119], TCC_EA0_RDREQ[11], TCC_EA0_RDREQ[120], TCC_EA0_RDREQ[121], TCC_EA0_RDREQ[122], TCC_EA0_RDREQ[123], TCC_EA0_RDREQ[124], TCC_EA0_RDREQ[125], TCC_EA0_RDREQ[126], TCC_EA0_RDREQ[127], TCC_EA0_RDREQ[12], TCC_EA0_RDREQ[13], TCC_EA0_RDREQ[14], TCC_EA0_RDREQ[15], TCC_EA0_RDREQ[16], TCC_EA0_RDREQ[17], TCC_EA0_RDREQ[18], TCC_EA0_RDREQ[19], TCC_EA0_RDREQ[1], TCC_EA0_RDREQ[20], TCC_EA0_RDREQ[21], TCC_EA0_RDREQ[22], TCC_EA0_RDREQ[23], TCC_EA0_RDREQ[24], TCC_EA0_RDREQ[25], TCC_EA0_RDREQ[26], TCC_EA0_RDREQ[27], TCC_EA0_RDREQ[28], TCC_EA0_RDREQ[29], TCC_EA0_RDREQ[2], TCC_EA0_RDREQ[30], TCC_EA0_RDREQ[31], TCC_EA0_RDREQ[32], TCC_EA0_RDREQ[33], TCC_EA0_RDREQ[34], TCC_EA0_RDREQ[35], TCC_EA0_RDREQ[36], TCC_EA0_RDREQ[37], TCC_EA0_RDREQ[38], TCC_EA0_RDREQ[39], TCC_EA0_RDREQ[3], TCC_EA0_RDREQ[40], TCC_EA0_RDREQ[41], TCC_EA0_RDREQ[42], TCC_EA0_RDREQ[43], TCC_EA0_RDREQ[44], TCC_EA0_RDREQ[45], TCC_EA0_RDREQ[46], TCC_EA0_RDREQ[47], TCC_EA0_RDREQ[48], TCC_EA0_RDREQ[49], TCC_EA0_RDREQ[4], TCC_EA0_RDREQ[50], TCC_EA0_RDREQ[51], TCC_EA0_RDREQ[52], TCC_EA0_RDREQ[53], TCC_EA0_RDREQ[54], TCC_EA0_RDREQ[55], TCC_EA0_RDREQ[56], TCC_EA0_RDREQ[57], TCC_EA0_RDREQ[58], TCC_EA0_RDREQ[59], TCC_EA0_RDREQ[5], TCC_EA0_RDREQ[60], TCC_EA0_RDREQ[61], TCC_EA0_RDREQ[62], TCC_EA0_RDREQ[63], TCC_EA0_RDREQ[64], TCC_EA0_RDREQ[65], TCC_EA0_RDREQ[66], TCC_EA0_RDREQ[67], TCC_EA0_RDREQ[68], TCC_EA0_RDREQ[69], TCC_EA0_RDREQ[6], TCC_EA0_RDREQ[70], TCC_EA0_RDREQ[71], TCC_EA0_RDREQ[72], TCC_EA0_RDREQ[73], TCC_EA0_RDREQ[74], TCC_EA0_RDREQ[75], TCC_EA0_RDREQ[76], TCC_EA0_RDREQ[77], TCC_EA0_RDREQ[78], TCC_EA0_RDREQ[79], TCC_EA0_RDREQ[7], TCC_EA0_RDREQ[80], TCC_EA0_RDREQ[81], TCC_EA0_RDREQ[82], TCC_EA0_RDREQ[83], TCC_EA0_RDREQ[84], TCC_EA0_RDREQ[85], TCC_EA0_RDREQ[86], TCC_EA0_RDREQ[87], TCC_EA0_RDREQ[88], TCC_EA0_RDREQ[89], TCC_EA0_RDREQ[8], TCC_EA0_RDREQ[90], TCC_EA0_RDREQ[91], TCC_EA0_RDREQ[92], TCC_EA0_RDREQ[93], TCC_EA0_RDREQ[94], TCC_EA0_RDREQ[95], TCC_EA0_RDREQ[96], TCC_EA0_RDREQ[97], TCC_EA0_RDREQ[98], TCC_EA0_RDREQ[99], TCC_EA0_RDREQ[9], TCC_EA0_WRREQ_LEVEL[0], TCC_EA0_WRREQ_LEVEL[100], TCC_EA0_WRREQ_LEVEL[101], TCC_EA0_WRREQ_LEVEL[102], TCC_EA0_WRREQ_LEVEL[103], TCC_EA0_WRREQ_LEVEL[104], TCC_EA0_WRREQ_LEVEL[105], TCC_EA0_WRREQ_LEVEL[106], TCC_EA0_WRREQ_LEVEL[107], TCC_EA0_WRREQ_LEVEL[108], TCC_EA0_WRREQ_LEVEL[109], TCC_EA0_WRREQ_LEVEL[10], TCC_EA0_WRREQ_LEVEL[110], TCC_EA0_WRREQ_LEVEL[111], TCC_EA0_WRREQ_LEVEL[112], TCC_EA0_WRREQ_LEVEL[113], TCC_EA0_WRREQ_LEVEL[114], TCC_EA0_WRREQ_LEVEL[115], TCC_EA0_WRREQ_LEVEL[116], TCC_EA0_WRREQ_LEVEL[117], TCC_EA0_WRREQ_LEVEL[118], TCC_EA0_WRREQ_LEVEL[119], TCC_EA0_WRREQ_LEVEL[11], TCC_EA0_WRREQ_LEVEL[120], TCC_EA0_WRREQ_LEVEL[121], TCC_EA0_WRREQ_LEVEL[122], TCC_EA0_WRREQ_LEVEL[123], TCC_EA0_WRREQ_LEVEL[124], TCC_EA0_WRREQ_LEVEL[125], TCC_EA0_WRREQ_LEVEL[126], TCC_EA0_WRREQ_LEVEL[127], TCC_EA0_WRREQ_LEVEL[12], TCC_EA0_WRREQ_LEVEL[13], TCC_EA0_WRREQ_LEVEL[14], TCC_EA0_WRREQ_LEVEL[15], TCC_EA0_WRREQ_LEVEL[16], TCC_EA0_WRREQ_LEVEL[17], TCC_EA0_WRREQ_LEVEL[18], TCC_EA0_WRREQ_LEVEL[19], TCC_EA0_WRREQ_LEVEL[1], TCC_EA0_WRREQ_LEVEL[20], TCC_EA0_WRREQ_LEVEL[21], TCC_EA0_WRREQ_LEVEL[22], TCC_EA0_WRREQ_LEVEL[23], TCC_EA0_WRREQ_LEVEL[24], TCC_EA0_WRREQ_LEVEL[25], TCC_EA0_WRREQ_LEVEL[26], TCC_EA0_WRREQ_LEVEL[27], TCC_EA0_WRREQ_LEVEL[28], TCC_EA0_WRREQ_LEVEL[29], TCC_EA0_WRREQ_LEVEL[2], TCC_EA0_WRREQ_LEVEL[30], TCC_EA0_WRREQ_LEVEL[31], TCC_EA0_WRREQ_LEVEL[32], TCC_EA0_WRREQ_LEVEL[33], TCC_EA0_WRREQ_LEVEL[34], TCC_EA0_WRREQ_LEVEL[35], TCC_EA0_WRREQ_LEVEL[36], TCC_EA0_WRREQ_LEVEL[37], TCC_EA0_WRREQ_LEVEL[38], TCC_EA0_WRREQ_LEVEL[39], TCC_EA0_WRREQ_LEVEL[3], TCC_EA0_WRREQ_LEVEL[40], TCC_EA0_WRREQ_LEVEL[41], TCC_EA0_WRREQ_LEVEL[42], TCC_EA0_WRREQ_LEVEL[43], TCC_EA0_WRREQ_LEVEL[44], TCC_EA0_WRREQ_LEVEL[45], TCC_EA0_WRREQ_LEVEL[46], TCC_EA0_WRREQ_LEVEL[47], TCC_EA0_WRREQ_LEVEL[48], TCC_EA0_WRREQ_LEVEL[49], TCC_EA0_WRREQ_LEVEL[4], TCC_EA0_WRREQ_LEVEL[50], TCC_EA0_WRREQ_LEVEL[51], TCC_EA0_WRREQ_LEVEL[52], TCC_EA0_WRREQ_LEVEL[53], TCC_EA0_WRREQ_LEVEL[54], TCC_EA0_WRREQ_LEVEL[55], TCC_EA0_WRREQ_LEVEL[56], TCC_EA0_WRREQ_LEVEL[57], TCC_EA0_WRREQ_LEVEL[58], TCC_EA0_WRREQ_LEVEL[59], TCC_EA0_WRREQ_LEVEL[5], TCC_EA0_WRREQ_LEVEL[60], TCC_EA0_WRREQ_LEVEL[61], TCC_EA0_WRREQ_LEVEL[62], TCC_EA0_WRREQ_LEVEL[63], TCC_EA0_WRREQ_LEVEL[64], TCC_EA0_WRREQ_LEVEL[65], TCC_EA0_WRREQ_LEVEL[66], TCC_EA0_WRREQ_LEVEL[67], TCC_EA0_WRREQ_LEVEL[68], TCC_EA0_WRREQ_LEVEL[69], TCC_EA0_WRREQ_LEVEL[6], TCC_EA0_WRREQ_LEVEL[70], TCC_EA0_WRREQ_LEVEL[71], TCC_EA0_WRREQ_LEVEL[72], TCC_EA0_WRREQ_LEVEL[73], TCC_EA0_WRREQ_LEVEL[74], TCC_EA0_WRREQ_LEVEL[75], TCC_EA0_WRREQ_LEVEL[76], TCC_EA0_WRREQ_LEVEL[77], TCC_EA0_WRREQ_LEVEL[78], TCC_EA0_WRREQ_LEVEL[79], TCC_EA0_WRREQ_LEVEL[7], TCC_EA0_WRREQ_LEVEL[80], TCC_EA0_WRREQ_LEVEL[81], TCC_EA0_WRREQ_LEVEL[82], TCC_EA0_WRREQ_LEVEL[83], TCC_EA0_WRREQ_LEVEL[84], TCC_EA0_WRREQ_LEVEL[85], TCC_EA0_WRREQ_LEVEL[86], TCC_EA0_WRREQ_LEVEL[87], TCC_EA0_WRREQ_LEVEL[88], TCC_EA0_WRREQ_LEVEL[89], TCC_EA0_WRREQ_LEVEL[8], TCC_EA0_WRREQ_LEVEL[90], TCC_EA0_WRREQ_LEVEL[91], TCC_EA0_WRREQ_LEVEL[92], TCC_EA0_WRREQ_LEVEL[93], TCC_EA0_WRREQ_LEVEL[94], TCC_EA0_WRREQ_LEVEL[95], TCC_EA0_WRREQ_LEVEL[96], TCC_EA0_WRREQ_LEVEL[97], TCC_EA0_WRREQ_LEVEL[98], TCC_EA0_WRREQ_LEVEL[99], TCC_EA0_WRREQ_LEVEL[9], TCC_NC_REQ_sum, TCC_REQ[0], TCC_REQ[100], TCC_REQ[101], TCC_REQ[102], TCC_REQ[103], TCC_REQ[104], TCC_REQ[105], TCC_REQ[106], TCC_REQ[107], TCC_REQ[108], TCC_REQ[109], TCC_REQ[10], TCC_REQ[110], TCC_REQ[111], TCC_REQ[112], TCC_REQ[113], TCC_REQ[114], TCC_REQ[115], TCC_REQ[116], TCC_REQ[117], TCC_REQ[118], TCC_REQ[119], TCC_REQ[11], TCC_REQ[120], TCC_REQ[121], TCC_REQ[122], TCC_REQ[123], TCC_REQ[124], TCC_REQ[125], TCC_REQ[126], TCC_REQ[127], TCC_REQ[12], TCC_REQ[13], TCC_REQ[14], TCC_REQ[15], TCC_REQ[16], TCC_REQ[17], TCC_REQ[18], TCC_REQ[19], TCC_REQ[1], TCC_REQ[20], TCC_REQ[21], TCC_REQ[22], TCC_REQ[23], TCC_REQ[24], TCC_REQ[25], TCC_REQ[26], TCC_REQ[27], TCC_REQ[28], TCC_REQ[29], TCC_REQ[2], TCC_REQ[30], TCC_REQ[31], TCC_REQ[32], TCC_REQ[33], TCC_REQ[34], TCC_REQ[35], TCC_REQ[36], TCC_REQ[37], TCC_REQ[38], TCC_REQ[39], TCC_REQ[3], TCC_REQ[40], TCC_REQ[41], TCC_REQ[42], TCC_REQ[43], TCC_REQ[44], TCC_REQ[45], TCC_REQ[46], TCC_REQ[47], TCC_REQ[48], TCC_REQ[49], TCC_REQ[4], TCC_REQ[50], TCC_REQ[51], TCC_REQ[52], TCC_REQ[53], TCC_REQ[54], TCC_REQ[55], TCC_REQ[56], TCC_REQ[57], TCC_REQ[58], TCC_REQ[59], TCC_REQ[5], TCC_REQ[60], TCC_REQ[61], TCC_REQ[62], TCC_REQ[63], TCC_REQ[64], TCC_REQ[65], TCC_REQ[66], TCC_REQ[67], TCC_REQ[68], TCC_REQ[69], TCC_REQ[6], TCC_REQ[70], TCC_REQ[71], TCC_REQ[72], TCC_REQ[73], TCC_REQ[74], TCC_REQ[75], TCC_REQ[76], TCC_REQ[77], TCC_REQ[78], TCC_REQ[79], TCC_REQ[7], TCC_REQ[80], TCC_REQ[81], TCC_REQ[82], TCC_REQ[83], TCC_REQ[84], TCC_REQ[85], TCC_REQ[86], TCC_REQ[87], TCC_REQ[88], TCC_REQ[89], TCC_REQ[8], TCC_REQ[90], TCC_REQ[91], TCC_REQ[92], TCC_REQ[93], TCC_REQ[94], TCC_REQ[95], TCC_REQ[96], TCC_REQ[97], TCC_REQ[98], TCC_REQ[99], TCC_REQ[9], TCP_GATE_EN1_sum, TCP_TCC_NC_ATOMIC_REQ_sum, TCP_TCC_RW_ATOMIC_REQ_sum, TCP_TOTAL_WRITE_sum, TD_ATOMIC_WAVEFRONT_sum, TD_TC_STALL_sum]. Found: [CPC_ME1_BUSY_FOR_PACKET_DECODE, CPC_SYNC_WRREQ_FIFO_BUSY, CPF_CMP_UTCL1_STALL_ON_TRANSLATION, CPF_CPF_STAT_BUSY, GRBM_GUI_ACTIVE, SPI_CS0_WAVE, SPI_CS1_WAVE, SPI_CS2_WAVE, SPI_CS3_WAVE, SQC_DCACHE_HITS, SQC_ICACHE_MISSES, SQC_ICACHE_MISSES_DUPLICATE, SQ_IFETCH_LEVEL, SQ_INSTS_VALU_FMA_F64, SQ_INSTS_VALU_MFMA_MOPS_I8, SQ_VMEM_WR_TA_DATA_FIFO_FULL, TA_ADDR_STALLED_BY_TC_CYCLES_sum, TA_FLAT_WAVEFRONTS_sum, TCC_EA0_RDREQ[0], TCC_EA0_RDREQ[100], TCC_EA0_RDREQ[101], TCC_EA0_RDREQ[102], TCC_EA0_RDREQ[103], TCC_EA0_RDREQ[104], TCC_EA0_RDREQ[105], TCC_EA0_RDREQ[106], TCC_EA0_RDREQ[107], TCC_EA0_RDREQ[108], TCC_EA0_RDREQ[109], TCC_EA0_RDREQ[10], TCC_EA0_RDREQ[110], TCC_EA0_RDREQ[111], TCC_EA0_RDREQ[112], TCC_EA0_RDREQ[113], TCC_EA0_RDREQ[114], TCC_EA0_RDREQ[115], TCC_EA0_RDREQ[116], TCC_EA0_RDREQ[117], TCC_EA0_RDREQ[118], TCC_EA0_RDREQ[119], TCC_EA0_RDREQ[11], TCC_EA0_RDREQ[120], TCC_EA0_RDREQ[121], TCC_EA0_RDREQ[122], TCC_EA0_RDREQ[123], TCC_EA0_RDREQ[124], TCC_EA0_RDREQ[125], TCC_EA0_RDREQ[126], TCC_EA0_RDREQ[127], TCC_EA0_RDREQ[12], TCC_EA0_RDREQ[13], TCC_EA0_RDREQ[14], TCC_EA0_RDREQ[15], TCC_EA0_RDREQ[16], TCC_EA0_RDREQ[17], TCC_EA0_RDREQ[18], TCC_EA0_RDREQ[19], TCC_EA0_RDREQ[1], TCC_EA0_RDREQ[20], TCC_EA0_RDREQ[21], TCC_EA0_RDREQ[22], TCC_EA0_RDREQ[23], TCC_EA0_RDREQ[24], TCC_EA0_RDREQ[25], TCC_EA0_RDREQ[26], TCC_EA0_RDREQ[27], TCC_EA0_RDREQ[28], TCC_EA0_RDREQ[29], TCC_EA0_RDREQ[2], TCC_EA0_RDREQ[30], TCC_EA0_RDREQ[31], TCC_EA0_RDREQ[32], TCC_EA0_RDREQ[33], TCC_EA0_RDREQ[34], TCC_EA0_RDREQ[35], TCC_EA0_RDREQ[36], TCC_EA0_RDREQ[37], TCC_EA0_RDREQ[38], TCC_EA0_RDREQ[39], TCC_EA0_RDREQ[3], TCC_EA0_RDREQ[40], TCC_EA0_RDREQ[41], TCC_EA0_RDREQ[42], TCC_EA0_RDREQ[43], TCC_EA0_RDREQ[44], TCC_EA0_RDREQ[45], TCC_EA0_RDREQ[46], TCC_EA0_RDREQ[47], TCC_EA0_RDREQ[48], TCC_EA0_RDREQ[49], TCC_EA0_RDREQ[4], TCC_EA0_RDREQ[50], TCC_EA0_RDREQ[51], TCC_EA0_RDREQ[52], TCC_EA0_RDREQ[53], TCC_EA0_RDREQ[54], TCC_EA0_RDREQ[55], TCC_EA0_RDREQ[56], TCC_EA0_RDREQ[57], TCC_EA0_RDREQ[58], TCC_EA0_RDREQ[59], TCC_EA0_RDREQ[5], TCC_EA0_RDREQ[60], TCC_EA0_RDREQ[61], TCC_EA0_RDREQ[62], TCC_EA0_RDREQ[63], TCC_EA0_RDREQ[64], TCC_EA0_RDREQ[65], TCC_EA0_RDREQ[66], TCC_EA0_RDREQ[67], TCC_EA0_RDREQ[68], TCC_EA0_RDREQ[69], TCC_EA0_RDREQ[6], TCC_EA0_RDREQ[70], TCC_EA0_RDREQ[71], TCC_EA0_RDREQ[72], TCC_EA0_RDREQ[73], TCC_EA0_RDREQ[74], TCC_EA0_RDREQ[75], TCC_EA0_RDREQ[76], TCC_EA0_RDREQ[77], TCC_EA0_RDREQ[78], TCC_EA0_RDREQ[79], TCC_EA0_RDREQ[7], TCC_EA0_RDREQ[80], TCC_EA0_RDREQ[81], TCC_EA0_RDREQ[82], TCC_EA0_RDREQ[83], TCC_EA0_RDREQ[84], TCC_EA0_RDREQ[85], TCC_EA0_RDREQ[86], TCC_EA0_RDREQ[87], TCC_EA0_RDREQ[88], TCC_EA0_RDREQ[89], TCC_EA0_RDREQ[8], TCC_EA0_RDREQ[90], TCC_EA0_RDREQ[91], TCC_EA0_RDREQ[92], TCC_EA0_RDREQ[93], TCC_EA0_RDREQ[94], TCC_EA0_RDREQ[95], TCC_EA0_RDREQ[96], TCC_EA0_RDREQ[97], TCC_EA0_RDREQ[98], TCC_EA0_RDREQ[99], TCC_EA0_RDREQ[9], TCC_EA0_WRREQ_LEVEL[0], TCC_EA0_WRREQ_LEVEL[100], TCC_EA0_WRREQ_LEVEL[101], TCC_EA0_WRREQ_LEVEL[102], TCC_EA0_WRREQ_LEVEL[103], TCC_EA0_WRREQ_LEVEL[104], TCC_EA0_WRREQ_LEVEL[105], TCC_EA0_WRREQ_LEVEL[106], TCC_EA0_WRREQ_LEVEL[107], TCC_EA0_WRREQ_LEVEL[108], TCC_EA0_WRREQ_LEVEL[109], TCC_EA0_WRREQ_LEVEL[10], TCC_EA0_WRREQ_LEVEL[110], TCC_EA0_WRREQ_LEVEL[111], TCC_EA0_WRREQ_LEVEL[112], TCC_EA0_WRREQ_LEVEL[113], TCC_EA0_WRREQ_LEVEL[114], TCC_EA0_WRREQ_LEVEL[115], TCC_EA0_WRREQ_LEVEL[116], TCC_EA0_WRREQ_LEVEL[117], TCC_EA0_WRREQ_LEVEL[118], TCC_EA0_WRREQ_LEVEL[119], TCC_EA0_WRREQ_LEVEL[11], TCC_EA0_WRREQ_LEVEL[120], TCC_EA0_WRREQ_LEVEL[121], TCC_EA0_WRREQ_LEVEL[122], TCC_EA0_WRREQ_LEVEL[123], TCC_EA0_WRREQ_LEVEL[124], TCC_EA0_WRREQ_LEVEL[125], TCC_EA0_WRREQ_LEVEL[126], TCC_EA0_WRREQ_LEVEL[127], TCC_EA0_WRREQ_LEVEL[12], TCC_EA0_WRREQ_LEVEL[13], TCC_EA0_WRREQ_LEVEL[14], TCC_EA0_WRREQ_LEVEL[15], TCC_EA0_WRREQ_LEVEL[16], TCC_EA0_WRREQ_LEVEL[17], TCC_EA0_WRREQ_LEVEL[18], TCC_EA0_WRREQ_LEVEL[19], TCC_EA0_WRREQ_LEVEL[1], TCC_EA0_WRREQ_LEVEL[20], TCC_EA0_WRREQ_LEVEL[21], TCC_EA0_WRREQ_LEVEL[22], TCC_EA0_WRREQ_LEVEL[23], TCC_EA0_WRREQ_LEVEL[24], TCC_EA0_WRREQ_LEVEL[25], TCC_EA0_WRREQ_LEVEL[26], TCC_EA0_WRREQ_LEVEL[27], TCC_EA0_WRREQ_LEVEL[28], TCC_EA0_WRREQ_LEVEL[29], TCC_EA0_WRREQ_LEVEL[2], TCC_EA0_WRREQ_LEVEL[30], TCC_EA0_WRREQ_LEVEL[31], TCC_EA0_WRREQ_LEVEL[32], TCC_EA0_WRREQ_LEVEL[33], TCC_EA0_WRREQ_LEVEL[34], TCC_EA0_WRREQ_LEVEL[35], TCC_EA0_WRREQ_LEVEL[36], TCC_EA0_WRREQ_LEVEL[37], TCC_EA0_WRREQ_LEVEL[38], TCC_EA0_WRREQ_LEVEL[39], TCC_EA0_WRREQ_LEVEL[3], TCC_EA0_WRREQ_LEVEL[40], TCC_EA0_WRREQ_LEVEL[41], TCC_EA0_WRREQ_LEVEL[42], TCC_EA0_WRREQ_LEVEL[43], TCC_EA0_WRREQ_LEVEL[44], TCC_EA0_WRREQ_LEVEL[45], TCC_EA0_WRREQ_LEVEL[46], TCC_EA0_WRREQ_LEVEL[47], TCC_EA0_WRREQ_LEVEL[48], TCC_EA0_WRREQ_LEVEL[49], TCC_EA0_WRREQ_LEVEL[4], TCC_EA0_WRREQ_LEVEL[50], TCC_EA0_WRREQ_LEVEL[51], TCC_EA0_WRREQ_LEVEL[52], TCC_EA0_WRREQ_LEVEL[53], TCC_EA0_WRREQ_LEVEL[54], TCC_EA0_WRREQ_LEVEL[55], TCC_EA0_WRREQ_LEVEL[56], TCC_EA0_WRREQ_LEVEL[57], TCC_EA0_WRREQ_LEVEL[58], TCC_EA0_WRREQ_LEVEL[59], TCC_EA0_WRREQ_LEVEL[5], TCC_EA0_WRREQ_LEVEL[60], TCC_EA0_WRREQ_LEVEL[61], TCC_EA0_WRREQ_LEVEL[62], TCC_EA0_WRREQ_LEVEL[63], TCC_EA0_WRREQ_LEVEL[64], TCC_EA0_WRREQ_LEVEL[65], TCC_EA0_WRREQ_LEVEL[66], TCC_EA0_WRREQ_LEVEL[67], TCC_EA0_WRREQ_LEVEL[68], TCC_EA0_WRREQ_LEVEL[69], TCC_EA0_WRREQ_LEVEL[6], TCC_EA0_WRREQ_LEVEL[70], TCC_EA0_WRREQ_LEVEL[71], TCC_EA0_WRREQ_LEVEL[72], TCC_EA0_WRREQ_LEVEL[73], TCC_EA0_WRREQ_LEVEL[74], TCC_EA0_WRREQ_LEVEL[75], TCC_EA0_WRREQ_LEVEL[76], TCC_EA0_WRREQ_LEVEL[77], TCC_EA0_WRREQ_LEVEL[78], TCC_EA0_WRREQ_LEVEL[79], TCC_EA0_WRREQ_LEVEL[7], TCC_EA0_WRREQ_LEVEL[80], TCC_EA0_WRREQ_LEVEL[81], TCC_EA0_WRREQ_LEVEL[82], TCC_EA0_WRREQ_LEVEL[83], TCC_EA0_WRREQ_LEVEL[84], TCC_EA0_WRREQ_LEVEL[85], TCC_EA0_WRREQ_LEVEL[86], TCC_EA0_WRREQ_LEVEL[87], TCC_EA0_WRREQ_LEVEL[88], TCC_EA0_WRREQ_LEVEL[89], TCC_EA0_WRREQ_LEVEL[8], TCC_EA0_WRREQ_LEVEL[90], TCC_EA0_WRREQ_LEVEL[91], TCC_EA0_WRREQ_LEVEL[92], TCC_EA0_WRREQ_LEVEL[93], TCC_EA0_WRREQ_LEVEL[94], TCC_EA0_WRREQ_LEVEL[95], TCC_EA0_WRREQ_LEVEL[96], TCC_EA0_WRREQ_LEVEL[97], TCC_EA0_WRREQ_LEVEL[98], TCC_EA0_WRREQ_LEVEL[99], TCC_EA0_WRREQ_LEVEL[9], TCC_NC_REQ_sum, TCC_REQ[0], TCC_REQ[100], TCC_REQ[101], TCC_REQ[102], TCC_REQ[103], TCC_REQ[104], TCC_REQ[105], TCC_REQ[106], TCC_REQ[107], TCC_REQ[108], TCC_REQ[109], TCC_REQ[10], TCC_REQ[110], TCC_REQ[111], TCC_REQ[112], TCC_REQ[113], TCC_REQ[114], TCC_REQ[115], TCC_REQ[116], TCC_REQ[117], TCC_REQ[118], TCC_REQ[119], TCC_REQ[11], TCC_REQ[120], TCC_REQ[121], TCC_REQ[122], TCC_REQ[123], TCC_REQ[124], TCC_REQ[125], TCC_REQ[126], TCC_REQ[127], TCC_REQ[12], TCC_REQ[13], TCC_REQ[14], TCC_REQ[15], TCC_REQ[16], TCC_REQ[17], TCC_REQ[18], TCC_REQ[19], TCC_REQ[1], TCC_REQ[20], TCC_REQ[21], TCC_REQ[22], TCC_REQ[23], TCC_REQ[24], TCC_REQ[25], TCC_REQ[26], TCC_REQ[27], TCC_REQ[28], TCC_REQ[29], TCC_REQ[2], TCC_REQ[30], TCC_REQ[31], TCC_REQ[32], TCC_REQ[33], TCC_REQ[34], TCC_REQ[35], TCC_REQ[36], TCC_REQ[37], TCC_REQ[38], TCC_REQ[39], TCC_REQ[3], TCC_REQ[40], TCC_REQ[41], TCC_REQ[42], TCC_REQ[43], TCC_REQ[44], TCC_REQ[45], TCC_REQ[46], TCC_REQ[47], TCC_REQ[48], TCC_REQ[49], TCC_REQ[4], TCC_REQ[50], TCC_REQ[51], TCC_REQ[52], TCC_REQ[53], TCC_REQ[54], TCC_REQ[55], TCC_REQ[56], TCC_REQ[57], TCC_REQ[58], TCC_REQ[59], TCC_REQ[5], TCC_REQ[60], TCC_REQ[61], TCC_REQ[62], TCC_REQ[63], TCC_REQ[64], TCC_REQ[65], TCC_REQ[66], TCC_REQ[67], TCC_REQ[68], TCC_REQ[69], TCC_REQ[6], TCC_REQ[70], TCC_REQ[71], TCC_REQ[72], TCC_REQ[73], TCC_REQ[74], TCC_REQ[75], TCC_REQ[76], TCC_REQ[77], TCC_REQ[78], TCC_REQ[79], TCC_REQ[7], TCC_REQ[80], TCC_REQ[81], TCC_REQ[82], TCC_REQ[83], TCC_REQ[84], TCC_REQ[85], TCC_REQ[86], TCC_REQ[87], TCC_REQ[88], TCC_REQ[89], TCC_REQ[8], TCC_REQ[90], TCC_REQ[91], TCC_REQ[92], TCC_REQ[93], TCC_REQ[94], TCC_REQ[95], TCC_REQ[96], TCC_REQ[97], TCC_REQ[98], TCC_REQ[99], TCC_REQ[9], TCP_GATE_EN1_sum, TCP_TCC_NC_ATOMIC_REQ_sum, TCP_TCC_RW_ATOMIC_REQ_sum, TCP_TOTAL_WRITE_sum, TD_ATOMIC_WAVEFRONT_sum, TD_TC_STALL_sum] + |-> [rocprofv3] E20250328 22:43:59.489465 140180820113408 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15737_kernel_trace.csv + |-> [rocprofv3] E20250328 22:43:59.496185 140180820113408 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15737_counter_collection.csv + |-> [rocprofv3] E20250328 22:43:59.499819 140180820113408 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15737_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.txt, the time it takes was 0 m 0.5342490673065186 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.txt is 0 m 0.5495765209197998 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.txt +pmc file: SQ_INST_LEVEL_LDS.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.yaml -i /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] W20250328 22:44:00.019005 139673533200384 tool.cpp:930] Unable to find all counters for agent 1 (gpu-0, gfx950) in [CPC_CPC_TCIU_BUSY, CPC_ME1_DC0_SPI_BUSY, SPI_RA_REQ_NO_ALLOC_CSN, SPI_VWC0_VDATA_VALID_WR, SQC_DCACHE_ATOMIC, SQC_DCACHE_MISSES, SQC_ICACHE_REQ, SQC_TC_STALL, SQ_INSTS_VALU_MUL_F16, SQ_INST_LEVEL_LDS, SQ_INST_LEVEL_LDS_ACCUM, SQ_WAVES_SAVED, TA_BUFFER_WRITE_WAVEFRONTS_sum, TA_TA_BUSY_sum, TCC_ATOMIC_sum, TCC_EA0_ATOMIC_LEVEL_sum, TCC_EA0_WRREQ_sum, TCC_TOO_MANY_EA_WRREQS_STALL_sum, TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum, TCP_TCC_ATOMIC_WITH_RET_REQ_sum, TCP_TOTAL_WRITEBACK_INVALIDATES_sum, TCP_UTCL1_REQUEST_sum]. Found: [CPC_CPC_TCIU_BUSY, CPC_ME1_DC0_SPI_BUSY, SPI_RA_REQ_NO_ALLOC_CSN, SPI_VWC0_VDATA_VALID_WR, SQC_DCACHE_ATOMIC, SQC_DCACHE_MISSES, SQC_ICACHE_REQ, SQC_TC_STALL, SQ_INSTS_VALU_MUL_F16, SQ_INST_LEVEL_LDS, SQ_WAVES_SAVED, TA_BUFFER_WRITE_WAVEFRONTS_sum, TA_TA_BUSY_sum, TCC_ATOMIC_sum, TCC_EA0_ATOMIC_LEVEL_sum, TCC_EA0_WRREQ_sum, TCC_TOO_MANY_EA_WRREQS_STALL_sum, TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum, TCP_TCC_ATOMIC_WITH_RET_REQ_sum, TCP_TOTAL_WRITEBACK_INVALIDATES_sum, TCP_UTCL1_REQUEST_sum] + |-> [rocprofv3] E20250328 22:44:00.029844 139673533200384 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15744_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:00.036337 139673533200384 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15744_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:00.039437 139673533200384 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15744_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.txt, the time it takes was 0 m 0.5213537216186523 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.txt is 0 m 0.530348539352417 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt +pmc file: SQ_INST_LEVEL_SMEM.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.yaml -i /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] W20250328 22:44:00.560194 140472799942656 tool.cpp:930] Unable to find all counters for agent 1 (gpu-0, gfx950) in [CPC_CPC_STAT_BUSY, CPC_CPC_STAT_IDLE, CPF_CPF_STAT_IDLE, CPF_CPF_STAT_STALL, SPI_CSQ_P0_OCCUPANCY, SPI_CSQ_P1_OCCUPANCY, SPI_CSQ_P2_OCCUPANCY, SPI_CSQ_P3_OCCUPANCY, SPI_RA_SGPR_SIMD_FULL_CSN, SQC_DCACHE_REQ_READ_16, SQ_BUSY_CU_CYCLES, SQ_INSTS_LDS_LOAD, SQ_INSTS_LDS_STORE, SQ_INSTS_VALU_MUL_F64, SQ_INST_LEVEL_SMEM, SQ_INST_LEVEL_SMEM_ACCUM, SQ_LDS_CMD_FIFO_FULL, TA_BUFFER_TOTAL_CYCLES_sum, TA_FLAT_READ_WAVEFRONTS_sum, TCC_ATOMIC[0], TCC_ATOMIC[100], TCC_ATOMIC[101], TCC_ATOMIC[102], TCC_ATOMIC[103], TCC_ATOMIC[104], TCC_ATOMIC[105], TCC_ATOMIC[106], TCC_ATOMIC[107], TCC_ATOMIC[108], TCC_ATOMIC[109], TCC_ATOMIC[10], TCC_ATOMIC[110], TCC_ATOMIC[111], TCC_ATOMIC[112], TCC_ATOMIC[113], TCC_ATOMIC[114], TCC_ATOMIC[115], TCC_ATOMIC[116], TCC_ATOMIC[117], TCC_ATOMIC[118], TCC_ATOMIC[119], TCC_ATOMIC[11], TCC_ATOMIC[120], TCC_ATOMIC[121], TCC_ATOMIC[122], TCC_ATOMIC[123], TCC_ATOMIC[124], TCC_ATOMIC[125], TCC_ATOMIC[126], TCC_ATOMIC[127], TCC_ATOMIC[12], TCC_ATOMIC[13], TCC_ATOMIC[14], TCC_ATOMIC[15], TCC_ATOMIC[16], TCC_ATOMIC[17], TCC_ATOMIC[18], TCC_ATOMIC[19], TCC_ATOMIC[1], TCC_ATOMIC[20], TCC_ATOMIC[21], TCC_ATOMIC[22], TCC_ATOMIC[23], TCC_ATOMIC[24], TCC_ATOMIC[25], TCC_ATOMIC[26], TCC_ATOMIC[27], TCC_ATOMIC[28], TCC_ATOMIC[29], TCC_ATOMIC[2], TCC_ATOMIC[30], TCC_ATOMIC[31], TCC_ATOMIC[32], TCC_ATOMIC[33], TCC_ATOMIC[34], TCC_ATOMIC[35], TCC_ATOMIC[36], TCC_ATOMIC[37], TCC_ATOMIC[38], TCC_ATOMIC[39], TCC_ATOMIC[3], TCC_ATOMIC[40], TCC_ATOMIC[41], TCC_ATOMIC[42], TCC_ATOMIC[43], TCC_ATOMIC[44], TCC_ATOMIC[45], TCC_ATOMIC[46], TCC_ATOMIC[47], TCC_ATOMIC[48], TCC_ATOMIC[49], TCC_ATOMIC[4], TCC_ATOMIC[50], TCC_ATOMIC[51], TCC_ATOMIC[52], TCC_ATOMIC[53], TCC_ATOMIC[54], TCC_ATOMIC[55], TCC_ATOMIC[56], TCC_ATOMIC[57], TCC_ATOMIC[58], TCC_ATOMIC[59], TCC_ATOMIC[5], TCC_ATOMIC[60], TCC_ATOMIC[61], TCC_ATOMIC[62], TCC_ATOMIC[63], TCC_ATOMIC[64], TCC_ATOMIC[65], TCC_ATOMIC[66], TCC_ATOMIC[67], TCC_ATOMIC[68], TCC_ATOMIC[69], TCC_ATOMIC[6], TCC_ATOMIC[70], TCC_ATOMIC[71], TCC_ATOMIC[72], TCC_ATOMIC[73], TCC_ATOMIC[74], TCC_ATOMIC[75], TCC_ATOMIC[76], TCC_ATOMIC[77], TCC_ATOMIC[78], TCC_ATOMIC[79], TCC_ATOMIC[7], TCC_ATOMIC[80], TCC_ATOMIC[81], TCC_ATOMIC[82], TCC_ATOMIC[83], TCC_ATOMIC[84], TCC_ATOMIC[85], TCC_ATOMIC[86], TCC_ATOMIC[87], TCC_ATOMIC[88], TCC_ATOMIC[89], TCC_ATOMIC[8], TCC_ATOMIC[90], TCC_ATOMIC[91], TCC_ATOMIC[92], TCC_ATOMIC[93], TCC_ATOMIC[94], TCC_ATOMIC[95], TCC_ATOMIC[96], TCC_ATOMIC[97], TCC_ATOMIC[98], TCC_ATOMIC[99], TCC_ATOMIC[9], TCC_BUBBLE[0], TCC_BUBBLE[100], TCC_BUBBLE[101], TCC_BUBBLE[102], TCC_BUBBLE[103], TCC_BUBBLE[104], TCC_BUBBLE[105], TCC_BUBBLE[106], TCC_BUBBLE[107], TCC_BUBBLE[108], TCC_BUBBLE[109], TCC_BUBBLE[10], TCC_BUBBLE[110], TCC_BUBBLE[111], TCC_BUBBLE[112], TCC_BUBBLE[113], TCC_BUBBLE[114], TCC_BUBBLE[115], TCC_BUBBLE[116], TCC_BUBBLE[117], TCC_BUBBLE[118], TCC_BUBBLE[119], TCC_BUBBLE[11], TCC_BUBBLE[120], TCC_BUBBLE[121], TCC_BUBBLE[122], TCC_BUBBLE[123], TCC_BUBBLE[124], TCC_BUBBLE[125], TCC_BUBBLE[126], TCC_BUBBLE[127], TCC_BUBBLE[12], TCC_BUBBLE[13], TCC_BUBBLE[14], TCC_BUBBLE[15], TCC_BUBBLE[16], TCC_BUBBLE[17], TCC_BUBBLE[18], TCC_BUBBLE[19], TCC_BUBBLE[1], TCC_BUBBLE[20], TCC_BUBBLE[21], TCC_BUBBLE[22], TCC_BUBBLE[23], TCC_BUBBLE[24], TCC_BUBBLE[25], TCC_BUBBLE[26], TCC_BUBBLE[27], TCC_BUBBLE[28], TCC_BUBBLE[29], TCC_BUBBLE[2], TCC_BUBBLE[30], TCC_BUBBLE[31], TCC_BUBBLE[32], TCC_BUBBLE[33], TCC_BUBBLE[34], TCC_BUBBLE[35], TCC_BUBBLE[36], TCC_BUBBLE[37], TCC_BUBBLE[38], TCC_BUBBLE[39], TCC_BUBBLE[3], TCC_BUBBLE[40], TCC_BUBBLE[41], TCC_BUBBLE[42], TCC_BUBBLE[43], TCC_BUBBLE[44], TCC_BUBBLE[45], TCC_BUBBLE[46], TCC_BUBBLE[47], TCC_BUBBLE[48], TCC_BUBBLE[49], TCC_BUBBLE[4], TCC_BUBBLE[50], TCC_BUBBLE[51], TCC_BUBBLE[52], TCC_BUBBLE[53], TCC_BUBBLE[54], TCC_BUBBLE[55], TCC_BUBBLE[56], TCC_BUBBLE[57], TCC_BUBBLE[58], TCC_BUBBLE[59], TCC_BUBBLE[5], TCC_BUBBLE[60], TCC_BUBBLE[61], TCC_BUBBLE[62], TCC_BUBBLE[63], TCC_BUBBLE[64], TCC_BUBBLE[65], TCC_BUBBLE[66], TCC_BUBBLE[67], TCC_BUBBLE[68], TCC_BUBBLE[69], TCC_BUBBLE[6], TCC_BUBBLE[70], TCC_BUBBLE[71], TCC_BUBBLE[72], TCC_BUBBLE[73], TCC_BUBBLE[74], TCC_BUBBLE[75], TCC_BUBBLE[76], TCC_BUBBLE[77], TCC_BUBBLE[78], TCC_BUBBLE[79], TCC_BUBBLE[7], TCC_BUBBLE[80], TCC_BUBBLE[81], TCC_BUBBLE[82], TCC_BUBBLE[83], TCC_BUBBLE[84], TCC_BUBBLE[85], TCC_BUBBLE[86], TCC_BUBBLE[87], TCC_BUBBLE[88], TCC_BUBBLE[89], TCC_BUBBLE[8], TCC_BUBBLE[90], TCC_BUBBLE[91], TCC_BUBBLE[92], TCC_BUBBLE[93], TCC_BUBBLE[94], TCC_BUBBLE[95], TCC_BUBBLE[96], TCC_BUBBLE[97], TCC_BUBBLE[98], TCC_BUBBLE[99], TCC_BUBBLE[9], TCC_EA0_ATOMIC[0], TCC_EA0_ATOMIC[100], TCC_EA0_ATOMIC[101], TCC_EA0_ATOMIC[102], TCC_EA0_ATOMIC[103], TCC_EA0_ATOMIC[104], TCC_EA0_ATOMIC[105], TCC_EA0_ATOMIC[106], TCC_EA0_ATOMIC[107], TCC_EA0_ATOMIC[108], TCC_EA0_ATOMIC[109], TCC_EA0_ATOMIC[10], TCC_EA0_ATOMIC[110], TCC_EA0_ATOMIC[111], TCC_EA0_ATOMIC[112], TCC_EA0_ATOMIC[113], TCC_EA0_ATOMIC[114], TCC_EA0_ATOMIC[115], TCC_EA0_ATOMIC[116], TCC_EA0_ATOMIC[117], TCC_EA0_ATOMIC[118], TCC_EA0_ATOMIC[119], TCC_EA0_ATOMIC[11], TCC_EA0_ATOMIC[120], TCC_EA0_ATOMIC[121], TCC_EA0_ATOMIC[122], TCC_EA0_ATOMIC[123], TCC_EA0_ATOMIC[124], TCC_EA0_ATOMIC[125], TCC_EA0_ATOMIC[126], TCC_EA0_ATOMIC[127], TCC_EA0_ATOMIC[12], TCC_EA0_ATOMIC[13], TCC_EA0_ATOMIC[14], TCC_EA0_ATOMIC[15], TCC_EA0_ATOMIC[16], TCC_EA0_ATOMIC[17], TCC_EA0_ATOMIC[18], TCC_EA0_ATOMIC[19], TCC_EA0_ATOMIC[1], TCC_EA0_ATOMIC[20], TCC_EA0_ATOMIC[21], TCC_EA0_ATOMIC[22], TCC_EA0_ATOMIC[23], TCC_EA0_ATOMIC[24], TCC_EA0_ATOMIC[25], TCC_EA0_ATOMIC[26], TCC_EA0_ATOMIC[27], TCC_EA0_ATOMIC[28], TCC_EA0_ATOMIC[29], TCC_EA0_ATOMIC[2], TCC_EA0_ATOMIC[30], TCC_EA0_ATOMIC[31], TCC_EA0_ATOMIC[32], TCC_EA0_ATOMIC[33], TCC_EA0_ATOMIC[34], TCC_EA0_ATOMIC[35], TCC_EA0_ATOMIC[36], TCC_EA0_ATOMIC[37], TCC_EA0_ATOMIC[38], TCC_EA0_ATOMIC[39], TCC_EA0_ATOMIC[3], TCC_EA0_ATOMIC[40], TCC_EA0_ATOMIC[41], TCC_EA0_ATOMIC[42], TCC_EA0_ATOMIC[43], TCC_EA0_ATOMIC[44], TCC_EA0_ATOMIC[45], TCC_EA0_ATOMIC[46], TCC_EA0_ATOMIC[47], TCC_EA0_ATOMIC[48], TCC_EA0_ATOMIC[49], TCC_EA0_ATOMIC[4], TCC_EA0_ATOMIC[50], TCC_EA0_ATOMIC[51], TCC_EA0_ATOMIC[52], TCC_EA0_ATOMIC[53], TCC_EA0_ATOMIC[54], TCC_EA0_ATOMIC[55], TCC_EA0_ATOMIC[56], TCC_EA0_ATOMIC[57], TCC_EA0_ATOMIC[58], TCC_EA0_ATOMIC[59], TCC_EA0_ATOMIC[5], TCC_EA0_ATOMIC[60], TCC_EA0_ATOMIC[61], TCC_EA0_ATOMIC[62], TCC_EA0_ATOMIC[63], TCC_EA0_ATOMIC[64], TCC_EA0_ATOMIC[65], TCC_EA0_ATOMIC[66], TCC_EA0_ATOMIC[67], TCC_EA0_ATOMIC[68], TCC_EA0_ATOMIC[69], TCC_EA0_ATOMIC[6], TCC_EA0_ATOMIC[70], TCC_EA0_ATOMIC[71], TCC_EA0_ATOMIC[72], TCC_EA0_ATOMIC[73], TCC_EA0_ATOMIC[74], TCC_EA0_ATOMIC[75], TCC_EA0_ATOMIC[76], TCC_EA0_ATOMIC[77], TCC_EA0_ATOMIC[78], TCC_EA0_ATOMIC[79], TCC_EA0_ATOMIC[7], TCC_EA0_ATOMIC[80], TCC_EA0_ATOMIC[81], TCC_EA0_ATOMIC[82], TCC_EA0_ATOMIC[83], TCC_EA0_ATOMIC[84], TCC_EA0_ATOMIC[85], TCC_EA0_ATOMIC[86], TCC_EA0_ATOMIC[87], TCC_EA0_ATOMIC[88], TCC_EA0_ATOMIC[89], TCC_EA0_ATOMIC[8], TCC_EA0_ATOMIC[90], TCC_EA0_ATOMIC[91], TCC_EA0_ATOMIC[92], TCC_EA0_ATOMIC[93], TCC_EA0_ATOMIC[94], TCC_EA0_ATOMIC[95], TCC_EA0_ATOMIC[96], TCC_EA0_ATOMIC[97], TCC_EA0_ATOMIC[98], TCC_EA0_ATOMIC[99], TCC_EA0_ATOMIC[9], TCC_HIT[0], TCC_HIT[100], TCC_HIT[101], TCC_HIT[102], TCC_HIT[103], TCC_HIT[104], TCC_HIT[105], TCC_HIT[106], TCC_HIT[107], TCC_HIT[108], TCC_HIT[109], TCC_HIT[10], TCC_HIT[110], TCC_HIT[111], TCC_HIT[112], TCC_HIT[113], TCC_HIT[114], TCC_HIT[115], TCC_HIT[116], TCC_HIT[117], TCC_HIT[118], TCC_HIT[119], TCC_HIT[11], TCC_HIT[120], TCC_HIT[121], TCC_HIT[122], TCC_HIT[123], TCC_HIT[124], TCC_HIT[125], TCC_HIT[126], TCC_HIT[127], TCC_HIT[12], TCC_HIT[13], TCC_HIT[14], TCC_HIT[15], TCC_HIT[16], TCC_HIT[17], TCC_HIT[18], TCC_HIT[19], TCC_HIT[1], TCC_HIT[20], TCC_HIT[21], TCC_HIT[22], TCC_HIT[23], TCC_HIT[24], TCC_HIT[25], TCC_HIT[26], TCC_HIT[27], TCC_HIT[28], TCC_HIT[29], TCC_HIT[2], TCC_HIT[30], TCC_HIT[31], TCC_HIT[32], TCC_HIT[33], TCC_HIT[34], TCC_HIT[35], TCC_HIT[36], TCC_HIT[37], TCC_HIT[38], TCC_HIT[39], TCC_HIT[3], TCC_HIT[40], TCC_HIT[41], TCC_HIT[42], TCC_HIT[43], TCC_HIT[44], TCC_HIT[45], TCC_HIT[46], TCC_HIT[47], TCC_HIT[48], TCC_HIT[49], TCC_HIT[4], TCC_HIT[50], TCC_HIT[51], TCC_HIT[52], TCC_HIT[53], TCC_HIT[54], TCC_HIT[55], TCC_HIT[56], TCC_HIT[57], TCC_HIT[58], TCC_HIT[59], TCC_HIT[5], TCC_HIT[60], TCC_HIT[61], TCC_HIT[62], TCC_HIT[63], TCC_HIT[64], TCC_HIT[65], TCC_HIT[66], TCC_HIT[67], TCC_HIT[68], TCC_HIT[69], TCC_HIT[6], TCC_HIT[70], TCC_HIT[71], TCC_HIT[72], TCC_HIT[73], TCC_HIT[74], TCC_HIT[75], TCC_HIT[76], TCC_HIT[77], TCC_HIT[78], TCC_HIT[79], TCC_HIT[7], TCC_HIT[80], TCC_HIT[81], TCC_HIT[82], TCC_HIT[83], TCC_HIT[84], TCC_HIT[85], TCC_HIT[86], TCC_HIT[87], TCC_HIT[88], TCC_HIT[89], TCC_HIT[8], TCC_HIT[90], TCC_HIT[91], TCC_HIT[92], TCC_HIT[93], TCC_HIT[94], TCC_HIT[95], TCC_HIT[96], TCC_HIT[97], TCC_HIT[98], TCC_HIT[99], TCC_HIT[9], TCP_TA_TCP_STATE_READ_sum, TCP_TCC_UC_READ_REQ_sum, TCP_TOTAL_ATOMIC_WITH_RET_sum, TCP_UTCL1_TRANSLATION_HIT_sum, TD_LOAD_WAVEFRONT_sum, TD_STORE_WAVEFRONT_sum]. Found: [CPC_CPC_STAT_BUSY, CPC_CPC_STAT_IDLE, CPF_CPF_STAT_IDLE, CPF_CPF_STAT_STALL, SPI_CSQ_P0_OCCUPANCY, SPI_CSQ_P1_OCCUPANCY, SPI_CSQ_P2_OCCUPANCY, SPI_CSQ_P3_OCCUPANCY, SPI_RA_SGPR_SIMD_FULL_CSN, SQC_DCACHE_REQ_READ_16, SQ_BUSY_CU_CYCLES, SQ_INSTS_LDS_LOAD, SQ_INSTS_LDS_STORE, SQ_INSTS_VALU_MUL_F64, SQ_INST_LEVEL_SMEM, SQ_LDS_CMD_FIFO_FULL, TA_BUFFER_TOTAL_CYCLES_sum, TA_FLAT_READ_WAVEFRONTS_sum, TCC_ATOMIC[0], TCC_ATOMIC[100], TCC_ATOMIC[101], TCC_ATOMIC[102], TCC_ATOMIC[103], TCC_ATOMIC[104], TCC_ATOMIC[105], TCC_ATOMIC[106], TCC_ATOMIC[107], TCC_ATOMIC[108], TCC_ATOMIC[109], TCC_ATOMIC[10], TCC_ATOMIC[110], TCC_ATOMIC[111], TCC_ATOMIC[112], TCC_ATOMIC[113], TCC_ATOMIC[114], TCC_ATOMIC[115], TCC_ATOMIC[116], TCC_ATOMIC[117], TCC_ATOMIC[118], TCC_ATOMIC[119], TCC_ATOMIC[11], TCC_ATOMIC[120], TCC_ATOMIC[121], TCC_ATOMIC[122], TCC_ATOMIC[123], TCC_ATOMIC[124], TCC_ATOMIC[125], TCC_ATOMIC[126], TCC_ATOMIC[127], TCC_ATOMIC[12], TCC_ATOMIC[13], TCC_ATOMIC[14], TCC_ATOMIC[15], TCC_ATOMIC[16], TCC_ATOMIC[17], TCC_ATOMIC[18], TCC_ATOMIC[19], TCC_ATOMIC[1], TCC_ATOMIC[20], TCC_ATOMIC[21], TCC_ATOMIC[22], TCC_ATOMIC[23], TCC_ATOMIC[24], TCC_ATOMIC[25], TCC_ATOMIC[26], TCC_ATOMIC[27], TCC_ATOMIC[28], TCC_ATOMIC[29], TCC_ATOMIC[2], TCC_ATOMIC[30], TCC_ATOMIC[31], TCC_ATOMIC[32], TCC_ATOMIC[33], TCC_ATOMIC[34], TCC_ATOMIC[35], TCC_ATOMIC[36], TCC_ATOMIC[37], TCC_ATOMIC[38], TCC_ATOMIC[39], TCC_ATOMIC[3], TCC_ATOMIC[40], TCC_ATOMIC[41], TCC_ATOMIC[42], TCC_ATOMIC[43], TCC_ATOMIC[44], TCC_ATOMIC[45], TCC_ATOMIC[46], TCC_ATOMIC[47], TCC_ATOMIC[48], TCC_ATOMIC[49], TCC_ATOMIC[4], TCC_ATOMIC[50], TCC_ATOMIC[51], TCC_ATOMIC[52], TCC_ATOMIC[53], TCC_ATOMIC[54], TCC_ATOMIC[55], TCC_ATOMIC[56], TCC_ATOMIC[57], TCC_ATOMIC[58], TCC_ATOMIC[59], TCC_ATOMIC[5], TCC_ATOMIC[60], TCC_ATOMIC[61], TCC_ATOMIC[62], TCC_ATOMIC[63], TCC_ATOMIC[64], TCC_ATOMIC[65], TCC_ATOMIC[66], TCC_ATOMIC[67], TCC_ATOMIC[68], TCC_ATOMIC[69], TCC_ATOMIC[6], TCC_ATOMIC[70], TCC_ATOMIC[71], TCC_ATOMIC[72], TCC_ATOMIC[73], TCC_ATOMIC[74], TCC_ATOMIC[75], TCC_ATOMIC[76], TCC_ATOMIC[77], TCC_ATOMIC[78], TCC_ATOMIC[79], TCC_ATOMIC[7], TCC_ATOMIC[80], TCC_ATOMIC[81], TCC_ATOMIC[82], TCC_ATOMIC[83], TCC_ATOMIC[84], TCC_ATOMIC[85], TCC_ATOMIC[86], TCC_ATOMIC[87], TCC_ATOMIC[88], TCC_ATOMIC[89], TCC_ATOMIC[8], TCC_ATOMIC[90], TCC_ATOMIC[91], TCC_ATOMIC[92], TCC_ATOMIC[93], TCC_ATOMIC[94], TCC_ATOMIC[95], TCC_ATOMIC[96], TCC_ATOMIC[97], TCC_ATOMIC[98], TCC_ATOMIC[99], TCC_ATOMIC[9], TCC_BUBBLE[0], TCC_BUBBLE[100], TCC_BUBBLE[101], TCC_BUBBLE[102], TCC_BUBBLE[103], TCC_BUBBLE[104], TCC_BUBBLE[105], TCC_BUBBLE[106], TCC_BUBBLE[107], TCC_BUBBLE[108], TCC_BUBBLE[109], TCC_BUBBLE[10], TCC_BUBBLE[110], TCC_BUBBLE[111], TCC_BUBBLE[112], TCC_BUBBLE[113], TCC_BUBBLE[114], TCC_BUBBLE[115], TCC_BUBBLE[116], TCC_BUBBLE[117], TCC_BUBBLE[118], TCC_BUBBLE[119], TCC_BUBBLE[11], TCC_BUBBLE[120], TCC_BUBBLE[121], TCC_BUBBLE[122], TCC_BUBBLE[123], TCC_BUBBLE[124], TCC_BUBBLE[125], TCC_BUBBLE[126], TCC_BUBBLE[127], TCC_BUBBLE[12], TCC_BUBBLE[13], TCC_BUBBLE[14], TCC_BUBBLE[15], TCC_BUBBLE[16], TCC_BUBBLE[17], TCC_BUBBLE[18], TCC_BUBBLE[19], TCC_BUBBLE[1], TCC_BUBBLE[20], TCC_BUBBLE[21], TCC_BUBBLE[22], TCC_BUBBLE[23], TCC_BUBBLE[24], TCC_BUBBLE[25], TCC_BUBBLE[26], TCC_BUBBLE[27], TCC_BUBBLE[28], TCC_BUBBLE[29], TCC_BUBBLE[2], TCC_BUBBLE[30], TCC_BUBBLE[31], TCC_BUBBLE[32], TCC_BUBBLE[33], TCC_BUBBLE[34], TCC_BUBBLE[35], TCC_BUBBLE[36], TCC_BUBBLE[37], TCC_BUBBLE[38], TCC_BUBBLE[39], TCC_BUBBLE[3], TCC_BUBBLE[40], TCC_BUBBLE[41], TCC_BUBBLE[42], TCC_BUBBLE[43], TCC_BUBBLE[44], TCC_BUBBLE[45], TCC_BUBBLE[46], TCC_BUBBLE[47], TCC_BUBBLE[48], TCC_BUBBLE[49], TCC_BUBBLE[4], TCC_BUBBLE[50], TCC_BUBBLE[51], TCC_BUBBLE[52], TCC_BUBBLE[53], TCC_BUBBLE[54], TCC_BUBBLE[55], TCC_BUBBLE[56], TCC_BUBBLE[57], TCC_BUBBLE[58], TCC_BUBBLE[59], TCC_BUBBLE[5], TCC_BUBBLE[60], TCC_BUBBLE[61], TCC_BUBBLE[62], TCC_BUBBLE[63], TCC_BUBBLE[64], TCC_BUBBLE[65], TCC_BUBBLE[66], TCC_BUBBLE[67], TCC_BUBBLE[68], TCC_BUBBLE[69], TCC_BUBBLE[6], TCC_BUBBLE[70], TCC_BUBBLE[71], TCC_BUBBLE[72], TCC_BUBBLE[73], TCC_BUBBLE[74], TCC_BUBBLE[75], TCC_BUBBLE[76], TCC_BUBBLE[77], TCC_BUBBLE[78], TCC_BUBBLE[79], TCC_BUBBLE[7], TCC_BUBBLE[80], TCC_BUBBLE[81], TCC_BUBBLE[82], TCC_BUBBLE[83], TCC_BUBBLE[84], TCC_BUBBLE[85], TCC_BUBBLE[86], TCC_BUBBLE[87], TCC_BUBBLE[88], TCC_BUBBLE[89], TCC_BUBBLE[8], TCC_BUBBLE[90], TCC_BUBBLE[91], TCC_BUBBLE[92], TCC_BUBBLE[93], TCC_BUBBLE[94], TCC_BUBBLE[95], TCC_BUBBLE[96], TCC_BUBBLE[97], TCC_BUBBLE[98], TCC_BUBBLE[99], TCC_BUBBLE[9], TCC_EA0_ATOMIC[0], TCC_EA0_ATOMIC[100], TCC_EA0_ATOMIC[101], TCC_EA0_ATOMIC[102], TCC_EA0_ATOMIC[103], TCC_EA0_ATOMIC[104], TCC_EA0_ATOMIC[105], TCC_EA0_ATOMIC[106], TCC_EA0_ATOMIC[107], TCC_EA0_ATOMIC[108], TCC_EA0_ATOMIC[109], TCC_EA0_ATOMIC[10], TCC_EA0_ATOMIC[110], TCC_EA0_ATOMIC[111], TCC_EA0_ATOMIC[112], TCC_EA0_ATOMIC[113], TCC_EA0_ATOMIC[114], TCC_EA0_ATOMIC[115], TCC_EA0_ATOMIC[116], TCC_EA0_ATOMIC[117], TCC_EA0_ATOMIC[118], TCC_EA0_ATOMIC[119], TCC_EA0_ATOMIC[11], TCC_EA0_ATOMIC[120], TCC_EA0_ATOMIC[121], TCC_EA0_ATOMIC[122], TCC_EA0_ATOMIC[123], TCC_EA0_ATOMIC[124], TCC_EA0_ATOMIC[125], TCC_EA0_ATOMIC[126], TCC_EA0_ATOMIC[127], TCC_EA0_ATOMIC[12], TCC_EA0_ATOMIC[13], TCC_EA0_ATOMIC[14], TCC_EA0_ATOMIC[15], TCC_EA0_ATOMIC[16], TCC_EA0_ATOMIC[17], TCC_EA0_ATOMIC[18], TCC_EA0_ATOMIC[19], TCC_EA0_ATOMIC[1], TCC_EA0_ATOMIC[20], TCC_EA0_ATOMIC[21], TCC_EA0_ATOMIC[22], TCC_EA0_ATOMIC[23], TCC_EA0_ATOMIC[24], TCC_EA0_ATOMIC[25], TCC_EA0_ATOMIC[26], TCC_EA0_ATOMIC[27], TCC_EA0_ATOMIC[28], TCC_EA0_ATOMIC[29], TCC_EA0_ATOMIC[2], TCC_EA0_ATOMIC[30], TCC_EA0_ATOMIC[31], TCC_EA0_ATOMIC[32], TCC_EA0_ATOMIC[33], TCC_EA0_ATOMIC[34], TCC_EA0_ATOMIC[35], TCC_EA0_ATOMIC[36], TCC_EA0_ATOMIC[37], TCC_EA0_ATOMIC[38], TCC_EA0_ATOMIC[39], TCC_EA0_ATOMIC[3], TCC_EA0_ATOMIC[40], TCC_EA0_ATOMIC[41], TCC_EA0_ATOMIC[42], TCC_EA0_ATOMIC[43], TCC_EA0_ATOMIC[44], TCC_EA0_ATOMIC[45], TCC_EA0_ATOMIC[46], TCC_EA0_ATOMIC[47], TCC_EA0_ATOMIC[48], TCC_EA0_ATOMIC[49], TCC_EA0_ATOMIC[4], TCC_EA0_ATOMIC[50], TCC_EA0_ATOMIC[51], TCC_EA0_ATOMIC[52], TCC_EA0_ATOMIC[53], TCC_EA0_ATOMIC[54], TCC_EA0_ATOMIC[55], TCC_EA0_ATOMIC[56], TCC_EA0_ATOMIC[57], TCC_EA0_ATOMIC[58], TCC_EA0_ATOMIC[59], TCC_EA0_ATOMIC[5], TCC_EA0_ATOMIC[60], TCC_EA0_ATOMIC[61], TCC_EA0_ATOMIC[62], TCC_EA0_ATOMIC[63], TCC_EA0_ATOMIC[64], TCC_EA0_ATOMIC[65], TCC_EA0_ATOMIC[66], TCC_EA0_ATOMIC[67], TCC_EA0_ATOMIC[68], TCC_EA0_ATOMIC[69], TCC_EA0_ATOMIC[6], TCC_EA0_ATOMIC[70], TCC_EA0_ATOMIC[71], TCC_EA0_ATOMIC[72], TCC_EA0_ATOMIC[73], TCC_EA0_ATOMIC[74], TCC_EA0_ATOMIC[75], TCC_EA0_ATOMIC[76], TCC_EA0_ATOMIC[77], TCC_EA0_ATOMIC[78], TCC_EA0_ATOMIC[79], TCC_EA0_ATOMIC[7], TCC_EA0_ATOMIC[80], TCC_EA0_ATOMIC[81], TCC_EA0_ATOMIC[82], TCC_EA0_ATOMIC[83], TCC_EA0_ATOMIC[84], TCC_EA0_ATOMIC[85], TCC_EA0_ATOMIC[86], TCC_EA0_ATOMIC[87], TCC_EA0_ATOMIC[88], TCC_EA0_ATOMIC[89], TCC_EA0_ATOMIC[8], TCC_EA0_ATOMIC[90], TCC_EA0_ATOMIC[91], TCC_EA0_ATOMIC[92], TCC_EA0_ATOMIC[93], TCC_EA0_ATOMIC[94], TCC_EA0_ATOMIC[95], TCC_EA0_ATOMIC[96], TCC_EA0_ATOMIC[97], TCC_EA0_ATOMIC[98], TCC_EA0_ATOMIC[99], TCC_EA0_ATOMIC[9], TCC_HIT[0], TCC_HIT[100], TCC_HIT[101], TCC_HIT[102], TCC_HIT[103], TCC_HIT[104], TCC_HIT[105], TCC_HIT[106], TCC_HIT[107], TCC_HIT[108], TCC_HIT[109], TCC_HIT[10], TCC_HIT[110], TCC_HIT[111], TCC_HIT[112], TCC_HIT[113], TCC_HIT[114], TCC_HIT[115], TCC_HIT[116], TCC_HIT[117], TCC_HIT[118], TCC_HIT[119], TCC_HIT[11], TCC_HIT[120], TCC_HIT[121], TCC_HIT[122], TCC_HIT[123], TCC_HIT[124], TCC_HIT[125], TCC_HIT[126], TCC_HIT[127], TCC_HIT[12], TCC_HIT[13], TCC_HIT[14], TCC_HIT[15], TCC_HIT[16], TCC_HIT[17], TCC_HIT[18], TCC_HIT[19], TCC_HIT[1], TCC_HIT[20], TCC_HIT[21], TCC_HIT[22], TCC_HIT[23], TCC_HIT[24], TCC_HIT[25], TCC_HIT[26], TCC_HIT[27], TCC_HIT[28], TCC_HIT[29], TCC_HIT[2], TCC_HIT[30], TCC_HIT[31], TCC_HIT[32], TCC_HIT[33], TCC_HIT[34], TCC_HIT[35], TCC_HIT[36], TCC_HIT[37], TCC_HIT[38], TCC_HIT[39], TCC_HIT[3], TCC_HIT[40], TCC_HIT[41], TCC_HIT[42], TCC_HIT[43], TCC_HIT[44], TCC_HIT[45], TCC_HIT[46], TCC_HIT[47], TCC_HIT[48], TCC_HIT[49], TCC_HIT[4], TCC_HIT[50], TCC_HIT[51], TCC_HIT[52], TCC_HIT[53], TCC_HIT[54], TCC_HIT[55], TCC_HIT[56], TCC_HIT[57], TCC_HIT[58], TCC_HIT[59], TCC_HIT[5], TCC_HIT[60], TCC_HIT[61], TCC_HIT[62], TCC_HIT[63], TCC_HIT[64], TCC_HIT[65], TCC_HIT[66], TCC_HIT[67], TCC_HIT[68], TCC_HIT[69], TCC_HIT[6], TCC_HIT[70], TCC_HIT[71], TCC_HIT[72], TCC_HIT[73], TCC_HIT[74], TCC_HIT[75], TCC_HIT[76], TCC_HIT[77], TCC_HIT[78], TCC_HIT[79], TCC_HIT[7], TCC_HIT[80], TCC_HIT[81], TCC_HIT[82], TCC_HIT[83], TCC_HIT[84], TCC_HIT[85], TCC_HIT[86], TCC_HIT[87], TCC_HIT[88], TCC_HIT[89], TCC_HIT[8], TCC_HIT[90], TCC_HIT[91], TCC_HIT[92], TCC_HIT[93], TCC_HIT[94], TCC_HIT[95], TCC_HIT[96], TCC_HIT[97], TCC_HIT[98], TCC_HIT[99], TCC_HIT[9], TCP_TA_TCP_STATE_READ_sum, TCP_TCC_UC_READ_REQ_sum, TCP_TOTAL_ATOMIC_WITH_RET_sum, TCP_UTCL1_TRANSLATION_HIT_sum, TD_LOAD_WAVEFRONT_sum, TD_STORE_WAVEFRONT_sum] + |-> [rocprofv3] E20250328 22:44:00.574379 140472799942656 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15751_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:00.580668 140472799942656 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15751_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:00.584250 140472799942656 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15751_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt, the time it takes was 0 m 0.5386278629302979 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt is 0 m 0.5522944927215576 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt +pmc file: SQ_INST_LEVEL_VMEM.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.yaml -i /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] W20250328 22:44:01.114627 140613229746176 tool.cpp:930] Unable to find all counters for agent 1 (gpu-0, gfx950) in [CPC_CANE_STALL, CPC_CPC_STAT_STALL, CPF_CPF_TCIU_BUSY, CPF_CPF_TCIU_STALL, GRBM_COUNT, GRBM_SPI_BUSY, SPI_CS0_CRAWLER_STALL, SPI_CS1_CRAWLER_STALL, SPI_CS2_CRAWLER_STALL, SPI_CS3_CRAWLER_STALL, SQ_ACTIVE_INST_VMEM, SQ_INSTS_GDS, SQ_INSTS_LDS_ATOMIC, SQ_INSTS_VALU_MFMA_F16, SQ_INSTS_VALU_MFMA_MOPS_F32, SQ_INSTS_VSKIPPED, SQ_INST_LEVEL_VMEM, SQ_INST_LEVEL_VMEM_ACCUM, TA_ADDR_STALLED_BY_TD_CYCLES_sum, TA_BUFFER_COALESCED_READ_CYCLES_sum, TCC_EA0_WRREQ[0], TCC_EA0_WRREQ[100], TCC_EA0_WRREQ[101], TCC_EA0_WRREQ[102], TCC_EA0_WRREQ[103], TCC_EA0_WRREQ[104], TCC_EA0_WRREQ[105], TCC_EA0_WRREQ[106], TCC_EA0_WRREQ[107], TCC_EA0_WRREQ[108], TCC_EA0_WRREQ[109], TCC_EA0_WRREQ[10], TCC_EA0_WRREQ[110], TCC_EA0_WRREQ[111], TCC_EA0_WRREQ[112], TCC_EA0_WRREQ[113], TCC_EA0_WRREQ[114], TCC_EA0_WRREQ[115], TCC_EA0_WRREQ[116], TCC_EA0_WRREQ[117], TCC_EA0_WRREQ[118], TCC_EA0_WRREQ[119], TCC_EA0_WRREQ[11], TCC_EA0_WRREQ[120], TCC_EA0_WRREQ[121], TCC_EA0_WRREQ[122], TCC_EA0_WRREQ[123], TCC_EA0_WRREQ[124], TCC_EA0_WRREQ[125], TCC_EA0_WRREQ[126], TCC_EA0_WRREQ[127], TCC_EA0_WRREQ[12], TCC_EA0_WRREQ[13], TCC_EA0_WRREQ[14], TCC_EA0_WRREQ[15], TCC_EA0_WRREQ[16], TCC_EA0_WRREQ[17], TCC_EA0_WRREQ[18], TCC_EA0_WRREQ[19], TCC_EA0_WRREQ[1], TCC_EA0_WRREQ[20], TCC_EA0_WRREQ[21], TCC_EA0_WRREQ[22], TCC_EA0_WRREQ[23], TCC_EA0_WRREQ[24], TCC_EA0_WRREQ[25], TCC_EA0_WRREQ[26], TCC_EA0_WRREQ[27], TCC_EA0_WRREQ[28], TCC_EA0_WRREQ[29], TCC_EA0_WRREQ[2], TCC_EA0_WRREQ[30], TCC_EA0_WRREQ[31], TCC_EA0_WRREQ[32], TCC_EA0_WRREQ[33], TCC_EA0_WRREQ[34], TCC_EA0_WRREQ[35], TCC_EA0_WRREQ[36], TCC_EA0_WRREQ[37], TCC_EA0_WRREQ[38], TCC_EA0_WRREQ[39], TCC_EA0_WRREQ[3], TCC_EA0_WRREQ[40], TCC_EA0_WRREQ[41], TCC_EA0_WRREQ[42], TCC_EA0_WRREQ[43], TCC_EA0_WRREQ[44], TCC_EA0_WRREQ[45], TCC_EA0_WRREQ[46], TCC_EA0_WRREQ[47], TCC_EA0_WRREQ[48], TCC_EA0_WRREQ[49], TCC_EA0_WRREQ[4], TCC_EA0_WRREQ[50], TCC_EA0_WRREQ[51], TCC_EA0_WRREQ[52], TCC_EA0_WRREQ[53], TCC_EA0_WRREQ[54], TCC_EA0_WRREQ[55], TCC_EA0_WRREQ[56], TCC_EA0_WRREQ[57], TCC_EA0_WRREQ[58], TCC_EA0_WRREQ[59], TCC_EA0_WRREQ[5], TCC_EA0_WRREQ[60], TCC_EA0_WRREQ[61], TCC_EA0_WRREQ[62], TCC_EA0_WRREQ[63], TCC_EA0_WRREQ[64], TCC_EA0_WRREQ[65], TCC_EA0_WRREQ[66], TCC_EA0_WRREQ[67], TCC_EA0_WRREQ[68], TCC_EA0_WRREQ[69], TCC_EA0_WRREQ[6], TCC_EA0_WRREQ[70], TCC_EA0_WRREQ[71], TCC_EA0_WRREQ[72], TCC_EA0_WRREQ[73], TCC_EA0_WRREQ[74], TCC_EA0_WRREQ[75], TCC_EA0_WRREQ[76], TCC_EA0_WRREQ[77], TCC_EA0_WRREQ[78], TCC_EA0_WRREQ[79], TCC_EA0_WRREQ[7], TCC_EA0_WRREQ[80], TCC_EA0_WRREQ[81], TCC_EA0_WRREQ[82], TCC_EA0_WRREQ[83], TCC_EA0_WRREQ[84], TCC_EA0_WRREQ[85], TCC_EA0_WRREQ[86], TCC_EA0_WRREQ[87], TCC_EA0_WRREQ[88], TCC_EA0_WRREQ[89], TCC_EA0_WRREQ[8], TCC_EA0_WRREQ[90], TCC_EA0_WRREQ[91], TCC_EA0_WRREQ[92], TCC_EA0_WRREQ[93], TCC_EA0_WRREQ[94], TCC_EA0_WRREQ[95], TCC_EA0_WRREQ[96], TCC_EA0_WRREQ[97], TCC_EA0_WRREQ[98], TCC_EA0_WRREQ[99], TCC_EA0_WRREQ[9], TCC_MISS[0], TCC_MISS[100], TCC_MISS[101], TCC_MISS[102], TCC_MISS[103], TCC_MISS[104], TCC_MISS[105], TCC_MISS[106], TCC_MISS[107], TCC_MISS[108], TCC_MISS[109], TCC_MISS[10], TCC_MISS[110], TCC_MISS[111], TCC_MISS[112], TCC_MISS[113], TCC_MISS[114], TCC_MISS[115], TCC_MISS[116], TCC_MISS[117], TCC_MISS[118], TCC_MISS[119], TCC_MISS[11], TCC_MISS[120], TCC_MISS[121], TCC_MISS[122], TCC_MISS[123], TCC_MISS[124], TCC_MISS[125], TCC_MISS[126], TCC_MISS[127], TCC_MISS[12], TCC_MISS[13], TCC_MISS[14], TCC_MISS[15], TCC_MISS[16], TCC_MISS[17], TCC_MISS[18], TCC_MISS[19], TCC_MISS[1], TCC_MISS[20], TCC_MISS[21], TCC_MISS[22], TCC_MISS[23], TCC_MISS[24], TCC_MISS[25], TCC_MISS[26], TCC_MISS[27], TCC_MISS[28], TCC_MISS[29], TCC_MISS[2], TCC_MISS[30], TCC_MISS[31], TCC_MISS[32], TCC_MISS[33], TCC_MISS[34], TCC_MISS[35], TCC_MISS[36], TCC_MISS[37], TCC_MISS[38], TCC_MISS[39], TCC_MISS[3], TCC_MISS[40], TCC_MISS[41], TCC_MISS[42], TCC_MISS[43], TCC_MISS[44], TCC_MISS[45], TCC_MISS[46], TCC_MISS[47], TCC_MISS[48], TCC_MISS[49], TCC_MISS[4], TCC_MISS[50], TCC_MISS[51], TCC_MISS[52], TCC_MISS[53], TCC_MISS[54], TCC_MISS[55], TCC_MISS[56], TCC_MISS[57], TCC_MISS[58], TCC_MISS[59], TCC_MISS[5], TCC_MISS[60], TCC_MISS[61], TCC_MISS[62], TCC_MISS[63], TCC_MISS[64], TCC_MISS[65], TCC_MISS[66], TCC_MISS[67], TCC_MISS[68], TCC_MISS[69], TCC_MISS[6], TCC_MISS[70], TCC_MISS[71], TCC_MISS[72], TCC_MISS[73], TCC_MISS[74], TCC_MISS[75], TCC_MISS[76], TCC_MISS[77], TCC_MISS[78], TCC_MISS[79], TCC_MISS[7], TCC_MISS[80], TCC_MISS[81], TCC_MISS[82], TCC_MISS[83], TCC_MISS[84], TCC_MISS[85], TCC_MISS[86], TCC_MISS[87], TCC_MISS[88], TCC_MISS[89], TCC_MISS[8], TCC_MISS[90], TCC_MISS[91], TCC_MISS[92], TCC_MISS[93], TCC_MISS[94], TCC_MISS[95], TCC_MISS[96], TCC_MISS[97], TCC_MISS[98], TCC_MISS[99], TCC_MISS[9], TCC_READ[0], TCC_READ[100], TCC_READ[101], TCC_READ[102], TCC_READ[103], TCC_READ[104], TCC_READ[105], TCC_READ[106], TCC_READ[107], TCC_READ[108], TCC_READ[109], TCC_READ[10], TCC_READ[110], TCC_READ[111], TCC_READ[112], TCC_READ[113], TCC_READ[114], TCC_READ[115], TCC_READ[116], TCC_READ[117], TCC_READ[118], TCC_READ[119], TCC_READ[11], TCC_READ[120], TCC_READ[121], TCC_READ[122], TCC_READ[123], TCC_READ[124], TCC_READ[125], TCC_READ[126], TCC_READ[127], TCC_READ[12], TCC_READ[13], TCC_READ[14], TCC_READ[15], TCC_READ[16], TCC_READ[17], TCC_READ[18], TCC_READ[19], TCC_READ[1], TCC_READ[20], TCC_READ[21], TCC_READ[22], TCC_READ[23], TCC_READ[24], TCC_READ[25], TCC_READ[26], TCC_READ[27], TCC_READ[28], TCC_READ[29], TCC_READ[2], TCC_READ[30], TCC_READ[31], TCC_READ[32], TCC_READ[33], TCC_READ[34], TCC_READ[35], TCC_READ[36], TCC_READ[37], TCC_READ[38], TCC_READ[39], TCC_READ[3], TCC_READ[40], TCC_READ[41], TCC_READ[42], TCC_READ[43], TCC_READ[44], TCC_READ[45], TCC_READ[46], TCC_READ[47], TCC_READ[48], TCC_READ[49], TCC_READ[4], TCC_READ[50], TCC_READ[51], TCC_READ[52], TCC_READ[53], TCC_READ[54], TCC_READ[55], TCC_READ[56], TCC_READ[57], TCC_READ[58], TCC_READ[59], TCC_READ[5], TCC_READ[60], TCC_READ[61], TCC_READ[62], TCC_READ[63], TCC_READ[64], TCC_READ[65], TCC_READ[66], TCC_READ[67], TCC_READ[68], TCC_READ[69], TCC_READ[6], TCC_READ[70], TCC_READ[71], TCC_READ[72], TCC_READ[73], TCC_READ[74], TCC_READ[75], TCC_READ[76], TCC_READ[77], TCC_READ[78], TCC_READ[79], TCC_READ[7], TCC_READ[80], TCC_READ[81], TCC_READ[82], TCC_READ[83], TCC_READ[84], TCC_READ[85], TCC_READ[86], TCC_READ[87], TCC_READ[88], TCC_READ[89], TCC_READ[8], TCC_READ[90], TCC_READ[91], TCC_READ[92], TCC_READ[93], TCC_READ[94], TCC_READ[95], TCC_READ[96], TCC_READ[97], TCC_READ[98], TCC_READ[99], TCC_READ[9], TCC_WRITE[0], TCC_WRITE[100], TCC_WRITE[101], TCC_WRITE[102], TCC_WRITE[103], TCC_WRITE[104], TCC_WRITE[105], TCC_WRITE[106], TCC_WRITE[107], TCC_WRITE[108], TCC_WRITE[109], TCC_WRITE[10], TCC_WRITE[110], TCC_WRITE[111], TCC_WRITE[112], TCC_WRITE[113], TCC_WRITE[114], TCC_WRITE[115], TCC_WRITE[116], TCC_WRITE[117], TCC_WRITE[118], TCC_WRITE[119], TCC_WRITE[11], TCC_WRITE[120], TCC_WRITE[121], TCC_WRITE[122], TCC_WRITE[123], TCC_WRITE[124], TCC_WRITE[125], TCC_WRITE[126], TCC_WRITE[127], TCC_WRITE[12], TCC_WRITE[13], TCC_WRITE[14], TCC_WRITE[15], TCC_WRITE[16], TCC_WRITE[17], TCC_WRITE[18], TCC_WRITE[19], TCC_WRITE[1], TCC_WRITE[20], TCC_WRITE[21], TCC_WRITE[22], TCC_WRITE[23], TCC_WRITE[24], TCC_WRITE[25], TCC_WRITE[26], TCC_WRITE[27], TCC_WRITE[28], TCC_WRITE[29], TCC_WRITE[2], TCC_WRITE[30], TCC_WRITE[31], TCC_WRITE[32], TCC_WRITE[33], TCC_WRITE[34], TCC_WRITE[35], TCC_WRITE[36], TCC_WRITE[37], TCC_WRITE[38], TCC_WRITE[39], TCC_WRITE[3], TCC_WRITE[40], TCC_WRITE[41], TCC_WRITE[42], TCC_WRITE[43], TCC_WRITE[44], TCC_WRITE[45], TCC_WRITE[46], TCC_WRITE[47], TCC_WRITE[48], TCC_WRITE[49], TCC_WRITE[4], TCC_WRITE[50], TCC_WRITE[51], TCC_WRITE[52], TCC_WRITE[53], TCC_WRITE[54], TCC_WRITE[55], TCC_WRITE[56], TCC_WRITE[57], TCC_WRITE[58], TCC_WRITE[59], TCC_WRITE[5], TCC_WRITE[60], TCC_WRITE[61], TCC_WRITE[62], TCC_WRITE[63], TCC_WRITE[64], TCC_WRITE[65], TCC_WRITE[66], TCC_WRITE[67], TCC_WRITE[68], TCC_WRITE[69], TCC_WRITE[6], TCC_WRITE[70], TCC_WRITE[71], TCC_WRITE[72], TCC_WRITE[73], TCC_WRITE[74], TCC_WRITE[75], TCC_WRITE[76], TCC_WRITE[77], TCC_WRITE[78], TCC_WRITE[79], TCC_WRITE[7], TCC_WRITE[80], TCC_WRITE[81], TCC_WRITE[82], TCC_WRITE[83], TCC_WRITE[84], TCC_WRITE[85], TCC_WRITE[86], TCC_WRITE[87], TCC_WRITE[88], TCC_WRITE[89], TCC_WRITE[8], TCC_WRITE[90], TCC_WRITE[91], TCC_WRITE[92], TCC_WRITE[93], TCC_WRITE[94], TCC_WRITE[95], TCC_WRITE[96], TCC_WRITE[97], TCC_WRITE[98], TCC_WRITE[99], TCC_WRITE[9], TCP_READ_TAGCONFLICT_STALL_CYCLES_sum, TCP_TCC_NC_WRITE_REQ_sum, TCP_TCC_RW_READ_REQ_sum, TCP_TCP_LATENCY_sum, TD_COALESCABLE_WAVEFRONT_sum, TD_SPI_STALL_sum]. Found: [CPC_CANE_STALL, CPC_CPC_STAT_STALL, CPF_CPF_TCIU_BUSY, CPF_CPF_TCIU_STALL, GRBM_COUNT, GRBM_SPI_BUSY, SPI_CS0_CRAWLER_STALL, SPI_CS1_CRAWLER_STALL, SPI_CS2_CRAWLER_STALL, SPI_CS3_CRAWLER_STALL, SQ_ACTIVE_INST_VMEM, SQ_INSTS_GDS, SQ_INSTS_LDS_ATOMIC, SQ_INSTS_VALU_MFMA_F16, SQ_INSTS_VALU_MFMA_MOPS_F32, SQ_INSTS_VSKIPPED, SQ_INST_LEVEL_VMEM, TA_ADDR_STALLED_BY_TD_CYCLES_sum, TA_BUFFER_COALESCED_READ_CYCLES_sum, TCC_EA0_WRREQ[0], TCC_EA0_WRREQ[100], TCC_EA0_WRREQ[101], TCC_EA0_WRREQ[102], TCC_EA0_WRREQ[103], TCC_EA0_WRREQ[104], TCC_EA0_WRREQ[105], TCC_EA0_WRREQ[106], TCC_EA0_WRREQ[107], TCC_EA0_WRREQ[108], TCC_EA0_WRREQ[109], TCC_EA0_WRREQ[10], TCC_EA0_WRREQ[110], TCC_EA0_WRREQ[111], TCC_EA0_WRREQ[112], TCC_EA0_WRREQ[113], TCC_EA0_WRREQ[114], TCC_EA0_WRREQ[115], TCC_EA0_WRREQ[116], TCC_EA0_WRREQ[117], TCC_EA0_WRREQ[118], TCC_EA0_WRREQ[119], TCC_EA0_WRREQ[11], TCC_EA0_WRREQ[120], TCC_EA0_WRREQ[121], TCC_EA0_WRREQ[122], TCC_EA0_WRREQ[123], TCC_EA0_WRREQ[124], TCC_EA0_WRREQ[125], TCC_EA0_WRREQ[126], TCC_EA0_WRREQ[127], TCC_EA0_WRREQ[12], TCC_EA0_WRREQ[13], TCC_EA0_WRREQ[14], TCC_EA0_WRREQ[15], TCC_EA0_WRREQ[16], TCC_EA0_WRREQ[17], TCC_EA0_WRREQ[18], TCC_EA0_WRREQ[19], TCC_EA0_WRREQ[1], TCC_EA0_WRREQ[20], TCC_EA0_WRREQ[21], TCC_EA0_WRREQ[22], TCC_EA0_WRREQ[23], TCC_EA0_WRREQ[24], TCC_EA0_WRREQ[25], TCC_EA0_WRREQ[26], TCC_EA0_WRREQ[27], TCC_EA0_WRREQ[28], TCC_EA0_WRREQ[29], TCC_EA0_WRREQ[2], TCC_EA0_WRREQ[30], TCC_EA0_WRREQ[31], TCC_EA0_WRREQ[32], TCC_EA0_WRREQ[33], TCC_EA0_WRREQ[34], TCC_EA0_WRREQ[35], TCC_EA0_WRREQ[36], TCC_EA0_WRREQ[37], TCC_EA0_WRREQ[38], TCC_EA0_WRREQ[39], TCC_EA0_WRREQ[3], TCC_EA0_WRREQ[40], TCC_EA0_WRREQ[41], TCC_EA0_WRREQ[42], TCC_EA0_WRREQ[43], TCC_EA0_WRREQ[44], TCC_EA0_WRREQ[45], TCC_EA0_WRREQ[46], TCC_EA0_WRREQ[47], TCC_EA0_WRREQ[48], TCC_EA0_WRREQ[49], TCC_EA0_WRREQ[4], TCC_EA0_WRREQ[50], TCC_EA0_WRREQ[51], TCC_EA0_WRREQ[52], TCC_EA0_WRREQ[53], TCC_EA0_WRREQ[54], TCC_EA0_WRREQ[55], TCC_EA0_WRREQ[56], TCC_EA0_WRREQ[57], TCC_EA0_WRREQ[58], TCC_EA0_WRREQ[59], TCC_EA0_WRREQ[5], TCC_EA0_WRREQ[60], TCC_EA0_WRREQ[61], TCC_EA0_WRREQ[62], TCC_EA0_WRREQ[63], TCC_EA0_WRREQ[64], TCC_EA0_WRREQ[65], TCC_EA0_WRREQ[66], TCC_EA0_WRREQ[67], TCC_EA0_WRREQ[68], TCC_EA0_WRREQ[69], TCC_EA0_WRREQ[6], TCC_EA0_WRREQ[70], TCC_EA0_WRREQ[71], TCC_EA0_WRREQ[72], TCC_EA0_WRREQ[73], TCC_EA0_WRREQ[74], TCC_EA0_WRREQ[75], TCC_EA0_WRREQ[76], TCC_EA0_WRREQ[77], TCC_EA0_WRREQ[78], TCC_EA0_WRREQ[79], TCC_EA0_WRREQ[7], TCC_EA0_WRREQ[80], TCC_EA0_WRREQ[81], TCC_EA0_WRREQ[82], TCC_EA0_WRREQ[83], TCC_EA0_WRREQ[84], TCC_EA0_WRREQ[85], TCC_EA0_WRREQ[86], TCC_EA0_WRREQ[87], TCC_EA0_WRREQ[88], TCC_EA0_WRREQ[89], TCC_EA0_WRREQ[8], TCC_EA0_WRREQ[90], TCC_EA0_WRREQ[91], TCC_EA0_WRREQ[92], TCC_EA0_WRREQ[93], TCC_EA0_WRREQ[94], TCC_EA0_WRREQ[95], TCC_EA0_WRREQ[96], TCC_EA0_WRREQ[97], TCC_EA0_WRREQ[98], TCC_EA0_WRREQ[99], TCC_EA0_WRREQ[9], TCC_MISS[0], TCC_MISS[100], TCC_MISS[101], TCC_MISS[102], TCC_MISS[103], TCC_MISS[104], TCC_MISS[105], TCC_MISS[106], TCC_MISS[107], TCC_MISS[108], TCC_MISS[109], TCC_MISS[10], TCC_MISS[110], TCC_MISS[111], TCC_MISS[112], TCC_MISS[113], TCC_MISS[114], TCC_MISS[115], TCC_MISS[116], TCC_MISS[117], TCC_MISS[118], TCC_MISS[119], TCC_MISS[11], TCC_MISS[120], TCC_MISS[121], TCC_MISS[122], TCC_MISS[123], TCC_MISS[124], TCC_MISS[125], TCC_MISS[126], TCC_MISS[127], TCC_MISS[12], TCC_MISS[13], TCC_MISS[14], TCC_MISS[15], TCC_MISS[16], TCC_MISS[17], TCC_MISS[18], TCC_MISS[19], TCC_MISS[1], TCC_MISS[20], TCC_MISS[21], TCC_MISS[22], TCC_MISS[23], TCC_MISS[24], TCC_MISS[25], TCC_MISS[26], TCC_MISS[27], TCC_MISS[28], TCC_MISS[29], TCC_MISS[2], TCC_MISS[30], TCC_MISS[31], TCC_MISS[32], TCC_MISS[33], TCC_MISS[34], TCC_MISS[35], TCC_MISS[36], TCC_MISS[37], TCC_MISS[38], TCC_MISS[39], TCC_MISS[3], TCC_MISS[40], TCC_MISS[41], TCC_MISS[42], TCC_MISS[43], TCC_MISS[44], TCC_MISS[45], TCC_MISS[46], TCC_MISS[47], TCC_MISS[48], TCC_MISS[49], TCC_MISS[4], TCC_MISS[50], TCC_MISS[51], TCC_MISS[52], TCC_MISS[53], TCC_MISS[54], TCC_MISS[55], TCC_MISS[56], TCC_MISS[57], TCC_MISS[58], TCC_MISS[59], TCC_MISS[5], TCC_MISS[60], TCC_MISS[61], TCC_MISS[62], TCC_MISS[63], TCC_MISS[64], TCC_MISS[65], TCC_MISS[66], TCC_MISS[67], TCC_MISS[68], TCC_MISS[69], TCC_MISS[6], TCC_MISS[70], TCC_MISS[71], TCC_MISS[72], TCC_MISS[73], TCC_MISS[74], TCC_MISS[75], TCC_MISS[76], TCC_MISS[77], TCC_MISS[78], TCC_MISS[79], TCC_MISS[7], TCC_MISS[80], TCC_MISS[81], TCC_MISS[82], TCC_MISS[83], TCC_MISS[84], TCC_MISS[85], TCC_MISS[86], TCC_MISS[87], TCC_MISS[88], TCC_MISS[89], TCC_MISS[8], TCC_MISS[90], TCC_MISS[91], TCC_MISS[92], TCC_MISS[93], TCC_MISS[94], TCC_MISS[95], TCC_MISS[96], TCC_MISS[97], TCC_MISS[98], TCC_MISS[99], TCC_MISS[9], TCC_READ[0], TCC_READ[100], TCC_READ[101], TCC_READ[102], TCC_READ[103], TCC_READ[104], TCC_READ[105], TCC_READ[106], TCC_READ[107], TCC_READ[108], TCC_READ[109], TCC_READ[10], TCC_READ[110], TCC_READ[111], TCC_READ[112], TCC_READ[113], TCC_READ[114], TCC_READ[115], TCC_READ[116], TCC_READ[117], TCC_READ[118], TCC_READ[119], TCC_READ[11], TCC_READ[120], TCC_READ[121], TCC_READ[122], TCC_READ[123], TCC_READ[124], TCC_READ[125], TCC_READ[126], TCC_READ[127], TCC_READ[12], TCC_READ[13], TCC_READ[14], TCC_READ[15], TCC_READ[16], TCC_READ[17], TCC_READ[18], TCC_READ[19], TCC_READ[1], TCC_READ[20], TCC_READ[21], TCC_READ[22], TCC_READ[23], TCC_READ[24], TCC_READ[25], TCC_READ[26], TCC_READ[27], TCC_READ[28], TCC_READ[29], TCC_READ[2], TCC_READ[30], TCC_READ[31], TCC_READ[32], TCC_READ[33], TCC_READ[34], TCC_READ[35], TCC_READ[36], TCC_READ[37], TCC_READ[38], TCC_READ[39], TCC_READ[3], TCC_READ[40], TCC_READ[41], TCC_READ[42], TCC_READ[43], TCC_READ[44], TCC_READ[45], TCC_READ[46], TCC_READ[47], TCC_READ[48], TCC_READ[49], TCC_READ[4], TCC_READ[50], TCC_READ[51], TCC_READ[52], TCC_READ[53], TCC_READ[54], TCC_READ[55], TCC_READ[56], TCC_READ[57], TCC_READ[58], TCC_READ[59], TCC_READ[5], TCC_READ[60], TCC_READ[61], TCC_READ[62], TCC_READ[63], TCC_READ[64], TCC_READ[65], TCC_READ[66], TCC_READ[67], TCC_READ[68], TCC_READ[69], TCC_READ[6], TCC_READ[70], TCC_READ[71], TCC_READ[72], TCC_READ[73], TCC_READ[74], TCC_READ[75], TCC_READ[76], TCC_READ[77], TCC_READ[78], TCC_READ[79], TCC_READ[7], TCC_READ[80], TCC_READ[81], TCC_READ[82], TCC_READ[83], TCC_READ[84], TCC_READ[85], TCC_READ[86], TCC_READ[87], TCC_READ[88], TCC_READ[89], TCC_READ[8], TCC_READ[90], TCC_READ[91], TCC_READ[92], TCC_READ[93], TCC_READ[94], TCC_READ[95], TCC_READ[96], TCC_READ[97], TCC_READ[98], TCC_READ[99], TCC_READ[9], TCC_WRITE[0], TCC_WRITE[100], TCC_WRITE[101], TCC_WRITE[102], TCC_WRITE[103], TCC_WRITE[104], TCC_WRITE[105], TCC_WRITE[106], TCC_WRITE[107], TCC_WRITE[108], TCC_WRITE[109], TCC_WRITE[10], TCC_WRITE[110], TCC_WRITE[111], TCC_WRITE[112], TCC_WRITE[113], TCC_WRITE[114], TCC_WRITE[115], TCC_WRITE[116], TCC_WRITE[117], TCC_WRITE[118], TCC_WRITE[119], TCC_WRITE[11], TCC_WRITE[120], TCC_WRITE[121], TCC_WRITE[122], TCC_WRITE[123], TCC_WRITE[124], TCC_WRITE[125], TCC_WRITE[126], TCC_WRITE[127], TCC_WRITE[12], TCC_WRITE[13], TCC_WRITE[14], TCC_WRITE[15], TCC_WRITE[16], TCC_WRITE[17], TCC_WRITE[18], TCC_WRITE[19], TCC_WRITE[1], TCC_WRITE[20], TCC_WRITE[21], TCC_WRITE[22], TCC_WRITE[23], TCC_WRITE[24], TCC_WRITE[25], TCC_WRITE[26], TCC_WRITE[27], TCC_WRITE[28], TCC_WRITE[29], TCC_WRITE[2], TCC_WRITE[30], TCC_WRITE[31], TCC_WRITE[32], TCC_WRITE[33], TCC_WRITE[34], TCC_WRITE[35], TCC_WRITE[36], TCC_WRITE[37], TCC_WRITE[38], TCC_WRITE[39], TCC_WRITE[3], TCC_WRITE[40], TCC_WRITE[41], TCC_WRITE[42], TCC_WRITE[43], TCC_WRITE[44], TCC_WRITE[45], TCC_WRITE[46], TCC_WRITE[47], TCC_WRITE[48], TCC_WRITE[49], TCC_WRITE[4], TCC_WRITE[50], TCC_WRITE[51], TCC_WRITE[52], TCC_WRITE[53], TCC_WRITE[54], TCC_WRITE[55], TCC_WRITE[56], TCC_WRITE[57], TCC_WRITE[58], TCC_WRITE[59], TCC_WRITE[5], TCC_WRITE[60], TCC_WRITE[61], TCC_WRITE[62], TCC_WRITE[63], TCC_WRITE[64], TCC_WRITE[65], TCC_WRITE[66], TCC_WRITE[67], TCC_WRITE[68], TCC_WRITE[69], TCC_WRITE[6], TCC_WRITE[70], TCC_WRITE[71], TCC_WRITE[72], TCC_WRITE[73], TCC_WRITE[74], TCC_WRITE[75], TCC_WRITE[76], TCC_WRITE[77], TCC_WRITE[78], TCC_WRITE[79], TCC_WRITE[7], TCC_WRITE[80], TCC_WRITE[81], TCC_WRITE[82], TCC_WRITE[83], TCC_WRITE[84], TCC_WRITE[85], TCC_WRITE[86], TCC_WRITE[87], TCC_WRITE[88], TCC_WRITE[89], TCC_WRITE[8], TCC_WRITE[90], TCC_WRITE[91], TCC_WRITE[92], TCC_WRITE[93], TCC_WRITE[94], TCC_WRITE[95], TCC_WRITE[96], TCC_WRITE[97], TCC_WRITE[98], TCC_WRITE[99], TCC_WRITE[9], TCP_READ_TAGCONFLICT_STALL_CYCLES_sum, TCP_TCC_NC_WRITE_REQ_sum, TCP_TCC_RW_READ_REQ_sum, TCP_TCP_LATENCY_sum, TD_COALESCABLE_WAVEFRONT_sum, TD_SPI_STALL_sum] + |-> [rocprofv3] E20250328 22:44:01.129009 140613229746176 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15758_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:01.135559 140613229746176 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15758_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:01.139250 140613229746176 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15758_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt, the time it takes was 0 m 0.5387754440307617 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt is 0 m 0.5530288219451904 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.txt +pmc file: SQ_LEVEL_WAVES.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.yaml -i /app/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] W20250328 22:44:01.669645 139667039954944 tool.cpp:930] Unable to find all counters for agent 1 (gpu-0, gfx950) in [CPC_CPC_TCIU_IDLE, CPC_TG_SEND, CPF_CPF_TCIU_IDLE, SPI_CS0_BUSY, SPI_CS1_BUSY, SPI_CS2_BUSY, SPI_CS3_BUSY, SQ_INSTS_LDS, SQ_INSTS_LDS_LOAD_BANDWIDTH, SQ_INSTS_VALU_ADD_F16, SQ_INSTS_VALU_FMA_F16, SQ_LDS_IDX_ACTIVE, SQ_LEVEL_WAVES, SQ_LEVEL_WAVES_ACCUM, SQ_WAVE_CYCLES, TA_BUFFER_ATOMIC_WAVEFRONTS_sum, TA_FLAT_ATOMIC_WAVEFRONTS_sum, TCC_BUBBLE_sum, TCC_EA0_ATOMIC_LEVEL[0], TCC_EA0_ATOMIC_LEVEL[100], TCC_EA0_ATOMIC_LEVEL[101], TCC_EA0_ATOMIC_LEVEL[102], TCC_EA0_ATOMIC_LEVEL[103], TCC_EA0_ATOMIC_LEVEL[104], TCC_EA0_ATOMIC_LEVEL[105], TCC_EA0_ATOMIC_LEVEL[106], TCC_EA0_ATOMIC_LEVEL[107], TCC_EA0_ATOMIC_LEVEL[108], TCC_EA0_ATOMIC_LEVEL[109], TCC_EA0_ATOMIC_LEVEL[10], TCC_EA0_ATOMIC_LEVEL[110], TCC_EA0_ATOMIC_LEVEL[111], TCC_EA0_ATOMIC_LEVEL[112], TCC_EA0_ATOMIC_LEVEL[113], TCC_EA0_ATOMIC_LEVEL[114], TCC_EA0_ATOMIC_LEVEL[115], TCC_EA0_ATOMIC_LEVEL[116], TCC_EA0_ATOMIC_LEVEL[117], TCC_EA0_ATOMIC_LEVEL[118], TCC_EA0_ATOMIC_LEVEL[119], TCC_EA0_ATOMIC_LEVEL[11], TCC_EA0_ATOMIC_LEVEL[120], TCC_EA0_ATOMIC_LEVEL[121], TCC_EA0_ATOMIC_LEVEL[122], TCC_EA0_ATOMIC_LEVEL[123], TCC_EA0_ATOMIC_LEVEL[124], TCC_EA0_ATOMIC_LEVEL[125], TCC_EA0_ATOMIC_LEVEL[126], TCC_EA0_ATOMIC_LEVEL[127], TCC_EA0_ATOMIC_LEVEL[12], TCC_EA0_ATOMIC_LEVEL[13], TCC_EA0_ATOMIC_LEVEL[14], TCC_EA0_ATOMIC_LEVEL[15], TCC_EA0_ATOMIC_LEVEL[16], TCC_EA0_ATOMIC_LEVEL[17], TCC_EA0_ATOMIC_LEVEL[18], TCC_EA0_ATOMIC_LEVEL[19], TCC_EA0_ATOMIC_LEVEL[1], TCC_EA0_ATOMIC_LEVEL[20], TCC_EA0_ATOMIC_LEVEL[21], TCC_EA0_ATOMIC_LEVEL[22], TCC_EA0_ATOMIC_LEVEL[23], TCC_EA0_ATOMIC_LEVEL[24], TCC_EA0_ATOMIC_LEVEL[25], TCC_EA0_ATOMIC_LEVEL[26], TCC_EA0_ATOMIC_LEVEL[27], TCC_EA0_ATOMIC_LEVEL[28], TCC_EA0_ATOMIC_LEVEL[29], TCC_EA0_ATOMIC_LEVEL[2], TCC_EA0_ATOMIC_LEVEL[30], TCC_EA0_ATOMIC_LEVEL[31], TCC_EA0_ATOMIC_LEVEL[32], TCC_EA0_ATOMIC_LEVEL[33], TCC_EA0_ATOMIC_LEVEL[34], TCC_EA0_ATOMIC_LEVEL[35], TCC_EA0_ATOMIC_LEVEL[36], TCC_EA0_ATOMIC_LEVEL[37], TCC_EA0_ATOMIC_LEVEL[38], TCC_EA0_ATOMIC_LEVEL[39], TCC_EA0_ATOMIC_LEVEL[3], TCC_EA0_ATOMIC_LEVEL[40], TCC_EA0_ATOMIC_LEVEL[41], TCC_EA0_ATOMIC_LEVEL[42], TCC_EA0_ATOMIC_LEVEL[43], TCC_EA0_ATOMIC_LEVEL[44], TCC_EA0_ATOMIC_LEVEL[45], TCC_EA0_ATOMIC_LEVEL[46], TCC_EA0_ATOMIC_LEVEL[47], TCC_EA0_ATOMIC_LEVEL[48], TCC_EA0_ATOMIC_LEVEL[49], TCC_EA0_ATOMIC_LEVEL[4], TCC_EA0_ATOMIC_LEVEL[50], TCC_EA0_ATOMIC_LEVEL[51], TCC_EA0_ATOMIC_LEVEL[52], TCC_EA0_ATOMIC_LEVEL[53], TCC_EA0_ATOMIC_LEVEL[54], TCC_EA0_ATOMIC_LEVEL[55], TCC_EA0_ATOMIC_LEVEL[56], TCC_EA0_ATOMIC_LEVEL[57], TCC_EA0_ATOMIC_LEVEL[58], TCC_EA0_ATOMIC_LEVEL[59], TCC_EA0_ATOMIC_LEVEL[5], TCC_EA0_ATOMIC_LEVEL[60], TCC_EA0_ATOMIC_LEVEL[61], TCC_EA0_ATOMIC_LEVEL[62], TCC_EA0_ATOMIC_LEVEL[63], TCC_EA0_ATOMIC_LEVEL[64], TCC_EA0_ATOMIC_LEVEL[65], TCC_EA0_ATOMIC_LEVEL[66], TCC_EA0_ATOMIC_LEVEL[67], TCC_EA0_ATOMIC_LEVEL[68], TCC_EA0_ATOMIC_LEVEL[69], TCC_EA0_ATOMIC_LEVEL[6], TCC_EA0_ATOMIC_LEVEL[70], TCC_EA0_ATOMIC_LEVEL[71], TCC_EA0_ATOMIC_LEVEL[72], TCC_EA0_ATOMIC_LEVEL[73], TCC_EA0_ATOMIC_LEVEL[74], TCC_EA0_ATOMIC_LEVEL[75], TCC_EA0_ATOMIC_LEVEL[76], TCC_EA0_ATOMIC_LEVEL[77], TCC_EA0_ATOMIC_LEVEL[78], TCC_EA0_ATOMIC_LEVEL[79], TCC_EA0_ATOMIC_LEVEL[7], TCC_EA0_ATOMIC_LEVEL[80], TCC_EA0_ATOMIC_LEVEL[81], TCC_EA0_ATOMIC_LEVEL[82], TCC_EA0_ATOMIC_LEVEL[83], TCC_EA0_ATOMIC_LEVEL[84], TCC_EA0_ATOMIC_LEVEL[85], TCC_EA0_ATOMIC_LEVEL[86], TCC_EA0_ATOMIC_LEVEL[87], TCC_EA0_ATOMIC_LEVEL[88], TCC_EA0_ATOMIC_LEVEL[89], TCC_EA0_ATOMIC_LEVEL[8], TCC_EA0_ATOMIC_LEVEL[90], TCC_EA0_ATOMIC_LEVEL[91], TCC_EA0_ATOMIC_LEVEL[92], TCC_EA0_ATOMIC_LEVEL[93], TCC_EA0_ATOMIC_LEVEL[94], TCC_EA0_ATOMIC_LEVEL[95], TCC_EA0_ATOMIC_LEVEL[96], TCC_EA0_ATOMIC_LEVEL[97], TCC_EA0_ATOMIC_LEVEL[98], TCC_EA0_ATOMIC_LEVEL[99], TCC_EA0_ATOMIC_LEVEL[9], TCC_EA0_RDREQ_LEVEL[0], TCC_EA0_RDREQ_LEVEL[100], TCC_EA0_RDREQ_LEVEL[101], TCC_EA0_RDREQ_LEVEL[102], TCC_EA0_RDREQ_LEVEL[103], TCC_EA0_RDREQ_LEVEL[104], TCC_EA0_RDREQ_LEVEL[105], TCC_EA0_RDREQ_LEVEL[106], TCC_EA0_RDREQ_LEVEL[107], TCC_EA0_RDREQ_LEVEL[108], TCC_EA0_RDREQ_LEVEL[109], TCC_EA0_RDREQ_LEVEL[10], TCC_EA0_RDREQ_LEVEL[110], TCC_EA0_RDREQ_LEVEL[111], TCC_EA0_RDREQ_LEVEL[112], TCC_EA0_RDREQ_LEVEL[113], TCC_EA0_RDREQ_LEVEL[114], TCC_EA0_RDREQ_LEVEL[115], TCC_EA0_RDREQ_LEVEL[116], TCC_EA0_RDREQ_LEVEL[117], TCC_EA0_RDREQ_LEVEL[118], TCC_EA0_RDREQ_LEVEL[119], TCC_EA0_RDREQ_LEVEL[11], TCC_EA0_RDREQ_LEVEL[120], TCC_EA0_RDREQ_LEVEL[121], TCC_EA0_RDREQ_LEVEL[122], TCC_EA0_RDREQ_LEVEL[123], TCC_EA0_RDREQ_LEVEL[124], TCC_EA0_RDREQ_LEVEL[125], TCC_EA0_RDREQ_LEVEL[126], TCC_EA0_RDREQ_LEVEL[127], TCC_EA0_RDREQ_LEVEL[12], TCC_EA0_RDREQ_LEVEL[13], TCC_EA0_RDREQ_LEVEL[14], TCC_EA0_RDREQ_LEVEL[15], TCC_EA0_RDREQ_LEVEL[16], TCC_EA0_RDREQ_LEVEL[17], TCC_EA0_RDREQ_LEVEL[18], TCC_EA0_RDREQ_LEVEL[19], TCC_EA0_RDREQ_LEVEL[1], TCC_EA0_RDREQ_LEVEL[20], TCC_EA0_RDREQ_LEVEL[21], TCC_EA0_RDREQ_LEVEL[22], TCC_EA0_RDREQ_LEVEL[23], TCC_EA0_RDREQ_LEVEL[24], TCC_EA0_RDREQ_LEVEL[25], TCC_EA0_RDREQ_LEVEL[26], TCC_EA0_RDREQ_LEVEL[27], TCC_EA0_RDREQ_LEVEL[28], TCC_EA0_RDREQ_LEVEL[29], TCC_EA0_RDREQ_LEVEL[2], TCC_EA0_RDREQ_LEVEL[30], TCC_EA0_RDREQ_LEVEL[31], TCC_EA0_RDREQ_LEVEL[32], TCC_EA0_RDREQ_LEVEL[33], TCC_EA0_RDREQ_LEVEL[34], TCC_EA0_RDREQ_LEVEL[35], TCC_EA0_RDREQ_LEVEL[36], TCC_EA0_RDREQ_LEVEL[37], TCC_EA0_RDREQ_LEVEL[38], TCC_EA0_RDREQ_LEVEL[39], TCC_EA0_RDREQ_LEVEL[3], TCC_EA0_RDREQ_LEVEL[40], TCC_EA0_RDREQ_LEVEL[41], TCC_EA0_RDREQ_LEVEL[42], TCC_EA0_RDREQ_LEVEL[43], TCC_EA0_RDREQ_LEVEL[44], TCC_EA0_RDREQ_LEVEL[45], TCC_EA0_RDREQ_LEVEL[46], TCC_EA0_RDREQ_LEVEL[47], TCC_EA0_RDREQ_LEVEL[48], TCC_EA0_RDREQ_LEVEL[49], TCC_EA0_RDREQ_LEVEL[4], TCC_EA0_RDREQ_LEVEL[50], TCC_EA0_RDREQ_LEVEL[51], TCC_EA0_RDREQ_LEVEL[52], TCC_EA0_RDREQ_LEVEL[53], TCC_EA0_RDREQ_LEVEL[54], TCC_EA0_RDREQ_LEVEL[55], TCC_EA0_RDREQ_LEVEL[56], TCC_EA0_RDREQ_LEVEL[57], TCC_EA0_RDREQ_LEVEL[58], TCC_EA0_RDREQ_LEVEL[59], TCC_EA0_RDREQ_LEVEL[5], TCC_EA0_RDREQ_LEVEL[60], TCC_EA0_RDREQ_LEVEL[61], TCC_EA0_RDREQ_LEVEL[62], TCC_EA0_RDREQ_LEVEL[63], TCC_EA0_RDREQ_LEVEL[64], TCC_EA0_RDREQ_LEVEL[65], TCC_EA0_RDREQ_LEVEL[66], TCC_EA0_RDREQ_LEVEL[67], TCC_EA0_RDREQ_LEVEL[68], TCC_EA0_RDREQ_LEVEL[69], TCC_EA0_RDREQ_LEVEL[6], TCC_EA0_RDREQ_LEVEL[70], TCC_EA0_RDREQ_LEVEL[71], TCC_EA0_RDREQ_LEVEL[72], TCC_EA0_RDREQ_LEVEL[73], TCC_EA0_RDREQ_LEVEL[74], TCC_EA0_RDREQ_LEVEL[75], TCC_EA0_RDREQ_LEVEL[76], TCC_EA0_RDREQ_LEVEL[77], TCC_EA0_RDREQ_LEVEL[78], TCC_EA0_RDREQ_LEVEL[79], TCC_EA0_RDREQ_LEVEL[7], TCC_EA0_RDREQ_LEVEL[80], TCC_EA0_RDREQ_LEVEL[81], TCC_EA0_RDREQ_LEVEL[82], TCC_EA0_RDREQ_LEVEL[83], TCC_EA0_RDREQ_LEVEL[84], TCC_EA0_RDREQ_LEVEL[85], TCC_EA0_RDREQ_LEVEL[86], TCC_EA0_RDREQ_LEVEL[87], TCC_EA0_RDREQ_LEVEL[88], TCC_EA0_RDREQ_LEVEL[89], TCC_EA0_RDREQ_LEVEL[8], TCC_EA0_RDREQ_LEVEL[90], TCC_EA0_RDREQ_LEVEL[91], TCC_EA0_RDREQ_LEVEL[92], TCC_EA0_RDREQ_LEVEL[93], TCC_EA0_RDREQ_LEVEL[94], TCC_EA0_RDREQ_LEVEL[95], TCC_EA0_RDREQ_LEVEL[96], TCC_EA0_RDREQ_LEVEL[97], TCC_EA0_RDREQ_LEVEL[98], TCC_EA0_RDREQ_LEVEL[99], TCC_EA0_RDREQ_LEVEL[9], TCC_TOO_MANY_EA_WRREQS_STALL[0], TCC_TOO_MANY_EA_WRREQS_STALL[100], TCC_TOO_MANY_EA_WRREQS_STALL[101], TCC_TOO_MANY_EA_WRREQS_STALL[102], TCC_TOO_MANY_EA_WRREQS_STALL[103], TCC_TOO_MANY_EA_WRREQS_STALL[104], TCC_TOO_MANY_EA_WRREQS_STALL[105], TCC_TOO_MANY_EA_WRREQS_STALL[106], TCC_TOO_MANY_EA_WRREQS_STALL[107], TCC_TOO_MANY_EA_WRREQS_STALL[108], TCC_TOO_MANY_EA_WRREQS_STALL[109], TCC_TOO_MANY_EA_WRREQS_STALL[10], TCC_TOO_MANY_EA_WRREQS_STALL[110], TCC_TOO_MANY_EA_WRREQS_STALL[111], TCC_TOO_MANY_EA_WRREQS_STALL[112], TCC_TOO_MANY_EA_WRREQS_STALL[113], TCC_TOO_MANY_EA_WRREQS_STALL[114], TCC_TOO_MANY_EA_WRREQS_STALL[115], TCC_TOO_MANY_EA_WRREQS_STALL[116], TCC_TOO_MANY_EA_WRREQS_STALL[117], TCC_TOO_MANY_EA_WRREQS_STALL[118], TCC_TOO_MANY_EA_WRREQS_STALL[119], TCC_TOO_MANY_EA_WRREQS_STALL[11], TCC_TOO_MANY_EA_WRREQS_STALL[120], TCC_TOO_MANY_EA_WRREQS_STALL[121], TCC_TOO_MANY_EA_WRREQS_STALL[122], TCC_TOO_MANY_EA_WRREQS_STALL[123], TCC_TOO_MANY_EA_WRREQS_STALL[124], TCC_TOO_MANY_EA_WRREQS_STALL[125], TCC_TOO_MANY_EA_WRREQS_STALL[126], TCC_TOO_MANY_EA_WRREQS_STALL[127], TCC_TOO_MANY_EA_WRREQS_STALL[12], TCC_TOO_MANY_EA_WRREQS_STALL[13], TCC_TOO_MANY_EA_WRREQS_STALL[14], TCC_TOO_MANY_EA_WRREQS_STALL[15], TCC_TOO_MANY_EA_WRREQS_STALL[16], TCC_TOO_MANY_EA_WRREQS_STALL[17], TCC_TOO_MANY_EA_WRREQS_STALL[18], TCC_TOO_MANY_EA_WRREQS_STALL[19], TCC_TOO_MANY_EA_WRREQS_STALL[1], TCC_TOO_MANY_EA_WRREQS_STALL[20], TCC_TOO_MANY_EA_WRREQS_STALL[21], TCC_TOO_MANY_EA_WRREQS_STALL[22], TCC_TOO_MANY_EA_WRREQS_STALL[23], TCC_TOO_MANY_EA_WRREQS_STALL[24], TCC_TOO_MANY_EA_WRREQS_STALL[25], TCC_TOO_MANY_EA_WRREQS_STALL[26], TCC_TOO_MANY_EA_WRREQS_STALL[27], TCC_TOO_MANY_EA_WRREQS_STALL[28], TCC_TOO_MANY_EA_WRREQS_STALL[29], TCC_TOO_MANY_EA_WRREQS_STALL[2], TCC_TOO_MANY_EA_WRREQS_STALL[30], TCC_TOO_MANY_EA_WRREQS_STALL[31], TCC_TOO_MANY_EA_WRREQS_STALL[32], TCC_TOO_MANY_EA_WRREQS_STALL[33], TCC_TOO_MANY_EA_WRREQS_STALL[34], TCC_TOO_MANY_EA_WRREQS_STALL[35], TCC_TOO_MANY_EA_WRREQS_STALL[36], TCC_TOO_MANY_EA_WRREQS_STALL[37], TCC_TOO_MANY_EA_WRREQS_STALL[38], TCC_TOO_MANY_EA_WRREQS_STALL[39], TCC_TOO_MANY_EA_WRREQS_STALL[3], TCC_TOO_MANY_EA_WRREQS_STALL[40], TCC_TOO_MANY_EA_WRREQS_STALL[41], TCC_TOO_MANY_EA_WRREQS_STALL[42], TCC_TOO_MANY_EA_WRREQS_STALL[43], TCC_TOO_MANY_EA_WRREQS_STALL[44], TCC_TOO_MANY_EA_WRREQS_STALL[45], TCC_TOO_MANY_EA_WRREQS_STALL[46], TCC_TOO_MANY_EA_WRREQS_STALL[47], TCC_TOO_MANY_EA_WRREQS_STALL[48], TCC_TOO_MANY_EA_WRREQS_STALL[49], TCC_TOO_MANY_EA_WRREQS_STALL[4], TCC_TOO_MANY_EA_WRREQS_STALL[50], TCC_TOO_MANY_EA_WRREQS_STALL[51], TCC_TOO_MANY_EA_WRREQS_STALL[52], TCC_TOO_MANY_EA_WRREQS_STALL[53], TCC_TOO_MANY_EA_WRREQS_STALL[54], TCC_TOO_MANY_EA_WRREQS_STALL[55], TCC_TOO_MANY_EA_WRREQS_STALL[56], TCC_TOO_MANY_EA_WRREQS_STALL[57], TCC_TOO_MANY_EA_WRREQS_STALL[58], TCC_TOO_MANY_EA_WRREQS_STALL[59], TCC_TOO_MANY_EA_WRREQS_STALL[5], TCC_TOO_MANY_EA_WRREQS_STALL[60], TCC_TOO_MANY_EA_WRREQS_STALL[61], TCC_TOO_MANY_EA_WRREQS_STALL[62], TCC_TOO_MANY_EA_WRREQS_STALL[63], TCC_TOO_MANY_EA_WRREQS_STALL[64], TCC_TOO_MANY_EA_WRREQS_STALL[65], TCC_TOO_MANY_EA_WRREQS_STALL[66], TCC_TOO_MANY_EA_WRREQS_STALL[67], TCC_TOO_MANY_EA_WRREQS_STALL[68], TCC_TOO_MANY_EA_WRREQS_STALL[69], TCC_TOO_MANY_EA_WRREQS_STALL[6], TCC_TOO_MANY_EA_WRREQS_STALL[70], TCC_TOO_MANY_EA_WRREQS_STALL[71], TCC_TOO_MANY_EA_WRREQS_STALL[72], TCC_TOO_MANY_EA_WRREQS_STALL[73], TCC_TOO_MANY_EA_WRREQS_STALL[74], TCC_TOO_MANY_EA_WRREQS_STALL[75], TCC_TOO_MANY_EA_WRREQS_STALL[76], TCC_TOO_MANY_EA_WRREQS_STALL[77], TCC_TOO_MANY_EA_WRREQS_STALL[78], TCC_TOO_MANY_EA_WRREQS_STALL[79], TCC_TOO_MANY_EA_WRREQS_STALL[7], TCC_TOO_MANY_EA_WRREQS_STALL[80], TCC_TOO_MANY_EA_WRREQS_STALL[81], TCC_TOO_MANY_EA_WRREQS_STALL[82], TCC_TOO_MANY_EA_WRREQS_STALL[83], TCC_TOO_MANY_EA_WRREQS_STALL[84], TCC_TOO_MANY_EA_WRREQS_STALL[85], TCC_TOO_MANY_EA_WRREQS_STALL[86], TCC_TOO_MANY_EA_WRREQS_STALL[87], TCC_TOO_MANY_EA_WRREQS_STALL[88], TCC_TOO_MANY_EA_WRREQS_STALL[89], TCC_TOO_MANY_EA_WRREQS_STALL[8], TCC_TOO_MANY_EA_WRREQS_STALL[90], TCC_TOO_MANY_EA_WRREQS_STALL[91], TCC_TOO_MANY_EA_WRREQS_STALL[92], TCC_TOO_MANY_EA_WRREQS_STALL[93], TCC_TOO_MANY_EA_WRREQS_STALL[94], TCC_TOO_MANY_EA_WRREQS_STALL[95], TCC_TOO_MANY_EA_WRREQS_STALL[96], TCC_TOO_MANY_EA_WRREQS_STALL[97], TCC_TOO_MANY_EA_WRREQS_STALL[98], TCC_TOO_MANY_EA_WRREQS_STALL[99], TCC_TOO_MANY_EA_WRREQS_STALL[9], TCP_GATE_EN2_sum, TCP_TCC_RW_WRITE_REQ_sum, TCP_TCC_UC_ATOMIC_REQ_sum, TCP_TOTAL_CACHE_ACCESSES_sum, TD_TD_BUSY_sum]. Found: [CPC_CPC_TCIU_IDLE, CPC_TG_SEND, CPF_CPF_TCIU_IDLE, SPI_CS0_BUSY, SPI_CS1_BUSY, SPI_CS2_BUSY, SPI_CS3_BUSY, SQ_INSTS_LDS, SQ_INSTS_LDS_LOAD_BANDWIDTH, SQ_INSTS_VALU_ADD_F16, SQ_INSTS_VALU_FMA_F16, SQ_LDS_IDX_ACTIVE, SQ_LEVEL_WAVES, SQ_WAVE_CYCLES, TA_BUFFER_ATOMIC_WAVEFRONTS_sum, TA_FLAT_ATOMIC_WAVEFRONTS_sum, TCC_BUBBLE_sum, TCC_EA0_ATOMIC_LEVEL[0], TCC_EA0_ATOMIC_LEVEL[100], TCC_EA0_ATOMIC_LEVEL[101], TCC_EA0_ATOMIC_LEVEL[102], TCC_EA0_ATOMIC_LEVEL[103], TCC_EA0_ATOMIC_LEVEL[104], TCC_EA0_ATOMIC_LEVEL[105], TCC_EA0_ATOMIC_LEVEL[106], TCC_EA0_ATOMIC_LEVEL[107], TCC_EA0_ATOMIC_LEVEL[108], TCC_EA0_ATOMIC_LEVEL[109], TCC_EA0_ATOMIC_LEVEL[10], TCC_EA0_ATOMIC_LEVEL[110], TCC_EA0_ATOMIC_LEVEL[111], TCC_EA0_ATOMIC_LEVEL[112], TCC_EA0_ATOMIC_LEVEL[113], TCC_EA0_ATOMIC_LEVEL[114], TCC_EA0_ATOMIC_LEVEL[115], TCC_EA0_ATOMIC_LEVEL[116], TCC_EA0_ATOMIC_LEVEL[117], TCC_EA0_ATOMIC_LEVEL[118], TCC_EA0_ATOMIC_LEVEL[119], TCC_EA0_ATOMIC_LEVEL[11], TCC_EA0_ATOMIC_LEVEL[120], TCC_EA0_ATOMIC_LEVEL[121], TCC_EA0_ATOMIC_LEVEL[122], TCC_EA0_ATOMIC_LEVEL[123], TCC_EA0_ATOMIC_LEVEL[124], TCC_EA0_ATOMIC_LEVEL[125], TCC_EA0_ATOMIC_LEVEL[126], TCC_EA0_ATOMIC_LEVEL[127], TCC_EA0_ATOMIC_LEVEL[12], TCC_EA0_ATOMIC_LEVEL[13], TCC_EA0_ATOMIC_LEVEL[14], TCC_EA0_ATOMIC_LEVEL[15], TCC_EA0_ATOMIC_LEVEL[16], TCC_EA0_ATOMIC_LEVEL[17], TCC_EA0_ATOMIC_LEVEL[18], TCC_EA0_ATOMIC_LEVEL[19], TCC_EA0_ATOMIC_LEVEL[1], TCC_EA0_ATOMIC_LEVEL[20], TCC_EA0_ATOMIC_LEVEL[21], TCC_EA0_ATOMIC_LEVEL[22], TCC_EA0_ATOMIC_LEVEL[23], TCC_EA0_ATOMIC_LEVEL[24], TCC_EA0_ATOMIC_LEVEL[25], TCC_EA0_ATOMIC_LEVEL[26], TCC_EA0_ATOMIC_LEVEL[27], TCC_EA0_ATOMIC_LEVEL[28], TCC_EA0_ATOMIC_LEVEL[29], TCC_EA0_ATOMIC_LEVEL[2], TCC_EA0_ATOMIC_LEVEL[30], TCC_EA0_ATOMIC_LEVEL[31], TCC_EA0_ATOMIC_LEVEL[32], TCC_EA0_ATOMIC_LEVEL[33], TCC_EA0_ATOMIC_LEVEL[34], TCC_EA0_ATOMIC_LEVEL[35], TCC_EA0_ATOMIC_LEVEL[36], TCC_EA0_ATOMIC_LEVEL[37], TCC_EA0_ATOMIC_LEVEL[38], TCC_EA0_ATOMIC_LEVEL[39], TCC_EA0_ATOMIC_LEVEL[3], TCC_EA0_ATOMIC_LEVEL[40], TCC_EA0_ATOMIC_LEVEL[41], TCC_EA0_ATOMIC_LEVEL[42], TCC_EA0_ATOMIC_LEVEL[43], TCC_EA0_ATOMIC_LEVEL[44], TCC_EA0_ATOMIC_LEVEL[45], TCC_EA0_ATOMIC_LEVEL[46], TCC_EA0_ATOMIC_LEVEL[47], TCC_EA0_ATOMIC_LEVEL[48], TCC_EA0_ATOMIC_LEVEL[49], TCC_EA0_ATOMIC_LEVEL[4], TCC_EA0_ATOMIC_LEVEL[50], TCC_EA0_ATOMIC_LEVEL[51], TCC_EA0_ATOMIC_LEVEL[52], TCC_EA0_ATOMIC_LEVEL[53], TCC_EA0_ATOMIC_LEVEL[54], TCC_EA0_ATOMIC_LEVEL[55], TCC_EA0_ATOMIC_LEVEL[56], TCC_EA0_ATOMIC_LEVEL[57], TCC_EA0_ATOMIC_LEVEL[58], TCC_EA0_ATOMIC_LEVEL[59], TCC_EA0_ATOMIC_LEVEL[5], TCC_EA0_ATOMIC_LEVEL[60], TCC_EA0_ATOMIC_LEVEL[61], TCC_EA0_ATOMIC_LEVEL[62], TCC_EA0_ATOMIC_LEVEL[63], TCC_EA0_ATOMIC_LEVEL[64], TCC_EA0_ATOMIC_LEVEL[65], TCC_EA0_ATOMIC_LEVEL[66], TCC_EA0_ATOMIC_LEVEL[67], TCC_EA0_ATOMIC_LEVEL[68], TCC_EA0_ATOMIC_LEVEL[69], TCC_EA0_ATOMIC_LEVEL[6], TCC_EA0_ATOMIC_LEVEL[70], TCC_EA0_ATOMIC_LEVEL[71], TCC_EA0_ATOMIC_LEVEL[72], TCC_EA0_ATOMIC_LEVEL[73], TCC_EA0_ATOMIC_LEVEL[74], TCC_EA0_ATOMIC_LEVEL[75], TCC_EA0_ATOMIC_LEVEL[76], TCC_EA0_ATOMIC_LEVEL[77], TCC_EA0_ATOMIC_LEVEL[78], TCC_EA0_ATOMIC_LEVEL[79], TCC_EA0_ATOMIC_LEVEL[7], TCC_EA0_ATOMIC_LEVEL[80], TCC_EA0_ATOMIC_LEVEL[81], TCC_EA0_ATOMIC_LEVEL[82], TCC_EA0_ATOMIC_LEVEL[83], TCC_EA0_ATOMIC_LEVEL[84], TCC_EA0_ATOMIC_LEVEL[85], TCC_EA0_ATOMIC_LEVEL[86], TCC_EA0_ATOMIC_LEVEL[87], TCC_EA0_ATOMIC_LEVEL[88], TCC_EA0_ATOMIC_LEVEL[89], TCC_EA0_ATOMIC_LEVEL[8], TCC_EA0_ATOMIC_LEVEL[90], TCC_EA0_ATOMIC_LEVEL[91], TCC_EA0_ATOMIC_LEVEL[92], TCC_EA0_ATOMIC_LEVEL[93], TCC_EA0_ATOMIC_LEVEL[94], TCC_EA0_ATOMIC_LEVEL[95], TCC_EA0_ATOMIC_LEVEL[96], TCC_EA0_ATOMIC_LEVEL[97], TCC_EA0_ATOMIC_LEVEL[98], TCC_EA0_ATOMIC_LEVEL[99], TCC_EA0_ATOMIC_LEVEL[9], TCC_EA0_RDREQ_LEVEL[0], TCC_EA0_RDREQ_LEVEL[100], TCC_EA0_RDREQ_LEVEL[101], TCC_EA0_RDREQ_LEVEL[102], TCC_EA0_RDREQ_LEVEL[103], TCC_EA0_RDREQ_LEVEL[104], TCC_EA0_RDREQ_LEVEL[105], TCC_EA0_RDREQ_LEVEL[106], TCC_EA0_RDREQ_LEVEL[107], TCC_EA0_RDREQ_LEVEL[108], TCC_EA0_RDREQ_LEVEL[109], TCC_EA0_RDREQ_LEVEL[10], TCC_EA0_RDREQ_LEVEL[110], TCC_EA0_RDREQ_LEVEL[111], TCC_EA0_RDREQ_LEVEL[112], TCC_EA0_RDREQ_LEVEL[113], TCC_EA0_RDREQ_LEVEL[114], TCC_EA0_RDREQ_LEVEL[115], TCC_EA0_RDREQ_LEVEL[116], TCC_EA0_RDREQ_LEVEL[117], TCC_EA0_RDREQ_LEVEL[118], TCC_EA0_RDREQ_LEVEL[119], TCC_EA0_RDREQ_LEVEL[11], TCC_EA0_RDREQ_LEVEL[120], TCC_EA0_RDREQ_LEVEL[121], TCC_EA0_RDREQ_LEVEL[122], TCC_EA0_RDREQ_LEVEL[123], TCC_EA0_RDREQ_LEVEL[124], TCC_EA0_RDREQ_LEVEL[125], TCC_EA0_RDREQ_LEVEL[126], TCC_EA0_RDREQ_LEVEL[127], TCC_EA0_RDREQ_LEVEL[12], TCC_EA0_RDREQ_LEVEL[13], TCC_EA0_RDREQ_LEVEL[14], TCC_EA0_RDREQ_LEVEL[15], TCC_EA0_RDREQ_LEVEL[16], TCC_EA0_RDREQ_LEVEL[17], TCC_EA0_RDREQ_LEVEL[18], TCC_EA0_RDREQ_LEVEL[19], TCC_EA0_RDREQ_LEVEL[1], TCC_EA0_RDREQ_LEVEL[20], TCC_EA0_RDREQ_LEVEL[21], TCC_EA0_RDREQ_LEVEL[22], TCC_EA0_RDREQ_LEVEL[23], TCC_EA0_RDREQ_LEVEL[24], TCC_EA0_RDREQ_LEVEL[25], TCC_EA0_RDREQ_LEVEL[26], TCC_EA0_RDREQ_LEVEL[27], TCC_EA0_RDREQ_LEVEL[28], TCC_EA0_RDREQ_LEVEL[29], TCC_EA0_RDREQ_LEVEL[2], TCC_EA0_RDREQ_LEVEL[30], TCC_EA0_RDREQ_LEVEL[31], TCC_EA0_RDREQ_LEVEL[32], TCC_EA0_RDREQ_LEVEL[33], TCC_EA0_RDREQ_LEVEL[34], TCC_EA0_RDREQ_LEVEL[35], TCC_EA0_RDREQ_LEVEL[36], TCC_EA0_RDREQ_LEVEL[37], TCC_EA0_RDREQ_LEVEL[38], TCC_EA0_RDREQ_LEVEL[39], TCC_EA0_RDREQ_LEVEL[3], TCC_EA0_RDREQ_LEVEL[40], TCC_EA0_RDREQ_LEVEL[41], TCC_EA0_RDREQ_LEVEL[42], TCC_EA0_RDREQ_LEVEL[43], TCC_EA0_RDREQ_LEVEL[44], TCC_EA0_RDREQ_LEVEL[45], TCC_EA0_RDREQ_LEVEL[46], TCC_EA0_RDREQ_LEVEL[47], TCC_EA0_RDREQ_LEVEL[48], TCC_EA0_RDREQ_LEVEL[49], TCC_EA0_RDREQ_LEVEL[4], TCC_EA0_RDREQ_LEVEL[50], TCC_EA0_RDREQ_LEVEL[51], TCC_EA0_RDREQ_LEVEL[52], TCC_EA0_RDREQ_LEVEL[53], TCC_EA0_RDREQ_LEVEL[54], TCC_EA0_RDREQ_LEVEL[55], TCC_EA0_RDREQ_LEVEL[56], TCC_EA0_RDREQ_LEVEL[57], TCC_EA0_RDREQ_LEVEL[58], TCC_EA0_RDREQ_LEVEL[59], TCC_EA0_RDREQ_LEVEL[5], TCC_EA0_RDREQ_LEVEL[60], TCC_EA0_RDREQ_LEVEL[61], TCC_EA0_RDREQ_LEVEL[62], TCC_EA0_RDREQ_LEVEL[63], TCC_EA0_RDREQ_LEVEL[64], TCC_EA0_RDREQ_LEVEL[65], TCC_EA0_RDREQ_LEVEL[66], TCC_EA0_RDREQ_LEVEL[67], TCC_EA0_RDREQ_LEVEL[68], TCC_EA0_RDREQ_LEVEL[69], TCC_EA0_RDREQ_LEVEL[6], TCC_EA0_RDREQ_LEVEL[70], TCC_EA0_RDREQ_LEVEL[71], TCC_EA0_RDREQ_LEVEL[72], TCC_EA0_RDREQ_LEVEL[73], TCC_EA0_RDREQ_LEVEL[74], TCC_EA0_RDREQ_LEVEL[75], TCC_EA0_RDREQ_LEVEL[76], TCC_EA0_RDREQ_LEVEL[77], TCC_EA0_RDREQ_LEVEL[78], TCC_EA0_RDREQ_LEVEL[79], TCC_EA0_RDREQ_LEVEL[7], TCC_EA0_RDREQ_LEVEL[80], TCC_EA0_RDREQ_LEVEL[81], TCC_EA0_RDREQ_LEVEL[82], TCC_EA0_RDREQ_LEVEL[83], TCC_EA0_RDREQ_LEVEL[84], TCC_EA0_RDREQ_LEVEL[85], TCC_EA0_RDREQ_LEVEL[86], TCC_EA0_RDREQ_LEVEL[87], TCC_EA0_RDREQ_LEVEL[88], TCC_EA0_RDREQ_LEVEL[89], TCC_EA0_RDREQ_LEVEL[8], TCC_EA0_RDREQ_LEVEL[90], TCC_EA0_RDREQ_LEVEL[91], TCC_EA0_RDREQ_LEVEL[92], TCC_EA0_RDREQ_LEVEL[93], TCC_EA0_RDREQ_LEVEL[94], TCC_EA0_RDREQ_LEVEL[95], TCC_EA0_RDREQ_LEVEL[96], TCC_EA0_RDREQ_LEVEL[97], TCC_EA0_RDREQ_LEVEL[98], TCC_EA0_RDREQ_LEVEL[99], TCC_EA0_RDREQ_LEVEL[9], TCC_TOO_MANY_EA_WRREQS_STALL[0], TCC_TOO_MANY_EA_WRREQS_STALL[100], TCC_TOO_MANY_EA_WRREQS_STALL[101], TCC_TOO_MANY_EA_WRREQS_STALL[102], TCC_TOO_MANY_EA_WRREQS_STALL[103], TCC_TOO_MANY_EA_WRREQS_STALL[104], TCC_TOO_MANY_EA_WRREQS_STALL[105], TCC_TOO_MANY_EA_WRREQS_STALL[106], TCC_TOO_MANY_EA_WRREQS_STALL[107], TCC_TOO_MANY_EA_WRREQS_STALL[108], TCC_TOO_MANY_EA_WRREQS_STALL[109], TCC_TOO_MANY_EA_WRREQS_STALL[10], TCC_TOO_MANY_EA_WRREQS_STALL[110], TCC_TOO_MANY_EA_WRREQS_STALL[111], TCC_TOO_MANY_EA_WRREQS_STALL[112], TCC_TOO_MANY_EA_WRREQS_STALL[113], TCC_TOO_MANY_EA_WRREQS_STALL[114], TCC_TOO_MANY_EA_WRREQS_STALL[115], TCC_TOO_MANY_EA_WRREQS_STALL[116], TCC_TOO_MANY_EA_WRREQS_STALL[117], TCC_TOO_MANY_EA_WRREQS_STALL[118], TCC_TOO_MANY_EA_WRREQS_STALL[119], TCC_TOO_MANY_EA_WRREQS_STALL[11], TCC_TOO_MANY_EA_WRREQS_STALL[120], TCC_TOO_MANY_EA_WRREQS_STALL[121], TCC_TOO_MANY_EA_WRREQS_STALL[122], TCC_TOO_MANY_EA_WRREQS_STALL[123], TCC_TOO_MANY_EA_WRREQS_STALL[124], TCC_TOO_MANY_EA_WRREQS_STALL[125], TCC_TOO_MANY_EA_WRREQS_STALL[126], TCC_TOO_MANY_EA_WRREQS_STALL[127], TCC_TOO_MANY_EA_WRREQS_STALL[12], TCC_TOO_MANY_EA_WRREQS_STALL[13], TCC_TOO_MANY_EA_WRREQS_STALL[14], TCC_TOO_MANY_EA_WRREQS_STALL[15], TCC_TOO_MANY_EA_WRREQS_STALL[16], TCC_TOO_MANY_EA_WRREQS_STALL[17], TCC_TOO_MANY_EA_WRREQS_STALL[18], TCC_TOO_MANY_EA_WRREQS_STALL[19], TCC_TOO_MANY_EA_WRREQS_STALL[1], TCC_TOO_MANY_EA_WRREQS_STALL[20], TCC_TOO_MANY_EA_WRREQS_STALL[21], TCC_TOO_MANY_EA_WRREQS_STALL[22], TCC_TOO_MANY_EA_WRREQS_STALL[23], TCC_TOO_MANY_EA_WRREQS_STALL[24], TCC_TOO_MANY_EA_WRREQS_STALL[25], TCC_TOO_MANY_EA_WRREQS_STALL[26], TCC_TOO_MANY_EA_WRREQS_STALL[27], TCC_TOO_MANY_EA_WRREQS_STALL[28], TCC_TOO_MANY_EA_WRREQS_STALL[29], TCC_TOO_MANY_EA_WRREQS_STALL[2], TCC_TOO_MANY_EA_WRREQS_STALL[30], TCC_TOO_MANY_EA_WRREQS_STALL[31], TCC_TOO_MANY_EA_WRREQS_STALL[32], TCC_TOO_MANY_EA_WRREQS_STALL[33], TCC_TOO_MANY_EA_WRREQS_STALL[34], TCC_TOO_MANY_EA_WRREQS_STALL[35], TCC_TOO_MANY_EA_WRREQS_STALL[36], TCC_TOO_MANY_EA_WRREQS_STALL[37], TCC_TOO_MANY_EA_WRREQS_STALL[38], TCC_TOO_MANY_EA_WRREQS_STALL[39], TCC_TOO_MANY_EA_WRREQS_STALL[3], TCC_TOO_MANY_EA_WRREQS_STALL[40], TCC_TOO_MANY_EA_WRREQS_STALL[41], TCC_TOO_MANY_EA_WRREQS_STALL[42], TCC_TOO_MANY_EA_WRREQS_STALL[43], TCC_TOO_MANY_EA_WRREQS_STALL[44], TCC_TOO_MANY_EA_WRREQS_STALL[45], TCC_TOO_MANY_EA_WRREQS_STALL[46], TCC_TOO_MANY_EA_WRREQS_STALL[47], TCC_TOO_MANY_EA_WRREQS_STALL[48], TCC_TOO_MANY_EA_WRREQS_STALL[49], TCC_TOO_MANY_EA_WRREQS_STALL[4], TCC_TOO_MANY_EA_WRREQS_STALL[50], TCC_TOO_MANY_EA_WRREQS_STALL[51], TCC_TOO_MANY_EA_WRREQS_STALL[52], TCC_TOO_MANY_EA_WRREQS_STALL[53], TCC_TOO_MANY_EA_WRREQS_STALL[54], TCC_TOO_MANY_EA_WRREQS_STALL[55], TCC_TOO_MANY_EA_WRREQS_STALL[56], TCC_TOO_MANY_EA_WRREQS_STALL[57], TCC_TOO_MANY_EA_WRREQS_STALL[58], TCC_TOO_MANY_EA_WRREQS_STALL[59], TCC_TOO_MANY_EA_WRREQS_STALL[5], TCC_TOO_MANY_EA_WRREQS_STALL[60], TCC_TOO_MANY_EA_WRREQS_STALL[61], TCC_TOO_MANY_EA_WRREQS_STALL[62], TCC_TOO_MANY_EA_WRREQS_STALL[63], TCC_TOO_MANY_EA_WRREQS_STALL[64], TCC_TOO_MANY_EA_WRREQS_STALL[65], TCC_TOO_MANY_EA_WRREQS_STALL[66], TCC_TOO_MANY_EA_WRREQS_STALL[67], TCC_TOO_MANY_EA_WRREQS_STALL[68], TCC_TOO_MANY_EA_WRREQS_STALL[69], TCC_TOO_MANY_EA_WRREQS_STALL[6], TCC_TOO_MANY_EA_WRREQS_STALL[70], TCC_TOO_MANY_EA_WRREQS_STALL[71], TCC_TOO_MANY_EA_WRREQS_STALL[72], TCC_TOO_MANY_EA_WRREQS_STALL[73], TCC_TOO_MANY_EA_WRREQS_STALL[74], TCC_TOO_MANY_EA_WRREQS_STALL[75], TCC_TOO_MANY_EA_WRREQS_STALL[76], TCC_TOO_MANY_EA_WRREQS_STALL[77], TCC_TOO_MANY_EA_WRREQS_STALL[78], TCC_TOO_MANY_EA_WRREQS_STALL[79], TCC_TOO_MANY_EA_WRREQS_STALL[7], TCC_TOO_MANY_EA_WRREQS_STALL[80], TCC_TOO_MANY_EA_WRREQS_STALL[81], TCC_TOO_MANY_EA_WRREQS_STALL[82], TCC_TOO_MANY_EA_WRREQS_STALL[83], TCC_TOO_MANY_EA_WRREQS_STALL[84], TCC_TOO_MANY_EA_WRREQS_STALL[85], TCC_TOO_MANY_EA_WRREQS_STALL[86], TCC_TOO_MANY_EA_WRREQS_STALL[87], TCC_TOO_MANY_EA_WRREQS_STALL[88], TCC_TOO_MANY_EA_WRREQS_STALL[89], TCC_TOO_MANY_EA_WRREQS_STALL[8], TCC_TOO_MANY_EA_WRREQS_STALL[90], TCC_TOO_MANY_EA_WRREQS_STALL[91], TCC_TOO_MANY_EA_WRREQS_STALL[92], TCC_TOO_MANY_EA_WRREQS_STALL[93], TCC_TOO_MANY_EA_WRREQS_STALL[94], TCC_TOO_MANY_EA_WRREQS_STALL[95], TCC_TOO_MANY_EA_WRREQS_STALL[96], TCC_TOO_MANY_EA_WRREQS_STALL[97], TCC_TOO_MANY_EA_WRREQS_STALL[98], TCC_TOO_MANY_EA_WRREQS_STALL[99], TCC_TOO_MANY_EA_WRREQS_STALL[9], TCP_GATE_EN2_sum, TCP_TCC_RW_WRITE_REQ_sum, TCP_TCC_UC_ATOMIC_REQ_sum, TCP_TOTAL_CACHE_ACCESSES_sum, TD_TD_BUSY_sum] + |-> [rocprofv3] E20250328 22:44:01.683144 139667039954944 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15765_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:01.689887 139667039954944 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15765_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:01.693434 139667039954944 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15765_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.txt, the time it takes was 0 m 0.5417661666870117 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.txt is 0 m 0.580467700958252 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_0.txt +pmc file: pmc_perf_0.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_0.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_0.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_0.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_0.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:02.244642 140133276805120 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15772_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:02.251155 140133276805120 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15772_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:02.254238 140133276805120 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15772_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_0.txt, the time it takes was 0 m 0.520763635635376 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_0.txt is 0 m 0.5509796142578125 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_1.txt +pmc file: pmc_perf_1.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_1.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_1.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_1.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_1.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:02.774198 139877934254080 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15779_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:02.780803 139877934254080 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15779_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:02.783965 139877934254080 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15779_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_1.txt, the time it takes was 0 m 0.49741554260253906 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_1.txt is 0 m 0.5275735855102539 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_2.txt +pmc file: pmc_perf_2.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_2.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_2.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_2.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_2.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:03.328143 140410203478016 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15786_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:03.334680 140410203478016 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15786_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:03.337819 140410203478016 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15786_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_2.txt, the time it takes was 0 m 0.5256781578063965 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_2.txt is 0 m 0.5558264255523682 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_3.txt +pmc file: pmc_perf_3.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_3.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_3.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_3.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_3.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:03.877474 139773391017984 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15793_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:03.884064 139773391017984 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15793_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:03.887175 139773391017984 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15793_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_3.txt, the time it takes was 0 m 0.5174272060394287 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_3.txt is 0 m 0.5471975803375244 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_4.txt +pmc file: pmc_perf_4.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_4.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_4.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_4.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_4.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:04.425381 139659083270144 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15800_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:04.431890 139659083270144 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15800_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:04.434992 139659083270144 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15800_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_4.txt, the time it takes was 0 m 0.5173399448394775 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_4.txt is 0 m 0.5455985069274902 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_5.txt +pmc file: pmc_perf_5.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_5.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_5.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_5.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_5.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:04.975746 139690974885888 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15807_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:04.982230 139690974885888 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15807_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:04.985304 139690974885888 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15807_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_5.txt, the time it takes was 0 m 0.5242176055908203 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_5.txt is 0 m 0.5536882877349854 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_6.txt +pmc file: pmc_perf_6.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_6.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_6.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_6.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_6.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:05.528937 139905476130816 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15814_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:05.535486 139905476130816 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15814_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:05.538574 139905476130816 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15814_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_6.txt, the time it takes was 0 m 0.5223171710968018 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_6.txt is 0 m 0.5513536930084229 sec +[profiling] Current input file: /app/workloads/vcopy/MI350/perfmon/pmc_perf_7.txt +pmc file: pmc_perf_7.txt +rocprof command: ['rocprofv3', '-E', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_7.yaml', '-i', '/app/workloads/vcopy/MI350/perfmon/pmc_perf_7.txt', '-d', '/app/workloads/vcopy/MI350/out', '--kernel-trace', '--output-format', 'csv', '--', 'tests/vcopy', '-n', '1048576', '-b', '256', '-i', '3'] +[subprocess] Running: rocprofv3 -E /app/workloads/vcopy/MI350/perfmon/pmc_perf_7.yaml -i /app/workloads/vcopy/MI350/perfmon/pmc_perf_7.txt -d /app/workloads/vcopy/MI350/out --kernel-trace --output-format csv -- tests/vcopy -n 1048576 -b 256 -i 3 + |-> [rocprofv3] E20250328 22:44:06.078683 140554574170112 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15821_kernel_trace.csv + |-> [rocprofv3] E20250328 22:44:06.085252 140554574170112 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15821_counter_collection.csv + |-> [rocprofv3] E20250328 22:44:06.088343 140554574170112 output_stream.cpp:105] Opened result file: /app/workloads/vcopy/MI350/out/pmc_1/f77021840818/15821_agent_info.csv + |-> [rocprofv3] vcopy testing on GCD 0 + |-> [rocprofv3] Finished allocating vectors on the CPU +Finishing subprocess of fname /app/workloads/vcopy/MI350/perfmon/pmc_perf_7.txt, the time it takes was 0 m 0.5185859203338623 sec +The type of Agent ID from counter csv file is int64 +The time of run_prof of /app/workloads/vcopy/MI350/perfmon/pmc_perf_7.txt is 0 m 0.5476455688476562 sec +finished "run_profiling" and finished rocprof's workload, time taken was 0 m 7.149999380111694 sec +[profiling] performing post-processing using rocprofv3 profiler +Successfully joined GPU_ID in pmc_perf.csv +Successfully joined Grid_Size in pmc_perf.csv +Successfully joined Workgroup_Size in pmc_perf.csv +Successfully joined LDS_Per_Workgroup in pmc_perf.csv +Successfully joined Scratch_Per_Workitem in pmc_perf.csv +Successfully joined SGPR in pmc_perf.csv +Successfully joined Arch_VGPR in pmc_perf.csv +Successfully joined Accum_VGPR in pmc_perf.csv +time taken for "post_processing" was 0 seconds +[profiling] perform SoC post processing for gfx950 +[roofline] Skipping roofline diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.txt new file mode 100644 index 0000000000..93204ab025 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.txt @@ -0,0 +1,5 @@ +pmc: SQ_IFETCH_LEVEL SQ_IFETCH_LEVEL_ACCUM SQ_VMEM_WR_TA_DATA_FIFO_FULL SQC_ICACHE_MISSES_DUPLICATE SQC_ICACHE_MISSES SQ_INSTS_VALU_MFMA_MOPS_I8 SQC_DCACHE_HITS SQ_INSTS_VALU_FMA_F64 TA_ADDR_STALLED_BY_TC_CYCLES_sum TA_FLAT_WAVEFRONTS_sum TD_TC_STALL_sum TD_ATOMIC_WAVEFRONT_sum TCP_TCC_RW_ATOMIC_REQ_sum TCP_TOTAL_WRITE_sum TCP_GATE_EN1_sum TCP_TCC_NC_ATOMIC_REQ_sum TCC_EA0_RDREQ[36] TCC_EA0_WRREQ_LEVEL[59] TCC_NC_REQ_sum TCC_EA0_RDREQ[4] TCC_REQ[106] TCC_REQ[95] TCC_EA0_RDREQ[105] TCC_REQ[4] TCC_EA0_RDREQ[71] TCC_REQ[58] TCC_EA0_WRREQ_LEVEL[4] TCC_EA0_WRREQ_LEVEL[30] TCC_EA0_WRREQ_LEVEL[11] TCC_EA0_WRREQ_LEVEL[87] TCC_EA0_WRREQ_LEVEL[121] TCC_REQ[45] TCC_EA0_RDREQ[76] TCC_EA0_WRREQ_LEVEL[79] TCC_EA0_RDREQ[92] TCC_EA0_WRREQ_LEVEL[31] TCC_EA0_RDREQ[102] TCC_REQ[43] TCC_EA0_WRREQ_LEVEL[91] TCC_REQ[51] TCC_REQ[114] TCC_EA0_RDREQ[40] TCC_EA0_RDREQ[49] TCC_REQ[116] TCC_EA0_WRREQ_LEVEL[113] TCC_EA0_WRREQ_LEVEL[48] TCC_EA0_WRREQ_LEVEL[60] TCC_EA0_WRREQ_LEVEL[50] TCC_EA0_WRREQ_LEVEL[19] TCC_REQ[57] TCC_EA0_RDREQ[5] TCC_REQ[16] TCC_REQ[54] TCC_EA0_WRREQ_LEVEL[63] TCC_REQ[78] TCC_REQ[81] TCC_EA0_RDREQ[39] TCC_EA0_RDREQ[19] TCC_EA0_RDREQ[91] TCC_REQ[98] TCC_REQ[34] TCC_EA0_WRREQ_LEVEL[5] TCC_EA0_RDREQ[28] TCC_REQ[70] TCC_REQ[105] TCC_EA0_RDREQ[125] TCC_EA0_WRREQ_LEVEL[3] TCC_EA0_RDREQ[0] TCC_EA0_RDREQ[79] TCC_EA0_RDREQ[60] TCC_EA0_RDREQ[78] TCC_EA0_RDREQ[17] TCC_EA0_RDREQ[48] TCC_EA0_RDREQ[1] TCC_EA0_WRREQ_LEVEL[7] TCC_EA0_WRREQ_LEVEL[61] TCC_EA0_WRREQ_LEVEL[116] TCC_EA0_WRREQ_LEVEL[107] TCC_REQ[111] TCC_REQ[9] TCC_EA0_WRREQ_LEVEL[65] TCC_EA0_RDREQ[88] TCC_REQ[2] TCC_EA0_RDREQ[101] TCC_REQ[69] TCC_REQ[22] TCC_REQ[24] TCC_EA0_WRREQ_LEVEL[100] TCC_EA0_WRREQ_LEVEL[29] TCC_EA0_WRREQ_LEVEL[27] TCC_EA0_RDREQ[20] TCC_EA0_WRREQ_LEVEL[37] TCC_EA0_RDREQ[30] TCC_EA0_RDREQ[127] TCC_EA0_WRREQ_LEVEL[17] TCC_EA0_WRREQ_LEVEL[28] TCC_EA0_WRREQ_LEVEL[67] TCC_REQ[59] TCC_EA0_RDREQ[121] TCC_REQ[40] TCC_EA0_RDREQ[73] TCC_EA0_WRREQ_LEVEL[76] TCC_EA0_RDREQ[98] TCC_REQ[38] TCC_EA0_WRREQ_LEVEL[118] TCC_EA0_WRREQ_LEVEL[122] TCC_EA0_WRREQ_LEVEL[77] TCC_EA0_RDREQ[68] TCC_REQ[85] TCC_EA0_WRREQ_LEVEL[127] TCC_EA0_RDREQ[37] TCC_REQ[66] TCC_REQ[28] TCC_EA0_WRREQ_LEVEL[97] TCC_EA0_WRREQ_LEVEL[90] TCC_REQ[1] TCC_REQ[39] TCC_EA0_WRREQ_LEVEL[25] TCC_EA0_WRREQ_LEVEL[45] TCC_EA0_WRREQ_LEVEL[38] TCC_EA0_RDREQ[32] TCC_EA0_RDREQ[25] TCC_EA0_RDREQ[97] TCC_EA0_RDREQ[42] TCC_REQ[108] TCC_EA0_RDREQ[67] TCC_EA0_WRREQ_LEVEL[39] TCC_EA0_WRREQ_LEVEL[16] TCC_EA0_WRREQ_LEVEL[2] TCC_REQ[112] TCC_EA0_RDREQ[111] TCC_EA0_WRREQ_LEVEL[36] TCC_EA0_RDREQ[47] TCC_REQ[93] TCC_REQ[17] TCC_EA0_RDREQ[122] TCC_EA0_WRREQ_LEVEL[35] TCC_EA0_RDREQ[126] TCC_REQ[8] TCC_EA0_WRREQ_LEVEL[86] TCC_REQ[90] TCC_EA0_WRREQ_LEVEL[66] TCC_EA0_WRREQ_LEVEL[26] TCC_EA0_RDREQ[2] TCC_REQ[109] TCC_EA0_RDREQ[64] TCC_EA0_WRREQ_LEVEL[92] TCC_EA0_RDREQ[75] TCC_EA0_RDREQ[124] TCC_EA0_RDREQ[58] TCC_REQ[126] TCC_REQ[123] TCC_EA0_RDREQ[80] TCC_REQ[32] TCC_EA0_RDREQ[65] TCC_REQ[62] TCC_REQ[10] TCC_EA0_RDREQ[56] TCC_REQ[0] TCC_EA0_RDREQ[103] TCC_REQ[67] TCC_EA0_WRREQ_LEVEL[114] TCC_EA0_WRREQ_LEVEL[18] TCC_EA0_WRREQ_LEVEL[117] TCC_EA0_RDREQ[12] TCC_EA0_WRREQ_LEVEL[98] TCC_EA0_WRREQ_LEVEL[21] TCC_REQ[47] TCC_EA0_RDREQ[13] TCC_EA0_RDREQ[66] TCC_REQ[61] TCC_EA0_WRREQ_LEVEL[69] TCC_EA0_RDREQ[35] TCC_EA0_RDREQ[123] TCC_REQ[35] TCC_EA0_RDREQ[34] TCC_REQ[83] TCC_EA0_RDREQ[44] TCC_REQ[88] TCC_EA0_WRREQ_LEVEL[20] TCC_REQ[53] TCC_REQ[52] TCC_REQ[19] TCC_EA0_RDREQ[100] TCC_REQ[7] TCC_REQ[72] TCC_REQ[87] TCC_REQ[44] TCC_EA0_WRREQ_LEVEL[34] TCC_EA0_WRREQ_LEVEL[9] TCC_REQ[80] TCC_EA0_RDREQ[11] TCC_EA0_RDREQ[6] TCC_EA0_RDREQ[113] TCC_EA0_RDREQ[110] TCC_EA0_WRREQ_LEVEL[101] TCC_EA0_RDREQ[24] TCC_REQ[103] TCC_REQ[101] TCC_REQ[11] TCC_REQ[6] TCC_REQ[37] TCC_EA0_WRREQ_LEVEL[51] TCC_EA0_RDREQ[93] TCC_EA0_WRREQ_LEVEL[73] TCC_EA0_RDREQ[90] TCC_REQ[42] TCC_EA0_WRREQ_LEVEL[75] TCC_EA0_RDREQ[9] TCC_REQ[115] TCC_EA0_WRREQ_LEVEL[10] TCC_EA0_WRREQ_LEVEL[103] TCC_REQ[124] TCC_EA0_RDREQ[84] TCC_REQ[50] TCC_REQ[25] TCC_EA0_RDREQ[74] TCC_REQ[122] TCC_REQ[125] TCC_REQ[55] TCC_REQ[48] TCC_REQ[18] TCC_EA0_RDREQ[61] TCC_EA0_RDREQ[99] TCC_REQ[94] TCC_EA0_RDREQ[54] TCC_EA0_RDREQ[10] TCC_EA0_RDREQ[45] TCC_EA0_WRREQ_LEVEL[72] TCC_EA0_RDREQ[85] TCC_EA0_RDREQ[62] TCC_REQ[120] TCC_EA0_RDREQ[21] TCC_REQ[56] TCC_REQ[31] TCC_EA0_RDREQ[86] TCC_EA0_WRREQ_LEVEL[78] TCC_REQ[60] TCC_EA0_WRREQ_LEVEL[23] TCC_EA0_WRREQ_LEVEL[42] TCC_EA0_WRREQ_LEVEL[125] TCC_EA0_WRREQ_LEVEL[56] TCC_REQ[86] TCC_EA0_WRREQ_LEVEL[14] TCC_EA0_WRREQ_LEVEL[126] TCC_EA0_WRREQ_LEVEL[57] TCC_EA0_WRREQ_LEVEL[120] TCC_EA0_WRREQ_LEVEL[81] TCC_EA0_RDREQ[83] TCC_EA0_RDREQ[26] TCC_REQ[41] TCC_REQ[12] TCC_REQ[15] TCC_REQ[13] TCC_EA0_WRREQ_LEVEL[119] TCC_EA0_WRREQ_LEVEL[12] TCC_REQ[23] TCC_REQ[127] TCC_EA0_WRREQ_LEVEL[64] TCC_REQ[121] TCC_EA0_RDREQ[118] TCC_EA0_WRREQ_LEVEL[96] TCC_REQ[71] TCC_EA0_RDREQ[106] TCC_EA0_WRREQ_LEVEL[41] TCC_EA0_RDREQ[112] TCC_REQ[91] TCC_REQ[107] TCC_EA0_WRREQ_LEVEL[106] TCC_EA0_WRREQ_LEVEL[6] TCC_REQ[74] TCC_REQ[46] TCC_EA0_WRREQ_LEVEL[74] TCC_EA0_RDREQ[38] TCC_EA0_WRREQ_LEVEL[33] TCC_EA0_WRREQ_LEVEL[54] TCC_EA0_WRREQ_LEVEL[112] TCC_REQ[73] TCC_EA0_WRREQ_LEVEL[53] TCC_REQ[110] TCC_REQ[82] TCC_EA0_WRREQ_LEVEL[93] TCC_EA0_RDREQ[69] TCC_REQ[63] TCC_EA0_RDREQ[119] TCC_EA0_RDREQ[33] TCC_EA0_WRREQ_LEVEL[102] TCC_EA0_WRREQ_LEVEL[105] TCC_REQ[117] TCC_EA0_WRREQ_LEVEL[104] TCC_EA0_RDREQ[107] TCC_EA0_WRREQ_LEVEL[47] TCC_EA0_WRREQ_LEVEL[15] TCC_EA0_WRREQ_LEVEL[22] TCC_EA0_WRREQ_LEVEL[108] TCC_EA0_WRREQ_LEVEL[13] TCC_EA0_WRREQ_LEVEL[80] TCC_EA0_WRREQ_LEVEL[1] TCC_REQ[76] TCC_EA0_WRREQ_LEVEL[110] TCC_EA0_WRREQ_LEVEL[109] TCC_EA0_RDREQ[57] TCC_EA0_WRREQ_LEVEL[111] TCC_EA0_WRREQ_LEVEL[88] TCC_EA0_WRREQ_LEVEL[83] TCC_EA0_RDREQ[116] TCC_REQ[3] TCC_EA0_RDREQ[114] TCC_EA0_RDREQ[22] TCC_REQ[49] TCC_REQ[27] TCC_EA0_RDREQ[70] TCC_REQ[33] TCC_EA0_WRREQ_LEVEL[82] TCC_EA0_RDREQ[94] TCC_EA0_WRREQ_LEVEL[8] TCC_REQ[92] TCC_EA0_WRREQ_LEVEL[94] TCC_EA0_RDREQ[72] TCC_REQ[102] TCC_REQ[118] TCC_EA0_WRREQ_LEVEL[95] TCC_EA0_RDREQ[18] TCC_EA0_RDREQ[46] TCC_EA0_WRREQ_LEVEL[55] TCC_REQ[30] TCC_EA0_WRREQ_LEVEL[52] TCC_EA0_RDREQ[120] TCC_EA0_RDREQ[63] TCC_EA0_RDREQ[81] TCC_EA0_RDREQ[15] TCC_REQ[29] TCC_EA0_RDREQ[7] TCC_REQ[64] TCC_REQ[97] TCC_EA0_WRREQ_LEVEL[84] TCC_EA0_RDREQ[95] TCC_REQ[100] TCC_EA0_RDREQ[23] TCC_EA0_RDREQ[53] TCC_EA0_WRREQ_LEVEL[85] TCC_EA0_RDREQ[59] TCC_EA0_RDREQ[96] TCC_REQ[119] TCC_REQ[5] TCC_REQ[65] TCC_EA0_WRREQ_LEVEL[24] TCC_EA0_WRREQ_LEVEL[115] TCC_EA0_WRREQ_LEVEL[71] TCC_EA0_RDREQ[16] TCC_EA0_WRREQ_LEVEL[0] TCC_EA0_WRREQ_LEVEL[99] TCC_REQ[21] TCC_EA0_WRREQ_LEVEL[44] TCC_EA0_RDREQ[29] TCC_EA0_WRREQ_LEVEL[124] TCC_REQ[14] TCC_EA0_RDREQ[31] TCC_EA0_RDREQ[43] TCC_REQ[89] TCC_EA0_RDREQ[104] TCC_EA0_RDREQ[82] TCC_REQ[104] TCC_EA0_RDREQ[8] TCC_EA0_WRREQ_LEVEL[46] TCC_EA0_RDREQ[89] TCC_EA0_RDREQ[115] TCC_EA0_WRREQ_LEVEL[58] TCC_REQ[99] TCC_REQ[113] TCC_EA0_WRREQ_LEVEL[40] TCC_EA0_WRREQ_LEVEL[43] TCC_REQ[36] TCC_REQ[77] TCC_EA0_WRREQ_LEVEL[32] TCC_EA0_RDREQ[51] TCC_REQ[75] TCC_EA0_RDREQ[109] TCC_EA0_RDREQ[117] TCC_EA0_RDREQ[41] TCC_REQ[79] TCC_EA0_RDREQ[55] TCC_EA0_WRREQ_LEVEL[89] TCC_EA0_RDREQ[87] TCC_EA0_RDREQ[77] TCC_EA0_WRREQ_LEVEL[49] TCC_REQ[20] TCC_EA0_RDREQ[3] TCC_EA0_RDREQ[14] TCC_REQ[68] TCC_REQ[26] TCC_REQ[96] TCC_EA0_RDREQ[52] TCC_EA0_WRREQ_LEVEL[62] TCC_EA0_RDREQ[108] TCC_EA0_WRREQ_LEVEL[68] TCC_EA0_WRREQ_LEVEL[123] TCC_EA0_RDREQ[27] TCC_EA0_RDREQ[50] TCC_EA0_WRREQ_LEVEL[70] TCC_REQ[84] CPC_SYNC_WRREQ_FIFO_BUSY CPC_ME1_BUSY_FOR_PACKET_DECODE CPF_CPF_STAT_BUSY CPF_CMP_UTCL1_STALL_ON_TRANSLATION SPI_CS2_WAVE SPI_CS0_WAVE SPI_CS1_WAVE SPI_CS3_WAVE GRBM_GUI_ACTIVE + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.yaml b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.yaml new file mode 100644 index 0000000000..ad757566f9 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_IFETCH_LEVEL.yaml @@ -0,0 +1,1925 @@ +SQ_IFETCH_LEVEL_ACCUM: + architectures: + gfx942/gfx941/gfx940/gfx90a: + expression: accumulate(SQ_IFETCH_LEVEL, HIGH_RES) + description: SQ_IFETCH_LEVEL accumulation +TCC_EA0_RDREQ[0]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 0th XCC and 0th channel +TCC_EA0_RDREQ[100]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 6th XCC and 4th channel +TCC_EA0_RDREQ[101]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 6th XCC and 5th channel +TCC_EA0_RDREQ[102]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 6th XCC and 6th channel +TCC_EA0_RDREQ[103]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 6th XCC and 7th channel +TCC_EA0_RDREQ[104]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 6th XCC and 8th channel +TCC_EA0_RDREQ[105]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 6th XCC and 9th channel +TCC_EA0_RDREQ[106]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 6th XCC and 10th channel +TCC_EA0_RDREQ[107]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 6th XCC and 11th channel +TCC_EA0_RDREQ[108]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 6th XCC and 12th channel +TCC_EA0_RDREQ[109]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 6th XCC and 13th channel +TCC_EA0_RDREQ[10]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 0th XCC and 10th channel +TCC_EA0_RDREQ[110]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 6th XCC and 14th channel +TCC_EA0_RDREQ[111]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 6th XCC and 15th channel +TCC_EA0_RDREQ[112]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 7th XCC and 0th channel +TCC_EA0_RDREQ[113]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 7th XCC and 1th channel +TCC_EA0_RDREQ[114]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 7th XCC and 2th channel +TCC_EA0_RDREQ[115]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 7th XCC and 3th channel +TCC_EA0_RDREQ[116]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 7th XCC and 4th channel +TCC_EA0_RDREQ[117]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 7th XCC and 5th channel +TCC_EA0_RDREQ[118]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 7th XCC and 6th channel +TCC_EA0_RDREQ[119]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 7th XCC and 7th channel +TCC_EA0_RDREQ[11]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 0th XCC and 11th channel +TCC_EA0_RDREQ[120]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 7th XCC and 8th channel +TCC_EA0_RDREQ[121]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 7th XCC and 9th channel +TCC_EA0_RDREQ[122]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 7th XCC and 10th channel +TCC_EA0_RDREQ[123]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 7th XCC and 11th channel +TCC_EA0_RDREQ[124]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 7th XCC and 12th channel +TCC_EA0_RDREQ[125]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 7th XCC and 13th channel +TCC_EA0_RDREQ[126]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 7th XCC and 14th channel +TCC_EA0_RDREQ[127]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 7th XCC and 15th channel +TCC_EA0_RDREQ[12]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 0th XCC and 12th channel +TCC_EA0_RDREQ[13]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 0th XCC and 13th channel +TCC_EA0_RDREQ[14]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 0th XCC and 14th channel +TCC_EA0_RDREQ[15]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 0th XCC and 15th channel +TCC_EA0_RDREQ[16]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 1th XCC and 0th channel +TCC_EA0_RDREQ[17]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 1th XCC and 1th channel +TCC_EA0_RDREQ[18]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 1th XCC and 2th channel +TCC_EA0_RDREQ[19]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 1th XCC and 3th channel +TCC_EA0_RDREQ[1]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 0th XCC and 1th channel +TCC_EA0_RDREQ[20]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 1th XCC and 4th channel +TCC_EA0_RDREQ[21]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 1th XCC and 5th channel +TCC_EA0_RDREQ[22]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 1th XCC and 6th channel +TCC_EA0_RDREQ[23]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 1th XCC and 7th channel +TCC_EA0_RDREQ[24]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 1th XCC and 8th channel +TCC_EA0_RDREQ[25]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 1th XCC and 9th channel +TCC_EA0_RDREQ[26]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 1th XCC and 10th channel +TCC_EA0_RDREQ[27]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 1th XCC and 11th channel +TCC_EA0_RDREQ[28]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 1th XCC and 12th channel +TCC_EA0_RDREQ[29]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 1th XCC and 13th channel +TCC_EA0_RDREQ[2]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 0th XCC and 2th channel +TCC_EA0_RDREQ[30]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 1th XCC and 14th channel +TCC_EA0_RDREQ[31]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 1th XCC and 15th channel +TCC_EA0_RDREQ[32]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 2th XCC and 0th channel +TCC_EA0_RDREQ[33]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 2th XCC and 1th channel +TCC_EA0_RDREQ[34]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 2th XCC and 2th channel +TCC_EA0_RDREQ[35]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 2th XCC and 3th channel +TCC_EA0_RDREQ[36]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 2th XCC and 4th channel +TCC_EA0_RDREQ[37]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 2th XCC and 5th channel +TCC_EA0_RDREQ[38]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 2th XCC and 6th channel +TCC_EA0_RDREQ[39]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 2th XCC and 7th channel +TCC_EA0_RDREQ[3]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 0th XCC and 3th channel +TCC_EA0_RDREQ[40]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 2th XCC and 8th channel +TCC_EA0_RDREQ[41]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 2th XCC and 9th channel +TCC_EA0_RDREQ[42]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 2th XCC and 10th channel +TCC_EA0_RDREQ[43]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 2th XCC and 11th channel +TCC_EA0_RDREQ[44]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 2th XCC and 12th channel +TCC_EA0_RDREQ[45]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 2th XCC and 13th channel +TCC_EA0_RDREQ[46]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 2th XCC and 14th channel +TCC_EA0_RDREQ[47]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 2th XCC and 15th channel +TCC_EA0_RDREQ[48]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 3th XCC and 0th channel +TCC_EA0_RDREQ[49]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 3th XCC and 1th channel +TCC_EA0_RDREQ[4]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 0th XCC and 4th channel +TCC_EA0_RDREQ[50]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 3th XCC and 2th channel +TCC_EA0_RDREQ[51]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 3th XCC and 3th channel +TCC_EA0_RDREQ[52]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 3th XCC and 4th channel +TCC_EA0_RDREQ[53]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 3th XCC and 5th channel +TCC_EA0_RDREQ[54]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 3th XCC and 6th channel +TCC_EA0_RDREQ[55]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 3th XCC and 7th channel +TCC_EA0_RDREQ[56]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 3th XCC and 8th channel +TCC_EA0_RDREQ[57]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 3th XCC and 9th channel +TCC_EA0_RDREQ[58]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 3th XCC and 10th channel +TCC_EA0_RDREQ[59]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 3th XCC and 11th channel +TCC_EA0_RDREQ[5]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 0th XCC and 5th channel +TCC_EA0_RDREQ[60]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 3th XCC and 12th channel +TCC_EA0_RDREQ[61]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 3th XCC and 13th channel +TCC_EA0_RDREQ[62]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 3th XCC and 14th channel +TCC_EA0_RDREQ[63]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 3th XCC and 15th channel +TCC_EA0_RDREQ[64]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 4th XCC and 0th channel +TCC_EA0_RDREQ[65]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 4th XCC and 1th channel +TCC_EA0_RDREQ[66]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 4th XCC and 2th channel +TCC_EA0_RDREQ[67]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 4th XCC and 3th channel +TCC_EA0_RDREQ[68]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 4th XCC and 4th channel +TCC_EA0_RDREQ[69]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 4th XCC and 5th channel +TCC_EA0_RDREQ[6]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 0th XCC and 6th channel +TCC_EA0_RDREQ[70]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 4th XCC and 6th channel +TCC_EA0_RDREQ[71]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 4th XCC and 7th channel +TCC_EA0_RDREQ[72]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 4th XCC and 8th channel +TCC_EA0_RDREQ[73]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 4th XCC and 9th channel +TCC_EA0_RDREQ[74]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 4th XCC and 10th channel +TCC_EA0_RDREQ[75]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 4th XCC and 11th channel +TCC_EA0_RDREQ[76]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 4th XCC and 12th channel +TCC_EA0_RDREQ[77]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 4th XCC and 13th channel +TCC_EA0_RDREQ[78]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 4th XCC and 14th channel +TCC_EA0_RDREQ[79]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 4th XCC and 15th channel +TCC_EA0_RDREQ[7]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 0th XCC and 7th channel +TCC_EA0_RDREQ[80]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 5th XCC and 0th channel +TCC_EA0_RDREQ[81]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 5th XCC and 1th channel +TCC_EA0_RDREQ[82]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 5th XCC and 2th channel +TCC_EA0_RDREQ[83]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 5th XCC and 3th channel +TCC_EA0_RDREQ[84]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ on 5th XCC and 4th channel +TCC_EA0_RDREQ[85]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ on 5th XCC and 5th channel +TCC_EA0_RDREQ[86]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ on 5th XCC and 6th channel +TCC_EA0_RDREQ[87]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ on 5th XCC and 7th channel +TCC_EA0_RDREQ[88]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 5th XCC and 8th channel +TCC_EA0_RDREQ[89]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 5th XCC and 9th channel +TCC_EA0_RDREQ[8]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ on 0th XCC and 8th channel +TCC_EA0_RDREQ[90]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ on 5th XCC and 10th channel +TCC_EA0_RDREQ[91]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ on 5th XCC and 11th channel +TCC_EA0_RDREQ[92]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ on 5th XCC and 12th channel +TCC_EA0_RDREQ[93]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ on 5th XCC and 13th channel +TCC_EA0_RDREQ[94]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ on 5th XCC and 14th channel +TCC_EA0_RDREQ[95]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ on 5th XCC and 15th channel +TCC_EA0_RDREQ[96]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ on 6th XCC and 0th channel +TCC_EA0_RDREQ[97]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ on 6th XCC and 1th channel +TCC_EA0_RDREQ[98]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ on 6th XCC and 2th channel +TCC_EA0_RDREQ[99]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ on 6th XCC and 3th channel +TCC_EA0_RDREQ[9]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ on 0th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[0]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[100]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[101]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[102]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[103]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[104]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[105]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[106]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[107]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[108]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[109]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[10]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[110]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[111]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[112]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[113]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[114]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[115]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[116]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[117]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[118]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[119]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[11]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[120]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[121]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[122]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[123]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[124]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[125]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[126]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[127]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 7th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[12]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[13]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[14]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[15]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[16]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[17]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[18]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[19]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[1]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[20]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[21]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[22]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[23]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[24]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[25]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[26]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[27]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[28]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[29]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[2]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[30]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[31]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 1th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[32]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[33]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[34]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[35]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[36]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[37]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[38]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[39]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[3]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[40]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[41]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[42]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[43]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[44]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[45]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[46]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[47]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 2th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[48]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[49]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[4]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[50]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[51]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[52]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[53]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[54]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[55]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[56]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[57]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[58]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[59]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[5]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[60]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[61]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[62]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[63]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 3th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[64]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[65]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[66]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[67]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[68]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[69]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[6]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[70]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[71]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[72]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[73]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[74]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[75]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[76]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[77]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[78]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[79]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 4th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[7]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[80]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[81]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[82]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[83]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[84]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 4th channel +TCC_EA0_WRREQ_LEVEL[85]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 5th channel +TCC_EA0_WRREQ_LEVEL[86]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 6th channel +TCC_EA0_WRREQ_LEVEL[87]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 7th channel +TCC_EA0_WRREQ_LEVEL[88]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[89]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 9th channel +TCC_EA0_WRREQ_LEVEL[8]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 8th channel +TCC_EA0_WRREQ_LEVEL[90]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 10th channel +TCC_EA0_WRREQ_LEVEL[91]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 11th channel +TCC_EA0_WRREQ_LEVEL[92]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 12th channel +TCC_EA0_WRREQ_LEVEL[93]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 13th channel +TCC_EA0_WRREQ_LEVEL[94]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 14th channel +TCC_EA0_WRREQ_LEVEL[95]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ_LEVEL on 5th XCC and 15th channel +TCC_EA0_WRREQ_LEVEL[96]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 0th channel +TCC_EA0_WRREQ_LEVEL[97]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 1th channel +TCC_EA0_WRREQ_LEVEL[98]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 2th channel +TCC_EA0_WRREQ_LEVEL[99]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ_LEVEL on 6th XCC and 3th channel +TCC_EA0_WRREQ_LEVEL[9]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ_LEVEL on 0th XCC and 9th channel +TCC_REQ[0]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 0th XCC and 0th channel +TCC_REQ[100]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 6th XCC and 4th channel +TCC_REQ[101]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 6th XCC and 5th channel +TCC_REQ[102]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 6th XCC and 6th channel +TCC_REQ[103]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 6th XCC and 7th channel +TCC_REQ[104]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 6th XCC and 8th channel +TCC_REQ[105]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 6th XCC and 9th channel +TCC_REQ[106]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 6th XCC and 10th channel +TCC_REQ[107]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 6th XCC and 11th channel +TCC_REQ[108]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 6th XCC and 12th channel +TCC_REQ[109]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 6th XCC and 13th channel +TCC_REQ[10]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 0th XCC and 10th channel +TCC_REQ[110]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 6th XCC and 14th channel +TCC_REQ[111]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 6th XCC and 15th channel +TCC_REQ[112]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 7th XCC and 0th channel +TCC_REQ[113]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 7th XCC and 1th channel +TCC_REQ[114]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 7th XCC and 2th channel +TCC_REQ[115]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 7th XCC and 3th channel +TCC_REQ[116]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 7th XCC and 4th channel +TCC_REQ[117]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 7th XCC and 5th channel +TCC_REQ[118]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 7th XCC and 6th channel +TCC_REQ[119]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 7th XCC and 7th channel +TCC_REQ[11]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 0th XCC and 11th channel +TCC_REQ[120]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 7th XCC and 8th channel +TCC_REQ[121]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 7th XCC and 9th channel +TCC_REQ[122]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 7th XCC and 10th channel +TCC_REQ[123]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 7th XCC and 11th channel +TCC_REQ[124]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 7th XCC and 12th channel +TCC_REQ[125]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 7th XCC and 13th channel +TCC_REQ[126]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 7th XCC and 14th channel +TCC_REQ[127]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 7th XCC and 15th channel +TCC_REQ[12]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 0th XCC and 12th channel +TCC_REQ[13]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 0th XCC and 13th channel +TCC_REQ[14]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 0th XCC and 14th channel +TCC_REQ[15]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 0th XCC and 15th channel +TCC_REQ[16]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 1th XCC and 0th channel +TCC_REQ[17]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 1th XCC and 1th channel +TCC_REQ[18]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 1th XCC and 2th channel +TCC_REQ[19]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 1th XCC and 3th channel +TCC_REQ[1]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 0th XCC and 1th channel +TCC_REQ[20]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 1th XCC and 4th channel +TCC_REQ[21]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 1th XCC and 5th channel +TCC_REQ[22]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 1th XCC and 6th channel +TCC_REQ[23]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 1th XCC and 7th channel +TCC_REQ[24]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 1th XCC and 8th channel +TCC_REQ[25]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 1th XCC and 9th channel +TCC_REQ[26]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 1th XCC and 10th channel +TCC_REQ[27]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 1th XCC and 11th channel +TCC_REQ[28]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 1th XCC and 12th channel +TCC_REQ[29]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 1th XCC and 13th channel +TCC_REQ[2]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 0th XCC and 2th channel +TCC_REQ[30]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 1th XCC and 14th channel +TCC_REQ[31]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 1th XCC and 15th channel +TCC_REQ[32]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 2th XCC and 0th channel +TCC_REQ[33]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 2th XCC and 1th channel +TCC_REQ[34]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 2th XCC and 2th channel +TCC_REQ[35]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 2th XCC and 3th channel +TCC_REQ[36]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 2th XCC and 4th channel +TCC_REQ[37]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 2th XCC and 5th channel +TCC_REQ[38]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 2th XCC and 6th channel +TCC_REQ[39]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 2th XCC and 7th channel +TCC_REQ[3]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 0th XCC and 3th channel +TCC_REQ[40]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 2th XCC and 8th channel +TCC_REQ[41]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 2th XCC and 9th channel +TCC_REQ[42]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 2th XCC and 10th channel +TCC_REQ[43]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 2th XCC and 11th channel +TCC_REQ[44]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 2th XCC and 12th channel +TCC_REQ[45]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 2th XCC and 13th channel +TCC_REQ[46]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 2th XCC and 14th channel +TCC_REQ[47]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 2th XCC and 15th channel +TCC_REQ[48]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 3th XCC and 0th channel +TCC_REQ[49]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 3th XCC and 1th channel +TCC_REQ[4]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 0th XCC and 4th channel +TCC_REQ[50]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 3th XCC and 2th channel +TCC_REQ[51]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 3th XCC and 3th channel +TCC_REQ[52]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 3th XCC and 4th channel +TCC_REQ[53]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 3th XCC and 5th channel +TCC_REQ[54]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 3th XCC and 6th channel +TCC_REQ[55]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 3th XCC and 7th channel +TCC_REQ[56]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 3th XCC and 8th channel +TCC_REQ[57]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 3th XCC and 9th channel +TCC_REQ[58]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 3th XCC and 10th channel +TCC_REQ[59]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 3th XCC and 11th channel +TCC_REQ[5]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 0th XCC and 5th channel +TCC_REQ[60]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 3th XCC and 12th channel +TCC_REQ[61]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 3th XCC and 13th channel +TCC_REQ[62]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 3th XCC and 14th channel +TCC_REQ[63]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 3th XCC and 15th channel +TCC_REQ[64]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 4th XCC and 0th channel +TCC_REQ[65]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 4th XCC and 1th channel +TCC_REQ[66]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 4th XCC and 2th channel +TCC_REQ[67]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 4th XCC and 3th channel +TCC_REQ[68]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 4th XCC and 4th channel +TCC_REQ[69]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 4th XCC and 5th channel +TCC_REQ[6]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 0th XCC and 6th channel +TCC_REQ[70]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 4th XCC and 6th channel +TCC_REQ[71]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 4th XCC and 7th channel +TCC_REQ[72]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 4th XCC and 8th channel +TCC_REQ[73]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 4th XCC and 9th channel +TCC_REQ[74]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 4th XCC and 10th channel +TCC_REQ[75]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 4th XCC and 11th channel +TCC_REQ[76]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 4th XCC and 12th channel +TCC_REQ[77]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 4th XCC and 13th channel +TCC_REQ[78]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 4th XCC and 14th channel +TCC_REQ[79]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 4th XCC and 15th channel +TCC_REQ[7]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 0th XCC and 7th channel +TCC_REQ[80]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 5th XCC and 0th channel +TCC_REQ[81]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 5th XCC and 1th channel +TCC_REQ[82]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 5th XCC and 2th channel +TCC_REQ[83]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 5th XCC and 3th channel +TCC_REQ[84]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_REQ on 5th XCC and 4th channel +TCC_REQ[85]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_REQ on 5th XCC and 5th channel +TCC_REQ[86]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_REQ on 5th XCC and 6th channel +TCC_REQ[87]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_REQ on 5th XCC and 7th channel +TCC_REQ[88]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 5th XCC and 8th channel +TCC_REQ[89]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 5th XCC and 9th channel +TCC_REQ[8]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_REQ on 0th XCC and 8th channel +TCC_REQ[90]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_REQ on 5th XCC and 10th channel +TCC_REQ[91]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_REQ on 5th XCC and 11th channel +TCC_REQ[92]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_REQ on 5th XCC and 12th channel +TCC_REQ[93]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_REQ on 5th XCC and 13th channel +TCC_REQ[94]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_REQ on 5th XCC and 14th channel +TCC_REQ[95]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_REQ on 5th XCC and 15th channel +TCC_REQ[96]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_REQ on 6th XCC and 0th channel +TCC_REQ[97]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_REQ on 6th XCC and 1th channel +TCC_REQ[98]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_REQ on 6th XCC and 2th channel +TCC_REQ[99]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_REQ on 6th XCC and 3th channel +TCC_REQ[9]: + architectures: + gfx950: + expression: select(TCC_REQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_REQ on 0th XCC and 9th channel diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.txt new file mode 100644 index 0000000000..68dad9e8a5 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.txt @@ -0,0 +1,5 @@ +pmc: SQ_INST_LEVEL_LDS SQ_INST_LEVEL_LDS_ACCUM SQC_DCACHE_ATOMIC SQC_TC_STALL SQC_ICACHE_REQ SQC_DCACHE_MISSES SQ_INSTS_VALU_MUL_F16 SQ_WAVES_SAVED TA_BUFFER_WRITE_WAVEFRONTS_sum TA_TA_BUSY_sum TCP_TCC_ATOMIC_WITH_RET_REQ_sum TCP_UTCL1_REQUEST_sum TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum TCP_TOTAL_WRITEBACK_INVALIDATES_sum TCC_EA0_WRREQ_sum TCC_TOO_MANY_EA_WRREQS_STALL_sum TCC_ATOMIC_sum TCC_EA0_ATOMIC_LEVEL_sum CPC_ME1_DC0_SPI_BUSY CPC_CPC_TCIU_BUSY SPI_VWC0_VDATA_VALID_WR SPI_RA_REQ_NO_ALLOC_CSN + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.yaml b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.yaml new file mode 100644 index 0000000000..7e20aab5a9 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_LDS.yaml @@ -0,0 +1,5 @@ +SQ_INST_LEVEL_LDS_ACCUM: + architectures: + gfx942/gfx941/gfx940/gfx90a: + expression: accumulate(SQ_INST_LEVEL_LDS, HIGH_RES) + description: SQ_INST_LEVEL_LDS accumulation diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt new file mode 100644 index 0000000000..07699d7d74 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.txt @@ -0,0 +1,5 @@ +pmc: SQ_INST_LEVEL_SMEM SQ_INST_LEVEL_SMEM_ACCUM SQ_INSTS_LDS_LOAD SQ_LDS_CMD_FIFO_FULL SQ_BUSY_CU_CYCLES SQ_INSTS_LDS_STORE SQC_DCACHE_REQ_READ_16 SQ_INSTS_VALU_MUL_F64 TA_FLAT_READ_WAVEFRONTS_sum TA_BUFFER_TOTAL_CYCLES_sum TD_STORE_WAVEFRONT_sum TD_LOAD_WAVEFRONT_sum TCP_UTCL1_TRANSLATION_HIT_sum TCP_TOTAL_ATOMIC_WITH_RET_sum TCP_TCC_UC_READ_REQ_sum TCP_TA_TCP_STATE_READ_sum TCC_HIT[110] TCC_ATOMIC[112] TCC_HIT[49] TCC_ATOMIC[54] TCC_EA0_ATOMIC[108] TCC_BUBBLE[121] TCC_HIT[33] TCC_HIT[87] TCC_EA0_ATOMIC[44] TCC_BUBBLE[75] TCC_HIT[5] TCC_EA0_ATOMIC[96] TCC_EA0_ATOMIC[121] TCC_ATOMIC[72] TCC_HIT[123] TCC_ATOMIC[26] TCC_ATOMIC[88] TCC_ATOMIC[69] TCC_EA0_ATOMIC[79] TCC_BUBBLE[107] TCC_ATOMIC[81] TCC_HIT[100] TCC_HIT[84] TCC_ATOMIC[28] TCC_BUBBLE[82] TCC_HIT[9] TCC_BUBBLE[36] TCC_HIT[78] TCC_HIT[4] TCC_EA0_ATOMIC[66] TCC_HIT[48] TCC_HIT[79] TCC_EA0_ATOMIC[19] TCC_ATOMIC[91] TCC_EA0_ATOMIC[103] TCC_BUBBLE[109] TCC_BUBBLE[122] TCC_ATOMIC[48] TCC_EA0_ATOMIC[10] TCC_BUBBLE[24] TCC_EA0_ATOMIC[64] TCC_ATOMIC[39] TCC_ATOMIC[38] TCC_BUBBLE[53] TCC_ATOMIC[20] TCC_BUBBLE[96] TCC_HIT[12] TCC_BUBBLE[67] TCC_BUBBLE[87] TCC_HIT[126] TCC_BUBBLE[5] TCC_EA0_ATOMIC[46] TCC_ATOMIC[25] TCC_EA0_ATOMIC[118] TCC_EA0_ATOMIC[107] TCC_EA0_ATOMIC[26] TCC_HIT[75] TCC_HIT[7] TCC_EA0_ATOMIC[50] TCC_HIT[32] TCC_BUBBLE[39] TCC_EA0_ATOMIC[23] TCC_EA0_ATOMIC[61] TCC_BUBBLE[12] TCC_EA0_ATOMIC[62] TCC_BUBBLE[76] TCC_BUBBLE[8] TCC_EA0_ATOMIC[76] TCC_ATOMIC[40] TCC_HIT[80] TCC_HIT[115] TCC_EA0_ATOMIC[38] TCC_ATOMIC[45] TCC_EA0_ATOMIC[8] TCC_EA0_ATOMIC[42] TCC_HIT[52] TCC_BUBBLE[31] TCC_HIT[56] TCC_BUBBLE[32] TCC_HIT[47] TCC_ATOMIC[36] TCC_BUBBLE[43] TCC_ATOMIC[35] TCC_BUBBLE[23] TCC_ATOMIC[51] TCC_HIT[29] TCC_HIT[15] TCC_HIT[35] TCC_EA0_ATOMIC[67] TCC_HIT[51] TCC_EA0_ATOMIC[30] TCC_HIT[104] TCC_ATOMIC[115] TCC_EA0_ATOMIC[21] TCC_BUBBLE[26] TCC_HIT[124] TCC_HIT[92] TCC_EA0_ATOMIC[1] TCC_EA0_ATOMIC[72] TCC_HIT[93] TCC_HIT[28] TCC_HIT[8] TCC_EA0_ATOMIC[52] TCC_EA0_ATOMIC[32] TCC_BUBBLE[14] TCC_ATOMIC[66] TCC_EA0_ATOMIC[97] TCC_HIT[101] TCC_HIT[89] TCC_BUBBLE[106] TCC_EA0_ATOMIC[28] TCC_BUBBLE[99] TCC_BUBBLE[55] TCC_BUBBLE[110] TCC_ATOMIC[2] TCC_EA0_ATOMIC[7] TCC_EA0_ATOMIC[82] TCC_HIT[38] TCC_ATOMIC[110] TCC_BUBBLE[64] TCC_HIT[77] TCC_ATOMIC[86] TCC_BUBBLE[68] TCC_ATOMIC[4] TCC_BUBBLE[127] TCC_EA0_ATOMIC[54] TCC_BUBBLE[9] TCC_BUBBLE[3] TCC_EA0_ATOMIC[20] TCC_HIT[26] TCC_ATOMIC[22] TCC_BUBBLE[54] TCC_ATOMIC[96] TCC_EA0_ATOMIC[35] TCC_EA0_ATOMIC[126] TCC_ATOMIC[33] TCC_HIT[118] TCC_HIT[31] TCC_ATOMIC[95] TCC_EA0_ATOMIC[90] TCC_BUBBLE[105] TCC_BUBBLE[22] TCC_HIT[97] TCC_ATOMIC[113] TCC_ATOMIC[98] TCC_ATOMIC[63] TCC_ATOMIC[99] TCC_EA0_ATOMIC[15] TCC_ATOMIC[106] TCC_EA0_ATOMIC[14] TCC_HIT[19] TCC_BUBBLE[11] TCC_EA0_ATOMIC[70] TCC_BUBBLE[88] TCC_ATOMIC[82] TCC_ATOMIC[50] TCC_EA0_ATOMIC[51] TCC_HIT[46] TCC_HIT[1] TCC_EA0_ATOMIC[111] TCC_HIT[73] TCC_ATOMIC[41] TCC_ATOMIC[78] TCC_BUBBLE[17] TCC_ATOMIC[61] TCC_HIT[114] TCC_ATOMIC[44] TCC_BUBBLE[13] TCC_ATOMIC[57] TCC_ATOMIC[101] TCC_EA0_ATOMIC[122] TCC_EA0_ATOMIC[40] TCC_ATOMIC[67] TCC_BUBBLE[97] TCC_EA0_ATOMIC[113] TCC_HIT[36] TCC_BUBBLE[63] TCC_EA0_ATOMIC[77] TCC_HIT[58] TCC_EA0_ATOMIC[99] TCC_ATOMIC[89] TCC_ATOMIC[97] TCC_EA0_ATOMIC[47] TCC_EA0_ATOMIC[63] TCC_HIT[98] TCC_HIT[10] TCC_EA0_ATOMIC[123] TCC_HIT[86] TCC_HIT[106] TCC_EA0_ATOMIC[58] TCC_HIT[67] TCC_HIT[91] TCC_ATOMIC[105] TCC_HIT[121] TCC_HIT[64] TCC_BUBBLE[41] TCC_ATOMIC[29] TCC_BUBBLE[79] TCC_BUBBLE[115] TCC_ATOMIC[107] TCC_EA0_ATOMIC[89] TCC_EA0_ATOMIC[36] TCC_BUBBLE[50] TCC_BUBBLE[92] TCC_BUBBLE[48] TCC_EA0_ATOMIC[27] TCC_BUBBLE[81] TCC_BUBBLE[113] TCC_ATOMIC[127] TCC_HIT[16] TCC_BUBBLE[103] TCC_EA0_ATOMIC[12] TCC_ATOMIC[90] TCC_ATOMIC[16] TCC_EA0_ATOMIC[22] TCC_EA0_ATOMIC[41] TCC_BUBBLE[72] TCC_HIT[60] TCC_BUBBLE[66] TCC_ATOMIC[77] TCC_HIT[61] TCC_HIT[88] TCC_EA0_ATOMIC[11] TCC_ATOMIC[9] TCC_EA0_ATOMIC[88] TCC_ATOMIC[103] TCC_BUBBLE[6] TCC_HIT[37] TCC_ATOMIC[18] TCC_HIT[14] TCC_BUBBLE[118] TCC_EA0_ATOMIC[65] TCC_ATOMIC[116] TCC_EA0_ATOMIC[125] TCC_ATOMIC[83] TCC_BUBBLE[117] TCC_EA0_ATOMIC[106] TCC_HIT[0] TCC_HIT[71] TCC_EA0_ATOMIC[31] TCC_BUBBLE[91] TCC_EA0_ATOMIC[100] TCC_ATOMIC[75] TCC_ATOMIC[6] TCC_HIT[39] TCC_BUBBLE[7] TCC_BUBBLE[40] TCC_EA0_ATOMIC[39] TCC_EA0_ATOMIC[55] TCC_EA0_ATOMIC[56] TCC_BUBBLE[34] TCC_BUBBLE[52] TCC_ATOMIC[125] TCC_EA0_ATOMIC[80] TCC_HIT[70] TCC_BUBBLE[49] TCC_BUBBLE[20] TCC_ATOMIC[62] TCC_BUBBLE[4] TCC_HIT[6] TCC_ATOMIC[10] TCC_EA0_ATOMIC[120] TCC_HIT[127] TCC_ATOMIC[124] TCC_HIT[3] TCC_ATOMIC[70] TCC_EA0_ATOMIC[34] TCC_EA0_ATOMIC[3] TCC_HIT[120] TCC_BUBBLE[27] TCC_EA0_ATOMIC[5] TCC_ATOMIC[8] TCC_HIT[54] TCC_BUBBLE[10] TCC_BUBBLE[101] TCC_BUBBLE[19] TCC_HIT[62] TCC_HIT[85] TCC_ATOMIC[119] TCC_ATOMIC[76] TCC_HIT[103] TCC_EA0_ATOMIC[75] TCC_BUBBLE[102] TCC_ATOMIC[87] TCC_BUBBLE[56] TCC_EA0_ATOMIC[104] TCC_HIT[25] TCC_BUBBLE[47] TCC_EA0_ATOMIC[87] TCC_ATOMIC[46] TCC_HIT[125] TCC_HIT[13] TCC_ATOMIC[100] TCC_HIT[43] TCC_BUBBLE[15] TCC_BUBBLE[59] TCC_ATOMIC[85] TCC_ATOMIC[93] TCC_ATOMIC[68] TCC_ATOMIC[84] TCC_EA0_ATOMIC[81] TCC_BUBBLE[124] TCC_BUBBLE[123] TCC_EA0_ATOMIC[98] TCC_ATOMIC[13] TCC_ATOMIC[60] TCC_BUBBLE[70] TCC_HIT[30] TCC_HIT[23] TCC_BUBBLE[60] TCC_ATOMIC[37] TCC_EA0_ATOMIC[101] TCC_EA0_ATOMIC[116] TCC_ATOMIC[1] TCC_ATOMIC[80] TCC_ATOMIC[7] TCC_EA0_ATOMIC[110] TCC_BUBBLE[93] TCC_BUBBLE[126] TCC_ATOMIC[12] TCC_ATOMIC[74] TCC_HIT[117] TCC_ATOMIC[31] TCC_HIT[22] TCC_HIT[76] TCC_BUBBLE[104] TCC_HIT[55] TCC_EA0_ATOMIC[105] TCC_HIT[18] TCC_HIT[119] TCC_BUBBLE[33] TCC_HIT[34] TCC_BUBBLE[125] TCC_EA0_ATOMIC[13] TCC_EA0_ATOMIC[2] TCC_EA0_ATOMIC[48] TCC_HIT[111] TCC_HIT[109] TCC_EA0_ATOMIC[109] TCC_BUBBLE[114] TCC_BUBBLE[45] TCC_HIT[102] TCC_ATOMIC[27] TCC_BUBBLE[61] TCC_HIT[96] TCC_EA0_ATOMIC[74] TCC_BUBBLE[111] TCC_HIT[82] TCC_ATOMIC[59] TCC_HIT[21] TCC_EA0_ATOMIC[124] TCC_BUBBLE[0] TCC_ATOMIC[24] TCC_EA0_ATOMIC[114] TCC_BUBBLE[94] TCC_BUBBLE[108] TCC_BUBBLE[83] TCC_BUBBLE[95] TCC_HIT[41] TCC_HIT[53] TCC_HIT[20] TCC_ATOMIC[3] TCC_ATOMIC[55] TCC_BUBBLE[16] TCC_HIT[95] TCC_EA0_ATOMIC[49] TCC_EA0_ATOMIC[9] TCC_EA0_ATOMIC[68] TCC_ATOMIC[34] TCC_HIT[24] TCC_BUBBLE[98] TCC_ATOMIC[117] TCC_BUBBLE[28] TCC_BUBBLE[80] TCC_ATOMIC[108] TCC_ATOMIC[122] TCC_ATOMIC[5] TCC_EA0_ATOMIC[119] TCC_BUBBLE[44] TCC_BUBBLE[116] TCC_EA0_ATOMIC[59] TCC_EA0_ATOMIC[78] TCC_ATOMIC[64] TCC_EA0_ATOMIC[0] TCC_BUBBLE[90] TCC_EA0_ATOMIC[43] TCC_HIT[11] TCC_ATOMIC[71] TCC_HIT[68] TCC_BUBBLE[77] TCC_EA0_ATOMIC[37] TCC_BUBBLE[21] TCC_BUBBLE[112] TCC_ATOMIC[14] TCC_BUBBLE[120] TCC_EA0_ATOMIC[17] TCC_ATOMIC[23] TCC_BUBBLE[51] TCC_BUBBLE[57] TCC_EA0_ATOMIC[53] TCC_EA0_ATOMIC[93] TCC_EA0_ATOMIC[115] TCC_ATOMIC[32] TCC_EA0_ATOMIC[94] TCC_EA0_ATOMIC[4] TCC_BUBBLE[84] TCC_EA0_ATOMIC[33] TCC_ATOMIC[94] TCC_HIT[44] TCC_ATOMIC[43] TCC_ATOMIC[111] TCC_BUBBLE[30] TCC_EA0_ATOMIC[57] TCC_BUBBLE[2] TCC_BUBBLE[73] TCC_HIT[90] TCC_ATOMIC[73] TCC_EA0_ATOMIC[84] TCC_EA0_ATOMIC[86] TCC_EA0_ATOMIC[91] TCC_EA0_ATOMIC[6] TCC_EA0_ATOMIC[117] TCC_ATOMIC[104] TCC_BUBBLE[46] TCC_ATOMIC[126] TCC_BUBBLE[62] TCC_HIT[81] TCC_HIT[2] TCC_EA0_ATOMIC[73] TCC_BUBBLE[69] TCC_ATOMIC[49] TCC_BUBBLE[71] TCC_ATOMIC[109] TCC_EA0_ATOMIC[85] TCC_BUBBLE[35] TCC_ATOMIC[118] TCC_BUBBLE[37] TCC_ATOMIC[79] TCC_HIT[66] TCC_HIT[63] TCC_HIT[107] TCC_ATOMIC[15] TCC_EA0_ATOMIC[24] TCC_EA0_ATOMIC[127] TCC_ATOMIC[102] TCC_ATOMIC[58] TCC_BUBBLE[74] TCC_ATOMIC[121] TCC_HIT[40] TCC_BUBBLE[65] TCC_EA0_ATOMIC[45] TCC_ATOMIC[42] TCC_HIT[108] TCC_ATOMIC[114] TCC_BUBBLE[89] TCC_EA0_ATOMIC[102] TCC_BUBBLE[42] TCC_BUBBLE[119] TCC_HIT[94] TCC_BUBBLE[78] TCC_BUBBLE[25] TCC_ATOMIC[52] TCC_ATOMIC[19] TCC_HIT[65] TCC_ATOMIC[30] TCC_ATOMIC[65] TCC_BUBBLE[38] TCC_HIT[17] TCC_BUBBLE[85] TCC_HIT[112] TCC_EA0_ATOMIC[29] TCC_EA0_ATOMIC[25] TCC_ATOMIC[17] TCC_EA0_ATOMIC[60] TCC_EA0_ATOMIC[83] TCC_BUBBLE[58] TCC_HIT[83] TCC_HIT[59] TCC_BUBBLE[100] TCC_ATOMIC[56] TCC_HIT[122] TCC_EA0_ATOMIC[16] TCC_ATOMIC[21] TCC_EA0_ATOMIC[92] TCC_HIT[42] TCC_EA0_ATOMIC[71] TCC_HIT[74] TCC_ATOMIC[53] TCC_HIT[45] TCC_EA0_ATOMIC[95] TCC_ATOMIC[123] TCC_ATOMIC[47] TCC_HIT[57] TCC_HIT[69] TCC_ATOMIC[120] TCC_EA0_ATOMIC[69] TCC_HIT[50] TCC_ATOMIC[92] TCC_EA0_ATOMIC[112] TCC_HIT[105] TCC_HIT[27] TCC_BUBBLE[1] TCC_EA0_ATOMIC[18] TCC_HIT[72] TCC_BUBBLE[86] TCC_ATOMIC[11] TCC_HIT[113] TCC_BUBBLE[18] TCC_HIT[99] TCC_ATOMIC[0] TCC_BUBBLE[29] TCC_HIT[116] CPC_CPC_STAT_IDLE CPC_CPC_STAT_BUSY CPF_CPF_STAT_STALL CPF_CPF_STAT_IDLE SPI_RA_SGPR_SIMD_FULL_CSN SPI_CSQ_P1_OCCUPANCY SPI_CSQ_P2_OCCUPANCY SPI_CSQ_P0_OCCUPANCY SPI_CSQ_P3_OCCUPANCY + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.yaml b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.yaml new file mode 100644 index 0000000000..a8c352b332 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_SMEM.yaml @@ -0,0 +1,2565 @@ +SQ_INST_LEVEL_SMEM_ACCUM: + architectures: + gfx942/gfx941/gfx940/gfx90a: + expression: accumulate(SQ_INST_LEVEL_SMEM, HIGH_RES) + description: SQ_INST_LEVEL_SMEM accumulation +TCC_ATOMIC[0]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 0th XCC and 0th channel +TCC_ATOMIC[100]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 6th XCC and 4th channel +TCC_ATOMIC[101]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 6th XCC and 5th channel +TCC_ATOMIC[102]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 6th XCC and 6th channel +TCC_ATOMIC[103]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 6th XCC and 7th channel +TCC_ATOMIC[104]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 6th XCC and 8th channel +TCC_ATOMIC[105]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 6th XCC and 9th channel +TCC_ATOMIC[106]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 6th XCC and 10th channel +TCC_ATOMIC[107]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 6th XCC and 11th channel +TCC_ATOMIC[108]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 6th XCC and 12th channel +TCC_ATOMIC[109]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 6th XCC and 13th channel +TCC_ATOMIC[10]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 0th XCC and 10th channel +TCC_ATOMIC[110]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 6th XCC and 14th channel +TCC_ATOMIC[111]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 6th XCC and 15th channel +TCC_ATOMIC[112]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 7th XCC and 0th channel +TCC_ATOMIC[113]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 7th XCC and 1th channel +TCC_ATOMIC[114]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 7th XCC and 2th channel +TCC_ATOMIC[115]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 7th XCC and 3th channel +TCC_ATOMIC[116]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 7th XCC and 4th channel +TCC_ATOMIC[117]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 7th XCC and 5th channel +TCC_ATOMIC[118]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 7th XCC and 6th channel +TCC_ATOMIC[119]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 7th XCC and 7th channel +TCC_ATOMIC[11]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 0th XCC and 11th channel +TCC_ATOMIC[120]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 7th XCC and 8th channel +TCC_ATOMIC[121]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 7th XCC and 9th channel +TCC_ATOMIC[122]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 7th XCC and 10th channel +TCC_ATOMIC[123]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 7th XCC and 11th channel +TCC_ATOMIC[124]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 7th XCC and 12th channel +TCC_ATOMIC[125]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 7th XCC and 13th channel +TCC_ATOMIC[126]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 7th XCC and 14th channel +TCC_ATOMIC[127]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 7th XCC and 15th channel +TCC_ATOMIC[12]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 0th XCC and 12th channel +TCC_ATOMIC[13]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 0th XCC and 13th channel +TCC_ATOMIC[14]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 0th XCC and 14th channel +TCC_ATOMIC[15]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 0th XCC and 15th channel +TCC_ATOMIC[16]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 1th XCC and 0th channel +TCC_ATOMIC[17]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 1th XCC and 1th channel +TCC_ATOMIC[18]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 1th XCC and 2th channel +TCC_ATOMIC[19]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 1th XCC and 3th channel +TCC_ATOMIC[1]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 0th XCC and 1th channel +TCC_ATOMIC[20]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 1th XCC and 4th channel +TCC_ATOMIC[21]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 1th XCC and 5th channel +TCC_ATOMIC[22]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 1th XCC and 6th channel +TCC_ATOMIC[23]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 1th XCC and 7th channel +TCC_ATOMIC[24]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 1th XCC and 8th channel +TCC_ATOMIC[25]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 1th XCC and 9th channel +TCC_ATOMIC[26]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 1th XCC and 10th channel +TCC_ATOMIC[27]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 1th XCC and 11th channel +TCC_ATOMIC[28]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 1th XCC and 12th channel +TCC_ATOMIC[29]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 1th XCC and 13th channel +TCC_ATOMIC[2]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 0th XCC and 2th channel +TCC_ATOMIC[30]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 1th XCC and 14th channel +TCC_ATOMIC[31]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 1th XCC and 15th channel +TCC_ATOMIC[32]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 2th XCC and 0th channel +TCC_ATOMIC[33]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 2th XCC and 1th channel +TCC_ATOMIC[34]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 2th XCC and 2th channel +TCC_ATOMIC[35]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 2th XCC and 3th channel +TCC_ATOMIC[36]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 2th XCC and 4th channel +TCC_ATOMIC[37]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 2th XCC and 5th channel +TCC_ATOMIC[38]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 2th XCC and 6th channel +TCC_ATOMIC[39]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 2th XCC and 7th channel +TCC_ATOMIC[3]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 0th XCC and 3th channel +TCC_ATOMIC[40]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 2th XCC and 8th channel +TCC_ATOMIC[41]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 2th XCC and 9th channel +TCC_ATOMIC[42]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 2th XCC and 10th channel +TCC_ATOMIC[43]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 2th XCC and 11th channel +TCC_ATOMIC[44]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 2th XCC and 12th channel +TCC_ATOMIC[45]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 2th XCC and 13th channel +TCC_ATOMIC[46]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 2th XCC and 14th channel +TCC_ATOMIC[47]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 2th XCC and 15th channel +TCC_ATOMIC[48]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 3th XCC and 0th channel +TCC_ATOMIC[49]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 3th XCC and 1th channel +TCC_ATOMIC[4]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 0th XCC and 4th channel +TCC_ATOMIC[50]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 3th XCC and 2th channel +TCC_ATOMIC[51]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 3th XCC and 3th channel +TCC_ATOMIC[52]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 3th XCC and 4th channel +TCC_ATOMIC[53]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 3th XCC and 5th channel +TCC_ATOMIC[54]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 3th XCC and 6th channel +TCC_ATOMIC[55]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 3th XCC and 7th channel +TCC_ATOMIC[56]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 3th XCC and 8th channel +TCC_ATOMIC[57]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 3th XCC and 9th channel +TCC_ATOMIC[58]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 3th XCC and 10th channel +TCC_ATOMIC[59]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 3th XCC and 11th channel +TCC_ATOMIC[5]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 0th XCC and 5th channel +TCC_ATOMIC[60]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 3th XCC and 12th channel +TCC_ATOMIC[61]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 3th XCC and 13th channel +TCC_ATOMIC[62]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 3th XCC and 14th channel +TCC_ATOMIC[63]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 3th XCC and 15th channel +TCC_ATOMIC[64]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 4th XCC and 0th channel +TCC_ATOMIC[65]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 4th XCC and 1th channel +TCC_ATOMIC[66]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 4th XCC and 2th channel +TCC_ATOMIC[67]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 4th XCC and 3th channel +TCC_ATOMIC[68]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 4th XCC and 4th channel +TCC_ATOMIC[69]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 4th XCC and 5th channel +TCC_ATOMIC[6]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 0th XCC and 6th channel +TCC_ATOMIC[70]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 4th XCC and 6th channel +TCC_ATOMIC[71]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 4th XCC and 7th channel +TCC_ATOMIC[72]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 4th XCC and 8th channel +TCC_ATOMIC[73]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 4th XCC and 9th channel +TCC_ATOMIC[74]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 4th XCC and 10th channel +TCC_ATOMIC[75]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 4th XCC and 11th channel +TCC_ATOMIC[76]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 4th XCC and 12th channel +TCC_ATOMIC[77]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 4th XCC and 13th channel +TCC_ATOMIC[78]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 4th XCC and 14th channel +TCC_ATOMIC[79]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 4th XCC and 15th channel +TCC_ATOMIC[7]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 0th XCC and 7th channel +TCC_ATOMIC[80]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 5th XCC and 0th channel +TCC_ATOMIC[81]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 5th XCC and 1th channel +TCC_ATOMIC[82]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 5th XCC and 2th channel +TCC_ATOMIC[83]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 5th XCC and 3th channel +TCC_ATOMIC[84]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_ATOMIC on 5th XCC and 4th channel +TCC_ATOMIC[85]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_ATOMIC on 5th XCC and 5th channel +TCC_ATOMIC[86]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_ATOMIC on 5th XCC and 6th channel +TCC_ATOMIC[87]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_ATOMIC on 5th XCC and 7th channel +TCC_ATOMIC[88]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 5th XCC and 8th channel +TCC_ATOMIC[89]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 5th XCC and 9th channel +TCC_ATOMIC[8]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_ATOMIC on 0th XCC and 8th channel +TCC_ATOMIC[90]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_ATOMIC on 5th XCC and 10th channel +TCC_ATOMIC[91]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_ATOMIC on 5th XCC and 11th channel +TCC_ATOMIC[92]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_ATOMIC on 5th XCC and 12th channel +TCC_ATOMIC[93]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_ATOMIC on 5th XCC and 13th channel +TCC_ATOMIC[94]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_ATOMIC on 5th XCC and 14th channel +TCC_ATOMIC[95]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_ATOMIC on 5th XCC and 15th channel +TCC_ATOMIC[96]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_ATOMIC on 6th XCC and 0th channel +TCC_ATOMIC[97]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_ATOMIC on 6th XCC and 1th channel +TCC_ATOMIC[98]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_ATOMIC on 6th XCC and 2th channel +TCC_ATOMIC[99]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_ATOMIC on 6th XCC and 3th channel +TCC_ATOMIC[9]: + architectures: + gfx950: + expression: select(TCC_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_ATOMIC on 0th XCC and 9th channel +TCC_BUBBLE[0]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 0th XCC and 0th channel +TCC_BUBBLE[100]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 6th XCC and 4th channel +TCC_BUBBLE[101]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 6th XCC and 5th channel +TCC_BUBBLE[102]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 6th XCC and 6th channel +TCC_BUBBLE[103]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 6th XCC and 7th channel +TCC_BUBBLE[104]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 6th XCC and 8th channel +TCC_BUBBLE[105]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 6th XCC and 9th channel +TCC_BUBBLE[106]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 6th XCC and 10th channel +TCC_BUBBLE[107]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 6th XCC and 11th channel +TCC_BUBBLE[108]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 6th XCC and 12th channel +TCC_BUBBLE[109]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 6th XCC and 13th channel +TCC_BUBBLE[10]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 0th XCC and 10th channel +TCC_BUBBLE[110]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 6th XCC and 14th channel +TCC_BUBBLE[111]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 6th XCC and 15th channel +TCC_BUBBLE[112]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 7th XCC and 0th channel +TCC_BUBBLE[113]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 7th XCC and 1th channel +TCC_BUBBLE[114]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 7th XCC and 2th channel +TCC_BUBBLE[115]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 7th XCC and 3th channel +TCC_BUBBLE[116]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 7th XCC and 4th channel +TCC_BUBBLE[117]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 7th XCC and 5th channel +TCC_BUBBLE[118]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 7th XCC and 6th channel +TCC_BUBBLE[119]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 7th XCC and 7th channel +TCC_BUBBLE[11]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 0th XCC and 11th channel +TCC_BUBBLE[120]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 7th XCC and 8th channel +TCC_BUBBLE[121]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 7th XCC and 9th channel +TCC_BUBBLE[122]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 7th XCC and 10th channel +TCC_BUBBLE[123]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 7th XCC and 11th channel +TCC_BUBBLE[124]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 7th XCC and 12th channel +TCC_BUBBLE[125]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 7th XCC and 13th channel +TCC_BUBBLE[126]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 7th XCC and 14th channel +TCC_BUBBLE[127]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 7th XCC and 15th channel +TCC_BUBBLE[12]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 0th XCC and 12th channel +TCC_BUBBLE[13]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 0th XCC and 13th channel +TCC_BUBBLE[14]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 0th XCC and 14th channel +TCC_BUBBLE[15]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 0th XCC and 15th channel +TCC_BUBBLE[16]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 1th XCC and 0th channel +TCC_BUBBLE[17]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 1th XCC and 1th channel +TCC_BUBBLE[18]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 1th XCC and 2th channel +TCC_BUBBLE[19]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 1th XCC and 3th channel +TCC_BUBBLE[1]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 0th XCC and 1th channel +TCC_BUBBLE[20]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 1th XCC and 4th channel +TCC_BUBBLE[21]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 1th XCC and 5th channel +TCC_BUBBLE[22]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 1th XCC and 6th channel +TCC_BUBBLE[23]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 1th XCC and 7th channel +TCC_BUBBLE[24]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 1th XCC and 8th channel +TCC_BUBBLE[25]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 1th XCC and 9th channel +TCC_BUBBLE[26]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 1th XCC and 10th channel +TCC_BUBBLE[27]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 1th XCC and 11th channel +TCC_BUBBLE[28]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 1th XCC and 12th channel +TCC_BUBBLE[29]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 1th XCC and 13th channel +TCC_BUBBLE[2]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 0th XCC and 2th channel +TCC_BUBBLE[30]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 1th XCC and 14th channel +TCC_BUBBLE[31]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 1th XCC and 15th channel +TCC_BUBBLE[32]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 2th XCC and 0th channel +TCC_BUBBLE[33]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 2th XCC and 1th channel +TCC_BUBBLE[34]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 2th XCC and 2th channel +TCC_BUBBLE[35]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 2th XCC and 3th channel +TCC_BUBBLE[36]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 2th XCC and 4th channel +TCC_BUBBLE[37]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 2th XCC and 5th channel +TCC_BUBBLE[38]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 2th XCC and 6th channel +TCC_BUBBLE[39]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 2th XCC and 7th channel +TCC_BUBBLE[3]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 0th XCC and 3th channel +TCC_BUBBLE[40]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 2th XCC and 8th channel +TCC_BUBBLE[41]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 2th XCC and 9th channel +TCC_BUBBLE[42]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 2th XCC and 10th channel +TCC_BUBBLE[43]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 2th XCC and 11th channel +TCC_BUBBLE[44]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 2th XCC and 12th channel +TCC_BUBBLE[45]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 2th XCC and 13th channel +TCC_BUBBLE[46]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 2th XCC and 14th channel +TCC_BUBBLE[47]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 2th XCC and 15th channel +TCC_BUBBLE[48]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 3th XCC and 0th channel +TCC_BUBBLE[49]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 3th XCC and 1th channel +TCC_BUBBLE[4]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 0th XCC and 4th channel +TCC_BUBBLE[50]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 3th XCC and 2th channel +TCC_BUBBLE[51]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 3th XCC and 3th channel +TCC_BUBBLE[52]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 3th XCC and 4th channel +TCC_BUBBLE[53]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 3th XCC and 5th channel +TCC_BUBBLE[54]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 3th XCC and 6th channel +TCC_BUBBLE[55]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 3th XCC and 7th channel +TCC_BUBBLE[56]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 3th XCC and 8th channel +TCC_BUBBLE[57]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 3th XCC and 9th channel +TCC_BUBBLE[58]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 3th XCC and 10th channel +TCC_BUBBLE[59]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 3th XCC and 11th channel +TCC_BUBBLE[5]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 0th XCC and 5th channel +TCC_BUBBLE[60]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 3th XCC and 12th channel +TCC_BUBBLE[61]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 3th XCC and 13th channel +TCC_BUBBLE[62]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 3th XCC and 14th channel +TCC_BUBBLE[63]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 3th XCC and 15th channel +TCC_BUBBLE[64]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 4th XCC and 0th channel +TCC_BUBBLE[65]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 4th XCC and 1th channel +TCC_BUBBLE[66]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 4th XCC and 2th channel +TCC_BUBBLE[67]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 4th XCC and 3th channel +TCC_BUBBLE[68]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 4th XCC and 4th channel +TCC_BUBBLE[69]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 4th XCC and 5th channel +TCC_BUBBLE[6]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 0th XCC and 6th channel +TCC_BUBBLE[70]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 4th XCC and 6th channel +TCC_BUBBLE[71]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 4th XCC and 7th channel +TCC_BUBBLE[72]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 4th XCC and 8th channel +TCC_BUBBLE[73]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 4th XCC and 9th channel +TCC_BUBBLE[74]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 4th XCC and 10th channel +TCC_BUBBLE[75]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 4th XCC and 11th channel +TCC_BUBBLE[76]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 4th XCC and 12th channel +TCC_BUBBLE[77]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 4th XCC and 13th channel +TCC_BUBBLE[78]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 4th XCC and 14th channel +TCC_BUBBLE[79]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 4th XCC and 15th channel +TCC_BUBBLE[7]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 0th XCC and 7th channel +TCC_BUBBLE[80]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 5th XCC and 0th channel +TCC_BUBBLE[81]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 5th XCC and 1th channel +TCC_BUBBLE[82]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 5th XCC and 2th channel +TCC_BUBBLE[83]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 5th XCC and 3th channel +TCC_BUBBLE[84]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_BUBBLE on 5th XCC and 4th channel +TCC_BUBBLE[85]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_BUBBLE on 5th XCC and 5th channel +TCC_BUBBLE[86]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_BUBBLE on 5th XCC and 6th channel +TCC_BUBBLE[87]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_BUBBLE on 5th XCC and 7th channel +TCC_BUBBLE[88]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 5th XCC and 8th channel +TCC_BUBBLE[89]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 5th XCC and 9th channel +TCC_BUBBLE[8]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_BUBBLE on 0th XCC and 8th channel +TCC_BUBBLE[90]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_BUBBLE on 5th XCC and 10th channel +TCC_BUBBLE[91]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_BUBBLE on 5th XCC and 11th channel +TCC_BUBBLE[92]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_BUBBLE on 5th XCC and 12th channel +TCC_BUBBLE[93]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_BUBBLE on 5th XCC and 13th channel +TCC_BUBBLE[94]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_BUBBLE on 5th XCC and 14th channel +TCC_BUBBLE[95]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_BUBBLE on 5th XCC and 15th channel +TCC_BUBBLE[96]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_BUBBLE on 6th XCC and 0th channel +TCC_BUBBLE[97]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_BUBBLE on 6th XCC and 1th channel +TCC_BUBBLE[98]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_BUBBLE on 6th XCC and 2th channel +TCC_BUBBLE[99]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_BUBBLE on 6th XCC and 3th channel +TCC_BUBBLE[9]: + architectures: + gfx950: + expression: select(TCC_BUBBLE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_BUBBLE on 0th XCC and 9th channel +TCC_EA0_ATOMIC[0]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 0th XCC and 0th channel +TCC_EA0_ATOMIC[100]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 6th XCC and 4th channel +TCC_EA0_ATOMIC[101]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 6th XCC and 5th channel +TCC_EA0_ATOMIC[102]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 6th XCC and 6th channel +TCC_EA0_ATOMIC[103]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 6th XCC and 7th channel +TCC_EA0_ATOMIC[104]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 6th XCC and 8th channel +TCC_EA0_ATOMIC[105]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 6th XCC and 9th channel +TCC_EA0_ATOMIC[106]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 6th XCC and 10th channel +TCC_EA0_ATOMIC[107]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 6th XCC and 11th channel +TCC_EA0_ATOMIC[108]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 6th XCC and 12th channel +TCC_EA0_ATOMIC[109]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 6th XCC and 13th channel +TCC_EA0_ATOMIC[10]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 0th XCC and 10th channel +TCC_EA0_ATOMIC[110]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 6th XCC and 14th channel +TCC_EA0_ATOMIC[111]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 6th XCC and 15th channel +TCC_EA0_ATOMIC[112]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 7th XCC and 0th channel +TCC_EA0_ATOMIC[113]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 7th XCC and 1th channel +TCC_EA0_ATOMIC[114]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 7th XCC and 2th channel +TCC_EA0_ATOMIC[115]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 7th XCC and 3th channel +TCC_EA0_ATOMIC[116]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 7th XCC and 4th channel +TCC_EA0_ATOMIC[117]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 7th XCC and 5th channel +TCC_EA0_ATOMIC[118]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 7th XCC and 6th channel +TCC_EA0_ATOMIC[119]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 7th XCC and 7th channel +TCC_EA0_ATOMIC[11]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 0th XCC and 11th channel +TCC_EA0_ATOMIC[120]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 7th XCC and 8th channel +TCC_EA0_ATOMIC[121]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 7th XCC and 9th channel +TCC_EA0_ATOMIC[122]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 7th XCC and 10th channel +TCC_EA0_ATOMIC[123]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 7th XCC and 11th channel +TCC_EA0_ATOMIC[124]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 7th XCC and 12th channel +TCC_EA0_ATOMIC[125]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 7th XCC and 13th channel +TCC_EA0_ATOMIC[126]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 7th XCC and 14th channel +TCC_EA0_ATOMIC[127]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 7th XCC and 15th channel +TCC_EA0_ATOMIC[12]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 0th XCC and 12th channel +TCC_EA0_ATOMIC[13]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 0th XCC and 13th channel +TCC_EA0_ATOMIC[14]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 0th XCC and 14th channel +TCC_EA0_ATOMIC[15]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 0th XCC and 15th channel +TCC_EA0_ATOMIC[16]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 1th XCC and 0th channel +TCC_EA0_ATOMIC[17]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 1th XCC and 1th channel +TCC_EA0_ATOMIC[18]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 1th XCC and 2th channel +TCC_EA0_ATOMIC[19]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 1th XCC and 3th channel +TCC_EA0_ATOMIC[1]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 0th XCC and 1th channel +TCC_EA0_ATOMIC[20]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 1th XCC and 4th channel +TCC_EA0_ATOMIC[21]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 1th XCC and 5th channel +TCC_EA0_ATOMIC[22]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 1th XCC and 6th channel +TCC_EA0_ATOMIC[23]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 1th XCC and 7th channel +TCC_EA0_ATOMIC[24]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 1th XCC and 8th channel +TCC_EA0_ATOMIC[25]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 1th XCC and 9th channel +TCC_EA0_ATOMIC[26]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 1th XCC and 10th channel +TCC_EA0_ATOMIC[27]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 1th XCC and 11th channel +TCC_EA0_ATOMIC[28]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 1th XCC and 12th channel +TCC_EA0_ATOMIC[29]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 1th XCC and 13th channel +TCC_EA0_ATOMIC[2]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 0th XCC and 2th channel +TCC_EA0_ATOMIC[30]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 1th XCC and 14th channel +TCC_EA0_ATOMIC[31]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 1th XCC and 15th channel +TCC_EA0_ATOMIC[32]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 2th XCC and 0th channel +TCC_EA0_ATOMIC[33]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 2th XCC and 1th channel +TCC_EA0_ATOMIC[34]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 2th XCC and 2th channel +TCC_EA0_ATOMIC[35]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 2th XCC and 3th channel +TCC_EA0_ATOMIC[36]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 2th XCC and 4th channel +TCC_EA0_ATOMIC[37]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 2th XCC and 5th channel +TCC_EA0_ATOMIC[38]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 2th XCC and 6th channel +TCC_EA0_ATOMIC[39]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 2th XCC and 7th channel +TCC_EA0_ATOMIC[3]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 0th XCC and 3th channel +TCC_EA0_ATOMIC[40]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 2th XCC and 8th channel +TCC_EA0_ATOMIC[41]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 2th XCC and 9th channel +TCC_EA0_ATOMIC[42]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 2th XCC and 10th channel +TCC_EA0_ATOMIC[43]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 2th XCC and 11th channel +TCC_EA0_ATOMIC[44]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 2th XCC and 12th channel +TCC_EA0_ATOMIC[45]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 2th XCC and 13th channel +TCC_EA0_ATOMIC[46]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 2th XCC and 14th channel +TCC_EA0_ATOMIC[47]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 2th XCC and 15th channel +TCC_EA0_ATOMIC[48]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 3th XCC and 0th channel +TCC_EA0_ATOMIC[49]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 3th XCC and 1th channel +TCC_EA0_ATOMIC[4]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 0th XCC and 4th channel +TCC_EA0_ATOMIC[50]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 3th XCC and 2th channel +TCC_EA0_ATOMIC[51]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 3th XCC and 3th channel +TCC_EA0_ATOMIC[52]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 3th XCC and 4th channel +TCC_EA0_ATOMIC[53]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 3th XCC and 5th channel +TCC_EA0_ATOMIC[54]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 3th XCC and 6th channel +TCC_EA0_ATOMIC[55]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 3th XCC and 7th channel +TCC_EA0_ATOMIC[56]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 3th XCC and 8th channel +TCC_EA0_ATOMIC[57]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 3th XCC and 9th channel +TCC_EA0_ATOMIC[58]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 3th XCC and 10th channel +TCC_EA0_ATOMIC[59]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 3th XCC and 11th channel +TCC_EA0_ATOMIC[5]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 0th XCC and 5th channel +TCC_EA0_ATOMIC[60]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 3th XCC and 12th channel +TCC_EA0_ATOMIC[61]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 3th XCC and 13th channel +TCC_EA0_ATOMIC[62]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 3th XCC and 14th channel +TCC_EA0_ATOMIC[63]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 3th XCC and 15th channel +TCC_EA0_ATOMIC[64]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 4th XCC and 0th channel +TCC_EA0_ATOMIC[65]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 4th XCC and 1th channel +TCC_EA0_ATOMIC[66]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 4th XCC and 2th channel +TCC_EA0_ATOMIC[67]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 4th XCC and 3th channel +TCC_EA0_ATOMIC[68]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 4th XCC and 4th channel +TCC_EA0_ATOMIC[69]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 4th XCC and 5th channel +TCC_EA0_ATOMIC[6]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 0th XCC and 6th channel +TCC_EA0_ATOMIC[70]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 4th XCC and 6th channel +TCC_EA0_ATOMIC[71]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 4th XCC and 7th channel +TCC_EA0_ATOMIC[72]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 4th XCC and 8th channel +TCC_EA0_ATOMIC[73]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 4th XCC and 9th channel +TCC_EA0_ATOMIC[74]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 4th XCC and 10th channel +TCC_EA0_ATOMIC[75]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 4th XCC and 11th channel +TCC_EA0_ATOMIC[76]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 4th XCC and 12th channel +TCC_EA0_ATOMIC[77]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 4th XCC and 13th channel +TCC_EA0_ATOMIC[78]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 4th XCC and 14th channel +TCC_EA0_ATOMIC[79]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 4th XCC and 15th channel +TCC_EA0_ATOMIC[7]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 0th XCC and 7th channel +TCC_EA0_ATOMIC[80]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 5th XCC and 0th channel +TCC_EA0_ATOMIC[81]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 5th XCC and 1th channel +TCC_EA0_ATOMIC[82]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 5th XCC and 2th channel +TCC_EA0_ATOMIC[83]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 5th XCC and 3th channel +TCC_EA0_ATOMIC[84]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC on 5th XCC and 4th channel +TCC_EA0_ATOMIC[85]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC on 5th XCC and 5th channel +TCC_EA0_ATOMIC[86]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC on 5th XCC and 6th channel +TCC_EA0_ATOMIC[87]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC on 5th XCC and 7th channel +TCC_EA0_ATOMIC[88]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 5th XCC and 8th channel +TCC_EA0_ATOMIC[89]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 5th XCC and 9th channel +TCC_EA0_ATOMIC[8]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC on 0th XCC and 8th channel +TCC_EA0_ATOMIC[90]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC on 5th XCC and 10th channel +TCC_EA0_ATOMIC[91]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC on 5th XCC and 11th channel +TCC_EA0_ATOMIC[92]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC on 5th XCC and 12th channel +TCC_EA0_ATOMIC[93]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC on 5th XCC and 13th channel +TCC_EA0_ATOMIC[94]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC on 5th XCC and 14th channel +TCC_EA0_ATOMIC[95]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC on 5th XCC and 15th channel +TCC_EA0_ATOMIC[96]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC on 6th XCC and 0th channel +TCC_EA0_ATOMIC[97]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC on 6th XCC and 1th channel +TCC_EA0_ATOMIC[98]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC on 6th XCC and 2th channel +TCC_EA0_ATOMIC[99]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC on 6th XCC and 3th channel +TCC_EA0_ATOMIC[9]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC on 0th XCC and 9th channel +TCC_HIT[0]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 0th XCC and 0th channel +TCC_HIT[100]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 6th XCC and 4th channel +TCC_HIT[101]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 6th XCC and 5th channel +TCC_HIT[102]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 6th XCC and 6th channel +TCC_HIT[103]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 6th XCC and 7th channel +TCC_HIT[104]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 6th XCC and 8th channel +TCC_HIT[105]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 6th XCC and 9th channel +TCC_HIT[106]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 6th XCC and 10th channel +TCC_HIT[107]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 6th XCC and 11th channel +TCC_HIT[108]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 6th XCC and 12th channel +TCC_HIT[109]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 6th XCC and 13th channel +TCC_HIT[10]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 0th XCC and 10th channel +TCC_HIT[110]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 6th XCC and 14th channel +TCC_HIT[111]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 6th XCC and 15th channel +TCC_HIT[112]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 7th XCC and 0th channel +TCC_HIT[113]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 7th XCC and 1th channel +TCC_HIT[114]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 7th XCC and 2th channel +TCC_HIT[115]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 7th XCC and 3th channel +TCC_HIT[116]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 7th XCC and 4th channel +TCC_HIT[117]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 7th XCC and 5th channel +TCC_HIT[118]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 7th XCC and 6th channel +TCC_HIT[119]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 7th XCC and 7th channel +TCC_HIT[11]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 0th XCC and 11th channel +TCC_HIT[120]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 7th XCC and 8th channel +TCC_HIT[121]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 7th XCC and 9th channel +TCC_HIT[122]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 7th XCC and 10th channel +TCC_HIT[123]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 7th XCC and 11th channel +TCC_HIT[124]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 7th XCC and 12th channel +TCC_HIT[125]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 7th XCC and 13th channel +TCC_HIT[126]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 7th XCC and 14th channel +TCC_HIT[127]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 7th XCC and 15th channel +TCC_HIT[12]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 0th XCC and 12th channel +TCC_HIT[13]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 0th XCC and 13th channel +TCC_HIT[14]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 0th XCC and 14th channel +TCC_HIT[15]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 0th XCC and 15th channel +TCC_HIT[16]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 1th XCC and 0th channel +TCC_HIT[17]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 1th XCC and 1th channel +TCC_HIT[18]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 1th XCC and 2th channel +TCC_HIT[19]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 1th XCC and 3th channel +TCC_HIT[1]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 0th XCC and 1th channel +TCC_HIT[20]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 1th XCC and 4th channel +TCC_HIT[21]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 1th XCC and 5th channel +TCC_HIT[22]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 1th XCC and 6th channel +TCC_HIT[23]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 1th XCC and 7th channel +TCC_HIT[24]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 1th XCC and 8th channel +TCC_HIT[25]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 1th XCC and 9th channel +TCC_HIT[26]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 1th XCC and 10th channel +TCC_HIT[27]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 1th XCC and 11th channel +TCC_HIT[28]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 1th XCC and 12th channel +TCC_HIT[29]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 1th XCC and 13th channel +TCC_HIT[2]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 0th XCC and 2th channel +TCC_HIT[30]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 1th XCC and 14th channel +TCC_HIT[31]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 1th XCC and 15th channel +TCC_HIT[32]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 2th XCC and 0th channel +TCC_HIT[33]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 2th XCC and 1th channel +TCC_HIT[34]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 2th XCC and 2th channel +TCC_HIT[35]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 2th XCC and 3th channel +TCC_HIT[36]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 2th XCC and 4th channel +TCC_HIT[37]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 2th XCC and 5th channel +TCC_HIT[38]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 2th XCC and 6th channel +TCC_HIT[39]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 2th XCC and 7th channel +TCC_HIT[3]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 0th XCC and 3th channel +TCC_HIT[40]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 2th XCC and 8th channel +TCC_HIT[41]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 2th XCC and 9th channel +TCC_HIT[42]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 2th XCC and 10th channel +TCC_HIT[43]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 2th XCC and 11th channel +TCC_HIT[44]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 2th XCC and 12th channel +TCC_HIT[45]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 2th XCC and 13th channel +TCC_HIT[46]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 2th XCC and 14th channel +TCC_HIT[47]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 2th XCC and 15th channel +TCC_HIT[48]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 3th XCC and 0th channel +TCC_HIT[49]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 3th XCC and 1th channel +TCC_HIT[4]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 0th XCC and 4th channel +TCC_HIT[50]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 3th XCC and 2th channel +TCC_HIT[51]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 3th XCC and 3th channel +TCC_HIT[52]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 3th XCC and 4th channel +TCC_HIT[53]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 3th XCC and 5th channel +TCC_HIT[54]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 3th XCC and 6th channel +TCC_HIT[55]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 3th XCC and 7th channel +TCC_HIT[56]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 3th XCC and 8th channel +TCC_HIT[57]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 3th XCC and 9th channel +TCC_HIT[58]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 3th XCC and 10th channel +TCC_HIT[59]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 3th XCC and 11th channel +TCC_HIT[5]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 0th XCC and 5th channel +TCC_HIT[60]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 3th XCC and 12th channel +TCC_HIT[61]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 3th XCC and 13th channel +TCC_HIT[62]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 3th XCC and 14th channel +TCC_HIT[63]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 3th XCC and 15th channel +TCC_HIT[64]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 4th XCC and 0th channel +TCC_HIT[65]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 4th XCC and 1th channel +TCC_HIT[66]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 4th XCC and 2th channel +TCC_HIT[67]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 4th XCC and 3th channel +TCC_HIT[68]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 4th XCC and 4th channel +TCC_HIT[69]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 4th XCC and 5th channel +TCC_HIT[6]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 0th XCC and 6th channel +TCC_HIT[70]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 4th XCC and 6th channel +TCC_HIT[71]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 4th XCC and 7th channel +TCC_HIT[72]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 4th XCC and 8th channel +TCC_HIT[73]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 4th XCC and 9th channel +TCC_HIT[74]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 4th XCC and 10th channel +TCC_HIT[75]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 4th XCC and 11th channel +TCC_HIT[76]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 4th XCC and 12th channel +TCC_HIT[77]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 4th XCC and 13th channel +TCC_HIT[78]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 4th XCC and 14th channel +TCC_HIT[79]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 4th XCC and 15th channel +TCC_HIT[7]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 0th XCC and 7th channel +TCC_HIT[80]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 5th XCC and 0th channel +TCC_HIT[81]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 5th XCC and 1th channel +TCC_HIT[82]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 5th XCC and 2th channel +TCC_HIT[83]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 5th XCC and 3th channel +TCC_HIT[84]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_HIT on 5th XCC and 4th channel +TCC_HIT[85]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_HIT on 5th XCC and 5th channel +TCC_HIT[86]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_HIT on 5th XCC and 6th channel +TCC_HIT[87]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_HIT on 5th XCC and 7th channel +TCC_HIT[88]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 5th XCC and 8th channel +TCC_HIT[89]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 5th XCC and 9th channel +TCC_HIT[8]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_HIT on 0th XCC and 8th channel +TCC_HIT[90]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_HIT on 5th XCC and 10th channel +TCC_HIT[91]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_HIT on 5th XCC and 11th channel +TCC_HIT[92]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_HIT on 5th XCC and 12th channel +TCC_HIT[93]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_HIT on 5th XCC and 13th channel +TCC_HIT[94]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_HIT on 5th XCC and 14th channel +TCC_HIT[95]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_HIT on 5th XCC and 15th channel +TCC_HIT[96]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_HIT on 6th XCC and 0th channel +TCC_HIT[97]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_HIT on 6th XCC and 1th channel +TCC_HIT[98]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_HIT on 6th XCC and 2th channel +TCC_HIT[99]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_HIT on 6th XCC and 3th channel +TCC_HIT[9]: + architectures: + gfx950: + expression: select(TCC_HIT,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_HIT on 0th XCC and 9th channel diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt new file mode 100644 index 0000000000..7f8a7f6cd5 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.txt @@ -0,0 +1,5 @@ +pmc: SQ_INST_LEVEL_VMEM SQ_INST_LEVEL_VMEM_ACCUM SQ_INSTS_VSKIPPED SQ_INSTS_VALU_MFMA_MOPS_F32 SQ_INSTS_VALU_MFMA_F16 SQ_ACTIVE_INST_VMEM SQ_INSTS_LDS_ATOMIC SQ_INSTS_GDS TA_ADDR_STALLED_BY_TD_CYCLES_sum TA_BUFFER_COALESCED_READ_CYCLES_sum TD_SPI_STALL_sum TD_COALESCABLE_WAVEFRONT_sum TCP_READ_TAGCONFLICT_STALL_CYCLES_sum TCP_TCC_RW_READ_REQ_sum TCP_TCC_NC_WRITE_REQ_sum TCP_TCP_LATENCY_sum TCC_WRITE[52] TCC_READ[108] TCC_MISS[73] TCC_EA0_WRREQ[34] TCC_MISS[95] TCC_WRITE[12] TCC_READ[14] TCC_MISS[62] TCC_READ[21] TCC_READ[118] TCC_MISS[98] TCC_MISS[112] TCC_EA0_WRREQ[31] TCC_MISS[77] TCC_MISS[39] TCC_WRITE[33] TCC_WRITE[54] TCC_EA0_WRREQ[75] TCC_WRITE[89] TCC_EA0_WRREQ[37] TCC_READ[69] TCC_READ[53] TCC_MISS[59] TCC_WRITE[51] TCC_EA0_WRREQ[127] TCC_WRITE[38] TCC_EA0_WRREQ[117] TCC_EA0_WRREQ[0] TCC_EA0_WRREQ[64] TCC_EA0_WRREQ[93] TCC_EA0_WRREQ[57] TCC_READ[28] TCC_MISS[107] TCC_READ[24] TCC_WRITE[126] TCC_WRITE[69] TCC_EA0_WRREQ[102] TCC_EA0_WRREQ[25] TCC_EA0_WRREQ[32] TCC_EA0_WRREQ[26] TCC_MISS[84] TCC_WRITE[123] TCC_READ[110] TCC_READ[12] TCC_EA0_WRREQ[55] TCC_EA0_WRREQ[20] TCC_WRITE[6] TCC_READ[61] TCC_EA0_WRREQ[72] TCC_READ[57] TCC_WRITE[113] TCC_WRITE[118] TCC_EA0_WRREQ[114] TCC_WRITE[99] TCC_READ[49] TCC_WRITE[100] TCC_WRITE[106] TCC_READ[70] TCC_WRITE[28] TCC_MISS[60] TCC_WRITE[39] TCC_MISS[99] TCC_MISS[32] TCC_MISS[114] TCC_EA0_WRREQ[63] TCC_READ[121] TCC_WRITE[66] TCC_EA0_WRREQ[62] TCC_EA0_WRREQ[97] TCC_EA0_WRREQ[94] TCC_EA0_WRREQ[96] TCC_MISS[50] TCC_EA0_WRREQ[29] TCC_EA0_WRREQ[18] TCC_WRITE[85] TCC_EA0_WRREQ[7] TCC_READ[117] TCC_MISS[45] TCC_WRITE[62] TCC_MISS[37] TCC_READ[15] TCC_MISS[116] TCC_MISS[90] TCC_EA0_WRREQ[77] TCC_MISS[100] TCC_EA0_WRREQ[48] TCC_MISS[55] TCC_EA0_WRREQ[99] TCC_READ[35] TCC_WRITE[64] TCC_READ[59] TCC_EA0_WRREQ[126] TCC_READ[71] TCC_READ[122] TCC_MISS[127] TCC_READ[114] TCC_MISS[106] TCC_MISS[8] TCC_READ[6] TCC_WRITE[2] TCC_READ[73] TCC_MISS[103] TCC_READ[41] TCC_MISS[109] TCC_EA0_WRREQ[78] TCC_WRITE[24] TCC_EA0_WRREQ[58] TCC_MISS[83] TCC_MISS[18] TCC_MISS[91] TCC_READ[72] TCC_READ[101] TCC_MISS[80] TCC_MISS[58] TCC_MISS[67] TCC_MISS[93] TCC_MISS[122] TCC_MISS[74] TCC_WRITE[98] TCC_MISS[81] TCC_EA0_WRREQ[119] TCC_MISS[104] TCC_WRITE[121] TCC_WRITE[60] TCC_WRITE[53] TCC_EA0_WRREQ[85] TCC_EA0_WRREQ[4] TCC_READ[45] TCC_MISS[63] TCC_EA0_WRREQ[8] TCC_EA0_WRREQ[61] TCC_EA0_WRREQ[74] TCC_EA0_WRREQ[9] TCC_EA0_WRREQ[6] TCC_MISS[12] TCC_WRITE[83] TCC_MISS[71] TCC_WRITE[41] TCC_WRITE[124] TCC_MISS[4] TCC_READ[126] TCC_WRITE[8] TCC_READ[127] TCC_MISS[76] TCC_EA0_WRREQ[38] TCC_READ[56] TCC_WRITE[102] TCC_WRITE[72] TCC_READ[77] TCC_MISS[2] TCC_MISS[38] TCC_WRITE[90] TCC_MISS[10] TCC_WRITE[104] TCC_WRITE[4] TCC_READ[88] TCC_READ[9] TCC_WRITE[127] TCC_MISS[119] TCC_MISS[65] TCC_READ[96] TCC_MISS[14] TCC_WRITE[14] TCC_MISS[19] TCC_EA0_WRREQ[125] TCC_EA0_WRREQ[14] TCC_EA0_WRREQ[109] TCC_WRITE[48] TCC_EA0_WRREQ[52] TCC_MISS[54] TCC_READ[10] TCC_READ[63] TCC_WRITE[16] TCC_READ[87] TCC_MISS[89] TCC_EA0_WRREQ[53] TCC_EA0_WRREQ[49] TCC_WRITE[45] TCC_WRITE[76] TCC_READ[62] TCC_EA0_WRREQ[22] TCC_EA0_WRREQ[12] TCC_WRITE[36] TCC_EA0_WRREQ[11] TCC_READ[95] TCC_READ[113] TCC_READ[106] TCC_EA0_WRREQ[23] TCC_READ[120] TCC_MISS[92] TCC_WRITE[9] TCC_EA0_WRREQ[39] TCC_WRITE[18] TCC_MISS[20] TCC_MISS[82] TCC_READ[5] TCC_WRITE[0] TCC_WRITE[10] TCC_READ[36] TCC_MISS[26] TCC_WRITE[115] TCC_MISS[75] TCC_WRITE[81] TCC_WRITE[15] TCC_EA0_WRREQ[67] TCC_MISS[97] TCC_WRITE[3] TCC_WRITE[75] TCC_READ[13] TCC_WRITE[44] TCC_EA0_WRREQ[92] TCC_READ[76] TCC_WRITE[92] TCC_MISS[102] TCC_WRITE[57] TCC_EA0_WRREQ[121] TCC_WRITE[78] TCC_EA0_WRREQ[83] TCC_EA0_WRREQ[80] TCC_READ[91] TCC_WRITE[112] TCC_WRITE[120] TCC_MISS[41] TCC_READ[84] TCC_MISS[11] TCC_READ[39] TCC_WRITE[116] TCC_WRITE[71] TCC_EA0_WRREQ[115] TCC_MISS[111] TCC_EA0_WRREQ[59] TCC_READ[111] TCC_WRITE[50] TCC_MISS[124] TCC_MISS[66] TCC_READ[7] TCC_WRITE[119] TCC_READ[109] TCC_READ[80] TCC_WRITE[11] TCC_MISS[5] TCC_WRITE[37] TCC_WRITE[56] TCC_EA0_WRREQ[108] TCC_MISS[51] TCC_WRITE[19] TCC_WRITE[30] TCC_WRITE[117] TCC_MISS[126] TCC_READ[54] TCC_EA0_WRREQ[40] TCC_MISS[108] TCC_WRITE[43] TCC_MISS[7] TCC_WRITE[58] TCC_WRITE[67] TCC_READ[105] TCC_EA0_WRREQ[79] TCC_WRITE[91] TCC_EA0_WRREQ[111] TCC_WRITE[87] TCC_WRITE[34] TCC_READ[2] TCC_READ[116] TCC_WRITE[122] TCC_MISS[88] TCC_EA0_WRREQ[17] TCC_WRITE[96] TCC_READ[112] TCC_EA0_WRREQ[84] TCC_WRITE[17] TCC_MISS[23] TCC_EA0_WRREQ[86] TCC_WRITE[23] TCC_READ[11] TCC_MISS[27] TCC_READ[124] TCC_MISS[21] TCC_WRITE[46] TCC_EA0_WRREQ[82] TCC_WRITE[27] TCC_MISS[48] TCC_MISS[125] TCC_WRITE[7] TCC_READ[8] TCC_WRITE[101] TCC_EA0_WRREQ[71] TCC_READ[58] TCC_MISS[49] TCC_WRITE[95] TCC_READ[99] TCC_EA0_WRREQ[69] TCC_READ[119] TCC_READ[82] TCC_EA0_WRREQ[41] TCC_EA0_WRREQ[42] TCC_MISS[110] TCC_READ[66] TCC_MISS[70] TCC_MISS[17] TCC_MISS[120] TCC_MISS[31] TCC_MISS[28] TCC_EA0_WRREQ[45] TCC_WRITE[20] TCC_EA0_WRREQ[116] TCC_WRITE[109] TCC_WRITE[13] TCC_EA0_WRREQ[13] TCC_READ[85] TCC_READ[38] TCC_READ[34] TCC_EA0_WRREQ[87] TCC_EA0_WRREQ[30] TCC_MISS[86] TCC_READ[52] TCC_MISS[79] TCC_READ[22] TCC_EA0_WRREQ[66] TCC_WRITE[26] TCC_WRITE[32] TCC_MISS[115] TCC_MISS[13] TCC_MISS[15] TCC_WRITE[59] TCC_WRITE[97] TCC_READ[46] TCC_WRITE[65] TCC_EA0_WRREQ[16] TCC_WRITE[21] TCC_EA0_WRREQ[65] TCC_WRITE[108] TCC_EA0_WRREQ[76] TCC_WRITE[42] TCC_EA0_WRREQ[110] TCC_EA0_WRREQ[91] TCC_MISS[64] TCC_WRITE[73] TCC_WRITE[93] TCC_MISS[1] TCC_EA0_WRREQ[3] TCC_READ[29] TCC_WRITE[80] TCC_MISS[69] TCC_MISS[22] TCC_READ[92] TCC_EA0_WRREQ[56] TCC_EA0_WRREQ[68] TCC_EA0_WRREQ[98] TCC_MISS[118] TCC_READ[67] TCC_READ[86] TCC_MISS[24] TCC_READ[30] TCC_EA0_WRREQ[60] TCC_EA0_WRREQ[28] TCC_WRITE[82] TCC_EA0_WRREQ[54] TCC_WRITE[77] TCC_MISS[53] TCC_MISS[117] TCC_EA0_WRREQ[103] TCC_MISS[56] TCC_WRITE[1] TCC_READ[55] TCC_MISS[94] TCC_MISS[105] TCC_READ[123] TCC_EA0_WRREQ[19] TCC_READ[64] TCC_EA0_WRREQ[106] TCC_WRITE[35] TCC_READ[51] TCC_MISS[34] TCC_WRITE[88] TCC_READ[44] TCC_MISS[36] TCC_EA0_WRREQ[1] TCC_EA0_WRREQ[44] TCC_MISS[87] TCC_READ[103] TCC_WRITE[31] TCC_READ[90] TCC_READ[75] TCC_EA0_WRREQ[47] TCC_EA0_WRREQ[112] TCC_MISS[78] TCC_EA0_WRREQ[2] TCC_WRITE[5] TCC_READ[4] TCC_READ[16] TCC_WRITE[86] TCC_EA0_WRREQ[89] TCC_WRITE[68] TCC_READ[20] TCC_MISS[9] TCC_WRITE[63] TCC_MISS[35] TCC_READ[94] TCC_EA0_WRREQ[73] TCC_WRITE[29] TCC_MISS[57] TCC_MISS[85] TCC_EA0_WRREQ[5] TCC_MISS[43] TCC_READ[32] TCC_READ[65] TCC_READ[93] TCC_READ[100] TCC_WRITE[49] TCC_MISS[47] TCC_READ[98] TCC_EA0_WRREQ[95] TCC_READ[1] TCC_READ[79] TCC_EA0_WRREQ[70] TCC_EA0_WRREQ[120] TCC_READ[107] TCC_READ[81] TCC_MISS[0] TCC_READ[42] TCC_WRITE[25] TCC_EA0_WRREQ[122] TCC_WRITE[110] TCC_MISS[121] TCC_WRITE[79] TCC_READ[0] TCC_EA0_WRREQ[21] TCC_READ[104] TCC_MISS[52] TCC_READ[125] TCC_EA0_WRREQ[43] TCC_EA0_WRREQ[123] TCC_EA0_WRREQ[107] TCC_READ[18] TCC_WRITE[74] TCC_READ[83] TCC_WRITE[22] TCC_READ[68] TCC_MISS[61] TCC_MISS[30] TCC_READ[33] TCC_WRITE[55] TCC_EA0_WRREQ[50] TCC_WRITE[111] TCC_EA0_WRREQ[124] TCC_READ[48] TCC_MISS[123] TCC_READ[19] TCC_WRITE[84] TCC_WRITE[114] TCC_READ[26] TCC_EA0_WRREQ[36] TCC_READ[89] TCC_MISS[46] TCC_EA0_WRREQ[24] TCC_WRITE[105] TCC_EA0_WRREQ[101] TCC_READ[97] TCC_WRITE[61] TCC_WRITE[125] TCC_MISS[29] TCC_READ[17] TCC_MISS[33] TCC_WRITE[94] TCC_MISS[96] TCC_EA0_WRREQ[113] TCC_EA0_WRREQ[27] TCC_MISS[44] TCC_EA0_WRREQ[46] TCC_READ[23] TCC_READ[40] TCC_WRITE[107] TCC_EA0_WRREQ[35] TCC_EA0_WRREQ[81] TCC_EA0_WRREQ[51] TCC_MISS[40] TCC_READ[102] TCC_MISS[113] TCC_READ[115] TCC_READ[60] TCC_READ[3] TCC_EA0_WRREQ[88] TCC_READ[43] TCC_MISS[68] TCC_EA0_WRREQ[104] TCC_MISS[72] TCC_READ[47] TCC_EA0_WRREQ[105] TCC_EA0_WRREQ[33] TCC_READ[25] TCC_EA0_WRREQ[90] TCC_MISS[16] TCC_EA0_WRREQ[118] TCC_READ[31] TCC_WRITE[40] TCC_EA0_WRREQ[15] TCC_MISS[25] TCC_READ[50] TCC_READ[27] TCC_READ[74] TCC_MISS[101] TCC_MISS[3] TCC_WRITE[103] TCC_MISS[6] TCC_READ[37] TCC_WRITE[70] TCC_MISS[42] TCC_EA0_WRREQ[10] TCC_READ[78] TCC_EA0_WRREQ[100] TCC_WRITE[47] CPC_CANE_STALL CPC_CPC_STAT_STALL CPF_CPF_TCIU_STALL CPF_CPF_TCIU_BUSY SPI_CS1_CRAWLER_STALL SPI_CS0_CRAWLER_STALL SPI_CS3_CRAWLER_STALL SPI_CS2_CRAWLER_STALL GRBM_SPI_BUSY GRBM_COUNT + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.yaml b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.yaml new file mode 100644 index 0000000000..6f24742891 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_INST_LEVEL_VMEM.yaml @@ -0,0 +1,2565 @@ +SQ_INST_LEVEL_VMEM_ACCUM: + architectures: + gfx942/gfx941/gfx940/gfx90a: + expression: accumulate(SQ_INST_LEVEL_VMEM, HIGH_RES) + description: SQ_INST_LEVEL_VMEM accumulation +TCC_EA0_WRREQ[0]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 0th XCC and 0th channel +TCC_EA0_WRREQ[100]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 6th XCC and 4th channel +TCC_EA0_WRREQ[101]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 6th XCC and 5th channel +TCC_EA0_WRREQ[102]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 6th XCC and 6th channel +TCC_EA0_WRREQ[103]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 6th XCC and 7th channel +TCC_EA0_WRREQ[104]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 6th XCC and 8th channel +TCC_EA0_WRREQ[105]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 6th XCC and 9th channel +TCC_EA0_WRREQ[106]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 6th XCC and 10th channel +TCC_EA0_WRREQ[107]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 6th XCC and 11th channel +TCC_EA0_WRREQ[108]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 6th XCC and 12th channel +TCC_EA0_WRREQ[109]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 6th XCC and 13th channel +TCC_EA0_WRREQ[10]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 0th XCC and 10th channel +TCC_EA0_WRREQ[110]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 6th XCC and 14th channel +TCC_EA0_WRREQ[111]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 6th XCC and 15th channel +TCC_EA0_WRREQ[112]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 7th XCC and 0th channel +TCC_EA0_WRREQ[113]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 7th XCC and 1th channel +TCC_EA0_WRREQ[114]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 7th XCC and 2th channel +TCC_EA0_WRREQ[115]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 7th XCC and 3th channel +TCC_EA0_WRREQ[116]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 7th XCC and 4th channel +TCC_EA0_WRREQ[117]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 7th XCC and 5th channel +TCC_EA0_WRREQ[118]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 7th XCC and 6th channel +TCC_EA0_WRREQ[119]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 7th XCC and 7th channel +TCC_EA0_WRREQ[11]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 0th XCC and 11th channel +TCC_EA0_WRREQ[120]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 7th XCC and 8th channel +TCC_EA0_WRREQ[121]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 7th XCC and 9th channel +TCC_EA0_WRREQ[122]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 7th XCC and 10th channel +TCC_EA0_WRREQ[123]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 7th XCC and 11th channel +TCC_EA0_WRREQ[124]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 7th XCC and 12th channel +TCC_EA0_WRREQ[125]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 7th XCC and 13th channel +TCC_EA0_WRREQ[126]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 7th XCC and 14th channel +TCC_EA0_WRREQ[127]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 7th XCC and 15th channel +TCC_EA0_WRREQ[12]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 0th XCC and 12th channel +TCC_EA0_WRREQ[13]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 0th XCC and 13th channel +TCC_EA0_WRREQ[14]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 0th XCC and 14th channel +TCC_EA0_WRREQ[15]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 0th XCC and 15th channel +TCC_EA0_WRREQ[16]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 1th XCC and 0th channel +TCC_EA0_WRREQ[17]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 1th XCC and 1th channel +TCC_EA0_WRREQ[18]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 1th XCC and 2th channel +TCC_EA0_WRREQ[19]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 1th XCC and 3th channel +TCC_EA0_WRREQ[1]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 0th XCC and 1th channel +TCC_EA0_WRREQ[20]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 1th XCC and 4th channel +TCC_EA0_WRREQ[21]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 1th XCC and 5th channel +TCC_EA0_WRREQ[22]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 1th XCC and 6th channel +TCC_EA0_WRREQ[23]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 1th XCC and 7th channel +TCC_EA0_WRREQ[24]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 1th XCC and 8th channel +TCC_EA0_WRREQ[25]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 1th XCC and 9th channel +TCC_EA0_WRREQ[26]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 1th XCC and 10th channel +TCC_EA0_WRREQ[27]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 1th XCC and 11th channel +TCC_EA0_WRREQ[28]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 1th XCC and 12th channel +TCC_EA0_WRREQ[29]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 1th XCC and 13th channel +TCC_EA0_WRREQ[2]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 0th XCC and 2th channel +TCC_EA0_WRREQ[30]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 1th XCC and 14th channel +TCC_EA0_WRREQ[31]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 1th XCC and 15th channel +TCC_EA0_WRREQ[32]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 2th XCC and 0th channel +TCC_EA0_WRREQ[33]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 2th XCC and 1th channel +TCC_EA0_WRREQ[34]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 2th XCC and 2th channel +TCC_EA0_WRREQ[35]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 2th XCC and 3th channel +TCC_EA0_WRREQ[36]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 2th XCC and 4th channel +TCC_EA0_WRREQ[37]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 2th XCC and 5th channel +TCC_EA0_WRREQ[38]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 2th XCC and 6th channel +TCC_EA0_WRREQ[39]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 2th XCC and 7th channel +TCC_EA0_WRREQ[3]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 0th XCC and 3th channel +TCC_EA0_WRREQ[40]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 2th XCC and 8th channel +TCC_EA0_WRREQ[41]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 2th XCC and 9th channel +TCC_EA0_WRREQ[42]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 2th XCC and 10th channel +TCC_EA0_WRREQ[43]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 2th XCC and 11th channel +TCC_EA0_WRREQ[44]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 2th XCC and 12th channel +TCC_EA0_WRREQ[45]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 2th XCC and 13th channel +TCC_EA0_WRREQ[46]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 2th XCC and 14th channel +TCC_EA0_WRREQ[47]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 2th XCC and 15th channel +TCC_EA0_WRREQ[48]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 3th XCC and 0th channel +TCC_EA0_WRREQ[49]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 3th XCC and 1th channel +TCC_EA0_WRREQ[4]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 0th XCC and 4th channel +TCC_EA0_WRREQ[50]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 3th XCC and 2th channel +TCC_EA0_WRREQ[51]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 3th XCC and 3th channel +TCC_EA0_WRREQ[52]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 3th XCC and 4th channel +TCC_EA0_WRREQ[53]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 3th XCC and 5th channel +TCC_EA0_WRREQ[54]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 3th XCC and 6th channel +TCC_EA0_WRREQ[55]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 3th XCC and 7th channel +TCC_EA0_WRREQ[56]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 3th XCC and 8th channel +TCC_EA0_WRREQ[57]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 3th XCC and 9th channel +TCC_EA0_WRREQ[58]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 3th XCC and 10th channel +TCC_EA0_WRREQ[59]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 3th XCC and 11th channel +TCC_EA0_WRREQ[5]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 0th XCC and 5th channel +TCC_EA0_WRREQ[60]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 3th XCC and 12th channel +TCC_EA0_WRREQ[61]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 3th XCC and 13th channel +TCC_EA0_WRREQ[62]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 3th XCC and 14th channel +TCC_EA0_WRREQ[63]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 3th XCC and 15th channel +TCC_EA0_WRREQ[64]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 4th XCC and 0th channel +TCC_EA0_WRREQ[65]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 4th XCC and 1th channel +TCC_EA0_WRREQ[66]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 4th XCC and 2th channel +TCC_EA0_WRREQ[67]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 4th XCC and 3th channel +TCC_EA0_WRREQ[68]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 4th XCC and 4th channel +TCC_EA0_WRREQ[69]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 4th XCC and 5th channel +TCC_EA0_WRREQ[6]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 0th XCC and 6th channel +TCC_EA0_WRREQ[70]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 4th XCC and 6th channel +TCC_EA0_WRREQ[71]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 4th XCC and 7th channel +TCC_EA0_WRREQ[72]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 4th XCC and 8th channel +TCC_EA0_WRREQ[73]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 4th XCC and 9th channel +TCC_EA0_WRREQ[74]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 4th XCC and 10th channel +TCC_EA0_WRREQ[75]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 4th XCC and 11th channel +TCC_EA0_WRREQ[76]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 4th XCC and 12th channel +TCC_EA0_WRREQ[77]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 4th XCC and 13th channel +TCC_EA0_WRREQ[78]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 4th XCC and 14th channel +TCC_EA0_WRREQ[79]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 4th XCC and 15th channel +TCC_EA0_WRREQ[7]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 0th XCC and 7th channel +TCC_EA0_WRREQ[80]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 5th XCC and 0th channel +TCC_EA0_WRREQ[81]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 5th XCC and 1th channel +TCC_EA0_WRREQ[82]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 5th XCC and 2th channel +TCC_EA0_WRREQ[83]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 5th XCC and 3th channel +TCC_EA0_WRREQ[84]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_WRREQ on 5th XCC and 4th channel +TCC_EA0_WRREQ[85]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_WRREQ on 5th XCC and 5th channel +TCC_EA0_WRREQ[86]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_WRREQ on 5th XCC and 6th channel +TCC_EA0_WRREQ[87]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_WRREQ on 5th XCC and 7th channel +TCC_EA0_WRREQ[88]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 5th XCC and 8th channel +TCC_EA0_WRREQ[89]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 5th XCC and 9th channel +TCC_EA0_WRREQ[8]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_WRREQ on 0th XCC and 8th channel +TCC_EA0_WRREQ[90]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_WRREQ on 5th XCC and 10th channel +TCC_EA0_WRREQ[91]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_WRREQ on 5th XCC and 11th channel +TCC_EA0_WRREQ[92]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_WRREQ on 5th XCC and 12th channel +TCC_EA0_WRREQ[93]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_WRREQ on 5th XCC and 13th channel +TCC_EA0_WRREQ[94]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_WRREQ on 5th XCC and 14th channel +TCC_EA0_WRREQ[95]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_WRREQ on 5th XCC and 15th channel +TCC_EA0_WRREQ[96]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_WRREQ on 6th XCC and 0th channel +TCC_EA0_WRREQ[97]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_WRREQ on 6th XCC and 1th channel +TCC_EA0_WRREQ[98]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_WRREQ on 6th XCC and 2th channel +TCC_EA0_WRREQ[99]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_WRREQ on 6th XCC and 3th channel +TCC_EA0_WRREQ[9]: + architectures: + gfx950: + expression: select(TCC_EA0_WRREQ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_WRREQ on 0th XCC and 9th channel +TCC_MISS[0]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 0th XCC and 0th channel +TCC_MISS[100]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 6th XCC and 4th channel +TCC_MISS[101]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 6th XCC and 5th channel +TCC_MISS[102]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 6th XCC and 6th channel +TCC_MISS[103]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 6th XCC and 7th channel +TCC_MISS[104]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 6th XCC and 8th channel +TCC_MISS[105]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 6th XCC and 9th channel +TCC_MISS[106]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 6th XCC and 10th channel +TCC_MISS[107]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 6th XCC and 11th channel +TCC_MISS[108]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 6th XCC and 12th channel +TCC_MISS[109]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 6th XCC and 13th channel +TCC_MISS[10]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 0th XCC and 10th channel +TCC_MISS[110]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 6th XCC and 14th channel +TCC_MISS[111]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 6th XCC and 15th channel +TCC_MISS[112]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 7th XCC and 0th channel +TCC_MISS[113]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 7th XCC and 1th channel +TCC_MISS[114]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 7th XCC and 2th channel +TCC_MISS[115]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 7th XCC and 3th channel +TCC_MISS[116]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 7th XCC and 4th channel +TCC_MISS[117]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 7th XCC and 5th channel +TCC_MISS[118]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 7th XCC and 6th channel +TCC_MISS[119]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 7th XCC and 7th channel +TCC_MISS[11]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 0th XCC and 11th channel +TCC_MISS[120]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 7th XCC and 8th channel +TCC_MISS[121]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 7th XCC and 9th channel +TCC_MISS[122]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 7th XCC and 10th channel +TCC_MISS[123]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 7th XCC and 11th channel +TCC_MISS[124]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 7th XCC and 12th channel +TCC_MISS[125]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 7th XCC and 13th channel +TCC_MISS[126]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 7th XCC and 14th channel +TCC_MISS[127]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 7th XCC and 15th channel +TCC_MISS[12]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 0th XCC and 12th channel +TCC_MISS[13]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 0th XCC and 13th channel +TCC_MISS[14]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 0th XCC and 14th channel +TCC_MISS[15]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 0th XCC and 15th channel +TCC_MISS[16]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 1th XCC and 0th channel +TCC_MISS[17]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 1th XCC and 1th channel +TCC_MISS[18]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 1th XCC and 2th channel +TCC_MISS[19]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 1th XCC and 3th channel +TCC_MISS[1]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 0th XCC and 1th channel +TCC_MISS[20]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 1th XCC and 4th channel +TCC_MISS[21]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 1th XCC and 5th channel +TCC_MISS[22]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 1th XCC and 6th channel +TCC_MISS[23]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 1th XCC and 7th channel +TCC_MISS[24]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 1th XCC and 8th channel +TCC_MISS[25]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 1th XCC and 9th channel +TCC_MISS[26]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 1th XCC and 10th channel +TCC_MISS[27]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 1th XCC and 11th channel +TCC_MISS[28]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 1th XCC and 12th channel +TCC_MISS[29]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 1th XCC and 13th channel +TCC_MISS[2]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 0th XCC and 2th channel +TCC_MISS[30]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 1th XCC and 14th channel +TCC_MISS[31]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 1th XCC and 15th channel +TCC_MISS[32]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 2th XCC and 0th channel +TCC_MISS[33]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 2th XCC and 1th channel +TCC_MISS[34]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 2th XCC and 2th channel +TCC_MISS[35]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 2th XCC and 3th channel +TCC_MISS[36]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 2th XCC and 4th channel +TCC_MISS[37]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 2th XCC and 5th channel +TCC_MISS[38]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 2th XCC and 6th channel +TCC_MISS[39]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 2th XCC and 7th channel +TCC_MISS[3]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 0th XCC and 3th channel +TCC_MISS[40]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 2th XCC and 8th channel +TCC_MISS[41]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 2th XCC and 9th channel +TCC_MISS[42]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 2th XCC and 10th channel +TCC_MISS[43]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 2th XCC and 11th channel +TCC_MISS[44]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 2th XCC and 12th channel +TCC_MISS[45]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 2th XCC and 13th channel +TCC_MISS[46]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 2th XCC and 14th channel +TCC_MISS[47]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 2th XCC and 15th channel +TCC_MISS[48]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 3th XCC and 0th channel +TCC_MISS[49]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 3th XCC and 1th channel +TCC_MISS[4]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 0th XCC and 4th channel +TCC_MISS[50]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 3th XCC and 2th channel +TCC_MISS[51]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 3th XCC and 3th channel +TCC_MISS[52]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 3th XCC and 4th channel +TCC_MISS[53]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 3th XCC and 5th channel +TCC_MISS[54]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 3th XCC and 6th channel +TCC_MISS[55]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 3th XCC and 7th channel +TCC_MISS[56]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 3th XCC and 8th channel +TCC_MISS[57]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 3th XCC and 9th channel +TCC_MISS[58]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 3th XCC and 10th channel +TCC_MISS[59]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 3th XCC and 11th channel +TCC_MISS[5]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 0th XCC and 5th channel +TCC_MISS[60]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 3th XCC and 12th channel +TCC_MISS[61]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 3th XCC and 13th channel +TCC_MISS[62]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 3th XCC and 14th channel +TCC_MISS[63]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 3th XCC and 15th channel +TCC_MISS[64]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 4th XCC and 0th channel +TCC_MISS[65]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 4th XCC and 1th channel +TCC_MISS[66]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 4th XCC and 2th channel +TCC_MISS[67]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 4th XCC and 3th channel +TCC_MISS[68]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 4th XCC and 4th channel +TCC_MISS[69]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 4th XCC and 5th channel +TCC_MISS[6]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 0th XCC and 6th channel +TCC_MISS[70]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 4th XCC and 6th channel +TCC_MISS[71]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 4th XCC and 7th channel +TCC_MISS[72]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 4th XCC and 8th channel +TCC_MISS[73]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 4th XCC and 9th channel +TCC_MISS[74]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 4th XCC and 10th channel +TCC_MISS[75]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 4th XCC and 11th channel +TCC_MISS[76]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 4th XCC and 12th channel +TCC_MISS[77]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 4th XCC and 13th channel +TCC_MISS[78]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 4th XCC and 14th channel +TCC_MISS[79]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 4th XCC and 15th channel +TCC_MISS[7]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 0th XCC and 7th channel +TCC_MISS[80]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 5th XCC and 0th channel +TCC_MISS[81]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 5th XCC and 1th channel +TCC_MISS[82]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 5th XCC and 2th channel +TCC_MISS[83]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 5th XCC and 3th channel +TCC_MISS[84]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_MISS on 5th XCC and 4th channel +TCC_MISS[85]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_MISS on 5th XCC and 5th channel +TCC_MISS[86]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_MISS on 5th XCC and 6th channel +TCC_MISS[87]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_MISS on 5th XCC and 7th channel +TCC_MISS[88]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 5th XCC and 8th channel +TCC_MISS[89]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 5th XCC and 9th channel +TCC_MISS[8]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_MISS on 0th XCC and 8th channel +TCC_MISS[90]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_MISS on 5th XCC and 10th channel +TCC_MISS[91]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_MISS on 5th XCC and 11th channel +TCC_MISS[92]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_MISS on 5th XCC and 12th channel +TCC_MISS[93]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_MISS on 5th XCC and 13th channel +TCC_MISS[94]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_MISS on 5th XCC and 14th channel +TCC_MISS[95]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_MISS on 5th XCC and 15th channel +TCC_MISS[96]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_MISS on 6th XCC and 0th channel +TCC_MISS[97]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_MISS on 6th XCC and 1th channel +TCC_MISS[98]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_MISS on 6th XCC and 2th channel +TCC_MISS[99]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_MISS on 6th XCC and 3th channel +TCC_MISS[9]: + architectures: + gfx950: + expression: select(TCC_MISS,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_MISS on 0th XCC and 9th channel +TCC_READ[0]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 0th XCC and 0th channel +TCC_READ[100]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 6th XCC and 4th channel +TCC_READ[101]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 6th XCC and 5th channel +TCC_READ[102]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 6th XCC and 6th channel +TCC_READ[103]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 6th XCC and 7th channel +TCC_READ[104]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 6th XCC and 8th channel +TCC_READ[105]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 6th XCC and 9th channel +TCC_READ[106]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 6th XCC and 10th channel +TCC_READ[107]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 6th XCC and 11th channel +TCC_READ[108]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 6th XCC and 12th channel +TCC_READ[109]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 6th XCC and 13th channel +TCC_READ[10]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 0th XCC and 10th channel +TCC_READ[110]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 6th XCC and 14th channel +TCC_READ[111]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 6th XCC and 15th channel +TCC_READ[112]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 7th XCC and 0th channel +TCC_READ[113]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 7th XCC and 1th channel +TCC_READ[114]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 7th XCC and 2th channel +TCC_READ[115]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 7th XCC and 3th channel +TCC_READ[116]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 7th XCC and 4th channel +TCC_READ[117]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 7th XCC and 5th channel +TCC_READ[118]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 7th XCC and 6th channel +TCC_READ[119]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 7th XCC and 7th channel +TCC_READ[11]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 0th XCC and 11th channel +TCC_READ[120]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 7th XCC and 8th channel +TCC_READ[121]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 7th XCC and 9th channel +TCC_READ[122]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 7th XCC and 10th channel +TCC_READ[123]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 7th XCC and 11th channel +TCC_READ[124]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 7th XCC and 12th channel +TCC_READ[125]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 7th XCC and 13th channel +TCC_READ[126]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 7th XCC and 14th channel +TCC_READ[127]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 7th XCC and 15th channel +TCC_READ[12]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 0th XCC and 12th channel +TCC_READ[13]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 0th XCC and 13th channel +TCC_READ[14]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 0th XCC and 14th channel +TCC_READ[15]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 0th XCC and 15th channel +TCC_READ[16]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 1th XCC and 0th channel +TCC_READ[17]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 1th XCC and 1th channel +TCC_READ[18]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 1th XCC and 2th channel +TCC_READ[19]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 1th XCC and 3th channel +TCC_READ[1]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 0th XCC and 1th channel +TCC_READ[20]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 1th XCC and 4th channel +TCC_READ[21]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 1th XCC and 5th channel +TCC_READ[22]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 1th XCC and 6th channel +TCC_READ[23]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 1th XCC and 7th channel +TCC_READ[24]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 1th XCC and 8th channel +TCC_READ[25]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 1th XCC and 9th channel +TCC_READ[26]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 1th XCC and 10th channel +TCC_READ[27]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 1th XCC and 11th channel +TCC_READ[28]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 1th XCC and 12th channel +TCC_READ[29]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 1th XCC and 13th channel +TCC_READ[2]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 0th XCC and 2th channel +TCC_READ[30]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 1th XCC and 14th channel +TCC_READ[31]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 1th XCC and 15th channel +TCC_READ[32]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 2th XCC and 0th channel +TCC_READ[33]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 2th XCC and 1th channel +TCC_READ[34]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 2th XCC and 2th channel +TCC_READ[35]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 2th XCC and 3th channel +TCC_READ[36]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 2th XCC and 4th channel +TCC_READ[37]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 2th XCC and 5th channel +TCC_READ[38]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 2th XCC and 6th channel +TCC_READ[39]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 2th XCC and 7th channel +TCC_READ[3]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 0th XCC and 3th channel +TCC_READ[40]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 2th XCC and 8th channel +TCC_READ[41]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 2th XCC and 9th channel +TCC_READ[42]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 2th XCC and 10th channel +TCC_READ[43]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 2th XCC and 11th channel +TCC_READ[44]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 2th XCC and 12th channel +TCC_READ[45]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 2th XCC and 13th channel +TCC_READ[46]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 2th XCC and 14th channel +TCC_READ[47]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 2th XCC and 15th channel +TCC_READ[48]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 3th XCC and 0th channel +TCC_READ[49]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 3th XCC and 1th channel +TCC_READ[4]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 0th XCC and 4th channel +TCC_READ[50]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 3th XCC and 2th channel +TCC_READ[51]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 3th XCC and 3th channel +TCC_READ[52]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 3th XCC and 4th channel +TCC_READ[53]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 3th XCC and 5th channel +TCC_READ[54]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 3th XCC and 6th channel +TCC_READ[55]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 3th XCC and 7th channel +TCC_READ[56]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 3th XCC and 8th channel +TCC_READ[57]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 3th XCC and 9th channel +TCC_READ[58]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 3th XCC and 10th channel +TCC_READ[59]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 3th XCC and 11th channel +TCC_READ[5]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 0th XCC and 5th channel +TCC_READ[60]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 3th XCC and 12th channel +TCC_READ[61]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 3th XCC and 13th channel +TCC_READ[62]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 3th XCC and 14th channel +TCC_READ[63]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 3th XCC and 15th channel +TCC_READ[64]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 4th XCC and 0th channel +TCC_READ[65]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 4th XCC and 1th channel +TCC_READ[66]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 4th XCC and 2th channel +TCC_READ[67]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 4th XCC and 3th channel +TCC_READ[68]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 4th XCC and 4th channel +TCC_READ[69]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 4th XCC and 5th channel +TCC_READ[6]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 0th XCC and 6th channel +TCC_READ[70]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 4th XCC and 6th channel +TCC_READ[71]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 4th XCC and 7th channel +TCC_READ[72]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 4th XCC and 8th channel +TCC_READ[73]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 4th XCC and 9th channel +TCC_READ[74]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 4th XCC and 10th channel +TCC_READ[75]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 4th XCC and 11th channel +TCC_READ[76]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 4th XCC and 12th channel +TCC_READ[77]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 4th XCC and 13th channel +TCC_READ[78]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 4th XCC and 14th channel +TCC_READ[79]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 4th XCC and 15th channel +TCC_READ[7]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 0th XCC and 7th channel +TCC_READ[80]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 5th XCC and 0th channel +TCC_READ[81]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 5th XCC and 1th channel +TCC_READ[82]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 5th XCC and 2th channel +TCC_READ[83]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 5th XCC and 3th channel +TCC_READ[84]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_READ on 5th XCC and 4th channel +TCC_READ[85]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_READ on 5th XCC and 5th channel +TCC_READ[86]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_READ on 5th XCC and 6th channel +TCC_READ[87]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_READ on 5th XCC and 7th channel +TCC_READ[88]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 5th XCC and 8th channel +TCC_READ[89]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 5th XCC and 9th channel +TCC_READ[8]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_READ on 0th XCC and 8th channel +TCC_READ[90]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_READ on 5th XCC and 10th channel +TCC_READ[91]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_READ on 5th XCC and 11th channel +TCC_READ[92]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_READ on 5th XCC and 12th channel +TCC_READ[93]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_READ on 5th XCC and 13th channel +TCC_READ[94]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_READ on 5th XCC and 14th channel +TCC_READ[95]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_READ on 5th XCC and 15th channel +TCC_READ[96]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_READ on 6th XCC and 0th channel +TCC_READ[97]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_READ on 6th XCC and 1th channel +TCC_READ[98]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_READ on 6th XCC and 2th channel +TCC_READ[99]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_READ on 6th XCC and 3th channel +TCC_READ[9]: + architectures: + gfx950: + expression: select(TCC_READ,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_READ on 0th XCC and 9th channel +TCC_WRITE[0]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 0th XCC and 0th channel +TCC_WRITE[100]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 6th XCC and 4th channel +TCC_WRITE[101]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 6th XCC and 5th channel +TCC_WRITE[102]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 6th XCC and 6th channel +TCC_WRITE[103]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 6th XCC and 7th channel +TCC_WRITE[104]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 6th XCC and 8th channel +TCC_WRITE[105]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 6th XCC and 9th channel +TCC_WRITE[106]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 6th XCC and 10th channel +TCC_WRITE[107]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 6th XCC and 11th channel +TCC_WRITE[108]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 6th XCC and 12th channel +TCC_WRITE[109]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 6th XCC and 13th channel +TCC_WRITE[10]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 0th XCC and 10th channel +TCC_WRITE[110]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 6th XCC and 14th channel +TCC_WRITE[111]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 6th XCC and 15th channel +TCC_WRITE[112]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 7th XCC and 0th channel +TCC_WRITE[113]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 7th XCC and 1th channel +TCC_WRITE[114]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 7th XCC and 2th channel +TCC_WRITE[115]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 7th XCC and 3th channel +TCC_WRITE[116]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 7th XCC and 4th channel +TCC_WRITE[117]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 7th XCC and 5th channel +TCC_WRITE[118]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 7th XCC and 6th channel +TCC_WRITE[119]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 7th XCC and 7th channel +TCC_WRITE[11]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 0th XCC and 11th channel +TCC_WRITE[120]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 7th XCC and 8th channel +TCC_WRITE[121]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 7th XCC and 9th channel +TCC_WRITE[122]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 7th XCC and 10th channel +TCC_WRITE[123]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 7th XCC and 11th channel +TCC_WRITE[124]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 7th XCC and 12th channel +TCC_WRITE[125]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 7th XCC and 13th channel +TCC_WRITE[126]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 7th XCC and 14th channel +TCC_WRITE[127]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 7th XCC and 15th channel +TCC_WRITE[12]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 0th XCC and 12th channel +TCC_WRITE[13]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 0th XCC and 13th channel +TCC_WRITE[14]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 0th XCC and 14th channel +TCC_WRITE[15]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 0th XCC and 15th channel +TCC_WRITE[16]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 1th XCC and 0th channel +TCC_WRITE[17]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 1th XCC and 1th channel +TCC_WRITE[18]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 1th XCC and 2th channel +TCC_WRITE[19]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 1th XCC and 3th channel +TCC_WRITE[1]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 0th XCC and 1th channel +TCC_WRITE[20]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 1th XCC and 4th channel +TCC_WRITE[21]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 1th XCC and 5th channel +TCC_WRITE[22]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 1th XCC and 6th channel +TCC_WRITE[23]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 1th XCC and 7th channel +TCC_WRITE[24]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 1th XCC and 8th channel +TCC_WRITE[25]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 1th XCC and 9th channel +TCC_WRITE[26]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 1th XCC and 10th channel +TCC_WRITE[27]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 1th XCC and 11th channel +TCC_WRITE[28]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 1th XCC and 12th channel +TCC_WRITE[29]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 1th XCC and 13th channel +TCC_WRITE[2]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 0th XCC and 2th channel +TCC_WRITE[30]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 1th XCC and 14th channel +TCC_WRITE[31]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 1th XCC and 15th channel +TCC_WRITE[32]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 2th XCC and 0th channel +TCC_WRITE[33]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 2th XCC and 1th channel +TCC_WRITE[34]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 2th XCC and 2th channel +TCC_WRITE[35]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 2th XCC and 3th channel +TCC_WRITE[36]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 2th XCC and 4th channel +TCC_WRITE[37]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 2th XCC and 5th channel +TCC_WRITE[38]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 2th XCC and 6th channel +TCC_WRITE[39]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 2th XCC and 7th channel +TCC_WRITE[3]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 0th XCC and 3th channel +TCC_WRITE[40]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 2th XCC and 8th channel +TCC_WRITE[41]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 2th XCC and 9th channel +TCC_WRITE[42]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 2th XCC and 10th channel +TCC_WRITE[43]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 2th XCC and 11th channel +TCC_WRITE[44]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 2th XCC and 12th channel +TCC_WRITE[45]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 2th XCC and 13th channel +TCC_WRITE[46]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 2th XCC and 14th channel +TCC_WRITE[47]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 2th XCC and 15th channel +TCC_WRITE[48]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 3th XCC and 0th channel +TCC_WRITE[49]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 3th XCC and 1th channel +TCC_WRITE[4]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 0th XCC and 4th channel +TCC_WRITE[50]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 3th XCC and 2th channel +TCC_WRITE[51]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 3th XCC and 3th channel +TCC_WRITE[52]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 3th XCC and 4th channel +TCC_WRITE[53]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 3th XCC and 5th channel +TCC_WRITE[54]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 3th XCC and 6th channel +TCC_WRITE[55]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 3th XCC and 7th channel +TCC_WRITE[56]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 3th XCC and 8th channel +TCC_WRITE[57]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 3th XCC and 9th channel +TCC_WRITE[58]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 3th XCC and 10th channel +TCC_WRITE[59]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 3th XCC and 11th channel +TCC_WRITE[5]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 0th XCC and 5th channel +TCC_WRITE[60]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 3th XCC and 12th channel +TCC_WRITE[61]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 3th XCC and 13th channel +TCC_WRITE[62]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 3th XCC and 14th channel +TCC_WRITE[63]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 3th XCC and 15th channel +TCC_WRITE[64]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 4th XCC and 0th channel +TCC_WRITE[65]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 4th XCC and 1th channel +TCC_WRITE[66]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 4th XCC and 2th channel +TCC_WRITE[67]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 4th XCC and 3th channel +TCC_WRITE[68]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 4th XCC and 4th channel +TCC_WRITE[69]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 4th XCC and 5th channel +TCC_WRITE[6]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 0th XCC and 6th channel +TCC_WRITE[70]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 4th XCC and 6th channel +TCC_WRITE[71]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 4th XCC and 7th channel +TCC_WRITE[72]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 4th XCC and 8th channel +TCC_WRITE[73]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 4th XCC and 9th channel +TCC_WRITE[74]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 4th XCC and 10th channel +TCC_WRITE[75]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 4th XCC and 11th channel +TCC_WRITE[76]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 4th XCC and 12th channel +TCC_WRITE[77]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 4th XCC and 13th channel +TCC_WRITE[78]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 4th XCC and 14th channel +TCC_WRITE[79]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 4th XCC and 15th channel +TCC_WRITE[7]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 0th XCC and 7th channel +TCC_WRITE[80]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 5th XCC and 0th channel +TCC_WRITE[81]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 5th XCC and 1th channel +TCC_WRITE[82]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 5th XCC and 2th channel +TCC_WRITE[83]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 5th XCC and 3th channel +TCC_WRITE[84]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_WRITE on 5th XCC and 4th channel +TCC_WRITE[85]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_WRITE on 5th XCC and 5th channel +TCC_WRITE[86]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_WRITE on 5th XCC and 6th channel +TCC_WRITE[87]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_WRITE on 5th XCC and 7th channel +TCC_WRITE[88]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 5th XCC and 8th channel +TCC_WRITE[89]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 5th XCC and 9th channel +TCC_WRITE[8]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_WRITE on 0th XCC and 8th channel +TCC_WRITE[90]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_WRITE on 5th XCC and 10th channel +TCC_WRITE[91]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_WRITE on 5th XCC and 11th channel +TCC_WRITE[92]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_WRITE on 5th XCC and 12th channel +TCC_WRITE[93]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_WRITE on 5th XCC and 13th channel +TCC_WRITE[94]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_WRITE on 5th XCC and 14th channel +TCC_WRITE[95]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_WRITE on 5th XCC and 15th channel +TCC_WRITE[96]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_WRITE on 6th XCC and 0th channel +TCC_WRITE[97]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_WRITE on 6th XCC and 1th channel +TCC_WRITE[98]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_WRITE on 6th XCC and 2th channel +TCC_WRITE[99]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_WRITE on 6th XCC and 3th channel +TCC_WRITE[9]: + architectures: + gfx950: + expression: select(TCC_WRITE,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_WRITE on 0th XCC and 9th channel diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.txt new file mode 100644 index 0000000000..89a1f38eee --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.txt @@ -0,0 +1,5 @@ +pmc: SQ_LEVEL_WAVES SQ_LEVEL_WAVES_ACCUM SQ_LDS_IDX_ACTIVE SQ_INSTS_VALU_FMA_F16 SQ_INSTS_VALU_ADD_F16 SQ_INSTS_LDS_LOAD_BANDWIDTH SQ_WAVE_CYCLES SQ_INSTS_LDS TA_FLAT_ATOMIC_WAVEFRONTS_sum TA_BUFFER_ATOMIC_WAVEFRONTS_sum TD_TD_BUSY_sum TCP_TCC_UC_ATOMIC_REQ_sum TCP_TOTAL_CACHE_ACCESSES_sum TCP_TCC_RW_WRITE_REQ_sum TCP_GATE_EN2_sum TCC_EA0_RDREQ_LEVEL[111] TCC_EA0_RDREQ_LEVEL[40] TCC_BUBBLE_sum TCC_TOO_MANY_EA_WRREQS_STALL[102] TCC_TOO_MANY_EA_WRREQS_STALL[50] TCC_EA0_RDREQ_LEVEL[83] TCC_EA0_ATOMIC_LEVEL[51] TCC_TOO_MANY_EA_WRREQS_STALL[114] TCC_EA0_RDREQ_LEVEL[18] TCC_TOO_MANY_EA_WRREQS_STALL[51] TCC_EA0_ATOMIC_LEVEL[112] TCC_TOO_MANY_EA_WRREQS_STALL[124] TCC_EA0_ATOMIC_LEVEL[82] TCC_EA0_ATOMIC_LEVEL[105] TCC_EA0_RDREQ_LEVEL[108] TCC_TOO_MANY_EA_WRREQS_STALL[115] TCC_EA0_ATOMIC_LEVEL[50] TCC_EA0_ATOMIC_LEVEL[49] TCC_EA0_RDREQ_LEVEL[90] TCC_EA0_RDREQ_LEVEL[14] TCC_EA0_RDREQ_LEVEL[101] TCC_EA0_RDREQ_LEVEL[66] TCC_EA0_ATOMIC_LEVEL[107] TCC_TOO_MANY_EA_WRREQS_STALL[55] TCC_TOO_MANY_EA_WRREQS_STALL[60] TCC_EA0_ATOMIC_LEVEL[54] TCC_TOO_MANY_EA_WRREQS_STALL[44] TCC_EA0_RDREQ_LEVEL[110] TCC_TOO_MANY_EA_WRREQS_STALL[104] TCC_EA0_ATOMIC_LEVEL[8] TCC_EA0_ATOMIC_LEVEL[27] TCC_EA0_RDREQ_LEVEL[50] TCC_EA0_RDREQ_LEVEL[49] TCC_TOO_MANY_EA_WRREQS_STALL[127] TCC_TOO_MANY_EA_WRREQS_STALL[27] TCC_TOO_MANY_EA_WRREQS_STALL[82] TCC_EA0_ATOMIC_LEVEL[77] TCC_TOO_MANY_EA_WRREQS_STALL[32] TCC_TOO_MANY_EA_WRREQS_STALL[108] TCC_EA0_RDREQ_LEVEL[69] TCC_TOO_MANY_EA_WRREQS_STALL[45] TCC_TOO_MANY_EA_WRREQS_STALL[63] TCC_EA0_ATOMIC_LEVEL[72] TCC_EA0_RDREQ_LEVEL[105] TCC_EA0_RDREQ_LEVEL[10] TCC_EA0_RDREQ_LEVEL[45] TCC_EA0_ATOMIC_LEVEL[7] TCC_EA0_ATOMIC_LEVEL[89] TCC_EA0_RDREQ_LEVEL[79] TCC_EA0_RDREQ_LEVEL[13] TCC_EA0_ATOMIC_LEVEL[14] TCC_EA0_ATOMIC_LEVEL[69] TCC_EA0_RDREQ_LEVEL[11] TCC_TOO_MANY_EA_WRREQS_STALL[31] TCC_TOO_MANY_EA_WRREQS_STALL[59] TCC_EA0_ATOMIC_LEVEL[92] TCC_TOO_MANY_EA_WRREQS_STALL[86] TCC_EA0_RDREQ_LEVEL[82] TCC_EA0_ATOMIC_LEVEL[66] TCC_EA0_ATOMIC_LEVEL[56] TCC_EA0_ATOMIC_LEVEL[101] TCC_EA0_RDREQ_LEVEL[61] TCC_EA0_ATOMIC_LEVEL[97] TCC_EA0_RDREQ_LEVEL[22] TCC_EA0_RDREQ_LEVEL[44] TCC_EA0_RDREQ_LEVEL[35] TCC_EA0_RDREQ_LEVEL[51] TCC_EA0_ATOMIC_LEVEL[96] TCC_TOO_MANY_EA_WRREQS_STALL[110] TCC_EA0_RDREQ_LEVEL[37] TCC_EA0_ATOMIC_LEVEL[74] TCC_EA0_ATOMIC_LEVEL[23] TCC_EA0_ATOMIC_LEVEL[71] TCC_EA0_ATOMIC_LEVEL[126] TCC_EA0_RDREQ_LEVEL[17] TCC_TOO_MANY_EA_WRREQS_STALL[28] TCC_TOO_MANY_EA_WRREQS_STALL[117] TCC_EA0_ATOMIC_LEVEL[86] TCC_EA0_ATOMIC_LEVEL[61] TCC_EA0_ATOMIC_LEVEL[102] TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_TOO_MANY_EA_WRREQS_STALL[24] TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_EA0_ATOMIC_LEVEL[16] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_EA0_ATOMIC_LEVEL[44] TCC_TOO_MANY_EA_WRREQS_STALL[52] TCC_EA0_RDREQ_LEVEL[70] TCC_EA0_ATOMIC_LEVEL[78] TCC_EA0_RDREQ_LEVEL[74] TCC_EA0_RDREQ_LEVEL[85] TCC_EA0_RDREQ_LEVEL[20] TCC_TOO_MANY_EA_WRREQS_STALL[53] TCC_EA0_RDREQ_LEVEL[123] TCC_EA0_ATOMIC_LEVEL[95] TCC_EA0_RDREQ_LEVEL[19] TCC_EA0_RDREQ_LEVEL[25] TCC_EA0_RDREQ_LEVEL[76] TCC_EA0_ATOMIC_LEVEL[65] TCC_EA0_ATOMIC_LEVEL[114] TCC_TOO_MANY_EA_WRREQS_STALL[122] TCC_EA0_RDREQ_LEVEL[125] TCC_TOO_MANY_EA_WRREQS_STALL[41] TCC_TOO_MANY_EA_WRREQS_STALL[49] TCC_EA0_ATOMIC_LEVEL[20] TCC_EA0_RDREQ_LEVEL[104] TCC_TOO_MANY_EA_WRREQS_STALL[70] TCC_EA0_ATOMIC_LEVEL[42] TCC_TOO_MANY_EA_WRREQS_STALL[74] TCC_EA0_RDREQ_LEVEL[95] TCC_EA0_RDREQ_LEVEL[56] TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_EA0_RDREQ_LEVEL[102] TCC_TOO_MANY_EA_WRREQS_STALL[68] TCC_TOO_MANY_EA_WRREQS_STALL[23] TCC_TOO_MANY_EA_WRREQS_STALL[111] TCC_EA0_RDREQ_LEVEL[3] TCC_EA0_RDREQ_LEVEL[32] TCC_EA0_ATOMIC_LEVEL[39] TCC_EA0_RDREQ_LEVEL[8] TCC_EA0_RDREQ_LEVEL[120] TCC_TOO_MANY_EA_WRREQS_STALL[116] TCC_TOO_MANY_EA_WRREQS_STALL[97] TCC_TOO_MANY_EA_WRREQS_STALL[106] TCC_EA0_ATOMIC_LEVEL[38] TCC_TOO_MANY_EA_WRREQS_STALL[98] TCC_EA0_RDREQ_LEVEL[34] TCC_EA0_ATOMIC_LEVEL[18] TCC_EA0_RDREQ_LEVEL[54] TCC_EA0_RDREQ_LEVEL[2] TCC_EA0_ATOMIC_LEVEL[43] TCC_EA0_ATOMIC_LEVEL[104] TCC_EA0_RDREQ_LEVEL[72] TCC_EA0_RDREQ_LEVEL[78] TCC_EA0_RDREQ_LEVEL[41] TCC_EA0_RDREQ_LEVEL[30] TCC_EA0_ATOMIC_LEVEL[40] TCC_TOO_MANY_EA_WRREQS_STALL[83] TCC_EA0_ATOMIC_LEVEL[111] TCC_EA0_RDREQ_LEVEL[53] TCC_TOO_MANY_EA_WRREQS_STALL[42] TCC_EA0_RDREQ_LEVEL[73] TCC_EA0_RDREQ_LEVEL[103] TCC_EA0_ATOMIC_LEVEL[59] TCC_EA0_RDREQ_LEVEL[100] TCC_EA0_RDREQ_LEVEL[67] TCC_EA0_ATOMIC_LEVEL[57] TCC_EA0_ATOMIC_LEVEL[22] TCC_TOO_MANY_EA_WRREQS_STALL[15] TCC_EA0_ATOMIC_LEVEL[9] TCC_EA0_ATOMIC_LEVEL[100] TCC_EA0_ATOMIC_LEVEL[70] TCC_EA0_ATOMIC_LEVEL[24] TCC_TOO_MANY_EA_WRREQS_STALL[123] TCC_EA0_ATOMIC_LEVEL[98] TCC_EA0_RDREQ_LEVEL[112] TCC_EA0_RDREQ_LEVEL[81] TCC_EA0_ATOMIC_LEVEL[36] TCC_EA0_RDREQ_LEVEL[89] TCC_EA0_RDREQ_LEVEL[126] TCC_EA0_RDREQ_LEVEL[62] TCC_EA0_ATOMIC_LEVEL[30] TCC_EA0_ATOMIC_LEVEL[41] TCC_TOO_MANY_EA_WRREQS_STALL[40] TCC_EA0_ATOMIC_LEVEL[53] TCC_EA0_ATOMIC_LEVEL[85] TCC_EA0_RDREQ_LEVEL[21] TCC_EA0_RDREQ_LEVEL[29] TCC_EA0_RDREQ_LEVEL[58] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_EA0_RDREQ_LEVEL[96] TCC_TOO_MANY_EA_WRREQS_STALL[92] TCC_TOO_MANY_EA_WRREQS_STALL[112] TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_EA0_RDREQ_LEVEL[42] TCC_EA0_RDREQ_LEVEL[12] TCC_EA0_RDREQ_LEVEL[46] TCC_EA0_RDREQ_LEVEL[88] TCC_EA0_ATOMIC_LEVEL[35] TCC_TOO_MANY_EA_WRREQS_STALL[120] TCC_EA0_ATOMIC_LEVEL[25] TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_TOO_MANY_EA_WRREQS_STALL[34] TCC_TOO_MANY_EA_WRREQS_STALL[37] TCC_EA0_RDREQ_LEVEL[75] TCC_EA0_ATOMIC_LEVEL[32] TCC_EA0_ATOMIC_LEVEL[108] TCC_EA0_ATOMIC_LEVEL[10] TCC_EA0_RDREQ_LEVEL[55] TCC_TOO_MANY_EA_WRREQS_STALL[65] TCC_EA0_RDREQ_LEVEL[99] TCC_TOO_MANY_EA_WRREQS_STALL[103] TCC_TOO_MANY_EA_WRREQS_STALL[80] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_TOO_MANY_EA_WRREQS_STALL[29] TCC_TOO_MANY_EA_WRREQS_STALL[87] TCC_TOO_MANY_EA_WRREQS_STALL[20] TCC_EA0_ATOMIC_LEVEL[79] TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_TOO_MANY_EA_WRREQS_STALL[76] TCC_TOO_MANY_EA_WRREQS_STALL[19] TCC_EA0_ATOMIC_LEVEL[17] TCC_EA0_RDREQ_LEVEL[113] TCC_EA0_ATOMIC_LEVEL[21] TCC_EA0_RDREQ_LEVEL[71] TCC_EA0_RDREQ_LEVEL[94] TCC_EA0_ATOMIC_LEVEL[125] TCC_EA0_RDREQ_LEVEL[36] TCC_EA0_ATOMIC_LEVEL[55] TCC_TOO_MANY_EA_WRREQS_STALL[119] TCC_EA0_ATOMIC_LEVEL[48] TCC_EA0_RDREQ_LEVEL[33] TCC_EA0_RDREQ_LEVEL[86] TCC_EA0_RDREQ_LEVEL[9] TCC_TOO_MANY_EA_WRREQS_STALL[16] TCC_TOO_MANY_EA_WRREQS_STALL[64] TCC_EA0_RDREQ_LEVEL[122] TCC_EA0_RDREQ_LEVEL[121] TCC_TOO_MANY_EA_WRREQS_STALL[101] TCC_EA0_ATOMIC_LEVEL[15] TCC_EA0_RDREQ_LEVEL[31] TCC_EA0_RDREQ_LEVEL[7] TCC_TOO_MANY_EA_WRREQS_STALL[57] TCC_EA0_ATOMIC_LEVEL[3] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_EA0_RDREQ_LEVEL[119] TCC_EA0_RDREQ_LEVEL[92] TCC_EA0_ATOMIC_LEVEL[103] TCC_TOO_MANY_EA_WRREQS_STALL[96] TCC_EA0_ATOMIC_LEVEL[88] TCC_TOO_MANY_EA_WRREQS_STALL[43] TCC_TOO_MANY_EA_WRREQS_STALL[91] TCC_TOO_MANY_EA_WRREQS_STALL[54] TCC_TOO_MANY_EA_WRREQS_STALL[94] TCC_EA0_RDREQ_LEVEL[64] TCC_TOO_MANY_EA_WRREQS_STALL[125] TCC_EA0_RDREQ_LEVEL[63] TCC_TOO_MANY_EA_WRREQS_STALL[72] TCC_TOO_MANY_EA_WRREQS_STALL[95] TCC_EA0_ATOMIC_LEVEL[113] TCC_EA0_ATOMIC_LEVEL[90] TCC_EA0_RDREQ_LEVEL[106] TCC_EA0_ATOMIC_LEVEL[87] TCC_EA0_RDREQ_LEVEL[0] TCC_EA0_ATOMIC_LEVEL[47] TCC_TOO_MANY_EA_WRREQS_STALL[99] TCC_TOO_MANY_EA_WRREQS_STALL[58] TCC_EA0_ATOMIC_LEVEL[122] TCC_EA0_ATOMIC_LEVEL[81] TCC_EA0_ATOMIC_LEVEL[6] TCC_EA0_RDREQ_LEVEL[4] TCC_TOO_MANY_EA_WRREQS_STALL[100] TCC_EA0_RDREQ_LEVEL[118] TCC_EA0_ATOMIC_LEVEL[110] TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_EA0_ATOMIC_LEVEL[109] TCC_EA0_RDREQ_LEVEL[23] TCC_EA0_RDREQ_LEVEL[68] TCC_EA0_ATOMIC_LEVEL[116] TCC_EA0_RDREQ_LEVEL[1] TCC_EA0_ATOMIC_LEVEL[12] TCC_EA0_ATOMIC_LEVEL[64] TCC_EA0_RDREQ_LEVEL[114] TCC_EA0_ATOMIC_LEVEL[91] TCC_EA0_RDREQ_LEVEL[65] TCC_EA0_RDREQ_LEVEL[77] TCC_EA0_ATOMIC_LEVEL[52] TCC_EA0_ATOMIC_LEVEL[80] TCC_EA0_ATOMIC_LEVEL[94] TCC_TOO_MANY_EA_WRREQS_STALL[35] TCC_TOO_MANY_EA_WRREQS_STALL[77] TCC_EA0_ATOMIC_LEVEL[67] TCC_EA0_ATOMIC_LEVEL[106] TCC_EA0_RDREQ_LEVEL[115] TCC_EA0_ATOMIC_LEVEL[28] TCC_EA0_ATOMIC_LEVEL[75] TCC_TOO_MANY_EA_WRREQS_STALL[25] TCC_TOO_MANY_EA_WRREQS_STALL[88] TCC_TOO_MANY_EA_WRREQS_STALL[61] TCC_TOO_MANY_EA_WRREQS_STALL[69] TCC_EA0_RDREQ_LEVEL[26] TCC_TOO_MANY_EA_WRREQS_STALL[67] TCC_EA0_ATOMIC_LEVEL[26] TCC_TOO_MANY_EA_WRREQS_STALL[62] TCC_TOO_MANY_EA_WRREQS_STALL[90] TCC_TOO_MANY_EA_WRREQS_STALL[47] TCC_EA0_RDREQ_LEVEL[60] TCC_EA0_ATOMIC_LEVEL[5] TCC_TOO_MANY_EA_WRREQS_STALL[26] TCC_EA0_RDREQ_LEVEL[84] TCC_TOO_MANY_EA_WRREQS_STALL[126] TCC_TOO_MANY_EA_WRREQS_STALL[93] TCC_EA0_ATOMIC_LEVEL[34] TCC_EA0_ATOMIC_LEVEL[2] TCC_EA0_ATOMIC_LEVEL[117] TCC_EA0_RDREQ_LEVEL[97] TCC_EA0_RDREQ_LEVEL[93] TCC_EA0_RDREQ_LEVEL[87] TCC_EA0_ATOMIC_LEVEL[31] TCC_TOO_MANY_EA_WRREQS_STALL[113] TCC_EA0_ATOMIC_LEVEL[121] TCC_EA0_ATOMIC_LEVEL[124] TCC_EA0_RDREQ_LEVEL[28] TCC_TOO_MANY_EA_WRREQS_STALL[73] TCC_EA0_RDREQ_LEVEL[127] TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_EA0_RDREQ_LEVEL[47] TCC_EA0_ATOMIC_LEVEL[62] TCC_EA0_RDREQ_LEVEL[116] TCC_TOO_MANY_EA_WRREQS_STALL[81] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_EA0_ATOMIC_LEVEL[127] TCC_EA0_RDREQ_LEVEL[124] TCC_EA0_RDREQ_LEVEL[107] TCC_TOO_MANY_EA_WRREQS_STALL[66] TCC_EA0_RDREQ_LEVEL[5] TCC_EA0_ATOMIC_LEVEL[0] TCC_EA0_ATOMIC_LEVEL[19] TCC_EA0_ATOMIC_LEVEL[37] TCC_TOO_MANY_EA_WRREQS_STALL[33] TCC_EA0_RDREQ_LEVEL[27] TCC_TOO_MANY_EA_WRREQS_STALL[21] TCC_EA0_ATOMIC_LEVEL[123] TCC_TOO_MANY_EA_WRREQS_STALL[75] TCC_EA0_RDREQ_LEVEL[98] TCC_TOO_MANY_EA_WRREQS_STALL[89] TCC_TOO_MANY_EA_WRREQS_STALL[71] TCC_TOO_MANY_EA_WRREQS_STALL[48] TCC_EA0_ATOMIC_LEVEL[83] TCC_EA0_ATOMIC_LEVEL[68] TCC_TOO_MANY_EA_WRREQS_STALL[107] TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_EA0_ATOMIC_LEVEL[29] TCC_TOO_MANY_EA_WRREQS_STALL[118] TCC_TOO_MANY_EA_WRREQS_STALL[56] TCC_EA0_RDREQ_LEVEL[48] TCC_EA0_RDREQ_LEVEL[15] TCC_EA0_ATOMIC_LEVEL[46] TCC_EA0_ATOMIC_LEVEL[11] TCC_EA0_ATOMIC_LEVEL[60] TCC_EA0_ATOMIC_LEVEL[63] TCC_EA0_RDREQ_LEVEL[80] TCC_EA0_ATOMIC_LEVEL[4] TCC_EA0_ATOMIC_LEVEL[1] TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_EA0_ATOMIC_LEVEL[115] TCC_EA0_ATOMIC_LEVEL[84] TCC_TOO_MANY_EA_WRREQS_STALL[121] TCC_EA0_RDREQ_LEVEL[43] TCC_TOO_MANY_EA_WRREQS_STALL[105] TCC_EA0_ATOMIC_LEVEL[33] TCC_TOO_MANY_EA_WRREQS_STALL[39] TCC_EA0_RDREQ_LEVEL[24] TCC_EA0_ATOMIC_LEVEL[45] TCC_EA0_RDREQ_LEVEL[38] TCC_TOO_MANY_EA_WRREQS_STALL[109] TCC_TOO_MANY_EA_WRREQS_STALL[18] TCC_EA0_ATOMIC_LEVEL[73] TCC_EA0_ATOMIC_LEVEL[120] TCC_TOO_MANY_EA_WRREQS_STALL[84] TCC_EA0_RDREQ_LEVEL[91] TCC_TOO_MANY_EA_WRREQS_STALL[38] TCC_EA0_RDREQ_LEVEL[6] TCC_TOO_MANY_EA_WRREQS_STALL[85] TCC_EA0_RDREQ_LEVEL[52] TCC_EA0_RDREQ_LEVEL[59] TCC_TOO_MANY_EA_WRREQS_STALL[17] TCC_EA0_ATOMIC_LEVEL[99] TCC_EA0_ATOMIC_LEVEL[118] TCC_TOO_MANY_EA_WRREQS_STALL[46] TCC_TOO_MANY_EA_WRREQS_STALL[30] TCC_TOO_MANY_EA_WRREQS_STALL[79] TCC_EA0_ATOMIC_LEVEL[76] TCC_EA0_ATOMIC_LEVEL[93] TCC_EA0_RDREQ_LEVEL[109] TCC_EA0_ATOMIC_LEVEL[58] TCC_EA0_RDREQ_LEVEL[117] TCC_TOO_MANY_EA_WRREQS_STALL[22] TCC_TOO_MANY_EA_WRREQS_STALL[78] TCC_EA0_RDREQ_LEVEL[57] TCC_EA0_RDREQ_LEVEL[16] TCC_EA0_RDREQ_LEVEL[39] TCC_EA0_ATOMIC_LEVEL[119] TCC_EA0_ATOMIC_LEVEL[13] TCC_TOO_MANY_EA_WRREQS_STALL[36] CPC_TG_SEND CPC_CPC_TCIU_IDLE CPF_CPF_TCIU_IDLE SPI_CS2_BUSY SPI_CS1_BUSY SPI_CS0_BUSY SPI_CS3_BUSY + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.yaml b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.yaml new file mode 100644 index 0000000000..0094f14e0e --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/SQ_LEVEL_WAVES.yaml @@ -0,0 +1,1925 @@ +SQ_LEVEL_WAVES_ACCUM: + architectures: + gfx942/gfx941/gfx940/gfx90a: + expression: accumulate(SQ_LEVEL_WAVES, HIGH_RES) + description: SQ_LEVEL_WAVES accumulation +TCC_EA0_ATOMIC_LEVEL[0]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[100]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[101]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[102]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[103]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[104]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[105]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 9th channel +TCC_EA0_ATOMIC_LEVEL[106]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[107]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[108]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[109]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[10]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[110]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[111]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[112]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[113]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[114]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[115]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[116]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[117]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[118]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[119]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[11]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[120]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[121]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 9th channel +TCC_EA0_ATOMIC_LEVEL[122]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[123]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[124]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[125]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[126]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[127]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 7th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[12]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[13]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[14]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[15]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[16]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[17]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[18]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[19]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[1]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[20]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[21]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[22]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[23]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[24]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[25]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 9th channel +TCC_EA0_ATOMIC_LEVEL[26]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[27]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[28]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[29]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[2]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[30]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[31]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 1th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[32]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[33]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[34]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[35]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[36]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[37]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[38]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[39]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[3]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[40]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[41]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 9th channel +TCC_EA0_ATOMIC_LEVEL[42]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[43]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[44]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[45]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[46]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[47]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 2th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[48]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[49]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[4]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[50]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[51]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[52]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[53]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[54]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[55]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[56]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[57]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 9th channel +TCC_EA0_ATOMIC_LEVEL[58]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[59]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[5]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[60]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[61]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[62]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[63]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 3th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[64]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[65]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[66]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[67]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[68]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[69]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[6]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[70]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[71]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[72]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[73]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 9th channel +TCC_EA0_ATOMIC_LEVEL[74]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[75]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[76]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[77]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[78]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[79]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 4th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[7]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[80]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[81]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[82]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[83]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[84]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 4th channel +TCC_EA0_ATOMIC_LEVEL[85]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 5th channel +TCC_EA0_ATOMIC_LEVEL[86]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 6th channel +TCC_EA0_ATOMIC_LEVEL[87]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 7th channel +TCC_EA0_ATOMIC_LEVEL[88]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[89]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 9th channel +TCC_EA0_ATOMIC_LEVEL[8]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 8th channel +TCC_EA0_ATOMIC_LEVEL[90]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 10th channel +TCC_EA0_ATOMIC_LEVEL[91]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 11th channel +TCC_EA0_ATOMIC_LEVEL[92]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 12th channel +TCC_EA0_ATOMIC_LEVEL[93]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 13th channel +TCC_EA0_ATOMIC_LEVEL[94]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 14th channel +TCC_EA0_ATOMIC_LEVEL[95]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_ATOMIC_LEVEL on 5th XCC and 15th channel +TCC_EA0_ATOMIC_LEVEL[96]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 0th channel +TCC_EA0_ATOMIC_LEVEL[97]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 1th channel +TCC_EA0_ATOMIC_LEVEL[98]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 2th channel +TCC_EA0_ATOMIC_LEVEL[99]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_ATOMIC_LEVEL on 6th XCC and 3th channel +TCC_EA0_ATOMIC_LEVEL[9]: + architectures: + gfx950: + expression: select(TCC_EA0_ATOMIC_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_ATOMIC_LEVEL on 0th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[0]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[100]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[101]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[102]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[103]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[104]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[105]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[106]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[107]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[108]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[109]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[10]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[110]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[111]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[112]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[113]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[114]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[115]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[116]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[117]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[118]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[119]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[11]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[120]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[121]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[122]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[123]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[124]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[125]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[126]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[127]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 7th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[12]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[13]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[14]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[15]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[16]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[17]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[18]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[19]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[1]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[20]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[21]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[22]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[23]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[24]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[25]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[26]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[27]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[28]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[29]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[2]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[30]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[31]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 1th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[32]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[33]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[34]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[35]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[36]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[37]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[38]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[39]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[3]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[40]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[41]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[42]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[43]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[44]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[45]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[46]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[47]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 2th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[48]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[49]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[4]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[50]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[51]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[52]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[53]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[54]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[55]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[56]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[57]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[58]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[59]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[5]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[60]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[61]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[62]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[63]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 3th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[64]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[65]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[66]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[67]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[68]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[69]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[6]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[70]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[71]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[72]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[73]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[74]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[75]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[76]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[77]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[78]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[79]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 4th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[7]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[80]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[81]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[82]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[83]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[84]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 4th channel +TCC_EA0_RDREQ_LEVEL[85]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 5th channel +TCC_EA0_RDREQ_LEVEL[86]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 6th channel +TCC_EA0_RDREQ_LEVEL[87]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 7th channel +TCC_EA0_RDREQ_LEVEL[88]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[89]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 9th channel +TCC_EA0_RDREQ_LEVEL[8]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 8th channel +TCC_EA0_RDREQ_LEVEL[90]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 10th channel +TCC_EA0_RDREQ_LEVEL[91]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 11th channel +TCC_EA0_RDREQ_LEVEL[92]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 12th channel +TCC_EA0_RDREQ_LEVEL[93]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 13th channel +TCC_EA0_RDREQ_LEVEL[94]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 14th channel +TCC_EA0_RDREQ_LEVEL[95]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_EA0_RDREQ_LEVEL on 5th XCC and 15th channel +TCC_EA0_RDREQ_LEVEL[96]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 0th channel +TCC_EA0_RDREQ_LEVEL[97]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 1th channel +TCC_EA0_RDREQ_LEVEL[98]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 2th channel +TCC_EA0_RDREQ_LEVEL[99]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_EA0_RDREQ_LEVEL on 6th XCC and 3th channel +TCC_EA0_RDREQ_LEVEL[9]: + architectures: + gfx950: + expression: select(TCC_EA0_RDREQ_LEVEL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_EA0_RDREQ_LEVEL on 0th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[0]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[100]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[101]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[102]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[103]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[104]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[105]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[106]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[107]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[108]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[109]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[10]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[110]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[111]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[112]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[113]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[114]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[115]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[116]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[117]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[118]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[119]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[11]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[120]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[121]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[122]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[123]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[124]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[125]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[126]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[127]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[7], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 7th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[12]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[13]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[14]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[15]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[16]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[17]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[18]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[19]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[1]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[20]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[21]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[22]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[23]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[24]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[25]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[26]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[27]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[28]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[29]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[2]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[30]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[31]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[1], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 1th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[32]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[33]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[34]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[35]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[36]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[37]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[38]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[39]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[3]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[40]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[41]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[42]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[43]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[44]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[45]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[46]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[47]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[2], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 2th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[48]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[49]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[4]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[50]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[51]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[52]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[53]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[54]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[55]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[56]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[57]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[58]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[59]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[5]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[60]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[61]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[62]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[63]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[3], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 3th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[64]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[65]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[66]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[67]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[68]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[69]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[6]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[70]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[71]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[72]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[73]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[74]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[75]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[76]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[77]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[78]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[79]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[4], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 4th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[7]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[80]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[81]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[82]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[83]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[84]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[4]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 4th channel +TCC_TOO_MANY_EA_WRREQS_STALL[85]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[5]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 5th channel +TCC_TOO_MANY_EA_WRREQS_STALL[86]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[6]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 6th channel +TCC_TOO_MANY_EA_WRREQS_STALL[87]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[7]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 7th channel +TCC_TOO_MANY_EA_WRREQS_STALL[88]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[89]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 9th channel +TCC_TOO_MANY_EA_WRREQS_STALL[8]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[8]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 8th channel +TCC_TOO_MANY_EA_WRREQS_STALL[90]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[10]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 10th channel +TCC_TOO_MANY_EA_WRREQS_STALL[91]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[11]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 11th channel +TCC_TOO_MANY_EA_WRREQS_STALL[92]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[12]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 12th channel +TCC_TOO_MANY_EA_WRREQS_STALL[93]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[13]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 13th channel +TCC_TOO_MANY_EA_WRREQS_STALL[94]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[14]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 14th channel +TCC_TOO_MANY_EA_WRREQS_STALL[95]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[5], DIMENSION_INSTANCE=[15]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 5th XCC and 15th channel +TCC_TOO_MANY_EA_WRREQS_STALL[96]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[0]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 0th channel +TCC_TOO_MANY_EA_WRREQS_STALL[97]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[1]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 1th channel +TCC_TOO_MANY_EA_WRREQS_STALL[98]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[2]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 2th channel +TCC_TOO_MANY_EA_WRREQS_STALL[99]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[6], DIMENSION_INSTANCE=[3]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 6th XCC and 3th channel +TCC_TOO_MANY_EA_WRREQS_STALL[9]: + architectures: + gfx950: + expression: select(TCC_TOO_MANY_EA_WRREQS_STALL,[DIMENSION_XCC=[0], DIMENSION_INSTANCE=[9]]) + description: TCC_TOO_MANY_EA_WRREQS_STALL on 0th XCC and 9th channel diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_0.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_0.txt new file mode 100644 index 0000000000..6929e642c2 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_0.txt @@ -0,0 +1,5 @@ +pmc: SQ_INSTS_VALU_ADD_F64 SQ_ACTIVE_INST_VALU SQ_INSTS_SENDMSG SQ_VMEM_TA_CMD_FIFO_FULL SQC_DCACHE_REQ_READ_8 SQC_TC_DATA_ATOMIC_REQ SQ_LDS_BANK_CONFLICT SQ_BUSY_CYCLES TA_DATA_STALLED_BY_TC_CYCLES_sum TA_BUFFER_WAVEFRONTS_sum TCP_TCR_TCP_STALL_CYCLES_sum TCP_UTCL1_TRANSLATION_MISS_sum TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum TCP_TCC_READ_REQ_sum TCC_UC_REQ_sum TCC_ALL_TC_OP_INV_EVICT_sum TCC_ALL_TC_OP_WB_WRITEBACK_sum TCC_EA0_WRREQ_LEVEL_sum CPC_SYNC_FIFO_FULL CPC_CPC_UTCL2IU_BUSY SPI_CS2_NUM_THREADGROUPS SPI_CS3_NUM_THREADGROUPS SPI_CS1_NUM_THREADGROUPS SPI_CS0_NUM_THREADGROUPS + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_0.yaml b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_0.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_1.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_1.txt new file mode 100644 index 0000000000..d484937f6f --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_1.txt @@ -0,0 +1,5 @@ +pmc: SQ_INSTS_VALU_MFMA_MOPS_F16 SQC_TC_DATA_READ_REQ SQ_INSTS_VMEM SQ_VALU_MFMA_BUSY_CYCLES SQ_INSTS_VALU_MFMA_MOPS_F6F4 SQ_INSTS_VALU_INT64 SQC_DCACHE_REQ_READ_4 SQ_INSTS_VALU_TRANS_F64 TA_FLAT_WRITE_WAVEFRONTS_sum TA_BUFFER_READ_WAVEFRONTS_sum TCP_PENDING_STALL_CYCLES_sum TCP_TCC_NC_READ_REQ_sum TCP_TCC_UC_WRITE_REQ_sum TCP_UTCL1_PERMISSION_MISS_sum TCC_EA0_RD_UNCACHED_32B_sum TCC_CC_REQ_sum TCC_EA0_RDREQ_LEVEL_sum TCC_RW_REQ_sum CPC_GD_BUSY CPC_CANE_BUSY SPI_RA_REQ_NO_ALLOC SPI_SWC_CSC_WR + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_1.yaml b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_1.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_2.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_2.txt new file mode 100644 index 0000000000..713658c6cd --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_2.txt @@ -0,0 +1,5 @@ +pmc: SQ_THREAD_CYCLES_VALU SQC_DCACHE_MISSES_DUPLICATE SQ_INSTS_VALU_FMA_F32 SQ_INSTS_VALU_MFMA_MOPS_F8 SQ_INSTS_VALU_MFMA_F8 SQ_INSTS_SMEM SQ_INSTS_VALU_INT32 SQ_INSTS_VALU_TRANS_F32 TA_BUFFER_COALESCED_WRITE_CYCLES_sum TA_TOTAL_WAVEFRONTS_sum TCP_TCC_CC_READ_REQ_sum TCP_TCC_CC_ATOMIC_REQ_sum TCP_TCC_WRITE_REQ_sum TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum TCC_BUSY_sum TCC_HIT_sum TCC_NORMAL_WRITEBACK_sum TCC_READ_sum CPC_CPC_UTCL2IU_IDLE CPC_UTCL1_STALL_ON_TRANSLATION SPI_RA_RES_STALL_CSN SPI_RA_BAR_CU_FULL_CSN + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_2.yaml b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_2.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_3.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_3.txt new file mode 100644 index 0000000000..14d59e51d2 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_3.txt @@ -0,0 +1,5 @@ +pmc: SQC_DCACHE_REQ_READ_2 SQ_INSTS_LDS_STORE_BANDWIDTH SQ_LDS_MEM_VIOLATIONS SQ_ACTIVE_INST_ANY SQ_LDS_ATOMIC_RETURN SQ_INSTS_BRANCH SQ_INSTS_VALU_CVT SQ_ACTIVE_INST_MISC TCP_TOTAL_ACCESSES_sum TCP_TOTAL_READ_sum TCP_TOTAL_ATOMIC_WITHOUT_RET_sum TCP_TCC_CC_WRITE_REQ_sum TCC_WRITEBACK_sum TCC_PROBE_sum TCC_MISS_sum TCC_REQ_sum SPI_VWC1_VDATA_VALID_WR SPI_RA_VGPR_SIMD_FULL_CSN + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_3.yaml b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_3.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_4.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_4.txt new file mode 100644 index 0000000000..47fdf4f427 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_4.txt @@ -0,0 +1,5 @@ +pmc: SQ_WAVES_RESTORED SQ_WAVES SQ_LDS_DATA_FIFO_FULL SQC_TC_DATA_WRITE_REQ SQ_INSTS_VALU_MFMA_F64 SQ_INSTS_VALU_MFMA_BF16 SQ_ACTIVE_INST_LDS SQ_VMEM_TA_ADDR_FIFO_FULL TCC_EA0_WRREQ_64B_sum TCC_EA0_ATOMIC_sum TCC_EA0_RDREQ_DRAM_sum TCC_EA0_WRREQ_DRAM_sum SPI_CSC_WAVE_CNT_BUSY SPI_RA_WAVE_SIMD_FULL_CSN + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_4.yaml b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_4.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_5.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_5.txt new file mode 100644 index 0000000000..6c6703231c --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_5.txt @@ -0,0 +1,5 @@ +pmc: SQ_LDS_ADDR_CONFLICT SQC_ICACHE_HITS SQ_INSTS_LDS_ATOMIC_BANDWIDTH SQ_INSTS_MFMA SQ_WAIT_INST_ANY SQ_INSTS_VALU_MFMA_F6F4 SQ_INSTS_VALU_MUL_F32 SQC_DCACHE_REQ_READ_1 TCC_STREAMING_REQ_sum TCC_EA0_RDREQ_32B_sum TCC_EA0_RDREQ_sum TCC_WRITE_sum SPI_RA_LDS_CU_FULL_CSN SPI_RA_TMP_STALL_CSN + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_5.yaml b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_5.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_6.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_6.txt new file mode 100644 index 0000000000..57f5e105e2 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_6.txt @@ -0,0 +1,5 @@ +pmc: SQ_INSTS_VALU_MFMA_MOPS_F64 SQ_LDS_UNALIGNED_STALL SQ_INSTS_VALU_MFMA_I8 SQ_INSTS_VALU SQ_WAIT_ANY SQ_INSTS_VALU_TRANS_F16 SQ_INSTS_VALU_MFMA_MOPS_BF16 SQC_TC_INST_REQ TCC_EA0_WR_UNCACHED_32B_sum TCC_NORMAL_EVICT_sum SPI_RA_WVLIM_STALL_CSN SPI_RA_TGLIM_CU_FULL_CSN + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_6.yaml b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_6.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_7.txt b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_7.txt new file mode 100644 index 0000000000..875789310c --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_7.txt @@ -0,0 +1,5 @@ +pmc: SQC_DCACHE_REQ SQ_INSTS_SALU SQ_ACTIVE_INST_FLAT SQ_IFETCH SQ_ACTIVE_INST_SCA SQ_INSTS SQ_INSTS_VALU_MFMA_F32 SQ_INSTS_VALU_ADD_F32 + +gpu: +range: +kernel: diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_7.yaml b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/perfmon/pmc_perf_7.yaml new file mode 100644 index 0000000000..e69de29bb2 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_dispatch_info.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_dispatch_info.csv new file mode 100644 index 0000000000..c65b416c9a --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_dispatch_info.csv @@ -0,0 +1,4 @@ +Dispatch_ID,Kernel_Name,GPU_ID +0,"vecCopy(double*, double*, double*, int, int)",0 +1,"vecCopy(double*, double*, double*, int, int)",0 +2,"vecCopy(double*, double*, double*, int, int)",0 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf.csv new file mode 100644 index 0000000000..83f23a7a40 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Correlation_ID,Kernel_ID,CPC_CANE_BUSY,CPC_GD_BUSY,SPI_RA_REQ_NO_ALLOC,SPI_SWC_CSC_WR,SQC_DCACHE_REQ_READ_4,SQC_TC_DATA_READ_REQ,SQ_INSTS_VALU_INT64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_F6F4,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VMEM,SQ_VALU_MFMA_BUSY_CYCLES,TA_BUFFER_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TCC_CC_REQ_sum,TCC_EA0_RDREQ_LEVEL_sum,TCC_EA0_RD_UNCACHED_32B_sum,TCC_RW_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_UTCL1_PERMISSION_MISS_sum,Kernel_ID_1,CPC_CPC_UTCL2IU_BUSY,CPC_SYNC_FIFO_FULL,SPI_CS0_NUM_THREADGROUPS,SPI_CS1_NUM_THREADGROUPS,SPI_CS2_NUM_THREADGROUPS,SPI_CS3_NUM_THREADGROUPS,SQC_DCACHE_REQ_READ_8,SQC_TC_DATA_ATOMIC_REQ,SQ_ACTIVE_INST_VALU,SQ_BUSY_CYCLES,SQ_INSTS_SENDMSG,SQ_INSTS_VALU_ADD_F64,SQ_LDS_BANK_CONFLICT,SQ_VMEM_TA_CMD_FIFO_FULL,TA_BUFFER_WAVEFRONTS_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_EA0_WRREQ_LEVEL_sum,TCC_UC_REQ_sum,TCP_TCC_READ_REQ_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,Kernel_ID_2,SPI_RA_LDS_CU_FULL_CSN,SPI_RA_TMP_STALL_CSN,SQC_DCACHE_REQ_READ_1,SQC_ICACHE_HITS,SQ_INSTS_LDS_ATOMIC_BANDWIDTH,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_F6F4,SQ_INSTS_VALU_MUL_F32,SQ_LDS_ADDR_CONFLICT,SQ_WAIT_INST_ANY,TCC_EA0_RDREQ_32B_sum,TCC_EA0_RDREQ_sum,TCC_STREAMING_REQ_sum,TCC_WRITE_sum,Kernel_ID_3,SQC_DCACHE_REQ,SQ_ACTIVE_INST_FLAT,SQ_ACTIVE_INST_SCA,SQ_IFETCH,SQ_INSTS,SQ_INSTS_SALU,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MFMA_F32,Kernel_ID_4,SPI_RA_VGPR_SIMD_FULL_CSN,SPI_VWC1_VDATA_VALID_WR,SQC_DCACHE_REQ_READ_2,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_MISC,SQ_INSTS_BRANCH,SQ_INSTS_LDS_STORE_BANDWIDTH,SQ_INSTS_VALU_CVT,SQ_LDS_ATOMIC_RETURN,SQ_LDS_MEM_VIOLATIONS,TCC_MISS_sum,TCC_PROBE_sum,TCC_REQ_sum,TCC_WRITEBACK_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_READ_sum,Kernel_ID_5,CPC_CPC_UTCL2IU_IDLE,CPC_UTCL1_STALL_ON_TRANSLATION,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_RES_STALL_CSN,SQC_DCACHE_MISSES_DUPLICATE,SQ_INSTS_SMEM,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_MFMA_F8,SQ_INSTS_VALU_MFMA_MOPS_F8,SQ_INSTS_VALU_TRANS_F32,SQ_THREAD_CYCLES_VALU,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_BUSY_sum,TCC_HIT_sum,TCC_NORMAL_WRITEBACK_sum,TCC_READ_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,Kernel_ID_6,SPI_RA_TGLIM_CU_FULL_CSN,SPI_RA_WVLIM_STALL_CSN,SQC_TC_INST_REQ,SQ_INSTS_VALU,SQ_INSTS_VALU_MFMA_I8,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F64,SQ_INSTS_VALU_TRANS_F16,SQ_LDS_UNALIGNED_STALL,SQ_WAIT_ANY,TCC_EA0_WR_UNCACHED_32B_sum,TCC_NORMAL_EVICT_sum,Kernel_ID_7,SPI_CSC_WAVE_CNT_BUSY,SPI_RA_WAVE_SIMD_FULL_CSN,SQC_TC_DATA_WRITE_REQ,SQ_ACTIVE_INST_LDS,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F64,SQ_LDS_DATA_FIFO_FULL,SQ_VMEM_TA_ADDR_FIFO_FULL,SQ_WAVES,SQ_WAVES_RESTORED,TCC_EA0_ATOMIC_sum,TCC_EA0_RDREQ_DRAM_sum,TCC_EA0_WRREQ_64B_sum,TCC_EA0_WRREQ_DRAM_sum,Kernel_ID_8,CPC_CPC_TCIU_BUSY,CPC_ME1_DC0_SPI_BUSY,SPI_RA_REQ_NO_ALLOC_CSN,SPI_VWC0_VDATA_VALID_WR,SQC_DCACHE_ATOMIC,SQC_DCACHE_MISSES,SQC_ICACHE_REQ,SQC_TC_STALL,SQ_INSTS_VALU_MUL_F16,SQ_INST_LEVEL_LDS,SQ_WAVES_SAVED,TA_BUFFER_WRITE_WAVEFRONTS_sum,TA_TA_BUSY_sum,TCC_ATOMIC_sum,TCC_EA0_ATOMIC_LEVEL_sum,TCC_EA0_WRREQ_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_UTCL1_REQUEST_sum,Kernel_ID_9,CPC_CPC_TCIU_IDLE,CPC_TG_SEND,CPF_CPF_TCIU_IDLE,SPI_CS0_BUSY,SPI_CS1_BUSY,SPI_CS2_BUSY,SPI_CS3_BUSY,SQ_INSTS_LDS,SQ_INSTS_LDS_LOAD_BANDWIDTH,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_FMA_F16,SQ_LDS_IDX_ACTIVE,SQ_LEVEL_WAVES,SQ_WAVE_CYCLES,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TCC_BUBBLE_sum,TCC_EA0_ATOMIC_LEVEL[0],TCC_EA0_ATOMIC_LEVEL[11],TCC_EA0_ATOMIC_LEVEL[12],TCC_EA0_ATOMIC_LEVEL[13],TCC_EA0_ATOMIC_LEVEL[14],TCC_EA0_ATOMIC_LEVEL[16],TCC_EA0_ATOMIC_LEVEL[17],TCC_EA0_ATOMIC_LEVEL[18],TCC_EA0_ATOMIC_LEVEL[19],TCC_EA0_ATOMIC_LEVEL[1],TCC_EA0_ATOMIC_LEVEL[22],TCC_EA0_ATOMIC_LEVEL[23],TCC_EA0_ATOMIC_LEVEL[24],TCC_EA0_ATOMIC_LEVEL[25],TCC_EA0_ATOMIC_LEVEL[27],TCC_EA0_ATOMIC_LEVEL[28],TCC_EA0_ATOMIC_LEVEL[29],TCC_EA0_ATOMIC_LEVEL[2],TCC_EA0_ATOMIC_LEVEL[30],TCC_EA0_ATOMIC_LEVEL[32],TCC_EA0_ATOMIC_LEVEL[33],TCC_EA0_ATOMIC_LEVEL[34],TCC_EA0_ATOMIC_LEVEL[35],TCC_EA0_ATOMIC_LEVEL[37],TCC_EA0_ATOMIC_LEVEL[38],TCC_EA0_ATOMIC_LEVEL[39],TCC_EA0_ATOMIC_LEVEL[3],TCC_EA0_ATOMIC_LEVEL[40],TCC_EA0_ATOMIC_LEVEL[43],TCC_EA0_ATOMIC_LEVEL[44],TCC_EA0_ATOMIC_LEVEL[45],TCC_EA0_ATOMIC_LEVEL[46],TCC_EA0_ATOMIC_LEVEL[48],TCC_EA0_ATOMIC_LEVEL[49],TCC_EA0_ATOMIC_LEVEL[4],TCC_EA0_ATOMIC_LEVEL[50],TCC_EA0_ATOMIC_LEVEL[51],TCC_EA0_ATOMIC_LEVEL[53],TCC_EA0_ATOMIC_LEVEL[54],TCC_EA0_ATOMIC_LEVEL[55],TCC_EA0_ATOMIC_LEVEL[56],TCC_EA0_ATOMIC_LEVEL[58],TCC_EA0_ATOMIC_LEVEL[59],TCC_EA0_ATOMIC_LEVEL[60],TCC_EA0_ATOMIC_LEVEL[61],TCC_EA0_ATOMIC_LEVEL[6],TCC_EA0_ATOMIC_LEVEL[7],TCC_EA0_ATOMIC_LEVEL[8],TCC_EA0_ATOMIC_LEVEL[9],TCC_EA0_RDREQ_LEVEL[0],TCC_EA0_RDREQ_LEVEL[11],TCC_EA0_RDREQ_LEVEL[12],TCC_EA0_RDREQ_LEVEL[13],TCC_EA0_RDREQ_LEVEL[14],TCC_EA0_RDREQ_LEVEL[16],TCC_EA0_RDREQ_LEVEL[17],TCC_EA0_RDREQ_LEVEL[18],TCC_EA0_RDREQ_LEVEL[19],TCC_EA0_RDREQ_LEVEL[1],TCC_EA0_RDREQ_LEVEL[22],TCC_EA0_RDREQ_LEVEL[23],TCC_EA0_RDREQ_LEVEL[24],TCC_EA0_RDREQ_LEVEL[25],TCC_EA0_RDREQ_LEVEL[27],TCC_EA0_RDREQ_LEVEL[28],TCC_EA0_RDREQ_LEVEL[29],TCC_EA0_RDREQ_LEVEL[2],TCC_EA0_RDREQ_LEVEL[30],TCC_EA0_RDREQ_LEVEL[32],TCC_EA0_RDREQ_LEVEL[33],TCC_EA0_RDREQ_LEVEL[34],TCC_EA0_RDREQ_LEVEL[35],TCC_EA0_RDREQ_LEVEL[37],TCC_EA0_RDREQ_LEVEL[38],TCC_EA0_RDREQ_LEVEL[39],TCC_EA0_RDREQ_LEVEL[3],TCC_EA0_RDREQ_LEVEL[40],TCC_EA0_RDREQ_LEVEL[43],TCC_EA0_RDREQ_LEVEL[44],TCC_EA0_RDREQ_LEVEL[45],TCC_EA0_RDREQ_LEVEL[46],TCC_EA0_RDREQ_LEVEL[48],TCC_EA0_RDREQ_LEVEL[49],TCC_EA0_RDREQ_LEVEL[4],TCC_EA0_RDREQ_LEVEL[50],TCC_EA0_RDREQ_LEVEL[51],TCC_EA0_RDREQ_LEVEL[53],TCC_EA0_RDREQ_LEVEL[54],TCC_EA0_RDREQ_LEVEL[55],TCC_EA0_RDREQ_LEVEL[56],TCC_EA0_RDREQ_LEVEL[58],TCC_EA0_RDREQ_LEVEL[59],TCC_EA0_RDREQ_LEVEL[60],TCC_EA0_RDREQ_LEVEL[61],TCC_EA0_RDREQ_LEVEL[6],TCC_EA0_RDREQ_LEVEL[7],TCC_EA0_RDREQ_LEVEL[8],TCC_EA0_RDREQ_LEVEL[9],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_TOO_MANY_EA_WRREQS_STALL[32],TCC_TOO_MANY_EA_WRREQS_STALL[33],TCC_TOO_MANY_EA_WRREQS_STALL[34],TCC_TOO_MANY_EA_WRREQS_STALL[35],TCC_TOO_MANY_EA_WRREQS_STALL[37],TCC_TOO_MANY_EA_WRREQS_STALL[38],TCC_TOO_MANY_EA_WRREQS_STALL[39],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_TOO_MANY_EA_WRREQS_STALL[40],TCC_TOO_MANY_EA_WRREQS_STALL[43],TCC_TOO_MANY_EA_WRREQS_STALL[44],TCC_TOO_MANY_EA_WRREQS_STALL[45],TCC_TOO_MANY_EA_WRREQS_STALL[46],TCC_TOO_MANY_EA_WRREQS_STALL[48],TCC_TOO_MANY_EA_WRREQS_STALL[49],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_TOO_MANY_EA_WRREQS_STALL[50],TCC_TOO_MANY_EA_WRREQS_STALL[51],TCC_TOO_MANY_EA_WRREQS_STALL[53],TCC_TOO_MANY_EA_WRREQS_STALL[54],TCC_TOO_MANY_EA_WRREQS_STALL[55],TCC_TOO_MANY_EA_WRREQS_STALL[56],TCC_TOO_MANY_EA_WRREQS_STALL[58],TCC_TOO_MANY_EA_WRREQS_STALL[59],TCC_TOO_MANY_EA_WRREQS_STALL[60],TCC_TOO_MANY_EA_WRREQS_STALL[61],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCP_GATE_EN2_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TD_TD_BUSY_sum,Kernel_ID_10,CPC_ME1_BUSY_FOR_PACKET_DECODE,CPC_SYNC_WRREQ_FIFO_BUSY,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_BUSY,GRBM_GUI_ACTIVE,SPI_CS0_WAVE,SPI_CS1_WAVE,SPI_CS2_WAVE,SPI_CS3_WAVE,SQC_DCACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,SQ_IFETCH_LEVEL,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_VMEM_WR_TA_DATA_FIFO_FULL,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_FLAT_WAVEFRONTS_sum,TCC_EA0_RDREQ[0],TCC_EA0_RDREQ[10],TCC_EA0_RDREQ[11],TCC_EA0_RDREQ[12],TCC_EA0_RDREQ[13],TCC_EA0_RDREQ[14],TCC_EA0_RDREQ[15],TCC_EA0_RDREQ[16],TCC_EA0_RDREQ[17],TCC_EA0_RDREQ[18],TCC_EA0_RDREQ[19],TCC_EA0_RDREQ[1],TCC_EA0_RDREQ[20],TCC_EA0_RDREQ[21],TCC_EA0_RDREQ[22],TCC_EA0_RDREQ[23],TCC_EA0_RDREQ[25],TCC_EA0_RDREQ[26],TCC_EA0_RDREQ[27],TCC_EA0_RDREQ[28],TCC_EA0_RDREQ[29],TCC_EA0_RDREQ[2],TCC_EA0_RDREQ[30],TCC_EA0_RDREQ[31],TCC_EA0_RDREQ[32],TCC_EA0_RDREQ[33],TCC_EA0_RDREQ[34],TCC_EA0_RDREQ[35],TCC_EA0_RDREQ[36],TCC_EA0_RDREQ[37],TCC_EA0_RDREQ[38],TCC_EA0_RDREQ[39],TCC_EA0_RDREQ[3],TCC_EA0_RDREQ[40],TCC_EA0_RDREQ[41],TCC_EA0_RDREQ[42],TCC_EA0_RDREQ[43],TCC_EA0_RDREQ[45],TCC_EA0_RDREQ[46],TCC_EA0_RDREQ[47],TCC_EA0_RDREQ[48],TCC_EA0_RDREQ[49],TCC_EA0_RDREQ[50],TCC_EA0_RDREQ[51],TCC_EA0_RDREQ[52],TCC_EA0_RDREQ[53],TCC_EA0_RDREQ[54],TCC_EA0_RDREQ[55],TCC_EA0_RDREQ[56],TCC_EA0_RDREQ[57],TCC_EA0_RDREQ[58],TCC_EA0_RDREQ[59],TCC_EA0_RDREQ[5],TCC_EA0_RDREQ[60],TCC_EA0_RDREQ[61],TCC_EA0_RDREQ[62],TCC_EA0_RDREQ[63],TCC_EA0_RDREQ[6],TCC_EA0_RDREQ[7],TCC_EA0_RDREQ[8],TCC_EA0_RDREQ[9],TCC_EA0_WRREQ_LEVEL[0],TCC_EA0_WRREQ_LEVEL[10],TCC_EA0_WRREQ_LEVEL[11],TCC_EA0_WRREQ_LEVEL[12],TCC_EA0_WRREQ_LEVEL[13],TCC_EA0_WRREQ_LEVEL[14],TCC_EA0_WRREQ_LEVEL[15],TCC_EA0_WRREQ_LEVEL[16],TCC_EA0_WRREQ_LEVEL[17],TCC_EA0_WRREQ_LEVEL[18],TCC_EA0_WRREQ_LEVEL[19],TCC_EA0_WRREQ_LEVEL[1],TCC_EA0_WRREQ_LEVEL[20],TCC_EA0_WRREQ_LEVEL[21],TCC_EA0_WRREQ_LEVEL[22],TCC_EA0_WRREQ_LEVEL[23],TCC_EA0_WRREQ_LEVEL[25],TCC_EA0_WRREQ_LEVEL[26],TCC_EA0_WRREQ_LEVEL[27],TCC_EA0_WRREQ_LEVEL[28],TCC_EA0_WRREQ_LEVEL[29],TCC_EA0_WRREQ_LEVEL[2],TCC_EA0_WRREQ_LEVEL[30],TCC_EA0_WRREQ_LEVEL[31],TCC_EA0_WRREQ_LEVEL[32],TCC_EA0_WRREQ_LEVEL[33],TCC_EA0_WRREQ_LEVEL[34],TCC_EA0_WRREQ_LEVEL[35],TCC_EA0_WRREQ_LEVEL[36],TCC_EA0_WRREQ_LEVEL[37],TCC_EA0_WRREQ_LEVEL[38],TCC_EA0_WRREQ_LEVEL[39],TCC_EA0_WRREQ_LEVEL[3],TCC_EA0_WRREQ_LEVEL[40],TCC_EA0_WRREQ_LEVEL[41],TCC_EA0_WRREQ_LEVEL[42],TCC_EA0_WRREQ_LEVEL[43],TCC_EA0_WRREQ_LEVEL[45],TCC_EA0_WRREQ_LEVEL[46],TCC_EA0_WRREQ_LEVEL[47],TCC_EA0_WRREQ_LEVEL[48],TCC_EA0_WRREQ_LEVEL[49],TCC_EA0_WRREQ_LEVEL[50],TCC_EA0_WRREQ_LEVEL[51],TCC_EA0_WRREQ_LEVEL[52],TCC_EA0_WRREQ_LEVEL[53],TCC_EA0_WRREQ_LEVEL[54],TCC_EA0_WRREQ_LEVEL[55],TCC_EA0_WRREQ_LEVEL[56],TCC_EA0_WRREQ_LEVEL[57],TCC_EA0_WRREQ_LEVEL[58],TCC_EA0_WRREQ_LEVEL[59],TCC_EA0_WRREQ_LEVEL[5],TCC_EA0_WRREQ_LEVEL[60],TCC_EA0_WRREQ_LEVEL[61],TCC_EA0_WRREQ_LEVEL[62],TCC_EA0_WRREQ_LEVEL[63],TCC_EA0_WRREQ_LEVEL[6],TCC_EA0_WRREQ_LEVEL[7],TCC_EA0_WRREQ_LEVEL[8],TCC_EA0_WRREQ_LEVEL[9],TCC_NC_REQ_sum,TCC_REQ[0],TCC_REQ[10],TCC_REQ[11],TCC_REQ[12],TCC_REQ[13],TCC_REQ[14],TCC_REQ[15],TCC_REQ[16],TCC_REQ[17],TCC_REQ[18],TCC_REQ[19],TCC_REQ[1],TCC_REQ[20],TCC_REQ[21],TCC_REQ[22],TCC_REQ[23],TCC_REQ[25],TCC_REQ[26],TCC_REQ[27],TCC_REQ[28],TCC_REQ[29],TCC_REQ[2],TCC_REQ[30],TCC_REQ[31],TCC_REQ[32],TCC_REQ[33],TCC_REQ[34],TCC_REQ[35],TCC_REQ[36],TCC_REQ[37],TCC_REQ[38],TCC_REQ[39],TCC_REQ[3],TCC_REQ[40],TCC_REQ[41],TCC_REQ[42],TCC_REQ[43],TCC_REQ[45],TCC_REQ[46],TCC_REQ[47],TCC_REQ[48],TCC_REQ[49],TCC_REQ[50],TCC_REQ[51],TCC_REQ[52],TCC_REQ[53],TCC_REQ[54],TCC_REQ[55],TCC_REQ[56],TCC_REQ[57],TCC_REQ[58],TCC_REQ[59],TCC_REQ[5],TCC_REQ[60],TCC_REQ[61],TCC_REQ[62],TCC_REQ[63],TCC_REQ[6],TCC_REQ[7],TCC_REQ[8],TCC_REQ[9],TCP_GATE_EN1_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_TOTAL_WRITE_sum,TD_ATOMIC_WAVEFRONT_sum,TD_TC_STALL_sum,Kernel_ID_11,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_IDLE,CPF_CPF_STAT_STALL,SPI_CSQ_P0_OCCUPANCY,SPI_CSQ_P1_OCCUPANCY,SPI_CSQ_P2_OCCUPANCY,SPI_CSQ_P3_OCCUPANCY,SPI_RA_SGPR_SIMD_FULL_CSN,SQC_DCACHE_REQ_READ_16,SQ_BUSY_CU_CYCLES,SQ_INSTS_LDS_LOAD,SQ_INSTS_LDS_STORE,SQ_INSTS_VALU_MUL_F64,SQ_INST_LEVEL_SMEM,SQ_LDS_CMD_FIFO_FULL,TA_BUFFER_TOTAL_CYCLES_sum,TA_FLAT_READ_WAVEFRONTS_sum,TCC_ATOMIC[0],TCC_ATOMIC[10],TCC_ATOMIC[11],TCC_ATOMIC[12],TCC_ATOMIC[13],TCC_ATOMIC[15],TCC_ATOMIC[16],TCC_ATOMIC[17],TCC_ATOMIC[18],TCC_ATOMIC[19],TCC_ATOMIC[1],TCC_ATOMIC[21],TCC_ATOMIC[22],TCC_ATOMIC[23],TCC_ATOMIC[24],TCC_ATOMIC[26],TCC_ATOMIC[27],TCC_ATOMIC[28],TCC_ATOMIC[29],TCC_ATOMIC[2],TCC_ATOMIC[31],TCC_ATOMIC[32],TCC_ATOMIC[33],TCC_ATOMIC[34],TCC_ATOMIC[35],TCC_ATOMIC[37],TCC_ATOMIC[38],TCC_ATOMIC[39],TCC_ATOMIC[3],TCC_ATOMIC[40],TCC_ATOMIC[42],TCC_ATOMIC[43],TCC_ATOMIC[44],TCC_ATOMIC[45],TCC_ATOMIC[47],TCC_ATOMIC[48],TCC_ATOMIC[49],TCC_ATOMIC[50],TCC_ATOMIC[51],TCC_ATOMIC[53],TCC_ATOMIC[54],TCC_ATOMIC[55],TCC_ATOMIC[56],TCC_ATOMIC[58],TCC_ATOMIC[59],TCC_ATOMIC[5],TCC_ATOMIC[60],TCC_ATOMIC[61],TCC_ATOMIC[63],TCC_ATOMIC[6],TCC_ATOMIC[7],TCC_ATOMIC[8],TCC_BUBBLE[0],TCC_BUBBLE[10],TCC_BUBBLE[11],TCC_BUBBLE[12],TCC_BUBBLE[13],TCC_BUBBLE[15],TCC_BUBBLE[16],TCC_BUBBLE[17],TCC_BUBBLE[18],TCC_BUBBLE[19],TCC_BUBBLE[1],TCC_BUBBLE[21],TCC_BUBBLE[22],TCC_BUBBLE[23],TCC_BUBBLE[24],TCC_BUBBLE[26],TCC_BUBBLE[27],TCC_BUBBLE[28],TCC_BUBBLE[29],TCC_BUBBLE[2],TCC_BUBBLE[31],TCC_BUBBLE[32],TCC_BUBBLE[33],TCC_BUBBLE[34],TCC_BUBBLE[35],TCC_BUBBLE[37],TCC_BUBBLE[38],TCC_BUBBLE[39],TCC_BUBBLE[3],TCC_BUBBLE[40],TCC_BUBBLE[42],TCC_BUBBLE[43],TCC_BUBBLE[44],TCC_BUBBLE[45],TCC_BUBBLE[47],TCC_BUBBLE[48],TCC_BUBBLE[49],TCC_BUBBLE[50],TCC_BUBBLE[51],TCC_BUBBLE[53],TCC_BUBBLE[54],TCC_BUBBLE[55],TCC_BUBBLE[56],TCC_BUBBLE[58],TCC_BUBBLE[59],TCC_BUBBLE[5],TCC_BUBBLE[60],TCC_BUBBLE[61],TCC_BUBBLE[63],TCC_BUBBLE[6],TCC_BUBBLE[7],TCC_BUBBLE[8],TCC_EA0_ATOMIC[0],TCC_EA0_ATOMIC[10],TCC_EA0_ATOMIC[11],TCC_EA0_ATOMIC[12],TCC_EA0_ATOMIC[13],TCC_EA0_ATOMIC[15],TCC_EA0_ATOMIC[16],TCC_EA0_ATOMIC[17],TCC_EA0_ATOMIC[18],TCC_EA0_ATOMIC[19],TCC_EA0_ATOMIC[1],TCC_EA0_ATOMIC[21],TCC_EA0_ATOMIC[22],TCC_EA0_ATOMIC[23],TCC_EA0_ATOMIC[24],TCC_EA0_ATOMIC[26],TCC_EA0_ATOMIC[27],TCC_EA0_ATOMIC[28],TCC_EA0_ATOMIC[29],TCC_EA0_ATOMIC[2],TCC_EA0_ATOMIC[31],TCC_EA0_ATOMIC[32],TCC_EA0_ATOMIC[33],TCC_EA0_ATOMIC[34],TCC_EA0_ATOMIC[35],TCC_EA0_ATOMIC[37],TCC_EA0_ATOMIC[38],TCC_EA0_ATOMIC[39],TCC_EA0_ATOMIC[3],TCC_EA0_ATOMIC[40],TCC_EA0_ATOMIC[42],TCC_EA0_ATOMIC[43],TCC_EA0_ATOMIC[44],TCC_EA0_ATOMIC[45],TCC_EA0_ATOMIC[47],TCC_EA0_ATOMIC[48],TCC_EA0_ATOMIC[49],TCC_EA0_ATOMIC[50],TCC_EA0_ATOMIC[51],TCC_EA0_ATOMIC[53],TCC_EA0_ATOMIC[54],TCC_EA0_ATOMIC[55],TCC_EA0_ATOMIC[56],TCC_EA0_ATOMIC[58],TCC_EA0_ATOMIC[59],TCC_EA0_ATOMIC[5],TCC_EA0_ATOMIC[60],TCC_EA0_ATOMIC[61],TCC_EA0_ATOMIC[63],TCC_EA0_ATOMIC[6],TCC_EA0_ATOMIC[7],TCC_EA0_ATOMIC[8],TCC_HIT[0],TCC_HIT[10],TCC_HIT[11],TCC_HIT[12],TCC_HIT[13],TCC_HIT[15],TCC_HIT[16],TCC_HIT[17],TCC_HIT[18],TCC_HIT[19],TCC_HIT[1],TCC_HIT[21],TCC_HIT[22],TCC_HIT[23],TCC_HIT[24],TCC_HIT[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diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_0.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_0.csv new file mode 100644 index 0000000000..23ee498894 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_0.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,CPC_CPC_UTCL2IU_BUSY,CPC_SYNC_FIFO_FULL,SPI_CS0_NUM_THREADGROUPS,SPI_CS1_NUM_THREADGROUPS,SPI_CS2_NUM_THREADGROUPS,SPI_CS3_NUM_THREADGROUPS,SQC_DCACHE_REQ_READ_8,SQC_TC_DATA_ATOMIC_REQ,SQ_ACTIVE_INST_VALU,SQ_BUSY_CYCLES,SQ_INSTS_SENDMSG,SQ_INSTS_VALU_ADD_F64,SQ_LDS_BANK_CONFLICT,SQ_VMEM_TA_CMD_FIFO_FULL,TA_BUFFER_WAVEFRONTS_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_EA0_WRREQ_LEVEL_sum,TCC_UC_REQ_sum,TCP_TCC_READ_REQ_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum +0,0,1,15772,15772,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248227257271964,1248227257293723,1,13,389.0,0.0,4096.0,0.0,0.0,0.0,0.0,0.0,98304.0,126903.0,16384.0,0.0,0.0,0.0,0.0,154249.0,0.0,36146.0,9826410.0,26.0,65536.0,11.0,768.0,0.0 +1,0,1,15772,15772,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248227257962097,1248227257979016,2,13,0.0,0.0,4096.0,0.0,0.0,0.0,0.0,0.0,98304.0,96924.0,16384.0,0.0,0.0,0.0,0.0,103050.0,0.0,36209.0,10285296.0,8.0,65536.0,0.0,0.0,0.0 +2,0,1,15772,15772,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248227258551114,1248227258567914,3,13,0.0,0.0,4096.0,0.0,0.0,0.0,0.0,0.0,98304.0,96768.0,16384.0,0.0,0.0,0.0,0.0,100616.0,0.0,36239.0,10281734.0,0.0,65536.0,0.0,0.0,0.0 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_1.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_1.csv new file mode 100644 index 0000000000..269e6fbd13 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_1.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,CPC_CANE_BUSY,CPC_GD_BUSY,SPI_RA_REQ_NO_ALLOC,SPI_SWC_CSC_WR,SQC_DCACHE_REQ_READ_4,SQC_TC_DATA_READ_REQ,SQ_INSTS_VALU_INT64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_F6F4,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VMEM,SQ_VALU_MFMA_BUSY_CYCLES,TA_BUFFER_READ_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TCC_CC_REQ_sum,TCC_EA0_RDREQ_LEVEL_sum,TCC_EA0_RD_UNCACHED_32B_sum,TCC_RW_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_UTCL1_PERMISSION_MISS_sum +0,0,1,15779,15779,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248227786612853,1248227786635252,1,13,630.0,30469.0,12744.0,32768.0,0.0,72.0,32768.0,0.0,0.0,0.0,32768.0,0.0,0.0,16384.0,0.0,22666001.0,58.0,197976.0,406733.0,0.0,0.0,0.0 +1,0,1,15779,15779,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248227787316865,1248227787333785,2,13,631.0,22019.0,4288.0,32768.0,0.0,72.0,32768.0,0.0,0.0,0.0,32768.0,0.0,0.0,16384.0,0.0,11922030.0,16.0,197976.0,289225.0,0.0,0.0,0.0 +2,0,1,15779,15779,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248227787897083,1248227787913762,3,13,630.0,21586.0,3860.0,32768.0,0.0,72.0,32768.0,0.0,0.0,0.0,32768.0,0.0,0.0,16384.0,0.0,11792534.0,0.0,197976.0,286818.0,0.0,0.0,0.0 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_2.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_2.csv new file mode 100644 index 0000000000..16fe385445 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_2.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,CPC_CPC_UTCL2IU_IDLE,CPC_UTCL1_STALL_ON_TRANSLATION,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_RES_STALL_CSN,SQC_DCACHE_MISSES_DUPLICATE,SQ_INSTS_SMEM,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_INT32,SQ_INSTS_VALU_MFMA_F8,SQ_INSTS_VALU_MFMA_MOPS_F8,SQ_INSTS_VALU_TRANS_F32,SQ_THREAD_CYCLES_VALU,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_BUSY_sum,TCC_HIT_sum,TCC_NORMAL_WRITEBACK_sum,TCC_READ_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum +0,0,1,15786,15786,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248228340675080,1248228340696799,1,13,76981.0,399.0,0.0,9346.0,2160.0,65536.0,0.0,49152.0,0.0,0.0,0.0,6291456.0,0.0,32768.0,533130.0,66864.0,30395.0,66936.0,0.0,0.0,0.0,131072.0 +1,0,1,15786,15786,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248228341369934,1248228341386613,2,13,65633.0,0.0,0.0,3274.0,2160.0,65536.0,0.0,49152.0,0.0,0.0,0.0,6291456.0,0.0,32768.0,459164.0,66864.0,29343.0,66912.0,0.0,0.0,0.0,131072.0 +2,0,1,15786,15786,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248228341957512,1248228341974431,3,13,62962.0,0.0,0.0,3253.0,2160.0,65536.0,0.0,49152.0,0.0,0.0,0.0,6291456.0,0.0,32768.0,460697.0,66864.0,29330.0,66904.0,0.0,0.0,0.0,131072.0 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_3.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_3.csv new file mode 100644 index 0000000000..80a96c3e0d --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_3.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,SPI_RA_VGPR_SIMD_FULL_CSN,SPI_VWC1_VDATA_VALID_WR,SQC_DCACHE_REQ_READ_2,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_MISC,SQ_INSTS_BRANCH,SQ_INSTS_LDS_STORE_BANDWIDTH,SQ_INSTS_VALU_CVT,SQ_LDS_ATOMIC_RETURN,SQ_LDS_MEM_VIOLATIONS,TCC_MISS_sum,TCC_PROBE_sum,TCC_REQ_sum,TCC_WRITEBACK_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_READ_sum +0,0,1,15793,15793,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248228890145284,1248228890166603,1,13,0.0,32768.0,32768.0,278528.0,32768.0,16384.0,0.0,0.0,0.0,0.0,131138.0,0.0,198002.0,65596.0,0.0,2097152.0,0.0,1048576.0 +1,0,1,15793,15793,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248228890710662,1248228890727781,2,13,0.0,32768.0,32768.0,278528.0,32768.0,16384.0,0.0,0.0,0.0,0.0,131120.0,0.0,197984.0,65596.0,0.0,2097152.0,0.0,1048576.0 +2,0,1,15793,15793,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248228891192003,1248228891208963,3,13,0.0,32768.0,32768.0,278528.0,32768.0,16384.0,0.0,0.0,0.0,0.0,131112.0,0.0,197976.0,65596.0,0.0,2097152.0,0.0,1048576.0 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_4.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_4.csv new file mode 100644 index 0000000000..78185bb32f --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_4.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,SPI_CSC_WAVE_CNT_BUSY,SPI_RA_WAVE_SIMD_FULL_CSN,SQC_TC_DATA_WRITE_REQ,SQ_ACTIVE_INST_LDS,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F64,SQ_LDS_DATA_FIFO_FULL,SQ_VMEM_TA_ADDR_FIFO_FULL,SQ_WAVES,SQ_WAVES_RESTORED,TCC_EA0_ATOMIC_sum,TCC_EA0_RDREQ_DRAM_sum,TCC_EA0_WRREQ_64B_sum,TCC_EA0_WRREQ_DRAM_sum +0,0,1,15800,15800,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248229438857357,1248229438879317,1,13,129716.0,279581.0,0.0,0.0,0.0,0.0,0.0,0.0,16384.0,0.0,0.0,65622.0,131072.0,131072.0 +1,0,1,15800,15800,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248229439181269,1248229439198349,2,13,97526.0,104638.0,0.0,0.0,0.0,0.0,0.0,0.0,16384.0,0.0,0.0,65612.0,131072.0,131072.0 +2,0,1,15800,15800,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248229439450184,1248229439467063,3,13,97380.0,103228.0,0.0,0.0,0.0,0.0,0.0,0.0,16384.0,0.0,0.0,65612.0,131072.0,131072.0 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_5.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_5.csv new file mode 100644 index 0000000000..45731a4561 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_5.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,SPI_RA_LDS_CU_FULL_CSN,SPI_RA_TMP_STALL_CSN,SQC_DCACHE_REQ_READ_1,SQC_ICACHE_HITS,SQ_INSTS_LDS_ATOMIC_BANDWIDTH,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_F6F4,SQ_INSTS_VALU_MUL_F32,SQ_LDS_ADDR_CONFLICT,SQ_WAIT_INST_ANY,TCC_EA0_RDREQ_32B_sum,TCC_EA0_RDREQ_sum,TCC_STREAMING_REQ_sum,TCC_WRITE_sum +0,0,1,15807,15807,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248229989191714,1248229989213393,1,13,0.0,0.0,32768.0,64005.0,0.0,0.0,0.0,0.0,0.0,656853.0,0.0,65640.0,0.0,131072.0 +1,0,1,15807,15807,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248229989539141,1248229989555860,2,13,0.0,0.0,32768.0,64262.0,0.0,0.0,0.0,0.0,0.0,95857.0,0.0,65612.0,0.0,131072.0 +2,0,1,15807,15807,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248229989799091,1248229989816011,3,13,0.0,0.0,32768.0,64364.0,0.0,0.0,0.0,0.0,0.0,120606.0,0.0,65612.0,0.0,131072.0 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_6.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_6.csv new file mode 100644 index 0000000000..0ca4acee02 --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_6.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,SPI_RA_TGLIM_CU_FULL_CSN,SPI_RA_WVLIM_STALL_CSN,SQC_TC_INST_REQ,SQ_INSTS_VALU,SQ_INSTS_VALU_MFMA_I8,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F64,SQ_INSTS_VALU_TRANS_F16,SQ_LDS_UNALIGNED_STALL,SQ_WAIT_ANY,TCC_EA0_WR_UNCACHED_32B_sum,TCC_NORMAL_EVICT_sum +0,0,1,15814,15814,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248230542355535,1248230542376494,1,13,0.0,0.0,1296.0,98304.0,0.0,0.0,0.0,0.0,0.0,5300250.0,0.0,44.0 +1,0,1,15814,15814,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248230542613524,1248230542630444,2,13,0.0,0.0,1296.0,98304.0,0.0,0.0,0.0,0.0,0.0,4063067.0,0.0,44.0 +2,0,1,15814,15814,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248230542841396,1248230542858275,3,13,0.0,0.0,1296.0,98304.0,0.0,0.0,0.0,0.0,0.0,4109650.0,0.0,44.0 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_7.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_7.csv new file mode 100644 index 0000000000..6adbe9b90e --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/pmc_perf_7.csv @@ -0,0 +1,4 @@ +Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,Kernel_ID,SQC_DCACHE_REQ,SQ_ACTIVE_INST_FLAT,SQ_ACTIVE_INST_SCA,SQ_IFETCH,SQ_INSTS,SQ_INSTS_SALU,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MFMA_F32 +0,0,1,15821,15821,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248231092253037,1248231092274436,1,13,65536.0,32768.0,114688.0,65536.0,327680.0,49152.0,0.0,0.0 +1,0,1,15821,15821,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248231092448589,1248231092465748,2,13,65536.0,32768.0,114688.0,65536.0,327680.0,49152.0,0.0,0.0 +2,0,1,15821,15821,1048576,256,0,0,4,0,16,64,"vecCopy(double*, double*, double*, int, int)",1248231092604703,1248231092621702,3,13,65536.0,32768.0,114688.0,65536.0,327680.0,49152.0,0.0,0.0 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/profiling_config.yaml b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/profiling_config.yaml new file mode 100644 index 0000000000..8182466e4b --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/profiling_config.yaml @@ -0,0 +1,39 @@ +config_dir: /app/src/rocprof_compute_soc/analysis_configs +device: -1 +dispatch: null +filter_blocks: {} +format_rocprof_output: csv +hip_trace: false +join_type: grid +kernel: null +kernel_names: false +kokkos_trace: false +list_metrics: null +loglevel: 10 +lucky: false +mem_level: ALL +mode: profile +name: vcopy +no_roof: true +path: /app/workloads/vcopy/MI350 +quiet: false +remaining: +- -- +- tests/vcopy +- -n +- '1048576' +- -b +- '256' +- -i +- '3' +roof_only: false +roofline_data_type: +- FP32 +sort: kernels +spatial_multiplexing: null +specs: false +subpath: gpu +summaries: false +target: null +use_rocscope: false +verbose: 1 diff --git a/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/sysinfo.csv b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/sysinfo.csv new file mode 100644 index 0000000000..a30291968b --- /dev/null +++ b/projects/rocprofiler-compute/tests/workloads/vcopy/MI350/sysinfo.csv @@ -0,0 +1,2 @@ +workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_series,gpu_model,gpu_arch,gpu_chip_id,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,num_xcd,num_hbm_channels +vcopy,tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Fri Mar 28 22:43:57 2025 (UTC),3,f77021840818,AMD Ryzen Threadripper PRO 7985WX 64-Cores,AMDVBS1052957N.FD,Ubuntu 22.04.5 LTS,5.15.0-70-generic,,527456116,,6.5.0-831,113-M3550101-100,SPX,NPS1,MI350,MI350,gfx950,30112,32,4096,128,4,16,64,1024,32,0,,0,,128,32,64,4,8,128