P4 to Git Change 1109955 by wchau@wchau_WINDOWS7_OCL on 2015/01/08 14:00:03
ECR #399840 - OpenCL Runtime HW Debug support development - HW debeg core and runtime support Affected files ... ... //depot/stg/opencl/drivers/opencl/api/opencl/amdocl/cl_debugger_amd.cpp#2 edit ... //depot/stg/opencl/drivers/opencl/api/opencl/amdocl/cl_debugger_amd.h#2 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/device.hpp#236 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudebugger.hpp#1 add ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudebugmanager.cpp#1 add ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudebugmanager.hpp#1 add ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudevice.cpp#488 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudevice.hpp#135 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpukernel.cpp#273 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpukernel.hpp#104 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuresource.cpp#198 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuscsi.cpp#28 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpusettings.cpp#295 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuvirtual.cpp#344 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuvirtual.hpp#122 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/GSLContext.cpp#67 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/GSLContext.h#40 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/hwdebug.cpp#1 add ... //depot/stg/opencl/drivers/opencl/runtime/device/hwdebug.hpp#2 edit ... //depot/stg/opencl/drivers/opencl/runtime/utils/flags.hpp#221 edit
This commit is contained in:
foreman
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/*******************************************************************************
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*
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* Copyright (c) 2014 Advanced Micro Devices, Inc. (unpublished)
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*
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* All rights reserved. This notice is intended as a precaution against
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* inadvertent publication and does not imply publication or any waiver
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* of confidentiality. The year included in the foregoing notice is the
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* year of creation of the work.
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*
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******************************************************************************/
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#ifndef HWDBG_GPUDEBGGER_H_
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#define HWDBG_GPUDEBGGER_H_
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#include <cstddef>
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#include <cstdint>
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#include "hsa.h"
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#include "sc-hsa/Interface/SCHSAInterface.h"
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#include "device/device.hpp"
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#include "device/hwdebug.hpp"
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static const int NumberReserveVgprs = 4;
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namespace gpu {
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/**
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* \defgroup Services_API OCL Runtime Services API
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* @{
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*/
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/*! \brief Dispatch packet information
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*
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* This structure contains the packet information for kernel dispatch
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*/
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struct PacketAmdInfo
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{
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uint32_t trapReservedVgprIndex_; //!< reserved VGPR index, -1 when they are not valid
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uint32_t scratchBufferWaveOffset_; //!< scratch buffer wave offset, -1 when no scratch buffer
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void* pointerToIsaBuffer_; //!< pointer to the buffer containing ISA
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size_t sizeOfIsaBuffer_; //!< size of the ISA buffer
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uint32_t numberOfVgprs_; //!< number of VGPRs used by the kernel
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uint32_t numberOfSgprs_; //!< number of SGPRs used by the kernel
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size_t sizeOfStaticGroupMemory_; //!< Static local memory used by the kernel
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};
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/*! \brief Cache mask for invalidation
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*/
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struct HwDbgGpuCacheMask
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{
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HwDbgGpuCacheMask() :ui32All_(0) {}
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HwDbgGpuCacheMask(uint32_t mask) :ui32All_(mask) {}
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union {
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struct {
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uint32_t sqICache_ : 1; //!< Instruction cache
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uint32_t sqKCache_ : 1; //!< Data cache
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uint32_t tcL1_ : 1; //!< tcL1 cache
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uint32_t tcL2_ : 1; //!< tcL2 cache
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uint32_t reserved_ : 28;
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};
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uint32_t ui32All_;
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};
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};
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/*! \brief Address watch information
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*
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* Information about each watch point - address, mask, mode and event
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*/
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struct HwDbgAddressWatch
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{
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void* watchAddress_; //! The address of watch point
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uint64_t watchMask_; //! The mask for watch point (lower 24 bits)
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cl_dbg_address_watch_mode_amd watchMode_; //! The watch mode for this watch
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DebugEvent event_; //! Event of the watch point (not used for now)
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};
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/*! \brief Runtime structure used to communicate debug information
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* between Ocl services and core for a kernel dispatch.
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*/
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struct DebugToolInfo
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{
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uint64_t scratchAddress_; //! Scratch memory address
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size_t scratchSize_; //! Scratch memory size
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uint64_t globalAddress_; //! Global memory address
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uint32_t cacheDisableMask_; //! Cache mask, indicating caches disabled
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uint32_t exceptionMask_; //! Exception mask
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uint32_t reservedCuNum_; //! Number of reserved CUs for display,
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//! which ranges from 0 to 7 in the current implementation.
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bool monitorMode_; //! Debug or profiler mode
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bool gpuSingleStepMode_; //! SQ debug mode
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amd::Memory* trapHandler_; //! Trap handler address
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amd::Memory* trapBuffer_; //! Trap buffer address
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bool sqPerfcounterEnable_; //! whether SQ perf counters are enabled
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};
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/*! \brief Message used by the KFD wave control for CI
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*
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* Structure indicates the various information used by the wave control function.
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*/
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struct HwDebugWaveAddr
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{
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uint32_t VMID_ : 4; //! Virtual memory id
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uint32_t wave_ : 4; //! Wave id
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uint32_t SIMD_ : 2; //! SIMD id
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uint32_t CU_ : 4; //! Compute unit
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uint32_t SH_ : 1; //! Shader array
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uint32_t SE_ : 1; //! Shader engine
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};
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/*! \brief Kernel code information
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*
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* This structure contains the pointer of mapped kernel code for host access
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* and its size (in bytes)
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*/
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struct AqlCodeInfo
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{
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amd_kernel_code_t * aqlCode_; //! pointer of AQL code to allow host access
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uint32_t aqlCodeSize_; //! size of AQL code
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};
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/**@}*/
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} // namespace gpu
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#endif // HWDBG_GPUDEBGGER_H_
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@@ -0,0 +1,361 @@
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/*******************************************************************************
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*
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* Copyright (c) 2014 Advanced Micro Devices, Inc. (unpublished)
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*
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* All rights reserved. This notice is intended as a precaution against
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* inadvertent publication and does not imply publication or any waiver
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* of confidentiality. The year included in the foregoing notice is the
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* year of creation of the work.
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*
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******************************************************************************/
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#include "gpudebugmanager.hpp"
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#include "gpudevice.hpp"
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#include "platform/commandqueue.hpp"
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#include "device/device.hpp"
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#include "device/gpu/gpumemory.hpp"
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#include <iostream>
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#include <sstream>
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#include <fstream>
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namespace gpu {
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class VirtualGPU;
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class Device;
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class Memory;
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/*
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***************************************************************************
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* Implementation of GPU Debug Manager class
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***************************************************************************
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*/
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GpuDebugManager::GpuDebugManager(amd::Device* device)
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: HwDebugManager(device)
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, vGpu_(NULL)
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, debugMessages_(0)
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, addressWatch_(NULL)
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, addressWatchSize_(0)
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, oclEventHandle_(NULL)
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{
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// Initialize the exception info and the kernel execution mode
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excpPolicy_.exceptionMask = 0x0;
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excpPolicy_.waveAction = CL_DBG_WAVES_RESUME;
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excpPolicy_.hostAction = CL_DBG_HOST_IGNORE;
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excpPolicy_.waveMode = CL_DBG_WAVEMODE_BROADCAST;
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execMode_.ui32All = 0;
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rtTrapHandlerInfo_.trap_.trapHandler_ = NULL;
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rtTrapHandlerInfo_.trap_.trapBuffer_ = NULL;
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aqlPacket_ = (hsa_kernel_dispatch_packet_t *) NULL;
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return;
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}
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GpuDebugManager::~GpuDebugManager()
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{
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if (NULL != addressWatch_) {
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delete [] addressWatch_;
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}
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}
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void
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GpuDebugManager::executePreDispatchCallBack(void* aqlPacket,
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void* toolInfo)
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{
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DebugToolInfo* info = reinterpret_cast<DebugToolInfo*>(toolInfo);
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aqlPacket_ = reinterpret_cast<hsa_kernel_dispatch_packet_t*>(aqlPacket);
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// Only if the pre-dispatch callback is set, will we update cache
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// flush configuration and build the memory descriptor.
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if (NULL != preDispatchCallBackFunc_) {
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// Build the scratch memory descriptor
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device()->gslCtx()->BuildScratchBufferResource(debugInfo_.scratchMemoryDescriptor_,
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info->scratchAddress_,
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info->scratchSize_);
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// Build the global memory descriptor
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device()->gslCtx()->BuildHeapBufferResource(debugInfo_.globalMemoryDescriptor_,
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info->globalAddress_);
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// // for invalidate cache (BuildEndOfKernelNotifyCommands)
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// aqlPacket->release_fence_scope = 2;
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cl_device_id clDeviceId = as_cl(device_);
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preDispatchCallBackFunc_(clDeviceId,
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oclEventHandle_,
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aqlPacket_,
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aclBinary_,
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deviceTrapInfo_,
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preDispatchCallBackArgs_);
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}
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// Copy the various info set by the debugger/profiler to the tool info structure
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setupTrapInformation(info);
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}
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void
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GpuDebugManager::executePostDispatchCallBack()
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{
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if (NULL != postDispatchCallBackFunc_) {
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cl_device_id clDeviceId = as_cl(device_);
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postDispatchCallBackFunc_(clDeviceId,
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aqlPacket_->completion_signal.handle,
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postDispatchCallBackArgs_);
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}
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}
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cl_int
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GpuDebugManager::registerDebugger(amd::Context* context, uintptr_t messageStorage)
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{
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//! @todo: obtain the global mutex of HW debug to make sure only one debugger process exist
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if (!device()->settings().enableHwDebug_) {
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LogError("debugmanager: Register debugger error - HW DEBUG is not enable");
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return CL_DEBUGGER_REGISTER_FAILURE_AMD;
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}
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// first time register - set the message storage, flush queue and enable hw debug
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if (!isRegistered()) {
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debugMessages_ = messageStorage;
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dbgMsgBufferReady_ = true;
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isRegistered_ = false;
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}
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context_ = context;
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return CL_SUCCESS;
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}
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void
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GpuDebugManager::unregisterDebugger()
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{
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if (isRegistered()) {
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//! @todo: release the global mutex of HW debug
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// reset the debugger registration flag
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isRegistered_ = false;
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dbgMsgBufferReady_ = false;
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context_ = NULL;
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}
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}
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cl_int
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GpuDebugManager::registerDebuggerOnQueue(device::VirtualDevice* vDevice)
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{
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if (!isMsgBufferReady()) {
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return CL_DEBUGGER_REGISTER_FAILURE_AMD;
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}
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if (isRegistered()) { // The debugger has already been registered,
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return CL_SUCCESS; // nothing to be done
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}
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VirtualGPU* vGpu = reinterpret_cast<gpu::VirtualGPU*>(vDevice);
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// populate the fields in the debugMessages structure used by the GPU exception notification
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if (vGpu->RegisterHwDebugger(debugMessages_)) {
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vGpu_ = vGpu;
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isRegistered_ = true;
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return CL_SUCCESS;
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}
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return CL_DEBUGGER_REGISTER_FAILURE_AMD;
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}
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void
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GpuDebugManager::flushCache(uint32_t mask)
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{
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HwDbgGpuCacheMask cacheMask(mask);
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device()->xferQueue()->flushCuCaches(cacheMask);
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}
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void
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GpuDebugManager::setupTrapInformation(DebugToolInfo* toolInfo)
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{
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toolInfo->scratchAddress_ = 0;
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toolInfo->scratchSize_ = 0;
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toolInfo->globalAddress_ = 0;
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toolInfo->sqPerfcounterEnable_ = false;
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// Set up trap related info in the kernel info structure to be
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// used in the kernel dispatch.
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toolInfo->exceptionMask_ = excpPolicy_.exceptionMask;
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toolInfo->gpuSingleStepMode_ = execMode_.gpuSingleStepMode;
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toolInfo->monitorMode_ = execMode_.monitorMode;
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// The order of these three bits is determined by the definition
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// of the register COMPUTE_DISPATCH_INITIATOR
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toolInfo->cacheDisableMask_ = ((execMode_.disableL1Scalar << 2)
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| (execMode_.disableL2Cache << 1)
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| (execMode_.disableL1Vector));
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toolInfo->reservedCuNum_ = execMode_.reservedCuNum;
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toolInfo->trapHandler_ =
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as_amd(reinterpret_cast<cl_mem>(deviceTrapInfo_[kDebugTrapHandlerLocation]));
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toolInfo->trapBuffer_ =
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as_amd(reinterpret_cast<cl_mem>(deviceTrapInfo_[kDebugTrapBufferLocation]));
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}
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void
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GpuDebugManager::getPacketAmdInfo(
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const void* aqlCodeInfo,
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void* packetInfo) const
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{
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const AqlCodeInfo* codeInfo =
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reinterpret_cast<const AqlCodeInfo*>(aqlCodeInfo);
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const amd_kernel_code_t* hostAqlCode = codeInfo->aqlCode_;
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PacketAmdInfo* packet =
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reinterpret_cast<PacketAmdInfo*>(packetInfo);
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const amd_kernel_code_t* akc = hostAqlCode;
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packet->numberOfSgprs_ = akc->wavefront_sgpr_count;
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packet->numberOfVgprs_ = akc->workitem_vgpr_count;
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// use mapped kernel_object_address for host accessing of ISA buffer
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packet->pointerToIsaBuffer_ = (char*) (hostAqlCode) +
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akc->kernel_code_entry_byte_offset;
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packet->scratchBufferWaveOffset_ =
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akc->debug_wavefront_private_segment_offset_sgpr;
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packet->sizeOfIsaBuffer_ = codeInfo->aqlCodeSize_;
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packet->sizeOfStaticGroupMemory_ = akc->workgroup_group_segment_byte_size;
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// The trap_reserved_vgpr_index will be 4 less the original
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// This value must be used only by the debugger
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packet->trapReservedVgprIndex_ = akc->workitem_vgpr_count - NumberReserveVgprs;
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}
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DebugEvent
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GpuDebugManager::createDebugEvent(
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const bool autoReset)
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{
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if (!isRegistered()) {
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LogError("debugmanager: Failed to flush cache - hw debug is not available");
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return 0;
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}
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// create the event object
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osEventHandle shaderEvent = osEventCreate(!autoReset);
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// event object has been created, set the initial state
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if (shaderEvent != 0) {
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osEventReset(shaderEvent); // initial state is non-signaled
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if (vGpu_->ExceptionNotification(shaderEvent)) {
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isRegistered_ = true;
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return shaderEvent;
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}
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}
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return 0;
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}
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cl_int
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GpuDebugManager::waitDebugEvent(
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DebugEvent pEvent,
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uint32_t timeOut) const
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{
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if (osEventTimedWait(pEvent, timeOut)) {
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return CL_SUCCESS;
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}
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else {
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return CL_EVENT_TIMEOUT_AMD;
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}
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}
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void
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GpuDebugManager::destroyDebugEvent(DebugEvent* pEvent)
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{
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osEventDestroy(*pEvent);
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*pEvent = 0;
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vGpu_->ExceptionNotification(0);
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}
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void
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GpuDebugManager::wavefrontControl(
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uint32_t waveAction,
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uint32_t waveMode,
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uint32_t trapId,
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void* waveAddr) const
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{
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device()->gslCtx()->executeSqCommand(waveAction, waveMode, trapId, waveAddr);
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}
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void
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GpuDebugManager::setAddressWatch(
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uint32_t numWatchPoints,
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void** watchAddress,
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uint64_t* watchMask,
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uint64_t* watchMode,
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DebugEvent* event)
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{
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size_t requiredSize = numWatchPoints * sizeof(HwDbgAddressWatch);
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// previously allocated size is not big enough, allocate new memory
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if (addressWatchSize_ < requiredSize) {
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if (NULL != addressWatch_) { // free the smaller address watch storage
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delete [] addressWatch_;
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}
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addressWatch_ = new HwDbgAddressWatch[numWatchPoints];
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addressWatchSize_ = requiredSize;
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}
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// fill in the address watch structure
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memset(addressWatch_, 0, addressWatchSize_);
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for (uint32_t i = 0; i < numWatchPoints; i++)
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{
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amd::Memory* watchMem = as_amd(reinterpret_cast<cl_mem>(watchAddress[i]));
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Memory* watchMemAddress = device()->getGpuMemory(watchMem);
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addressWatch_[i].watchAddress_ = reinterpret_cast<void*>(watchMemAddress->vmAddress());
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addressWatch_[i].watchMask_ = watchMask[i];
|
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addressWatch_[i].watchMode_ = (cl_dbg_address_watch_mode_amd) watchMode[i];
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addressWatch_[i].event_ = (0 != event) ? event[i] : 0;
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}
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||||
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// setup the watch addresses
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device()->gslCtx()->setAddressWatch(numWatchPoints, (void*) addressWatch_);
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||||
|
||||
}
|
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void
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||||
GpuDebugManager::setGlobalMemory(
|
||||
amd::Memory* memObj,
|
||||
uint32_t offset,
|
||||
void* srcPtr,
|
||||
uint32_t size)
|
||||
{
|
||||
gpu::Memory* globalMem = device()->getGpuMemory(memObj);
|
||||
|
||||
address mappedMem = static_cast<address>(globalMem->map(NULL,0));
|
||||
assert(mappedMem != 0);
|
||||
|
||||
void* dest_ptr = reinterpret_cast<void*>(mappedMem + offset);
|
||||
memcpy(dest_ptr, srcPtr, size);
|
||||
|
||||
globalMem->unmap(NULL);
|
||||
}
|
||||
|
||||
|
||||
} // namespace gpu
|
||||
@@ -0,0 +1,132 @@
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Copyright (c) 2014 Advanced Micro Devices, Inc. (unpublished)
|
||||
*
|
||||
* All rights reserved. This notice is intended as a precaution against
|
||||
* inadvertent publication and does not imply publication or any waiver
|
||||
* of confidentiality. The year included in the foregoing notice is the
|
||||
* year of creation of the work.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef HWDBG_DEBUGMANAGER_H__
|
||||
#define HWDBG_DEBUGMANAGER_H__
|
||||
|
||||
#include "gpuvirtual.hpp"
|
||||
#include "gpudebugger.hpp"
|
||||
|
||||
namespace gpu {
|
||||
|
||||
class GpuDebugManager;
|
||||
class Device;
|
||||
class Memory;
|
||||
|
||||
|
||||
/*! \brief Debug Manager Class
|
||||
*
|
||||
* The debug manager class is used to pass all the trap info to the
|
||||
* kernel dispatch and then the kernel execution can use such trap information
|
||||
* for kernel execution. This class contains the trap handler and shader event
|
||||
* objects. The trap handler is setup by users and passed to the kernel dispatch.
|
||||
* The shader event is to receive interrupts from the GPU and then users can
|
||||
* perform various operations.
|
||||
*
|
||||
* This class also provides the interface for setting up the pre-dispatch
|
||||
* callback functions used by the profiler and debugger. It also provides
|
||||
* a way to retrieve various debug information for the kernel execution.
|
||||
*
|
||||
*/
|
||||
class GpuDebugManager : public amd::HwDebugManager {
|
||||
public:
|
||||
|
||||
//! Constructor of the debug manager class
|
||||
GpuDebugManager(amd::Device* device);
|
||||
|
||||
//! Destructor of the debug manager class
|
||||
~GpuDebugManager();
|
||||
|
||||
//! Get the single instance of the GpuDebugManager class
|
||||
static GpuDebugManager* getDefaultInstance();
|
||||
|
||||
//! Destroy the GpuDebugManager class object
|
||||
static void destroyInstances();
|
||||
|
||||
//! Flush cache
|
||||
void flushCache(uint32_t mask);
|
||||
|
||||
//! Create the debug event
|
||||
DebugEvent createDebugEvent(const bool autoReset);
|
||||
|
||||
//! Wait for the debug event
|
||||
cl_int waitDebugEvent(DebugEvent pEvent, uint32_t timeOut) const;
|
||||
|
||||
//! Destroy the debug event
|
||||
void destroyDebugEvent(DebugEvent* pEvent);
|
||||
|
||||
//! Register the debugger
|
||||
cl_int registerDebugger(amd::Context*context, uintptr_t messageStorage);
|
||||
|
||||
//! Register the debugger with KMD after command queue has been created
|
||||
cl_int registerDebuggerOnQueue(device::VirtualDevice* vDevice);
|
||||
|
||||
//! Unregister the debugger
|
||||
void unregisterDebugger();
|
||||
|
||||
//! Send the wavefront control cmmand
|
||||
void wavefrontControl(uint32_t waveAction,
|
||||
uint32_t waveMode,
|
||||
uint32_t trapId,
|
||||
void* waveAddr) const;
|
||||
|
||||
//! Set address watching point
|
||||
void setAddressWatch(uint32_t numWatchPoints,
|
||||
void** watchAddress,
|
||||
uint64_t* watchMask,
|
||||
uint64_t* watchMode,
|
||||
DebugEvent* pEvent);
|
||||
|
||||
//! Get the packet information for dispatch
|
||||
void getPacketAmdInfo(const void* aqlCodeInfo, void* packetInfo) const;
|
||||
|
||||
//! Set global memory values
|
||||
void setGlobalMemory(amd::Memory* memObj, uint32_t offset, void* srcPtr, uint32_t size);
|
||||
|
||||
//! Execute the post-dispatch callback function
|
||||
void executePostDispatchCallBack();
|
||||
|
||||
//! Execute the pre-dispatch callback function
|
||||
void executePreDispatchCallBack(void* aqlPacket,
|
||||
void* toolInfo);
|
||||
|
||||
private:
|
||||
|
||||
//! Setup trap handler info for kernel execution
|
||||
void setupTrapInformation(DebugToolInfo* toolInfo);
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
const VirtualGPU* vGpu() const { return vGpu_; }
|
||||
|
||||
private:
|
||||
|
||||
const gpu::Device* device() const {
|
||||
return reinterpret_cast<const gpu::Device *>(device_); }
|
||||
|
||||
VirtualGPU* vGpu_; //!< the virtual GPU
|
||||
|
||||
uintptr_t debugMessages_; //!< Pointer to a SHARED_DEBUG_MESSAGES pass to the KMD
|
||||
|
||||
HwDbgAddressWatch* addressWatch_; //!< Address watch data
|
||||
size_t addressWatchSize_; //!< Size of address watch data
|
||||
|
||||
//! Arguments used by the callback function
|
||||
void* oclEventHandle_; //!< event handler
|
||||
const hsa_kernel_dispatch_packet_t* aqlPacket_; //!< AQL packet
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
} // namespace gpu
|
||||
|
||||
#endif // HWDBG_DEBUGMANAGER_H__
|
||||
@@ -38,6 +38,8 @@
|
||||
#include <iostream>
|
||||
#include <ctype.h>
|
||||
|
||||
#include "gpudebugmanager.hpp"
|
||||
|
||||
bool DeviceLoad()
|
||||
{
|
||||
bool ret = false;
|
||||
@@ -890,6 +892,7 @@ Device::create(CALuint ordinal, CALuint numOfDevices)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#ifdef DEBUG
|
||||
std::stringstream message;
|
||||
if (settings().remoteAlloc_) {
|
||||
@@ -1225,7 +1228,7 @@ Device::init()
|
||||
{
|
||||
CALuint numDevices = 0;
|
||||
bool result = false;
|
||||
bool useDeviceList = false;
|
||||
bool useDeviceList = false;
|
||||
requestedDevices_t requestedDevices;
|
||||
|
||||
const char *library = getenv("COMPILER_LIBRARY");
|
||||
@@ -2662,4 +2665,27 @@ Device::SrdManager::fillResourceList(std::vector<const Resource*>& memList)
|
||||
}
|
||||
}
|
||||
|
||||
cl_int
|
||||
Device::hwDebugManagerInit(amd::Context *context, uintptr_t messageStorage)
|
||||
{
|
||||
hwDebugMgr_ = new GpuDebugManager(this);
|
||||
cl_int status = hwDebugMgr_->registerDebugger(context, messageStorage);
|
||||
|
||||
if (CL_SUCCESS != status) {
|
||||
delete hwDebugMgr_;
|
||||
hwDebugMgr_ = NULL;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
void
|
||||
Device::hwDebugManagerRemove()
|
||||
{
|
||||
hwDebugMgr_->unregisterDebugger();
|
||||
|
||||
delete hwDebugMgr_;
|
||||
hwDebugMgr_ = NULL;
|
||||
}
|
||||
|
||||
} // namespace gpu
|
||||
|
||||
@@ -560,6 +560,12 @@ public:
|
||||
//! Returns SRD manger object
|
||||
SrdManager& srds() const { return *srdManager_; }
|
||||
|
||||
//! Initial the Hardware Debug Manager
|
||||
cl_int hwDebugManagerInit(amd::Context *context, uintptr_t messageStorage);
|
||||
|
||||
//! Remove the Hardware Debug Manager
|
||||
void hwDebugManagerRemove();
|
||||
|
||||
private:
|
||||
//! Disable copy constructor
|
||||
Device(const Device&);
|
||||
|
||||
@@ -3510,6 +3510,7 @@ HSAILKernel::HSAILKernel(std::string name,
|
||||
, prog_(*prog)
|
||||
, index_(0)
|
||||
, code_(NULL)
|
||||
, codeSize_(0)
|
||||
, hwMetaData_(NULL)
|
||||
{
|
||||
hsa_ = true;
|
||||
@@ -3924,6 +3925,11 @@ HSAILKernel::loadArguments(
|
||||
mem->signalWrite(&dev());
|
||||
}
|
||||
memList.push_back(gpuMem);
|
||||
|
||||
// save the memory object pointer to allow global memory access
|
||||
if (NULL != dev().hwDebugMgr()) {
|
||||
dev().hwDebugMgr()->assignKernelParamMem(i, gpuMem->owner());
|
||||
}
|
||||
}
|
||||
// If it is a local pointer
|
||||
else {
|
||||
|
||||
@@ -862,7 +862,10 @@ public:
|
||||
const void* cpuAqlCode() const { return cpuAqlCode_; }
|
||||
|
||||
//! Returns memory object with AQL code
|
||||
const gpu::Memory* gpuAqlCode() const { return code_; }
|
||||
gpu::Memory* gpuAqlCode() const { return code_; }
|
||||
|
||||
//! Returns size of AQL code
|
||||
size_t aqlCodeSize() const { return codeSize_; }
|
||||
|
||||
//! Returns the size of argument buffer
|
||||
size_t argsBufferSize() const
|
||||
@@ -883,7 +886,7 @@ public:
|
||||
amd::NDRange& lclWorkSize //!< Local work size
|
||||
) const;
|
||||
|
||||
//! Returns AQL packet in CPU memory
|
||||
//! Returns AQL packet in CPU memory
|
||||
//! if the kerenl arguments were successfully loaded, otherwise NULL
|
||||
hsa_kernel_dispatch_packet_t* loadArguments(
|
||||
VirtualGPU& gpu, //!< Running GPU context
|
||||
@@ -939,6 +942,8 @@ private:
|
||||
uint index_; //!< Kernel index in the program
|
||||
|
||||
gpu::Memory* code_; //!< Memory object with ISA code
|
||||
size_t codeSize_; //!< Size of ISA code
|
||||
|
||||
char* hwMetaData_; //!< SI metadata
|
||||
|
||||
union Flags {
|
||||
|
||||
@@ -363,7 +363,8 @@ Resource::create(MemoryType memType, CreateParams* params, bool heap)
|
||||
elementSize_ = static_cast<CALuint>(memoryFormatSize(cal()->format_).size_);
|
||||
cal_.type_ = memType;
|
||||
if (memType == Scratch) {
|
||||
cal_.type_ = Local;
|
||||
// use local memory for scratch buffer unless it is using HW DEBUG
|
||||
cal_.type_ = (!dev().settings().enableHwDebug_) ? Local : RemoteUSWC;
|
||||
cal_.scratch_ = true;
|
||||
}
|
||||
|
||||
@@ -463,7 +464,7 @@ Resource::create(MemoryType memType, CreateParams* params, bool heap)
|
||||
else if ((gslRef_ != NULL) && (!dev().settings().use64BitPtr_)) {
|
||||
// Make sure runtime didn't pick a resource with > 4GB address
|
||||
if ((cal()->dimension_ == GSL_MOA_BUFFER) &&
|
||||
(static_cast<uint64_t>(gslRef_->gslResource()->getSurfaceAddress() +
|
||||
(static_cast<uint64_t>(gslRef_->gslResource()->getSurfaceAddress() +
|
||||
gslRef_->gslResource()->getSurfaceSize()) > (uint64_t(4) * Gi))) {
|
||||
gslRef_->release();
|
||||
gslRef_ = NULL;
|
||||
|
||||
@@ -172,13 +172,17 @@ HSAILKernel::aqlCreateHWInfo(const void* shader, size_t shaderSize)
|
||||
|
||||
address codeStartAddress = reinterpret_cast<address>(akc);
|
||||
address codeEndAddress = reinterpret_cast<address>(hcd) + siMetaData->common.codeLenInByte;
|
||||
uint64_t codeSize = codeEndAddress - codeStartAddress;
|
||||
code_ = new gpu::Memory(dev(), amd::alignUp(codeSize, gpu::ConstBuffer::VectorSize));
|
||||
codeSize_ = codeEndAddress - codeStartAddress;
|
||||
code_ = new gpu::Memory(dev(), amd::alignUp(codeSize_, gpu::ConstBuffer::VectorSize));
|
||||
|
||||
// force to use remote memory for HW DEBUG
|
||||
Resource::MemoryType resMemType = (!dev().settings().enableHwDebug_) ? Resource::Local : Resource::RemoteUSWC;
|
||||
|
||||
// Initialize kernel ISA code
|
||||
if ((code_ != NULL) && code_->create(Resource::Local)) {
|
||||
if ((code_ != NULL) && code_->create(resMemType)) {
|
||||
address cpuCodePtr = static_cast<address>(code_->map(NULL, Resource::WriteOnly));
|
||||
// Copy only amd_kernel_code_t
|
||||
memcpy(cpuCodePtr, codeStartAddress, codeSize);
|
||||
memcpy(cpuCodePtr, codeStartAddress, codeSize_);
|
||||
code_->unmap(NULL);
|
||||
}
|
||||
else {
|
||||
|
||||
@@ -134,6 +134,7 @@ Settings::Settings()
|
||||
|
||||
// Use host queue for device enqueuing by default
|
||||
useDeviceQueue_ = GPU_USE_DEVICE_QUEUE;
|
||||
|
||||
}
|
||||
|
||||
bool
|
||||
@@ -311,7 +312,7 @@ Settings::create(
|
||||
calAttr.isWorkstation || hsail_) : GPU_FORCE_64BIT_PTR;
|
||||
}
|
||||
else {
|
||||
if (GPU_FORCE_64BIT_PTR || LP64_SWITCH(false, (hsail_
|
||||
if (GPU_FORCE_64BIT_PTR || LP64_SWITCH(false, (hsail_
|
||||
|| (oclVersion_ >= OpenCL20)))) {
|
||||
use64BitPtr_ = true;
|
||||
}
|
||||
@@ -440,6 +441,11 @@ Settings::create(
|
||||
if (oclVersion_ >= OpenCL20) {
|
||||
enableExtension(ClKhrSubGroups);
|
||||
enableExtension(ClKhrDepthImages);
|
||||
|
||||
// Enable HW debug
|
||||
if (GPU_ENABLE_HW_DEBUG) {
|
||||
enableHwDebug_ = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (apuSystem_ &&
|
||||
|
||||
@@ -14,6 +14,7 @@
|
||||
#include "device/gpu/gputhreadtrace.hpp"
|
||||
#include "device/gpu/gputimestamp.hpp"
|
||||
#include "device/gpu/gpublit.hpp"
|
||||
#include "device/gpu/gpudebugger.hpp"
|
||||
#include "hsa.h"
|
||||
#include "sc-hsa/Interface/SCHSAInterface.h"
|
||||
#include <fstream>
|
||||
@@ -402,6 +403,7 @@ VirtualGPU::VirtualGPU(
|
||||
, schedParamIdx_(0)
|
||||
, deviceQueueSize_(0)
|
||||
, hsaQueueMem_(NULL)
|
||||
, useHwDebug_(false)
|
||||
{
|
||||
memset(&cal_, 0, sizeof(CalVirtualDesc));
|
||||
for (uint i = 0; i < AllEngines; ++i) {
|
||||
@@ -585,6 +587,14 @@ VirtualGPU::create(
|
||||
return false;
|
||||
}
|
||||
|
||||
// Check if HW Debug is used and register the debugger if not done yet
|
||||
amd::HwDebugManager * dbgManager = dev().hwDebugMgr();
|
||||
|
||||
if ( dbgManager && dbgManager->isMsgBufferReady() ) {
|
||||
if ( dbgManager->registerDebuggerOnQueue(this) == CL_SUCCESS ) {
|
||||
useHwDebug_ = true;
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
@@ -1720,6 +1730,12 @@ VirtualGPU::submitKernelInternalHSA(
|
||||
hsaKernel.prog().kernelTable()->vmAddress());
|
||||
}
|
||||
|
||||
// setup the storage for the memory pointers of the kernel parameters
|
||||
uint numParams = kernel.signature().numParameters();
|
||||
if (useHwDebug_) {
|
||||
dev().hwDebugMgr()->allocParamMemList(numParams);
|
||||
}
|
||||
|
||||
// Program the kernel arguments for the GPU execution
|
||||
hsa_kernel_dispatch_packet_t* aqlPkt =
|
||||
hsaKernel.loadArguments(*this, kernel, sizes, parameters, nativeMem,
|
||||
@@ -1745,10 +1761,25 @@ VirtualGPU::submitKernelInternalHSA(
|
||||
addVmMemory(memList[i]);
|
||||
}
|
||||
|
||||
// HW Debug for the kernel?
|
||||
HwDbgKernelInfo kernelInfo;
|
||||
HwDbgKernelInfo *pKernelInfo = NULL;
|
||||
|
||||
if (useHwDebug_) {
|
||||
buildKernelInfo(hsaKernel, aqlPkt, kernelInfo);
|
||||
pKernelInfo = &kernelInfo;
|
||||
}
|
||||
|
||||
GpuEvent gpuEvent;
|
||||
// Run AQL dispatch in HW
|
||||
runAqlDispatch(gpuEvent, aqlPkt, vmMems(), cal_.memCount_,
|
||||
scratch, scratchOffset, hsaKernel.cpuAqlCode(), hsaQueueMem_->vmAddress());
|
||||
scratch, scratchOffset, hsaKernel.cpuAqlCode(), hsaQueueMem_->vmAddress(), pKernelInfo);
|
||||
|
||||
if (useHwDebug_) {
|
||||
if (NULL != dev().hwDebugMgr()->postDispatchCallBackFunc()) {
|
||||
dev().hwDebugMgr()->executePostDispatchCallBack();
|
||||
}
|
||||
}
|
||||
|
||||
if (hsaKernel.dynamicParallelism()) {
|
||||
// Make sure exculsive access to the device queue
|
||||
@@ -3410,4 +3441,155 @@ VirtualGPU::writeVQueueHeader(VirtualGPU& hostQ, uint64_t kernelTable)
|
||||
virtualQueue_->writeRawData(hostQ, sizeof(AmdVQueueHeader), vqHeader_, !Wait);
|
||||
}
|
||||
|
||||
void
|
||||
VirtualGPU::flushCuCaches(HwDbgGpuCacheMask cache_mask)
|
||||
{
|
||||
//! @todo: fix issue of no event available for the flush/invalidate cache command
|
||||
InvalidateSqCaches(cache_mask.sqICache_,
|
||||
cache_mask.sqKCache_,
|
||||
cache_mask.tcL1_,
|
||||
cache_mask.tcL2_);
|
||||
|
||||
flushDMA(engineID_);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void
|
||||
VirtualGPU::buildKernelInfo(const HSAILKernel& hsaKernel,
|
||||
hsa_kernel_dispatch_packet_t* aqlPkt,
|
||||
HwDbgKernelInfo& kernelInfo)
|
||||
{
|
||||
amd::HwDebugManager * dbgManager = dev().hwDebugMgr();
|
||||
assert (dbgManager && "No HW Debug Manager!");
|
||||
|
||||
// Initialize structure with default values
|
||||
|
||||
if (hsaKernel.prog().maxScratchRegs() > 0) {
|
||||
gpu::Memory* scratchBuf = dev().scratch(hwRing())->memObjs_[0];
|
||||
kernelInfo.scratchBufAddr = scratchBuf->vmAddress();
|
||||
kernelInfo.scratchBufferSizeInBytes = scratchBuf->size();
|
||||
|
||||
// Get the address of the scratch buffer and its size for CPU access
|
||||
address scratchRingAddr = NULL;
|
||||
scratchRingAddr = static_cast<address>(scratchBuf->map(NULL, 0));
|
||||
dbgManager->setScratchRing(scratchRingAddr,scratchBuf->size());
|
||||
scratchBuf->unmap(NULL);
|
||||
}
|
||||
else {
|
||||
kernelInfo.scratchBufAddr = 0;
|
||||
kernelInfo.scratchBufferSizeInBytes = 0;
|
||||
dbgManager->setScratchRing(NULL, 0);
|
||||
}
|
||||
|
||||
|
||||
//! @todo: need to verify what is wanted for the global memory
|
||||
kernelInfo.heapBufAddr = (dev().globalMem()).vmAddress();
|
||||
|
||||
kernelInfo.pAqlDispatchPacket = aqlPkt;
|
||||
kernelInfo.pAqlQueuePtr = reinterpret_cast<void*>(hsaQueueMem_->vmAddress());
|
||||
|
||||
// Get the address of the kernel code and its size for CPU access
|
||||
gpu::Memory* aqlCode = hsaKernel.gpuAqlCode();
|
||||
if (NULL != aqlCode) {
|
||||
address aqlCodeAddr = static_cast<address>(aqlCode->map(NULL, 0));
|
||||
dbgManager->setKernelCodeInfo(aqlCodeAddr, hsaKernel.aqlCodeSize());
|
||||
aqlCode->unmap(NULL);
|
||||
}
|
||||
else {
|
||||
dbgManager->setKernelCodeInfo(NULL, 0);
|
||||
}
|
||||
|
||||
kernelInfo.trapPresent = false;
|
||||
kernelInfo.trapHandler = NULL;
|
||||
kernelInfo.trapHandlerBuffer = NULL;
|
||||
|
||||
kernelInfo.excpEn = 0;
|
||||
kernelInfo.cacheDisableMask = 0;
|
||||
kernelInfo.sqDebugMode = 0;
|
||||
|
||||
kernelInfo.mgmtSe0Mask = 0xFFFFFFFF;
|
||||
kernelInfo.mgmtSe1Mask = 0xFFFFFFFF;
|
||||
|
||||
// set kernel info for HW debug and call the callback function
|
||||
if (NULL != dbgManager->preDispatchCallBackFunc()) {
|
||||
DebugToolInfo dbgSetting;
|
||||
dbgSetting.scratchAddress_ = kernelInfo.scratchBufAddr;
|
||||
dbgSetting.scratchSize_ = kernelInfo.scratchBufferSizeInBytes;
|
||||
dbgSetting.globalAddress_ = kernelInfo.heapBufAddr;
|
||||
|
||||
// Call the predispatch callback function & set the trap info
|
||||
AqlCodeInfo aqlCodeInfo;
|
||||
aqlCodeInfo.aqlCode_ = (amd_kernel_code_t *) hsaKernel.cpuAqlCode();
|
||||
aqlCodeInfo.aqlCodeSize_ = hsaKernel.aqlCodeSize();
|
||||
|
||||
// Execute the pre-dispatch call back function
|
||||
dbgManager->executePreDispatchCallBack(reinterpret_cast<void*>(aqlPkt), &dbgSetting);
|
||||
|
||||
// assign the TMA and TBA for kernel dispatch
|
||||
if (NULL != dbgSetting.trapHandler_ && NULL != dbgSetting.trapBuffer_) {
|
||||
assignTrapHandler(dbgSetting, kernelInfo);
|
||||
}
|
||||
|
||||
kernelInfo.trapPresent = (kernelInfo.trapHandler) ? true : false;
|
||||
|
||||
// Execption policy
|
||||
kernelInfo.excpEn = dbgSetting.exceptionMask_;
|
||||
kernelInfo.cacheDisableMask = dbgSetting.cacheDisableMask_;
|
||||
kernelInfo.sqDebugMode = dbgSetting.gpuSingleStepMode_;
|
||||
|
||||
// Compute the mask for reserved CUs. These two dwords correspond to
|
||||
// two registers used for reserving CUs for display. In the current
|
||||
// implementation, the number of CUs reserved can be 0 to 7, and it
|
||||
// is set by debugger users.
|
||||
if (dbgSetting.monitorMode_) {
|
||||
uint32_t i = dbgSetting.reservedCuNum_ / 2;
|
||||
kernelInfo.mgmtSe0Mask <<= i;
|
||||
i = dbgSetting.reservedCuNum_ - i;
|
||||
kernelInfo.mgmtSe1Mask <<= i;
|
||||
}
|
||||
|
||||
// flush/invalidate the instruction, data, L1 and L2 caches
|
||||
InvalidateSqCaches();
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
VirtualGPU::assignTrapHandler(const DebugToolInfo& dbgSetting,
|
||||
HwDbgKernelInfo& kernelInfo)
|
||||
{
|
||||
|
||||
Memory * trapHandlerMem = dev().getGpuMemory(dbgSetting.trapHandler_);
|
||||
Memory * trapBufferMem = dev().getGpuMemory(dbgSetting.trapBuffer_);
|
||||
|
||||
addVmMemory(trapHandlerMem);
|
||||
addVmMemory(trapBufferMem);
|
||||
|
||||
// Handle TMA corruption hw bug workaround -
|
||||
// The trap handler buffer has extra 256 bytes allocated, the TMA address
|
||||
// is stored in the first two DWORDs and the actual trap handler code
|
||||
// is stored starting at the location of 256 bytes.
|
||||
//
|
||||
// - kernelInfo.trapHandler points directly to the trap handler code
|
||||
// - kernelInfo.trapHandlerBuffer points directly to the trap buffer (TMA)
|
||||
//
|
||||
kernelInfo.trapHandler = reinterpret_cast<void *>(trapHandlerMem->vmAddress() + TbaStartOffset);
|
||||
kernelInfo.trapHandlerBuffer = reinterpret_cast<void *>(trapBufferMem->vmAddress());
|
||||
|
||||
// Address of the trap handler code/buffer should be 256-byte aligned
|
||||
uint64_t tmaAddress = reinterpret_cast<uint64_t>(kernelInfo.trapHandlerBuffer);
|
||||
if ((reinterpret_cast<uint64_t>(kernelInfo.trapHandler) & 0xFF) != 0
|
||||
|| (tmaAddress & 0xFF) != 0) {
|
||||
assert(false && "Trap handler/buffer is not 256-byte aligned");
|
||||
}
|
||||
|
||||
// map the trap handler buffer address for host access, and store the trap
|
||||
// buffer address at the beginning of the allocated buffer
|
||||
address trapHandlerAddress = static_cast<address>(trapHandlerMem->map(NULL,0));
|
||||
uint32_t * tmaStorage = reinterpret_cast<uint32_t *>(trapHandlerAddress);
|
||||
tmaStorage[0] = tmaAddress & 0xFFFFFFFF;
|
||||
tmaStorage[1] = (tmaAddress >> 32) & 0xFFFFFFFF;
|
||||
trapHandlerMem->unmap(NULL);
|
||||
}
|
||||
|
||||
} // namespace gpu
|
||||
|
||||
@@ -12,6 +12,9 @@
|
||||
#include "device/gpu/gpusched.hpp"
|
||||
#include "device/blit.hpp"
|
||||
|
||||
#include "device/gpu/gpudebugger.hpp"
|
||||
|
||||
|
||||
/*! \addtogroup GPU GPU Resource Implementation
|
||||
* @{
|
||||
*/
|
||||
@@ -28,6 +31,7 @@ class VirtualGPU;
|
||||
class Program;
|
||||
class BlitManager;
|
||||
class ThreadTrace;
|
||||
class HSAILKernel;
|
||||
|
||||
//! Virtual GPU
|
||||
class VirtualGPU : public device::VirtualDevice, public CALGSLContext
|
||||
@@ -400,6 +404,8 @@ public:
|
||||
State state_; //!< virtual GPU current state
|
||||
CalVirtualDesc cal_; //!< CAL virtual device descriptor
|
||||
|
||||
void flushCuCaches(HwDbgGpuCacheMask cache_mask); //!< flush/invalidate SQ cache
|
||||
|
||||
protected:
|
||||
virtual void profileEvent(EngineType engine, bool type) const;
|
||||
|
||||
@@ -496,6 +502,17 @@ private:
|
||||
const amd::BufferRect& dstRect //!< region of destination for copy
|
||||
);
|
||||
|
||||
void buildKernelInfo(
|
||||
const HSAILKernel& hsaKernel, //!< hsa kernel
|
||||
hsa_kernel_dispatch_packet_t* aqlPkt, //!< aql packet for dispatch
|
||||
HwDbgKernelInfo& kernelInfo //!< kernel info for the dispatch
|
||||
);
|
||||
|
||||
void assignTrapHandler(
|
||||
const DebugToolInfo& dbgSetting, //!< debug settings
|
||||
HwDbgKernelInfo& kernelInfo //!< kernel info for the dispatch
|
||||
);
|
||||
|
||||
GslKernels gslKernels_; //!< GSL kernel descriptors
|
||||
GslKernelDesc* activeKernelDesc_; //!< active GSL kernel descriptors
|
||||
GpuEvents gpuEvents_; //!< GPU events
|
||||
@@ -534,6 +551,8 @@ private:
|
||||
uint deviceQueueSize_; //!< Device queue size
|
||||
|
||||
Memory* hsaQueueMem_; //!< Memory for the amd_queue_t object
|
||||
|
||||
bool useHwDebug_; //!< Flag of using HW debug
|
||||
};
|
||||
|
||||
/*@}*/} // namespace gpu
|
||||
|
||||
@@ -440,7 +440,7 @@ CALGSLContext::isDone(GpuEvent* event)
|
||||
if (m_eventQueue[event->engineId_].isDone(event->id))
|
||||
{
|
||||
event->invalidate();
|
||||
return true;
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
@@ -1269,10 +1269,10 @@ CALGSLContext::writeTimer(bool sdma, const gslMemObject mem, uint32 offset) cons
|
||||
void
|
||||
CALGSLContext::runAqlDispatch(GpuEvent& event, const void* aqlPacket,
|
||||
const gslMemObject* mems, uint32 numMems, gslMemObject scratch, uint32 scratchOffset,
|
||||
const void* cpuKernelCode, uint64 hsaQueueVA)
|
||||
const void* cpuKernelCode, uint64 hsaQueueVA, const void* kernelInfo)
|
||||
{
|
||||
eventBegin(MainEngine);
|
||||
m_cs->AqlDispatch(aqlPacket, mems, numMems, scratch, scratchOffset, cpuKernelCode, hsaQueueVA);
|
||||
m_cs->AqlDispatch(aqlPacket, mems, numMems, scratch, scratchOffset, cpuKernelCode, hsaQueueVA, kernelInfo);
|
||||
eventEnd(MainEngine, event);
|
||||
}
|
||||
|
||||
@@ -1299,3 +1299,30 @@ CALGSLContext::virtualQueueHandshake(GpuEvent& event, const gslMemObject mem, mc
|
||||
m_cs->VirtualQueueHandshake(mem, parentState, newStateValue, parentChildCounter, signal, dedicatedQueue);
|
||||
eventEnd(MainEngine, event);
|
||||
}
|
||||
|
||||
bool
|
||||
CALGSLContext::RegisterHwDebugger(uint64 debugMessages)
|
||||
{
|
||||
return m_cs->registerHwDebugger(debugMessages);
|
||||
}
|
||||
|
||||
bool
|
||||
CALGSLContext::ExceptionNotification(osEventHandle debugEvent)
|
||||
{
|
||||
return m_cs->exceptionNotification(debugEvent);
|
||||
}
|
||||
|
||||
void
|
||||
CALGSLContext::InvalidateSqCaches(bool instInvalidate, bool dataInvalidate, bool tcL1, bool tcL2)
|
||||
{
|
||||
// invalidating instruction/data L1 caches using Escape
|
||||
if (instInvalidate || dataInvalidate) {
|
||||
m_cs->invalidateSqCaches(instInvalidate, dataInvalidate);
|
||||
}
|
||||
|
||||
if (tcL1) {
|
||||
flushCUCaches(tcL2);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
@@ -44,7 +44,8 @@ public:
|
||||
bool runProgramGrid(GpuEvent& event, const ProgramGrid* pProgramGrid, const gslMemObject* mems, uint32 numMems);
|
||||
bool runProgramVideoDecode(GpuEvent& event, gslMemObject mo, const CALprogramVideoDecode& decode);
|
||||
void runAqlDispatch(GpuEvent& event, const void* aqlPacket, const gslMemObject* mems,
|
||||
uint32 numMems, gslMemObject scratch, uint32 scratchOffset, const void* cpuKernelCode, uint64 hsaQueueVA);
|
||||
uint32 numMems, gslMemObject scratch, uint32 scratchOffset, const void* cpuKernelCode,
|
||||
uint64 hsaQueueVA, const void* kernelInfo);
|
||||
mcaddr virtualQueueDispatcherStart();
|
||||
void virtualQueueDispatcherEnd(GpuEvent& event, const gslMemObject* mems, uint32 numMems,
|
||||
mcaddr signal, mcaddr loopStart, uint32 numTemplates);
|
||||
@@ -140,6 +141,11 @@ public:
|
||||
void writeTimer(bool sdma, const gslMemObject mem, uint32 offset) const;
|
||||
void writeSurfRaw(GpuEvent& event, gslMemObject mem, size_t size, const void* data);
|
||||
|
||||
/// HW Debug support functions
|
||||
bool RegisterHwDebugger(uint64 debugMessages);
|
||||
bool ExceptionNotification(osEventHandle debugEvent);
|
||||
void InvalidateSqCaches(bool instInvalidate = true, bool dataInvalidate = true, bool tcL1 = true, bool tcL2 = true);
|
||||
|
||||
protected:
|
||||
void setScratchBuffer(gslMemObject mem, int32 engineId);
|
||||
virtual void profileEvent(EngineType engine, bool type) const {}
|
||||
|
||||
Reference in New Issue
Block a user