diff --git a/projects/clr/rocclr/device/device.hpp b/projects/clr/rocclr/device/device.hpp
index b77d25b326..d0fdc72769 100755
--- a/projects/clr/rocclr/device/device.hpp
+++ b/projects/clr/rocclr/device/device.hpp
@@ -556,6 +556,10 @@ struct Info : public amd::EmbeddedObject {
 
   //! Target ID string
   char targetId_[0x40];
+
+  uint32_t  hmmSupported_;            //!< ROCr supports HMM interfaces
+  uint32_t  hmmCpuMemoryAccessible_;  //!< CPU memory is accessible by GPU without pinning/register
+  uint32_t  hmmDirectHostAccess_;     //!< HMM memory is accessible from the host without migration
 };
 
 //! Device settings
diff --git a/projects/clr/rocclr/device/rocm/rocdevice.cpp b/projects/clr/rocclr/device/rocm/rocdevice.cpp
index 0ff244fb1a..004be5a9c0 100755
--- a/projects/clr/rocclr/device/rocm/rocdevice.cpp
+++ b/projects/clr/rocclr/device/rocm/rocdevice.cpp
@@ -1418,7 +1418,7 @@ bool Device::populateOCLDeviceConstants() {
       return false;
     }
 
-    uint32_t asic_revision;
+    uint32_t asic_revision = 0;
     if (HSA_STATUS_SUCCESS !=
         hsa_agent_get_info(_bkendDevice,
                            static_cast<hsa_agent_info_t>(HSA_AMD_AGENT_INFO_ASIC_REVISION),
@@ -1470,6 +1470,21 @@ bool Device::populateOCLDeviceConstants() {
         ? (atoi(sgprValue.c_str()))
         : 0;
   }
+
+#if AMD_HMM_SUPPORT
+  // Generic support for HMM interfaces
+  if (HSA_STATUS_SUCCESS != hsa_system_get_info(HSA_AMD_SYSTEM_INFO_SVM_SUPPORTED,
+      &info_.hmmSupported_)) {
+    LogError("HSA_AMD_SYSTEM_INFO_SVM_SUPPORTED query failed. HMM will be disabled");
+  }
+
+  // This capability should be available with xnack enabled
+  if (HSA_STATUS_SUCCESS != hsa_system_get_info(HSA_AMD_SYSTEM_INFO_SVM_ACCESSIBLE_BY_DEFAULT,
+      &info_.hmmCpuMemoryAccessible_)) {
+    LogError("HSA_AMD_SYSTEM_INFO_SVM_ACCESSIBLE_BY_DEFAULT query failed.");
+  }
+#endif  // AMD_HMM_SUPPORT
+
   return true;
 }