From 2cc279dbbcd628116e6e28d7b9224e5e29af6861 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 11 Sep 2024 10:38:29 +0800 Subject: [PATCH] rocr: try DefaultSignal if interrupt is disabled Reviewed-by: Shane Xiao Change-Id: I5d3a3813f56990f3aca61be23215faeb0a9629cb Signed-off-by: Flora Cui --- runtime/hsa-runtime/core/runtime/amd_blit_sdma.cpp | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/runtime/hsa-runtime/core/runtime/amd_blit_sdma.cpp b/runtime/hsa-runtime/core/runtime/amd_blit_sdma.cpp index 064c4cd27e..b3ba00454a 100644 --- a/runtime/hsa-runtime/core/runtime/amd_blit_sdma.cpp +++ b/runtime/hsa-runtime/core/runtime/amd_blit_sdma.cpp @@ -54,6 +54,7 @@ #include "core/inc/sdma_registers.h" #include "core/inc/signal.h" #include "core/inc/interrupt_signal.h" +#include "core/inc/default_signal.h" namespace rocr { namespace AMD { @@ -204,8 +205,13 @@ hsa_status_t BlitSdma: cached_reserve_index_ = *reinterpret_cast(queue_resource_.Queue_write_ptr); cached_commit_index_ = cached_reserve_index_; - signals_[0].reset(new core::InterruptSignal(0)); - signals_[1].reset(new core::InterruptSignal(0)); + if (core::g_use_interrupt_wait) { + signals_[0].reset(new core::InterruptSignal(0)); + signals_[1].reset(new core::InterruptSignal(0)); + } else { + signals_[0].reset(new core::DefaultSignal(0)); + signals_[1].reset(new core::DefaultSignal(0)); + } max_single_linear_copy_size_ = linear_copy_size_override;