SWDEV-451594 - Implement Readback and Avoid HDP Flush workaround for device kernel args

Change-Id: I6d41a089a17f55306e7ff402588a1e831b20a7a7


[ROCm/clr commit: bf74ef4025]

projects/clr/hipamd/src/hip_graph_internal.cpp

@@ -395,19 +395,28 @@ hipError_t GraphExec::CaptureAQLPackets() {
       }
     }
 
-    if (device_kernarg_pool_ && !device->isXgmi()) {
-      if (device->info().hdpMemFlushCntl != nullptr) {
+    auto kernArgImpl = device->settings().kernel_arg_impl_;
+
+    const auto applyMemOrderingWA =
+        ((kernArgImpl == KernelArgImpl::DeviceKernelArgsReadback) ||
+         (kernArgImpl == KernelArgImpl::DeviceKernelArgsHDP)) &&
+        kernarg_pool_size_graph_ > 0;
+
+    if (device_kernarg_pool_ && applyMemOrderingWA) {
+      address dev_ptr = kernarg_pool_graph_ + kernarg_pool_size_graph_;
+      volatile char kSentinel = *(dev_ptr - 1);
+      // Memory ordering workaround for pcie: execute sfence followed by
+      // write the last byte of kernarg.
+      _mm_sfence();
+      *(dev_ptr - 1) = kSentinel;
+      // HDP flush is required to guarantee ordering in Navi and MI100
+      if (kernArgImpl == KernelArgImpl::DeviceKernelArgsHDP) {
         *device->info().hdpMemFlushCntl = 1u;
-        if (*device->info().hdpMemFlushCntl != UINT32_MAX) {
-          LogError("Unexpected HDP Register readback value!");
-        }
-      } else {
-        amd::Command* command = new amd::Marker(*capture_stream_, true);
-        if (command != nullptr) {
-          command->enqueue();
-          command->release();
-        }
       }
+      // Memory ordering workaround for pcie: execute mfence followed by
+      // read of the last byte of kernarg.
+      _mm_mfence();
+      kSentinel = *(dev_ptr - 1);
     }
 
     ResetQueueIndex();