diff --git a/projects/aqlprofile/gfxip/gfx9/gfx9_block_table.h b/projects/aqlprofile/gfxip/gfx9/gfx9_block_table.h index 91c4eb999b..9b6735e3ad 100644 --- a/projects/aqlprofile/gfxip/gfx9/gfx9_block_table.h +++ b/projects/aqlprofile/gfxip/gfx9/gfx9_block_table.h @@ -23,6 +23,7 @@ #ifndef _GFX9_BLOCKTABLE_H_ #define _GFX9_BLOCKTABLE_H_ + namespace gfxip { namespace gfx9 { /* @@ -33,319 +34,319 @@ namespace gfx9 { * SQ */ static const CounterRegInfo SqCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER0_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER1_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER1_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER2_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER2_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER3_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER3_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER4_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER4_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER5_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER5_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER6_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER6_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER6_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER7_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER7_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER7_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER8_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER8_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER8_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER9_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER9_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER9_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER10_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER10_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER10_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER11_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER11_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER11_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER12_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER12_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER12_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER13_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER13_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER13_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER14_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER14_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER14_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER15_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER15_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER15_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER1_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER1_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER3_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER3_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER5_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER5_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER7_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER7_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER7_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER8_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER8_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER8_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER9_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER9_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER9_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER10_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER10_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER10_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER11_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER11_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER11_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER12_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER12_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER12_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER13_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER13_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER13_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER14_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER14_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER14_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER15_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER15_LO), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER15_HI), REG_32B_NULL}}; /* * GRBM */ static const CounterRegInfo GrbmCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER0_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER1_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER0_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER1_HI), REG_32B_NULL}}; /* * GRBM_SE */ static const CounterRegInfo GrbmSeCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmGRBM_SE0_PERFCOUNTER_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmGRBM_SE0_PERFCOUNTER_LO), - REG_32B_ADDR(GC, 0, mmGRBM_SE0_PERFCOUNTER_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmGRBM_SE1_PERFCOUNTER_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmGRBM_SE1_PERFCOUNTER_LO), - REG_32B_ADDR(GC, 0, mmGRBM_SE1_PERFCOUNTER_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmGRBM_SE2_PERFCOUNTER_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmGRBM_SE2_PERFCOUNTER_LO), - REG_32B_ADDR(GC, 0, mmGRBM_SE2_PERFCOUNTER_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmGRBM_SE3_PERFCOUNTER_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmGRBM_SE3_PERFCOUNTER_LO), - REG_32B_ADDR(GC, 0, mmGRBM_SE3_PERFCOUNTER_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regGRBM_SE0_PERFCOUNTER_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regGRBM_SE0_PERFCOUNTER_LO), + REG_32B_ADDR(GC, 0, regGRBM_SE0_PERFCOUNTER_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regGRBM_SE1_PERFCOUNTER_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regGRBM_SE1_PERFCOUNTER_LO), + REG_32B_ADDR(GC, 0, regGRBM_SE1_PERFCOUNTER_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regGRBM_SE2_PERFCOUNTER_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regGRBM_SE2_PERFCOUNTER_LO), + REG_32B_ADDR(GC, 0, regGRBM_SE2_PERFCOUNTER_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regGRBM_SE3_PERFCOUNTER_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regGRBM_SE3_PERFCOUNTER_LO), + REG_32B_ADDR(GC, 0, regGRBM_SE3_PERFCOUNTER_HI), REG_32B_NULL}}; /* * PA_SU */ static const CounterRegInfo PaSuCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER1_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER2_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER2_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER3_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER3_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER1_SELECT1)}, + {REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER2_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER2_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER3_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regPA_SU_PERFCOUNTER3_HI), REG_32B_NULL}}; /* * PA_SC */ static const CounterRegInfo PaScCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER1_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER2_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER2_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER3_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER3_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER4_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER4_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER5_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER5_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER6_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER6_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER6_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER7_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER7_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER7_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER1_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER2_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER2_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER3_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER3_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER4_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER4_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER5_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER5_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER6_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER6_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER6_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER7_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER7_LO), REG_32B_ADDR(GC, 0, regPA_SC_PERFCOUNTER7_HI), REG_32B_NULL}}; /* * SPI */ static const CounterRegInfo SpiCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER1_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER2_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER2_HI), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER2_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER3_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER3_HI), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER3_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER4_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER4_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER5_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER5_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_SELECT1)}, + {REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_HI), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_SELECT1)}, + {REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_HI), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_SELECT1)}, + {REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER4_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER4_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER5_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER5_HI), REG_32B_NULL}}; /* * TCA */ static const CounterRegInfo TcaCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER1_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER2_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER2_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER3_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER3_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER1_SELECT1)}, + {REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER2_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER2_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER3_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regTCA_PERFCOUNTER3_HI), REG_32B_NULL}}; /* * TCC */ static const CounterRegInfo TccCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER1_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER2_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER2_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER3_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER3_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER1_SELECT1)}, + {REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER2_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER2_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER3_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regTCC_PERFCOUNTER3_HI), REG_32B_NULL}}; /* * TCP */ static const CounterRegInfo TcpCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER1_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER2_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER2_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER3_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER3_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_SELECT1)}, + {REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER2_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER2_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER3_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER3_HI), REG_32B_NULL}}; /* * CB */ static const CounterRegInfo CbCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER1_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER2_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER2_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER3_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER3_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER1_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER2_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER2_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER3_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regCB_PERFCOUNTER3_HI), REG_32B_NULL}}; /* * DB */ static const CounterRegInfo DbCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER1_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER2_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER2_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER3_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER3_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER1_SELECT1)}, + {REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER2_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER2_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER3_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regDB_PERFCOUNTER3_HI), REG_32B_NULL}}; /* * RLC */ static const CounterRegInfo RlcCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER0_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER1_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regRLC_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regRLC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regRLC_PERFCOUNTER0_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regRLC_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regRLC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regRLC_PERFCOUNTER1_HI), REG_32B_NULL}}; /* * SX */ static const CounterRegInfo SxCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER1_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER2_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER2_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER3_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER3_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_SELECT1)}, + {REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER2_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER2_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER3_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER3_HI), REG_32B_NULL}}; /* * TA */ static const CounterRegInfo TaCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER1_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER1_HI), REG_32B_NULL}}; /* * TD */ static const CounterRegInfo TdCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER1_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regTD_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTD_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTD_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regTD_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regTD_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regTD_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTD_PERFCOUNTER1_HI), REG_32B_NULL}}; /* * GDS */ static const CounterRegInfo GdsCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER1_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER2_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER2_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER3_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER3_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER1_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER2_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER2_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER3_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER3_HI), REG_32B_NULL}}; /* * VGT */ static const CounterRegInfo VgtCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER1_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER2_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER2_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER3_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER3_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER1_SELECT1)}, + {REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER2_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER2_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER3_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regVGT_PERFCOUNTER3_HI), REG_32B_NULL}}; /* * IA */ static const CounterRegInfo IaCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER1_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER2_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER2_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER3_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER3_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER1_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER2_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER2_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER3_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regIA_PERFCOUNTER3_HI), REG_32B_NULL}}; /* * WD */ static const CounterRegInfo WdCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER0_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER1_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER2_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER2_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER3_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER3_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER0_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER1_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER2_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER2_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER3_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regWD_PERFCOUNTER3_HI), REG_32B_NULL}}; /* * CPC */ static const CounterRegInfo CpcCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER1_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER1_HI), REG_32B_NULL}}; /* * CPF */ static const CounterRegInfo CpfCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER1_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER1_HI), REG_32B_NULL}}; /* * CPG */ static const CounterRegInfo CpgCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER0_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER1_SELECT), REG_32B_NULL, - REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER1_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regCPG_PERFCOUNTER0_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regCPG_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regCPG_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regCPG_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regCPG_PERFCOUNTER1_SELECT), REG_32B_NULL, + REG_32B_ADDR(GC, 0, regCPG_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regCPG_PERFCOUNTER1_HI), REG_32B_NULL}}; // RMI static const CounterRegInfo RmiCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, mmRMI_PERF_COUNTER_CNTL), - REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER0_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER1_SELECT), REG_32B_ADDR(GC, 0, mmRMI_PERF_COUNTER_CNTL), - REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER1_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER2_SELECT), REG_32B_ADDR(GC, 0, mmRMI_PERF_COUNTER_CNTL), - REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER2_HI), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER2_SELECT1)}, - {REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER3_SELECT), REG_32B_ADDR(GC, 0, mmRMI_PERF_COUNTER_CNTL), - REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER3_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, regRMI_PERF_COUNTER_CNTL), + REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER0_SELECT1)}, + {REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER1_SELECT), REG_32B_ADDR(GC, 0, regRMI_PERF_COUNTER_CNTL), + REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER1_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER2_SELECT), REG_32B_ADDR(GC, 0, regRMI_PERF_COUNTER_CNTL), + REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER2_HI), REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER2_SELECT1)}, + {REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER3_SELECT), REG_32B_ADDR(GC, 0, regRMI_PERF_COUNTER_CNTL), + REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regRMI_PERFCOUNTER3_HI), REG_32B_NULL}}; // GCEA static const CounterRegInfo GceaCounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER0_CFG), - REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_LO), - REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER1_CFG), - REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_LO), - REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER0_CFG), + REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_LO), + REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER1_CFG), + REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_LO), + REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_HI), REG_32B_NULL}}; // ATC static const CounterRegInfo AtcCounterRegAddr[] = { @@ -364,12 +365,12 @@ static const CounterRegInfo AtcCounterRegAddr[] = { // ATC L2 static const CounterRegInfo AtcL2CounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER0_CFG), - REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_RSLT_CNTL), - REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER1_CFG), - REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_RSLT_CNTL), - REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER0_CFG), + REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER_RSLT_CNTL), + REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER1_CFG), + REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER_RSLT_CNTL), + REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, regATC_L2_PERFCOUNTER_HI), REG_32B_NULL}}; // RPB static const CounterRegInfo RpbCounterRegAddr[] = { @@ -388,38 +389,38 @@ static const CounterRegInfo RpbCounterRegAddr[] = { // MC VM L2 static const CounterRegInfo McVmL2CounterRegAddr[] = { - {REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER0_CFG), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER1_CFG), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER2_CFG), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER3_CFG), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER4_CFG), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER5_CFG), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER6_CFG), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}, - {REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER7_CFG), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO), - REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}}; + {REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER0_CFG), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER1_CFG), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER2_CFG), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER3_CFG), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER4_CFG), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER5_CFG), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER6_CFG), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}, + {REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER7_CFG), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_RSLT_CNTL), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_LO), + REG_32B_ADDR(GC, 0, regMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}}; // BlockDelayInfo for SPM static const uint32_t SqBlockDelayValue[] = {0x3b, 0x38, 0x39, 0x36}; // Verified @@ -456,24 +457,24 @@ static const uint32_t CpcBlockDelayValue[] = {0x3c}; static const uint32_t CpfBlockDelayValue[] = {0x32}; static const uint32_t CpgBlockDelayValue[] = {0x30}; // Verified -static const BlockDelayInfo SqBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY), SqBlockDelayValue}; -static const BlockDelayInfo PaSuBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY), PaSuBlockDelayValue}; -static const BlockDelayInfo PaScBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY), PaScBlockDelayValue}; -static const BlockDelayInfo SpiBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY), SpiBlockDelayValue}; -static const BlockDelayInfo TcaBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY), TcaBlockDelayValue}; -static const BlockDelayInfo TccBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), TccBlockDelayValue}; -static const BlockDelayInfo TcpBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), TcpBlockDelayValue}; -static const BlockDelayInfo CbBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), CbBlockDelayValue}; -static const BlockDelayInfo DbBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), DbBlockDelayValue}; -static const BlockDelayInfo SxBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY), SxBlockDelayValue}; -static const BlockDelayInfo TaBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), TaBlockDelayValue}; -static const BlockDelayInfo TdBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), TdBlockDelayValue}; -static const BlockDelayInfo GdsBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY), GdsBlockDelayValue}; -static const BlockDelayInfo VgtBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY), VgtBlockDelayValue}; -static const BlockDelayInfo IaBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY), IaBlockDelayValue}; -static const BlockDelayInfo CpcBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY), CpcBlockDelayValue}; -static const BlockDelayInfo CpfBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY), CpfBlockDelayValue}; -static const BlockDelayInfo CpgBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY), CpgBlockDelayValue}; +static const BlockDelayInfo SqBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY), SqBlockDelayValue}; +static const BlockDelayInfo PaSuBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_PA_PERFMON_SAMPLE_DELAY), PaSuBlockDelayValue}; +static const BlockDelayInfo PaScBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_SC_PERFMON_SAMPLE_DELAY), PaScBlockDelayValue}; +static const BlockDelayInfo SpiBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY), SpiBlockDelayValue}; +static const BlockDelayInfo TcaBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY), TcaBlockDelayValue}; +static const BlockDelayInfo TccBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), TccBlockDelayValue}; +static const BlockDelayInfo TcpBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), TcpBlockDelayValue}; +static const BlockDelayInfo CbBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_CB_PERFMON_SAMPLE_DELAY), CbBlockDelayValue}; +static const BlockDelayInfo DbBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_DB_PERFMON_SAMPLE_DELAY), DbBlockDelayValue}; +static const BlockDelayInfo SxBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_SX_PERFMON_SAMPLE_DELAY), SxBlockDelayValue}; +static const BlockDelayInfo TaBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_TA_PERFMON_SAMPLE_DELAY), TaBlockDelayValue}; +static const BlockDelayInfo TdBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_TD_PERFMON_SAMPLE_DELAY), TdBlockDelayValue}; +static const BlockDelayInfo GdsBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY), GdsBlockDelayValue}; +static const BlockDelayInfo VgtBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY), VgtBlockDelayValue}; +static const BlockDelayInfo IaBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_IA_PERFMON_SAMPLE_DELAY), IaBlockDelayValue}; +static const BlockDelayInfo CpcBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY), CpcBlockDelayValue}; +static const BlockDelayInfo CpfBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY), CpfBlockDelayValue}; +static const BlockDelayInfo CpgBlockDelayInfo = {REG_32B_ADDR(GC, 0, regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY), CpgBlockDelayValue}; // Counter block info table // SPM global blocks: CPG, CPC, CPF, GDS, TCC, TCA, IA, TCS diff --git a/projects/aqlprofile/gfxip/gfx9/gfx9_primitives.h b/projects/aqlprofile/gfxip/gfx9/gfx9_primitives.h index 9a14317817..e85e64d39b 100644 --- a/projects/aqlprofile/gfxip/gfx9/gfx9_primitives.h +++ b/projects/aqlprofile/gfxip/gfx9/gfx9_primitives.h @@ -63,45 +63,45 @@ class gfx9_cntx_prim { public: static const uint32_t GFXIP_LEVEL = 9; static const uint32_t NUMBER_OF_BLOCKS = LastCounterBlockId + 1; - static constexpr Register GRBM_GFX_INDEX_ADDR = REG_32B_ADDR(GC, 0, mmGRBM_GFX_INDEX); + static constexpr Register GRBM_GFX_INDEX_ADDR = REG_32B_ADDR(GC, 0, regGRBM_GFX_INDEX); static constexpr Register COMPUTE_PERFCOUNT_ENABLE_ADDR = - REG_32B_ADDR(GC, 0, mmCOMPUTE_PERFCOUNT_ENABLE); - static constexpr Register RLC_PERFMON_CLK_CNTL_ADDR = REG_32B_ADDR(GC, 0, mmRLC_PERFMON_CLK_CNTL); - static constexpr Register CP_PERFMON_CNTL_ADDR = REG_32B_ADDR(GC, 0, mmCP_PERFMON_CNTL); + REG_32B_ADDR(GC, 0, regCOMPUTE_PERFCOUNT_ENABLE); + static constexpr Register RLC_PERFMON_CLK_CNTL_ADDR = REG_32B_ADDR(GC, 0, regRLC_PERFMON_CLK_CNTL); + static constexpr Register CP_PERFMON_CNTL_ADDR = REG_32B_ADDR(GC, 0, regCP_PERFMON_CNTL); static const uint32_t MC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK_PRM = 0x01000000L; static const uint32_t MC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK_PRM = 0x02000000L; static constexpr Register SPI_SQG_EVENT_CTL_ADDR{}; - static constexpr Register SQ_PERFCOUNTER_CTRL_ADDR = REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL); + static constexpr Register SQ_PERFCOUNTER_CTRL_ADDR = REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL); static constexpr Register SQ_PERFCOUNTER_CTRL2_ADDR{}; static constexpr Register COMPUTE_THREAD_TRACE_ENABLE_ADDR{}; - static constexpr Register SQ_PERFCOUNTER_MASK_ADDR = REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_MASK); - static constexpr Register SQ_THREAD_TRACE_MASK_ADDR = REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_MASK); + static constexpr Register SQ_PERFCOUNTER_MASK_ADDR = REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_MASK); + static constexpr Register SQ_THREAD_TRACE_MASK_ADDR = REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_MASK); static constexpr Register SQ_THREAD_TRACE_PERF_MASK_ADDR = - REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_PERF_MASK); + REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_PERF_MASK); static constexpr Register SQ_THREAD_TRACE_TOKEN_MASK_ADDR = - REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_TOKEN_MASK); + REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_TOKEN_MASK); static constexpr Register SQ_THREAD_TRACE_TOKEN_MASK2_ADDR = - REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_TOKEN_MASK2); - static constexpr Register SQ_THREAD_TRACE_MODE_ADDR = REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_MODE); + REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_TOKEN_MASK2); + static constexpr Register SQ_THREAD_TRACE_MODE_ADDR = REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_MODE); static constexpr Register SQ_THREAD_TRACE_BUF0_BASE_LO_ADDR{}; static constexpr Register SQ_THREAD_TRACE_BUF0_BASE_HI_ADDR{}; static constexpr Register SQ_THREAD_TRACE_BUF0_SIZE_ADDR{}; - static constexpr Register SQ_THREAD_TRACE_BASE_ADDR = REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_BASE); + static constexpr Register SQ_THREAD_TRACE_BASE_ADDR = REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_BASE); static constexpr Register SQ_THREAD_TRACE_BASE2_ADDR = - REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_BASE2); - static constexpr Register SQ_THREAD_TRACE_SIZE_ADDR = REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_SIZE); - static constexpr Register SQ_THREAD_TRACE_CTRL_ADDR = REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_CTRL); + REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_BASE2); + static constexpr Register SQ_THREAD_TRACE_SIZE_ADDR = REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_SIZE); + static constexpr Register SQ_THREAD_TRACE_CTRL_ADDR = REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_CTRL); static constexpr Register SQ_THREAD_TRACE_HIWATER_ADDR = - REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_HIWATER); + REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_HIWATER); static const uint32_t SQ_THREAD_TRACE_HIWATER_VAL = 0x6; static constexpr Register SQ_THREAD_TRACE_STATUS_ADDR = - REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_STATUS); - static constexpr Register SQ_THREAD_TRACE_CNTR_ADDR = REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_CNTR); - static constexpr Register SQ_THREAD_TRACE_WPTR_ADDR = REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_WPTR); + REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_STATUS); + static constexpr Register SQ_THREAD_TRACE_CNTR_ADDR = REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_CNTR); + static constexpr Register SQ_THREAD_TRACE_WPTR_ADDR = REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_WPTR); static constexpr Register SQ_THREAD_TRACE_STATUS_OFFSET = []() { - Register reg = REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_STATUS); + Register reg = REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_STATUS); reg.offset -= UCONFIG_SPACE_START; return reg; }(); @@ -111,16 +111,16 @@ class gfx9_cntx_prim { static const uint32_t UMC_COUNTER_BLOCK_NUM_INSTANCES = UmcCounterBlockMaxInstances; static constexpr Register RLC_SPM_PERFMON_CNTL__ADDR = - REG_32B_ADDR(GC, 0, mmRLC_SPM_PERFMON_CNTL); - static constexpr Register RLC_SPM_MC_CNTL__ADDR = REG_32B_ADDR(GC, 0, mmRLC_SPM_MC_CNTL); + REG_32B_ADDR(GC, 0, regRLC_SPM_PERFMON_CNTL); + static constexpr Register RLC_SPM_MC_CNTL__ADDR = REG_32B_ADDR(GC, 0, regRLC_SPM_MC_CNTL); static constexpr Register RLC_SPM_PERFMON_RING_BASE_LO__ADDR = - REG_32B_ADDR(GC, 0, mmRLC_SPM_PERFMON_RING_BASE_LO); + REG_32B_ADDR(GC, 0, regRLC_SPM_PERFMON_RING_BASE_LO); static constexpr Register RLC_SPM_PERFMON_RING_BASE_HI__ADDR = - REG_32B_ADDR(GC, 0, mmRLC_SPM_PERFMON_RING_BASE_HI); + REG_32B_ADDR(GC, 0, regRLC_SPM_PERFMON_RING_BASE_HI); static constexpr Register RLC_SPM_PERFMON_RING_SIZE__ADDR = - REG_32B_ADDR(GC, 0, mmRLC_SPM_PERFMON_RING_SIZE); + REG_32B_ADDR(GC, 0, regRLC_SPM_PERFMON_RING_SIZE); static constexpr Register RLC_SPM_PERFMON_SEGMENT_SIZE__ADDR = - REG_32B_ADDR(GC, 0, mmRLC_SPM_PERFMON_SEGMENT_SIZE); + REG_32B_ADDR(GC, 0, regRLC_SPM_PERFMON_SEGMENT_SIZE); #if defined(regRLC_SPM_PERFMON_SEGMENT_SIZE_CORE1) static constexpr Register RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__ADDR = REG_32B_ADDR(GC, 0, regRLC_SPM_PERFMON_SEGMENT_SIZE_CORE1); @@ -128,45 +128,45 @@ class gfx9_cntx_prim { static constexpr Register RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__ADDR = Register(0xDCAF); #endif static constexpr Register RLC_SPM_GLOBAL_MUXSEL_ADDR__ADDR = - REG_32B_ADDR(GC, 0, mmRLC_SPM_GLOBAL_MUXSEL_ADDR); + REG_32B_ADDR(GC, 0, regRLC_SPM_GLOBAL_MUXSEL_ADDR); static constexpr Register RLC_SPM_GLOBAL_MUXSEL_DATA__ADDR = - REG_32B_ADDR(GC, 0, mmRLC_SPM_GLOBAL_MUXSEL_DATA); + REG_32B_ADDR(GC, 0, regRLC_SPM_GLOBAL_MUXSEL_DATA); static constexpr Register RLC_SPM_SE_MUXSEL_ADDR__ADDR = - REG_32B_ADDR(GC, 0, mmRLC_SPM_SE_MUXSEL_ADDR); + REG_32B_ADDR(GC, 0, regRLC_SPM_SE_MUXSEL_ADDR); static constexpr Register RLC_SPM_SE_MUXSEL_DATA__ADDR = - REG_32B_ADDR(GC, 0, mmRLC_SPM_SE_MUXSEL_DATA); + REG_32B_ADDR(GC, 0, regRLC_SPM_SE_MUXSEL_DATA); static constexpr Register RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__ADDR = - REG_32B_ADDR(GC, 0, mmRLC_SPM_PERFMON_SAMPLE_DELAY_MAX); + REG_32B_ADDR(GC, 0, regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX); static const uint32_t RLC_SPM_COUNTERS_PER_LINE = 16; static const uint32_t RLC_SPM_TIMESTAMP_SIZE16 = 4; static constexpr Register SQ_THREAD_TRACE_USERDATA_0 = - REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_USERDATA_0); + REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_USERDATA_0); static constexpr Register SQ_THREAD_TRACE_USERDATA_1 = - REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_USERDATA_1); + REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_USERDATA_1); static constexpr Register SQ_THREAD_TRACE_USERDATA_2 = - REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_USERDATA_2); + REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_USERDATA_2); static constexpr Register SQ_THREAD_TRACE_USERDATA_3 = - REG_32B_ADDR(GC, 0, mmSQ_THREAD_TRACE_USERDATA_3); + REG_32B_ADDR(GC, 0, regSQ_THREAD_TRACE_USERDATA_3); static Register sqtt_perfcounter_addr(uint32_t index) { static const Register SQTT_PERFCOUNTERS_SELECT[16] = { - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER0_SELECT), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER1_SELECT), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER2_SELECT), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER3_SELECT), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER4_SELECT), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER5_SELECT), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER6_SELECT), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER7_SELECT), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER8_SELECT), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER9_SELECT), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER10_SELECT), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER11_SELECT), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER12_SELECT), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER13_SELECT), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER14_SELECT), - REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER15_SELECT)}; + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_SELECT), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER1_SELECT), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_SELECT), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER3_SELECT), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_SELECT), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER5_SELECT), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_SELECT), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER7_SELECT), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER8_SELECT), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER9_SELECT), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER10_SELECT), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER11_SELECT), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER12_SELECT), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER13_SELECT), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER14_SELECT), + REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER15_SELECT)}; return SQTT_PERFCOUNTERS_SELECT[index & 0xF]; } diff --git a/projects/aqlprofile/src/def/gfx908_def.h b/projects/aqlprofile/src/def/gfx908_def.h index a0c5924867..7598a1c3a2 100644 --- a/projects/aqlprofile/src/def/gfx908_def.h +++ b/projects/aqlprofile/src/def/gfx908_def.h @@ -27,8 +27,8 @@ #include "util/soc15_common.h" #include "util/reg_offsets.h" #include "linux/packets/soc15d.h" -#include "linux/registers/gc/gc_9_2_1_offset.h" -#include "linux/registers/gc/gc_9_2_1_sh_mask.h" +#include "linux/registers/gc/gc_9_4_2_offset.h" +#include "linux/registers/gc/gc_9_4_2_sh_mask.h" #include "linux/registers/athub/athub_1_0_offset.h" #include "linux/registers/athub/athub_1_0_sh_mask.h" #include "gfxip/gfx9/gfx9_block_info.h" diff --git a/projects/aqlprofile/src/def/gfx90a_def.h b/projects/aqlprofile/src/def/gfx90a_def.h index b7dde23a4d..3df587134b 100644 --- a/projects/aqlprofile/src/def/gfx90a_def.h +++ b/projects/aqlprofile/src/def/gfx90a_def.h @@ -27,8 +27,8 @@ #include "util/soc15_common.h" #include "util/reg_offsets.h" #include "linux/packets/soc15d.h" -#include "linux/registers/gc/gc_9_2_1_offset.h" -#include "linux/registers/gc/gc_9_2_1_sh_mask.h" +#include "linux/registers/gc/gc_9_4_2_offset.h" +#include "linux/registers/gc/gc_9_4_2_sh_mask.h" #include "linux/registers/athub/athub_1_0_offset.h" #include "linux/registers/athub/athub_1_0_sh_mask.h" #include "gfxip/gfx9/gfx9_block_info.h" diff --git a/projects/aqlprofile/src/def/gfx940_def.h b/projects/aqlprofile/src/def/gfx940_def.h index 5a40507fb3..da997a3860 100644 --- a/projects/aqlprofile/src/def/gfx940_def.h +++ b/projects/aqlprofile/src/def/gfx940_def.h @@ -27,8 +27,8 @@ #include "util/soc15_common.h" #include "util/reg_offsets.h" #include "linux/packets/soc15d.h" -#include "linux/registers/gc/gc_9_2_1_offset.h" -#include "linux/registers/gc/gc_9_2_1_sh_mask.h" +#include "linux/registers/gc/gc_9_4_2_offset.h" +#include "linux/registers/gc/gc_9_4_2_sh_mask.h" #include "linux/registers/athub/athub_1_0_offset.h" #include "linux/registers/athub/athub_1_0_sh_mask.h" #include "gfxip/gfx9/gfx9_block_info.h" diff --git a/projects/aqlprofile/src/def/gfx9_def.h b/projects/aqlprofile/src/def/gfx9_def.h index 973da0f962..d84be4fc08 100644 --- a/projects/aqlprofile/src/def/gfx9_def.h +++ b/projects/aqlprofile/src/def/gfx9_def.h @@ -27,8 +27,8 @@ #include "util/soc15_common.h" #include "util/reg_offsets.h" #include "linux/packets/soc15d.h" -#include "linux/registers/gc/gc_9_2_1_offset.h" -#include "linux/registers/gc/gc_9_2_1_sh_mask.h" +#include "linux/registers/gc/gc_9_4_2_offset.h" +#include "linux/registers/gc/gc_9_4_2_sh_mask.h" #include "linux/registers/athub/athub_1_0_offset.h" #include "linux/registers/athub/athub_1_0_sh_mask.h" #include "gfxip/gfx9/gfx9_block_info.h"