P4 to Git Change 1981122 by gandryey@gera-win10 on 2019/08/09 17:59:31
SWDEV-79445 - OCL generic changes and code clean-up
- Allow async execution with scratch on the same queue. COMPUTE_TMPRING_SIZE.WAVESIZE should be constant across all dispatches.
Affected files ...
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldevice.cpp#151 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldevice.hpp#40 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palvirtual.cpp#145 edit
[ROCm/clr commit: 0a2d4e2dc3]
This commit is contained in:
@@ -2370,12 +2370,15 @@ bool VirtualGPU::submitKernelInternal(const amd::NDRangeContainer& sizes, const
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dispatchParam.scratchAddr = scratch->memObj_->vmAddress();
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dispatchParam.scratchSize = scratch->size_;
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dispatchParam.scratchOffset = scratch->offset_;
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// Use maximum available slots for all dispatches to allow async on the same queue
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// HW value loaded into SGPR is an offset value calculated as
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// wave_slot * COMPUTE_TMPRING_SIZE.WAVESIZE
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dispatchParam.workitemPrivateSegmentSize = scratch->privateMemSize_;
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}
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dispatchParam.pCpuAqlCode = hsaKernel.cpuAqlCode();
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dispatchParam.hsaQueueVa = hsaQueueMem_->vmAddress();
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dispatchParam.wavesPerSh = (enqueueEvent != nullptr) ? enqueueEvent->profilingInfo().waves_ : 0;
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dispatchParam.useAtc = dev().settings().svmFineGrainSystem_ ? true : false;
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dispatchParam.workitemPrivateSegmentSize = hsaKernel.spillSegSize();
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dispatchParam.kernargSegmentSize = hsaKernel.argsBufferSize();
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// Run AQL dispatch in HW
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eventBegin(MainEngine);
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