From 38ce852b12af74409c82472201f26d81736ffc39 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Thu, 23 Nov 2023 21:15:38 +0000 Subject: [PATCH] Add RISC-V support Patch provided by user Xeonacid via github: https://github.com/RadeonOpenCompute/ROCR-Runtime/pull/172/ Change-Id: I5f9086b536383093e7995b9cfdc19dab213f0265 [ROCm/ROCR-Runtime commit: 251601b20b17c61c4ab1ab8c5c62e0511d6a10be] --- projects/rocr-runtime/runtime/hsa-runtime/inc/hsa.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/rocr-runtime/runtime/hsa-runtime/inc/hsa.h b/projects/rocr-runtime/runtime/hsa-runtime/inc/hsa.h index 31ff2b8a9a..d1fd9aff5c 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/inc/hsa.h +++ b/projects/rocr-runtime/runtime/hsa-runtime/inc/hsa.h @@ -80,7 +80,7 @@ // Try to detect CPU endianness #if !defined(LITTLEENDIAN_CPU) && !defined(BIGENDIAN_CPU) #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || \ - defined(_M_X64) || defined(__loongarch64) + defined(_M_X64) || defined(__loongarch64) || defined(__riscv) #define LITTLEENDIAN_CPU #endif #endif