AI/rocm-systems
2
0
Fork 0
Código Issues Pull Requests Ações Pacotes Projetos Versões Wiki Atividade

Implement Target ID Proposal

Ver Código-Fonte 
Changes from Konstantin Zhuravlyov, Tony Tye

Change-Id: I532801193afa9d5b8ac2a877b5497eab661f0597
Esse commit está contido em:
Konstantin Zhuravlyov
2020-11-10 13:41:20 -05:00
pai a09ba8bcc8
commit 3a08d0964e
22 arquivos alterados com 754 adições e 443 exclusões
Baixar Arquivo de Patch Baixar Arquivo de Diff Expandir todos os arquivos Colapsar todos os arquivos
runtime/hsa-runtime/core/inc/amd_elf_image.hpp
+2
Ver Arquivo
@@ -171,6 +171,8 @@ namespace elf {
virtual uint16_t Type() = 0;
virtual uint32_t EFlags() = 0;
virtual uint32_t ABIVersion() = 0;
virtual uint32_t EClass() = 0;
virtual uint32_t OsAbi() = 0;
std::string output() { return out.str(); }
runtime/hsa-runtime/core/inc/amd_hsa_code.hpp
+2
Ver Arquivo
@@ -230,6 +230,8 @@ namespace code {
amd::elf::SymbolTable* Symtab() { assert(img); return img->symtab(); }
uint16_t Machine() const { return img->Machine(); }
uint32_t EFlags() const { return img->EFlags(); }
uint32_t EClass() const { return img->EClass(); }
uint32_t OsAbi() const { return img->OsAbi(); }
AmdHsaCode(bool combineDataSegments = true);
virtual ~AmdHsaCode();
runtime/hsa-runtime/core/inc/isa.h
+47 -27
Ver Arquivo
@@ -82,6 +82,13 @@ private:
friend class Isa;
};
enum class IsaFeature : uint8_t {
Unsupported,
Any,
Disabled,
Enabled,
};
/// @class Isa.
/// @brief Instruction Set Architecture.
class Isa final: public amd::hsa::common::Signed<0xB13594F2BD8F212D> {
@@ -103,23 +110,36 @@ class Isa final: public amd::hsa::common::Signed<0xB13594F2BD8F212D> {
return isa_object;
}
/// @returns True if @p code_object_isa and @p agent_isa are compatible,
/// false otherwise.
static bool IsCompatible(const Isa &code_object_isa, const Isa &agent_isa);
/// @returns This Isa's version.
const Version &version() const {
return version_;
}
/// @returns True if this Isa has xnack enabled, false otherwise.
const bool &xnackEnabled() const {
return xnackEnabled_;
/// @returns SRAM ECC feature status.
const IsaFeature &sramecc() const {
return sramecc_;
}
/// @returns True if this Isa has sram ecc enabled, false otherwise.
const bool &sramEccEnabled() const {
return sramEcc_;
/// @returns XNACK feature status.
const IsaFeature &xnack() const {
return xnack_;
}
/// @returns This Isa's supported wavefront.
const Wavefront &wavefront() const {
return wavefront_;
}
/// @returns True if SRAMECC feature is supported, false otherwise.
bool IsSrameccSupported() const {
return sramecc_ != IsaFeature::Unsupported;
}
/// @returns True if XNACK feature is supported, false otherwise.
bool IsXnackSupported() const {
return xnack_ != IsaFeature::Unsupported;
}
/// @returns This Isa's architecture.
std::string GetArchitecture() const {
return "amdgcn";
@@ -153,19 +173,6 @@ class Isa final: public amd::hsa::common::Signed<0xB13594F2BD8F212D> {
return &wavefront_;
}
/// @returns True if this Isa is compatible with @p isa_object, false
/// otherwise.
bool IsCompatible(const Isa *isa_object) const {
assert(isa_object);
return version_ == isa_object->version_ &&
xnackEnabled_ == isa_object->xnackEnabled_;
}
/// @returns True if this Isa is compatible with @p isa_handle, false
/// otherwise.
bool IsCompatible(const hsa_isa_t &isa_handle) const {
assert(isa_handle.handle);
return IsCompatible(Object(isa_handle));
}
/// @brief Isa is always in valid state.
bool IsValid() const {
return true;
@@ -186,22 +193,33 @@ class Isa final: public amd::hsa::common::Signed<0xB13594F2BD8F212D> {
private:
/// @brief Default constructor.
Isa(): version_(Version(-1, -1, -1)), xnackEnabled_(false), sramEcc_(false) {}
Isa()
: version_(Version(-1, -1, -1)),
sramecc_(IsaFeature::Unsupported),
xnack_(IsaFeature::Unsupported) {}
/// @brief Construct from @p version.
Isa(const Version &version): version_(version), xnackEnabled_(false), sramEcc_(false) {}
Isa(const Version &version)
: version_(version),
sramecc_(IsaFeature::Unsupported),
xnack_(IsaFeature::Unsupported) {}
/// @brief Construct from @p version.
Isa(const Version &version, const bool xnack, const bool ecc): version_(version), xnackEnabled_(xnack), sramEcc_(ecc) {}
Isa(const Version &version,
IsaFeature sramecc,
IsaFeature xnack)
: version_(version),
sramecc_(sramecc),
xnack_(xnack) {}
/// @brief Isa's version.
Version version_;
/// @brief Isa's supported xnack flag.
bool xnackEnabled_;
/// @brief SRAMECC feature.
IsaFeature sramecc_;
/// @brief Isa's sram ecc flag.
bool sramEcc_;
/// @brief XNACK feature.
IsaFeature xnack_;
/// @brief Isa's supported wavefront.
Wavefront wavefront_;
@@ -217,7 +235,9 @@ class IsaRegistry final {
/// @returns Isa for requested @p full_name, null pointer if not supported.
static const Isa *GetIsa(const std::string &full_name);
/// @returns Isa for requested @p version, null pointer if not supported.
static const Isa *GetIsa(const Isa::Version &version, bool xnack, bool ecc);
static const Isa *GetIsa(const Isa::Version &version,
IsaFeature sramecc = IsaFeature::Any,
IsaFeature xnack = IsaFeature::Any);
private:
/// @brief IsaRegistry's map type.
runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp
+25 -2
Ver Arquivo
@@ -100,11 +100,34 @@ GpuAgent::GpuAgent(HSAuint32 node, const HsaNodeProperties& node_props)
historical_clock_ratio_ = 0.0;
assert(err == HSAKMT_STATUS_SUCCESS && "hsaGetClockCounters error");
const core::Isa *isa_base = core::IsaRegistry::GetIsa(
core::Isa::Version(node_props.EngineId.ui32.Major,
node_props.EngineId.ui32.Minor,
node_props.EngineId.ui32.Stepping));
if (!isa_base) {
throw AMD::hsa_exception(HSA_STATUS_ERROR_INVALID_ISA, "Agent creation failed.\nThe GPU node has an unrecognized id.\n");
}
rocr::core::IsaFeature sramecc = rocr::core::IsaFeature::Unsupported;
if (isa_base->IsSrameccSupported()) {
sramecc = node_props.Capability.ui32.SRAM_EDCSupport == 1
? core::IsaFeature::Enabled
: core::IsaFeature::Disabled;
}
rocr::core::IsaFeature xnack = rocr::core::IsaFeature::Unsupported;
if (isa_base->IsXnackSupported()) {
// TODO: This needs to be obtained form KFD once HMM implemented.
xnack = profile_ == HSA_PROFILE_FULL ? core::IsaFeature::Enabled
: core::IsaFeature::Disabled;
}
// Set instruction set architecture via node property, only on GPU device.
isa_ = (core::Isa*)core::IsaRegistry::GetIsa(
core::Isa::Version(node_props.EngineId.ui32.Major, node_props.EngineId.ui32.Minor,
node_props.EngineId.ui32.Stepping),
profile_ == HSA_PROFILE_FULL, false);//node_props.Capability.ui32.SRAM_EDCSupport == 1);
node_props.EngineId.ui32.Stepping), sramecc, xnack);
assert(isa_ != nullptr && "ISA registry inconsistency.");
// Check if the device is Kaveri, only on GPU device.
if (isa_->GetMajorVersion() == 7 && isa_->GetMinorVersion() == 0 &&
runtime/hsa-runtime/core/runtime/amd_loader_context.cpp
+19 -30
Ver Arquivo
@@ -371,32 +371,6 @@ bool RegionMemory::Freeze() {
return true;
}
hsa_status_t IsIsaEquivalent(hsa_isa_t isa, void *data) {
assert(data);
std::pair<hsa_isa_t, bool> *data_pair = (std::pair<hsa_isa_t, bool>*)data;
assert(data_pair);
assert(data_pair->first.handle != 0);
assert(data_pair->second != true);
const core::Isa *agent_isa = core::Isa::Object(isa);
assert(agent_isa);
const core::Isa *code_object_isa = core::Isa::Object(data_pair->first);
assert(code_object_isa);
// SRAM ECC enabled code may run on a system without ECC
// but a system which has ECC enabled requires ECC enabled code.
if (agent_isa->sramEccEnabled() && !code_object_isa->sramEccEnabled())
return HSA_STATUS_SUCCESS;
if (agent_isa->version() == code_object_isa->version()) {
data_pair->second = true;
return HSA_STATUS_INFO_BREAK;
}
return HSA_STATUS_SUCCESS;
}
} // namespace anonymous
namespace amd {
@@ -419,14 +393,29 @@ hsa_isa_t LoaderContext::IsaFromName(const char *name) {
bool LoaderContext::IsaSupportedByAgent(hsa_agent_t agent,
hsa_isa_t code_object_isa) {
assert(agent.handle != 0);
std::pair<hsa_isa_t, bool> comparison_data(code_object_isa, false);
auto IsIsaEquivalent = [](hsa_isa_t agent_isa_h, void *data) {
assert(data);
std::pair<hsa_isa_t, bool> data(code_object_isa, false);
hsa_status_t status = HSA::hsa_agent_iterate_isas(agent, IsIsaEquivalent, &data);
std::pair<hsa_isa_t, bool> *data_pair =
reinterpret_cast<decltype(&comparison_data)>(data);
assert(data_pair);
assert(data_pair->second != true);
const core::Isa *agent_isa = core::Isa::Object(agent_isa_h);
assert(agent_isa);
const core::Isa *code_object_isa = core::Isa::Object(data_pair->first);
assert(code_object_isa);
data_pair->second = core::Isa::IsCompatible(*code_object_isa, *agent_isa);
return data_pair->second ? HSA_STATUS_INFO_BREAK : HSA_STATUS_SUCCESS;
};
hsa_status_t status = HSA::hsa_agent_iterate_isas(agent, IsIsaEquivalent, &comparison_data);
if (status != HSA_STATUS_SUCCESS && status != HSA_STATUS_INFO_BREAK) {
return false;
}
return data.second;
return comparison_data.second;
}
void* LoaderContext::SegmentAlloc(amdgpu_hsa_elf_segment_t segment,
runtime/hsa-runtime/core/runtime/amd_topology.cpp
+19 -6
Ver Arquivo
@@ -80,13 +80,26 @@ CpuAgent* DiscoverCpu(HSAuint32 node_id, HsaNodeProperties& node_prop) {
}
GpuAgent* DiscoverGpu(HSAuint32 node_id, HsaNodeProperties& node_prop) {
GpuAgent* gpu = nullptr;
if (node_prop.NumFComputeCores == 0) {
return nullptr;
// Ignore non GPUs.
return nullptr;
}
try {
gpu = new GpuAgent(node_id, node_prop);
} catch (const hsa_exception& e) {
if(e.error_code() == HSA_STATUS_ERROR_INVALID_ISA) {
ifdebug {
if (!strIsEmpty(e.what())) debug_print("Warning: %s\n", e.what());
}
// Ignore unrecognized GPUs.
return nullptr;
} else {
// Rethrow remaining exceptions.
throw;
}
}
GpuAgent* gpu = new GpuAgent(node_id, node_prop);
core::Runtime::runtime_singleton_->RegisterAgent(gpu);
return gpu;
}
@@ -180,8 +193,8 @@ static void SurfaceGpuList(std::vector<int32_t>& gpu_list) {
// Instantiate a Gpu device. The IO links
// of this node have already been registered
const GpuAgent* gpu = DiscoverGpu(gpu_list[idx], node_prop);
assert((node_prop.NumFComputeCores != 0) && (gpu != nullptr) && "GPU device failed discovery.");
assert((node_prop.NumFComputeCores != 0) && "Improper node used for GPU device discovery.");
DiscoverGpu(gpu_list[idx], node_prop);
}
}
runtime/hsa-runtime/core/runtime/hsa.cpp
+58 -39
Ver Arquivo
@@ -1681,7 +1681,7 @@ hsa_status_t hsa_isa_compatible(
const Isa *agent_isa_object = Isa::Object(agent_isa);
IS_VALID(agent_isa_object);
*result = code_object_isa_object->IsCompatible(agent_isa_object);
*result = Isa::IsCompatible(*code_object_isa_object, *agent_isa_object);
return HSA_STATUS_SUCCESS;
CATCH;
}
@@ -1843,6 +1843,7 @@ hsa_status_t hsa_code_object_destroy(
static std::string ConvertOldTargetNameToNew(
const std::string &OldName, bool IsFinalizer, uint32_t EFlags) {
std::string NewName = "";
bool xnack_supported = false;
// FIXME #1: Should 9:0:3 be completely (loader, sc, etc.) removed?
// FIXME #2: What does PAL do with respect to boltzmann/usual fiji/tonga?
@@ -1858,60 +1859,78 @@ static std::string ConvertOldTargetNameToNew(
NewName = "amdgcn-amd-amdhsa--gfx704";
else if (OldName == "AMD:AMDGPU:8:0:0")
NewName = "amdgcn-amd-amdhsa--gfx800";
else if (OldName == "AMD:AMDGPU:8:0:1")
else if (OldName == "AMD:AMDGPU:8:0:1") {
NewName = "amdgcn-amd-amdhsa--gfx801";
xnack_supported = true;
}
else if (OldName == "AMD:AMDGPU:8:0:2")
NewName = "amdgcn-amd-amdhsa--gfx802";
else if (OldName == "AMD:AMDGPU:8:0:3")
NewName = "amdgcn-amd-amdhsa--gfx803";
else if (OldName == "AMD:AMDGPU:8:0:4")
NewName = "amdgcn-amd-amdhsa--gfx804";
else if (OldName == "AMD:AMDGPU:8:1:0")
else if (OldName == "AMD:AMDGPU:8:1:0") {
NewName = "amdgcn-amd-amdhsa--gfx810";
else if (OldName == "AMD:AMDGPU:9:0:0")
xnack_supported = true;
}
else if (OldName == "AMD:AMDGPU:9:0:0") {
NewName = "amdgcn-amd-amdhsa--gfx900";
else if (OldName == "AMD:AMDGPU:9:0:1")
xnack_supported = true;
}
else if (OldName == "AMD:AMDGPU:9:0:1") {
NewName = "amdgcn-amd-amdhsa--gfx900";
else if (OldName == "AMD:AMDGPU:9:0:2")
xnack_supported = true;
}
else if (OldName == "AMD:AMDGPU:9:0:2") {
NewName = "amdgcn-amd-amdhsa--gfx902";
else if (OldName == "AMD:AMDGPU:9:0:3")
xnack_supported = true;
}
else if (OldName == "AMD:AMDGPU:9:0:3") {
NewName = "amdgcn-amd-amdhsa--gfx902";
else if (OldName == "AMD:AMDGPU:9:0:4")
xnack_supported = true;
}
else if (OldName == "AMD:AMDGPU:9:0:4") {
NewName = "amdgcn-amd-amdhsa--gfx904";
else if (OldName == "AMD:AMDGPU:9:0:6")
xnack_supported = true;
}
else if (OldName == "AMD:AMDGPU:9:0:5") {
NewName = "amdgcn-amd-amdhsa--gfx904";
xnack_supported = true;
}
else if (OldName == "AMD:AMDGPU:9:0:6") {
NewName = "amdgcn-amd-amdhsa--gfx906";
else if (OldName == "AMD:AMDGPU:9:0:8")
NewName = "amdgcn-amd-amdhsa--gfx908";
else if (OldName == "AMD:AMDGPU:10:1:0")
NewName = "amdgcn-amd-amdhsa--gfx1010";
else if (OldName == "AMD:AMDGPU:10:1:1")
NewName = "amdgcn-amd-amdhsa--gfx1011";
else if (OldName == "AMD:AMDGPU:10:1:2")
NewName = "amdgcn-amd-amdhsa--gfx1012";
else if (OldName == "AMD:AMDGPU:10:3:0")
NewName = "amdgcn-amd-amdhsa--gfx1030";
else if (OldName == "AMD:AMDGPU:10:3:1")
NewName = "amdgcn-amd-amdhsa--gfx1031";
else
assert(false && "Unhandled target");
xnack_supported = true;
}
else if (OldName == "AMD:AMDGPU:9:0:7") {
NewName = "amdgcn-amd-amdhsa--gfx906";
xnack_supported = true;
}
else {
// Code object v2 only supports asics up to gfx906. Do NOT add handling
// of new asics into this if-else-if* block.
return "";
}
if (IsFinalizer && (EFlags & EF_AMDGPU_XNACK)) {
NewName = NewName + "+xnack";
if (IsFinalizer) {
if (EFlags & ELF::EF_AMDGPU_FEATURE_XNACK_V2)
NewName = NewName + ":xnack+";
else if (xnack_supported)
NewName = NewName + ":xnack-";
} else {
if (EFlags != 0 && (EFlags & EF_AMDGPU_XNACK_LC)) {
NewName = NewName + "+xnack";
} else {
if (OldName == "AMD:AMDGPU:8:0:1")
NewName = NewName + "+xnack";
else if (OldName == "AMD:AMDGPU:8:1:0")
NewName = NewName + "+xnack";
else if (OldName == "AMD:AMDGPU:9:0:1")
NewName = NewName + "+xnack";
else if (OldName == "AMD:AMDGPU:9:0:2")
NewName = NewName + "+xnack";
else if (OldName == "AMD:AMDGPU:9:0:3")
NewName = NewName + "+xnack";
}
if (OldName == "AMD:AMDGPU:8:0:1")
NewName = NewName + ":xnack+";
else if (OldName == "AMD:AMDGPU:8:1:0")
NewName = NewName + ":xnack+";
else if (OldName == "AMD:AMDGPU:9:0:1")
NewName = NewName + ":xnack+";
else if (OldName == "AMD:AMDGPU:9:0:3")
NewName = NewName + ":xnack+";
else if (OldName == "AMD:AMDGPU:9:0:5")
NewName = NewName + ":xnack+";
else if (OldName == "AMD:AMDGPU:9:0:7")
NewName = NewName + ":xnack+";
else if (xnack_supported)
NewName = NewName + ":xnack-";
}
return NewName;
runtime/hsa-runtime/core/runtime/isa.cpp
+106 -49
Ver Arquivo
@@ -67,17 +67,54 @@ bool Wavefront::GetInfo(
}
}
/* static */
bool Isa::IsCompatible(const Isa &code_object_isa,
const Isa &agent_isa) {
if (code_object_isa.version() != agent_isa.version())
return false;
assert(code_object_isa.IsSrameccSupported() == agent_isa.IsSrameccSupported() && agent_isa.sramecc() != IsaFeature::Any);
if ((code_object_isa.sramecc() == IsaFeature::Enabled ||
code_object_isa.sramecc() == IsaFeature::Disabled) &&
code_object_isa.sramecc() != agent_isa.sramecc())
return false;
assert(code_object_isa.IsXnackSupported() == agent_isa.IsXnackSupported() && agent_isa.xnack() != IsaFeature::Any);
if ((code_object_isa.xnack() == IsaFeature::Enabled ||
code_object_isa.xnack() == IsaFeature::Disabled) &&
code_object_isa.xnack() != agent_isa.xnack())
return false;
return true;
}
std::string Isa::GetFullName() const {
std::stringstream full_name;
full_name << GetArchitecture() << "-" << GetVendor() << "-" << GetOS() << "-"
<< GetEnvironment() << "-gfx" << GetMajorVersion()
<< GetMinorVersion() << GetStepping();
if (xnackEnabled_)
full_name << "+xnack";
switch (sramecc_) {
case IsaFeature::Disabled:
full_name << ":sramecc-";
break;
case IsaFeature::Enabled:
full_name << ":sramecc+";
break;
default:
break;
}
if (sramEcc_)
full_name << "+sram-ecc";
switch (xnack_) {
case IsaFeature::Disabled:
full_name << ":xnack-";
break;
case IsaFeature::Enabled:
full_name << ":xnack+";
break;
default:
break;
}
return full_name.str();
}
@@ -185,8 +222,8 @@ const Isa *IsaRegistry::GetIsa(const std::string &full_name) {
return isareg_iter == supported_isas_.end() ? nullptr : &isareg_iter->second;
}
const Isa *IsaRegistry::GetIsa(const Isa::Version &version, bool xnack, bool ecc) {
auto isareg_iter = supported_isas_.find(Isa(version, xnack, ecc).GetFullName());
const Isa *IsaRegistry::GetIsa(const Isa::Version &version, IsaFeature sramecc, IsaFeature xnack) {
auto isareg_iter = supported_isas_.find(Isa(version, sramecc, xnack).GetFullName());
return isareg_iter == supported_isas_.end() ? nullptr : &isareg_iter->second;
}
@@ -194,52 +231,72 @@ const IsaRegistry::IsaMap IsaRegistry::supported_isas_ =
IsaRegistry::GetSupportedIsas();
const IsaRegistry::IsaMap IsaRegistry::GetSupportedIsas() {
#define ISAREG_ENTRY_GEN(maj, min, stp, xnack, ecc) \
Isa amd_amdgpu_##maj##min##stp##xnack##ecc; \
amd_amdgpu_##maj##min##stp##xnack##ecc.version_ = Isa::Version(maj, min, stp); \
amd_amdgpu_##maj##min##stp##xnack##ecc.xnackEnabled_ = xnack; \
amd_amdgpu_##maj##min##stp##xnack##ecc.sramEcc_ = ecc; \
supported_isas.insert(std::make_pair( \
amd_amdgpu_##maj##min##stp##xnack##ecc.GetFullName(), \
amd_amdgpu_##maj##min##stp##xnack##ecc)); \
#define ISAREG_ENTRY_GEN(maj, min, stp, sramecc, xnack) \
Isa amd_amdgpu_##maj##min##stp##_SRAMECC_##sramecc##_XNACK_##xnack; \
amd_amdgpu_##maj##min##stp##_SRAMECC_##sramecc##_XNACK_##xnack.version_ = Isa::Version(maj, min, stp); \
amd_amdgpu_##maj##min##stp##_SRAMECC_##sramecc##_XNACK_##xnack.sramecc_ = sramecc; \
amd_amdgpu_##maj##min##stp##_SRAMECC_##sramecc##_XNACK_##xnack.xnack_ = xnack; \
supported_isas.insert(std::make_pair( \
amd_amdgpu_##maj##min##stp##_SRAMECC_##sramecc##_XNACK_##xnack.GetFullName(), \
amd_amdgpu_##maj##min##stp##_SRAMECC_##sramecc##_XNACK_##xnack)); \
IsaMap supported_isas;
IsaFeature unsupported = IsaFeature::Unsupported;
IsaFeature any = IsaFeature::Any;
IsaFeature disabled = IsaFeature::Disabled;
IsaFeature enabled = IsaFeature::Enabled;
ISAREG_ENTRY_GEN(7, 0, 0, false, false)
ISAREG_ENTRY_GEN(7, 0, 1, false, false)
ISAREG_ENTRY_GEN(7, 0, 2, false, false)
ISAREG_ENTRY_GEN(8, 0, 1, false, false)
ISAREG_ENTRY_GEN(8, 0, 1, true, false)
ISAREG_ENTRY_GEN(8, 0, 2, false, false)
ISAREG_ENTRY_GEN(8, 0, 2, true, false)
ISAREG_ENTRY_GEN(8, 0, 3, false, false)
ISAREG_ENTRY_GEN(8, 0, 3, true, false)
ISAREG_ENTRY_GEN(8, 1, 0, false, false)
ISAREG_ENTRY_GEN(8, 1, 0, true, false)
ISAREG_ENTRY_GEN(9, 0, 0, false, false)
ISAREG_ENTRY_GEN(9, 0, 0, true, false)
ISAREG_ENTRY_GEN(9, 0, 2, false, false)
ISAREG_ENTRY_GEN(9, 0, 2, true, false)
ISAREG_ENTRY_GEN(9, 0, 4, false, false)
ISAREG_ENTRY_GEN(9, 0, 4, true, false)
ISAREG_ENTRY_GEN(9, 0, 6, false, false)
ISAREG_ENTRY_GEN(9, 0, 6, true, false)
ISAREG_ENTRY_GEN(9, 0, 6, false, true )
ISAREG_ENTRY_GEN(9, 0, 6, true, true )
ISAREG_ENTRY_GEN(9, 0, 8, false, false)
ISAREG_ENTRY_GEN(9, 0, 8, true, false)
ISAREG_ENTRY_GEN(9, 0, 8, false, true )
ISAREG_ENTRY_GEN(9, 0, 8, true, true )
ISAREG_ENTRY_GEN(10, 1, 0, false, false)
ISAREG_ENTRY_GEN(10, 1, 0, true, false)
ISAREG_ENTRY_GEN(10, 1, 1, false, false)
ISAREG_ENTRY_GEN(10, 1, 1, true, false)
ISAREG_ENTRY_GEN(10, 1, 2, false, false)
ISAREG_ENTRY_GEN(10, 1, 2, true, false)
ISAREG_ENTRY_GEN(10, 3, 0, false, false)
ISAREG_ENTRY_GEN(10, 3, 0, true, false)
ISAREG_ENTRY_GEN(10, 3, 1, false, false)
ISAREG_ENTRY_GEN(10, 3, 1, true, false)
// Version SRAMECC XNACK
ISAREG_ENTRY_GEN(7, 0, 0, unsupported, unsupported)
ISAREG_ENTRY_GEN(7, 0, 1, unsupported, unsupported)
ISAREG_ENTRY_GEN(7, 0, 2, unsupported, unsupported)
ISAREG_ENTRY_GEN(8, 0, 1, unsupported, any)
ISAREG_ENTRY_GEN(8, 0, 1, unsupported, disabled)
ISAREG_ENTRY_GEN(8, 0, 1, unsupported, enabled)
ISAREG_ENTRY_GEN(8, 0, 2, unsupported, unsupported)
ISAREG_ENTRY_GEN(8, 0, 3, unsupported, unsupported)
ISAREG_ENTRY_GEN(8, 1, 0, unsupported, any)
ISAREG_ENTRY_GEN(8, 1, 0, unsupported, disabled)
ISAREG_ENTRY_GEN(8, 1, 0, unsupported, enabled)
ISAREG_ENTRY_GEN(9, 0, 0, unsupported, any)
ISAREG_ENTRY_GEN(9, 0, 0, unsupported, disabled)
ISAREG_ENTRY_GEN(9, 0, 0, unsupported, enabled)
ISAREG_ENTRY_GEN(9, 0, 2, unsupported, any)
ISAREG_ENTRY_GEN(9, 0, 2, unsupported, disabled)
ISAREG_ENTRY_GEN(9, 0, 2, unsupported, enabled)
ISAREG_ENTRY_GEN(9, 0, 4, unsupported, any)
ISAREG_ENTRY_GEN(9, 0, 4, unsupported, disabled)
ISAREG_ENTRY_GEN(9, 0, 4, unsupported, enabled)
ISAREG_ENTRY_GEN(9, 0, 6, any, any)
ISAREG_ENTRY_GEN(9, 0, 6, any, disabled)
ISAREG_ENTRY_GEN(9, 0, 6, any, enabled)
ISAREG_ENTRY_GEN(9, 0, 6, disabled, any)
ISAREG_ENTRY_GEN(9, 0, 6, enabled, any)
ISAREG_ENTRY_GEN(9, 0, 6, disabled, disabled)
ISAREG_ENTRY_GEN(9, 0, 6, disabled, enabled)
ISAREG_ENTRY_GEN(9, 0, 6, enabled, disabled)
ISAREG_ENTRY_GEN(9, 0, 6, enabled, enabled)
ISAREG_ENTRY_GEN(9, 0, 8, any, any)
ISAREG_ENTRY_GEN(9, 0, 8, any, disabled)
ISAREG_ENTRY_GEN(9, 0, 8, any, enabled)
ISAREG_ENTRY_GEN(9, 0, 8, disabled, any)
ISAREG_ENTRY_GEN(9, 0, 8, enabled, any)
ISAREG_ENTRY_GEN(9, 0, 8, disabled, disabled)
ISAREG_ENTRY_GEN(9, 0, 8, disabled, enabled)
ISAREG_ENTRY_GEN(9, 0, 8, enabled, disabled)
ISAREG_ENTRY_GEN(9, 0, 8, enabled, enabled)
ISAREG_ENTRY_GEN(10, 1, 0, unsupported, any)
ISAREG_ENTRY_GEN(10, 1, 0, unsupported, disabled)
ISAREG_ENTRY_GEN(10, 1, 0, unsupported, enabled)
ISAREG_ENTRY_GEN(10, 1, 1, unsupported, any)
ISAREG_ENTRY_GEN(10, 1, 1, unsupported, disabled)
ISAREG_ENTRY_GEN(10, 1, 1, unsupported, enabled)
ISAREG_ENTRY_GEN(10, 1, 2, unsupported, any)
ISAREG_ENTRY_GEN(10, 1, 2, unsupported, disabled)
ISAREG_ENTRY_GEN(10, 1, 2, unsupported, enabled)
ISAREG_ENTRY_GEN(10, 3, 0, unsupported, unsupported)
ISAREG_ENTRY_GEN(10, 3, 1, unsupported, unsupported)
#undef ISAREG_ENTRY_GEN
return supported_isas;
}
runtime/hsa-runtime/core/runtime/runtime.cpp
+3 -3
Ver Arquivo
@@ -1157,13 +1157,13 @@ bool Runtime::VMFaultHandler(hsa_signal_value_t val, void* arg) {
fault_info.fault_reason_mask |= HSA_AMD_MEMORY_FAULT_IMPRECISE;
}
if (fault.Failure.ECC == 1 && fault.Failure.ErrorType == 0) {
fault_info.fault_reason_mask |= HSA_AMD_MEMORY_FAULT_DRAM_ECC;
fault_info.fault_reason_mask |= HSA_AMD_MEMORY_FAULT_DRAMECC;
}
if (fault.Failure.ErrorType == 1) {
fault_info.fault_reason_mask |= HSA_AMD_MEMORY_FAULT_SRAM_ECC;
fault_info.fault_reason_mask |= HSA_AMD_MEMORY_FAULT_SRAMECC;
}
if (fault.Failure.ErrorType == 2) {
fault_info.fault_reason_mask |= HSA_AMD_MEMORY_FAULT_DRAM_ECC;
fault_info.fault_reason_mask |= HSA_AMD_MEMORY_FAULT_DRAMECC;
}
if (fault.Failure.ErrorType == 3) {
fault_info.fault_reason_mask |= HSA_AMD_MEMORY_FAULT_HANG;