From 3d866ee5df4f6206fddf1e3f2d0a36f6fde35f10 Mon Sep 17 00:00:00 2001 From: foreman Date: Mon, 10 Nov 2014 13:55:17 -0500 Subject: [PATCH] P4 to Git Change 1095445 by emankov@em-hsa-amd on 2014/11/10 13:48:06 ECR #333753 - hsa_foundation RT/Compiler Lib: recompilation algorithm rework 1. Recompilation algorithm rework in order to avoid superfluous recompilations. 2. Replace aclExtractSymbol/Section with aclQueryInfo for symbol/section detection. The replaced calls in RT previously performed actual extraction of the sections from the BIF with memory allocation and copying. But what is needed in fact is only to determine whether the section exists in BIF or not to make a further decision on needed recompilations. With aclQueryInfo and new added enums RT_CONTAINS_LLVMIR, RT_CONTAINS_OPTIONS, RT_CONTAINS_BRIG, RT_CONTAINS_HSAIL, RT_CONTAINS_ISA Runtime starts querying not the whole sections but the bool flag which indicates the existence of the corresponding section(s) without any memory allocations. Every compilation on RT starting from LLVMIR is affected by the change including compilation of blit kernels. 3. Fix in Compiler Lib for correct ACL_INVALID_ARG detection (for wrong/unsupported compilations). [Side Effects] performance improvement, memory consumption reduction [ToDo] Do not finalize program if ISA is already provided in BIF and options are unchanged. [Testing] pre check-in, ocltst complib, ocl conformance 2.0 compiler & api [Reviewers] German Andryeyev, Brian Sumner Affected files ... ... //depot/stg/opencl/drivers/opencl/compiler/lib/backends/common/v0_8/if_acl.cpp#56 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/hsa_foundation/hsaprogram.cpp#8 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/hsa_foundation/hsaprogram.hpp#3 edit [ROCm/clr commit: 9c4a22118e678051c24878fc352cd62d11cd5ebc] --- .../clr/rocclr/compiler/lib/backends/common/v0_8/if_acl.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/clr/rocclr/compiler/lib/backends/common/v0_8/if_acl.cpp b/projects/clr/rocclr/compiler/lib/backends/common/v0_8/if_acl.cpp index 7ba9e628a2..56247d6f02 100644 --- a/projects/clr/rocclr/compiler/lib/backends/common/v0_8/if_acl.cpp +++ b/projects/clr/rocclr/compiler/lib/backends/common/v0_8/if_acl.cpp @@ -1327,8 +1327,8 @@ if_aclCompile(aclCompiler *cl, } if (((from == ACL_TYPE_AMDIL_TEXT || from == ACL_TYPE_AMDIL_BINARY || from == ACL_TYPE_X86_TEXT || from == ACL_TYPE_X86_BINARY || - from == ACL_TYPE_HSAIL_TEXT || from == ACL_TYPE_HSAIL_BINARY) && to != ACL_TYPE_ISA) || - (from == ACL_TYPE_HSAIL_BINARY && to != ACL_TYPE_CG)) { + from == ACL_TYPE_HSAIL_TEXT) && to != ACL_TYPE_ISA) || + (from == ACL_TYPE_HSAIL_BINARY && to != ACL_TYPE_ISA && to != ACL_TYPE_CG)) { return ACL_INVALID_ARG; } uint8_t sectable[ACL_TYPE_LAST] = {0, 0, 1, 1, 1, 1, 0, 6, 0, 3, 4, 4, 4, 0, 5, 0, 1};