From 3e9e830351521fe8335b203358be88c407ba2fc1 Mon Sep 17 00:00:00 2001 From: Austin Kerbow Date: Fri, 28 Feb 2020 22:45:33 -0800 Subject: [PATCH] Update IsaRegistry for backend changes Changes in the compiler are being made to add controls for XNACK and SRAM ECC for all targets which can support these features. By default the conservatively correct settings of XNACK on and SRAM ECC on will be used. This change is to facilitate these backend updates. Change-Id: I2fd6b6bc1d32937737e7f56d8e08c70fe781c745 [ROCm/ROCR-Runtime commit: 87202d4408bca62d6f032def7da47f357740c170] --- .../runtime/hsa-runtime/core/runtime/isa.cpp | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/isa.cpp b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/isa.cpp index 2fa7d28722..5b56c84a48 100755 --- a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/isa.cpp +++ b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/isa.cpp @@ -207,20 +207,34 @@ const IsaRegistry::IsaMap IsaRegistry::GetSupportedIsas() { ISAREG_ENTRY_GEN(7, 0, 0, false, false) ISAREG_ENTRY_GEN(7, 0, 1, false, false) ISAREG_ENTRY_GEN(7, 0, 2, false, false) + ISAREG_ENTRY_GEN(8, 0, 1, false, false) ISAREG_ENTRY_GEN(8, 0, 1, true, false) ISAREG_ENTRY_GEN(8, 0, 2, false, false) + ISAREG_ENTRY_GEN(8, 0, 2, true, false) ISAREG_ENTRY_GEN(8, 0, 3, false, false) + ISAREG_ENTRY_GEN(8, 0, 3, true, false) + ISAREG_ENTRY_GEN(8, 1, 0, false, false) ISAREG_ENTRY_GEN(8, 1, 0, true, false) ISAREG_ENTRY_GEN(9, 0, 0, false, false) + ISAREG_ENTRY_GEN(9, 0, 0, true, false) + ISAREG_ENTRY_GEN(9, 0, 2, false, false) ISAREG_ENTRY_GEN(9, 0, 2, true, false) ISAREG_ENTRY_GEN(9, 0, 4, false, false) + ISAREG_ENTRY_GEN(9, 0, 4, true, false) ISAREG_ENTRY_GEN(9, 0, 6, false, false) + ISAREG_ENTRY_GEN(9, 0, 6, true, false) ISAREG_ENTRY_GEN(9, 0, 6, false, true ) - ISAREG_ENTRY_GEN(9, 0, 8, false, true ) + ISAREG_ENTRY_GEN(9, 0, 6, true, true ) ISAREG_ENTRY_GEN(9, 0, 8, false, false) + ISAREG_ENTRY_GEN(9, 0, 8, true, false) + ISAREG_ENTRY_GEN(9, 0, 8, false, true ) + ISAREG_ENTRY_GEN(9, 0, 8, true, true ) ISAREG_ENTRY_GEN(10, 1, 0, false, false) + ISAREG_ENTRY_GEN(10, 1, 0, true, false) ISAREG_ENTRY_GEN(10, 1, 1, false, false) + ISAREG_ENTRY_GEN(10, 1, 1, true, false) ISAREG_ENTRY_GEN(10, 1, 2, false, false) + ISAREG_ENTRY_GEN(10, 1, 2, true, false) return supported_isas; }