SWDEV-240804 - Remove AMD_HMM_SUPPORT define
Use dynamic logic for HMM based on it's availability Change-Id: I63751d94571d5af6eb57bef2cb0e071120bfa103
This commit is contained in:
+206
-188
@@ -1547,7 +1547,6 @@ bool Device::populateOCLDeviceConstants() {
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: 0;
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}
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#if AMD_HMM_SUPPORT
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// Generic support for HMM interfaces
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if (HSA_STATUS_SUCCESS != hsa_system_get_info(HSA_AMD_SYSTEM_INFO_SVM_SUPPORTED,
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&info_.hmmSupported_)) {
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@@ -1559,7 +1558,8 @@ bool Device::populateOCLDeviceConstants() {
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&info_.hmmCpuMemoryAccessible_)) {
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LogError("HSA_AMD_SYSTEM_INFO_SVM_ACCESSIBLE_BY_DEFAULT query failed.");
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}
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#endif // AMD_HMM_SUPPORT
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LogPrintfInfo("HMM support: %d, xnack: %d\n",
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info_.hmmSupported_, info_.hmmCpuMemoryAccessible_);
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info_.globalCUMask_ = {};
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@@ -2216,63 +2216,66 @@ bool Device::SetSvmAttributesInt(const void* dev_ptr, size_t count,
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return false;
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}
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}
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#if AMD_HMM_SUPPORT
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std::vector<hsa_amd_svm_attribute_pair_t> attr;
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if (first_alloc) {
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attr.push_back({HSA_AMD_SVM_ATTRIB_GLOBAL_FLAG, HSA_AMD_SVM_GLOBAL_FLAG_COARSE_GRAINED});
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}
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if (info().hmmSupported_) {
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std::vector<hsa_amd_svm_attribute_pair_t> attr;
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if (first_alloc) {
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attr.push_back({HSA_AMD_SVM_ATTRIB_GLOBAL_FLAG, HSA_AMD_SVM_GLOBAL_FLAG_COARSE_GRAINED});
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}
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switch (advice) {
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case amd::MemoryAdvice::SetReadMostly:
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attr.push_back({HSA_AMD_SVM_ATTRIB_READ_ONLY, true});
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break;
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case amd::MemoryAdvice::UnsetReadMostly:
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attr.push_back({HSA_AMD_SVM_ATTRIB_READ_ONLY, false});
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break;
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case amd::MemoryAdvice::SetPreferredLocation:
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if (use_cpu) {
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attr.push_back({HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION, getCpuAgent().handle});
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} else {
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attr.push_back({HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION, getBackendDevice().handle});
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}
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break;
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case amd::MemoryAdvice::UnsetPreferredLocation:
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// @note: 0 may cause a failure on old runtimes
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attr.push_back({HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION, 0});
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break;
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case amd::MemoryAdvice::SetAccessedBy:
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if (use_cpu) {
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attr.push_back({HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE, getCpuAgent().handle});
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} else {
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if (first_alloc) {
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// Provide access to all possible devices.
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//! @note: HMM should support automatic page table update with xnack enabled,
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//! but currently it doesn't and runtime explicitly enables access from all devices
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for (const auto dev : devices()) {
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attr.push_back({HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE,
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static_cast<Device*>(dev)->getBackendDevice().handle});
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}
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switch (advice) {
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case amd::MemoryAdvice::SetReadMostly:
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attr.push_back({HSA_AMD_SVM_ATTRIB_READ_ONLY, true});
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break;
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case amd::MemoryAdvice::UnsetReadMostly:
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attr.push_back({HSA_AMD_SVM_ATTRIB_READ_ONLY, false});
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break;
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case amd::MemoryAdvice::SetPreferredLocation:
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if (use_cpu) {
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attr.push_back({HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION, getCpuAgent().handle});
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} else {
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attr.push_back({HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE, getBackendDevice().handle});
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attr.push_back({HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION, getBackendDevice().handle});
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}
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}
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break;
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case amd::MemoryAdvice::UnsetPreferredLocation:
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// @note: 0 may cause a failure on old runtimes
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attr.push_back({HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION, 0});
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break;
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case amd::MemoryAdvice::SetAccessedBy:
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if (use_cpu) {
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attr.push_back({HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE, getCpuAgent().handle});
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} else {
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if (first_alloc) {
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// Provide access to all possible devices.
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//! @note: HMM should support automatic page table update with xnack enabled,
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//! but currently it doesn't and runtime explicitly enables access from all devices
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for (const auto dev : devices()) {
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attr.push_back({HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE,
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static_cast<Device*>(dev)->getBackendDevice().handle});
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}
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} else {
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attr.push_back({HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE,
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getBackendDevice().handle});
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}
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}
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break;
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case amd::MemoryAdvice::UnsetAccessedBy:
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// @note: 0 may cause a failure on old runtimes
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attr.push_back({HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE, 0});
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break;
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default:
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return false;
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break;
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case amd::MemoryAdvice::UnsetAccessedBy:
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// @note: 0 may cause a failure on old runtimes
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attr.push_back({HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE, 0});
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break;
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default:
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return false;
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break;
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}
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}
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hsa_status_t status = hsa_amd_svm_attributes_set(const_cast<void*>(dev_ptr), count,
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attr.data(), attr.size());
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if (status != HSA_STATUS_SUCCESS) {
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LogPrintfError("hsa_amd_svm_attributes_set() failed. Advice: %d", advice);
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return false;
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hsa_status_t status = hsa_amd_svm_attributes_set(const_cast<void*>(dev_ptr), count,
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attr.data(), attr.size());
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if (status != HSA_STATUS_SUCCESS) {
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LogPrintfError("hsa_amd_svm_attributes_set() failed. Advice: %d", advice);
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return false;
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}
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} else {
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LogWarning("hsa_amd_svm_attributes_set() is ignored, because no HMM support");
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}
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#endif // AMD_HMM_SUPPORT
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return true;
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}
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@@ -2296,131 +2299,139 @@ bool Device::GetSvmAttributes(void** data, size_t* data_sizes, int* attributes,
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return false;
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}
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}
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#if AMD_HMM_SUPPORT
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uint32_t accessed_by = 0;
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std::vector<hsa_amd_svm_attribute_pair_t> attr;
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if (info().hmmSupported_) {
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uint32_t accessed_by = 0;
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std::vector<hsa_amd_svm_attribute_pair_t> attr;
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for (size_t i = 0; i < num_attributes; ++i) {
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switch (attributes[i]) {
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case amd::MemRangeAttribute::ReadMostly:
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attr.push_back({HSA_AMD_SVM_ATTRIB_READ_ONLY, 0});
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for (size_t i = 0; i < num_attributes; ++i) {
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switch (attributes[i]) {
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case amd::MemRangeAttribute::ReadMostly:
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attr.push_back({HSA_AMD_SVM_ATTRIB_READ_ONLY, 0});
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break;
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case amd::MemRangeAttribute::PreferredLocation:
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attr.push_back({HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION, 0});
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break;
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case amd::MemRangeAttribute::AccessedBy:
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accessed_by = attr.size();
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// Add all GPU devices into the query
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for (const auto agent : getGpuAgents()) {
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attr.push_back({HSA_AMD_SVM_ATTRIB_ACCESS_QUERY, agent.handle});
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}
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// Add CPU devices
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for (const auto agent_info : getCpuAgents()) {
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attr.push_back({HSA_AMD_SVM_ATTRIB_ACCESS_QUERY, agent_info.agent.handle});
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}
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accessed_by = attr.size() - accessed_by;
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break;
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case amd::MemRangeAttribute::LastPrefetchLocation:
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attr.push_back({HSA_AMD_SVM_ATTRIB_PREFETCH_LOCATION, 0});
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break;
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default:
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return false;
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break;
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case amd::MemRangeAttribute::PreferredLocation:
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attr.push_back({HSA_AMD_SVM_ATTRIB_PREFERRED_LOCATION, 0});
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break;
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case amd::MemRangeAttribute::AccessedBy:
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accessed_by = attr.size();
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// Add all GPU devices into the query
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for (const auto agent : getGpuAgents()) {
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attr.push_back({HSA_AMD_SVM_ATTRIB_ACCESS_QUERY, agent.handle});
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}
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// Add CPU devices
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for (const auto agent_info : getCpuAgents()) {
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attr.push_back({HSA_AMD_SVM_ATTRIB_ACCESS_QUERY, agent_info.agent.handle});
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}
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accessed_by = attr.size() - accessed_by;
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break;
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case amd::MemRangeAttribute::LastPrefetchLocation:
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attr.push_back({HSA_AMD_SVM_ATTRIB_PREFETCH_LOCATION, 0});
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break;
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default:
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return false;
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break;
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}
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}
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}
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hsa_status_t status = hsa_amd_svm_attributes_get(const_cast<void*>(dev_ptr), count,
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attr.data(), attr.size());
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if (status != HSA_STATUS_SUCCESS) {
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LogError("hsa_amd_svm_attributes_get() failed");
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hsa_status_t status = hsa_amd_svm_attributes_get(const_cast<void*>(dev_ptr), count,
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attr.data(), attr.size());
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if (status != HSA_STATUS_SUCCESS) {
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LogError("hsa_amd_svm_attributes_get() failed");
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return false;
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}
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uint32_t idx = 0;
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uint32_t rocr_attr = 0;
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for (size_t i = 0; i < num_attributes; ++i) {
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const auto& it = attr[rocr_attr];
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switch (attributes[i]) {
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case amd::MemRangeAttribute::ReadMostly:
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if (data_sizes[idx] != sizeof(uint32_t)) {
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return false;
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}
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// Cast ROCr value into the hip format
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*reinterpret_cast<uint32_t*>(data[idx]) =
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(static_cast<uint32_t>(it.value) > 0) ? true : false;
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break;
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// The logic should be identical for the both queries
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case amd::MemRangeAttribute::PreferredLocation:
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case amd::MemRangeAttribute::LastPrefetchLocation:
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if (data_sizes[idx] != sizeof(uint32_t)) {
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return false;
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}
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*reinterpret_cast<int32_t*>(data[idx]) = static_cast<int32_t>(amd::InvalidDeviceId);
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// Find device agent returned by ROCr
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for (auto& device : devices()) {
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if (static_cast<Device*>(device)->getBackendDevice().handle == it.value) {
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*reinterpret_cast<uint32_t*>(data[idx]) = static_cast<uint32_t>(device->index());
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}
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}
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// Find CPU agent returned by ROCr
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for (auto& agent_info : getCpuAgents()) {
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if (agent_info.agent.handle == it.value) {
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*reinterpret_cast<int32_t*>(data[idx]) = static_cast<int32_t>(amd::CpuDeviceId);
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}
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}
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break;
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case amd::MemRangeAttribute::AccessedBy: {
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uint32_t entry = 0;
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uint32_t device_count = data_sizes[idx] / 4;
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// Make sure it's multiple of 4
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if (data_sizes[idx] % 4 != 0) {
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return false;
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}
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for (uint32_t att = 0; att < accessed_by; ++att) {
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const auto& it = attr[rocr_attr + att];
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if (entry >= device_count) {
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// The size of the array is less than the amount of available devices
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break;
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}
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switch (it.attribute) {
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case HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE:
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case HSA_AMD_SVM_ATTRIB_AGENT_NO_ACCESS:
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break;
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case HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE:
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reinterpret_cast<int32_t*>(data[idx])[entry] =
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static_cast<int32_t>(amd::InvalidDeviceId);
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// Find device agent returned by ROCr
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for (auto& device : devices()) {
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if (static_cast<Device*>(device)->getBackendDevice().handle == it.value) {
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reinterpret_cast<uint32_t*>(data[idx])[entry] =
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static_cast<uint32_t>(device->index());
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}
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}
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// Find CPU agent returned by ROCr
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for (auto& agent_info : getCpuAgents()) {
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if (agent_info.agent.handle == it.value) {
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reinterpret_cast<int32_t*>(data[idx])[entry] =
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static_cast<int32_t>(amd::CpuDeviceId);
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}
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}
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++entry;
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break;
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default:
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LogWarning("Unexpected result from HSA_AMD_SVM_ATTRIB_ACCESS_QUERY");
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break;
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}
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}
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rocr_attr += accessed_by;
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for (uint32_t idx = entry; idx < device_count; ++idx) {
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reinterpret_cast<int32_t*>(data[idx])[idx] =
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static_cast<int32_t>(amd::InvalidDeviceId);
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}
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break;
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}
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default:
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return false;
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break;
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}
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// Find the next location in the query
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++idx;
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}
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} else {
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LogError("GetSvmAttributes() failed, because no HMM support");
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return false;
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}
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uint32_t idx = 0;
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uint32_t rocr_attr = 0;
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for (size_t i = 0; i < num_attributes; ++i) {
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const auto& it = attr[rocr_attr];
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switch (attributes[i]) {
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case amd::MemRangeAttribute::ReadMostly:
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if (data_sizes[idx] != sizeof(uint32_t)) {
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return false;
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}
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// Cast ROCr value into the hip format
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*reinterpret_cast<uint32_t*>(data[idx]) =
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(static_cast<uint32_t>(it.value) > 0) ? true : false;
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break;
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// The logic should be identical for the both queries
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case amd::MemRangeAttribute::PreferredLocation:
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case amd::MemRangeAttribute::LastPrefetchLocation:
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if (data_sizes[idx] != sizeof(uint32_t)) {
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return false;
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}
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*reinterpret_cast<int32_t*>(data[idx]) = static_cast<int32_t>(amd::InvalidDeviceId);
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// Find device agent returned by ROCr
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for (auto& device : devices()) {
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if (static_cast<Device*>(device)->getBackendDevice().handle == it.value) {
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*reinterpret_cast<uint32_t*>(data[idx]) = static_cast<uint32_t>(device->index());
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}
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}
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// Find CPU agent returned by ROCr
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for (auto& agent_info : getCpuAgents()) {
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if (agent_info.agent.handle == it.value) {
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*reinterpret_cast<int32_t*>(data[idx]) = static_cast<int32_t>(amd::CpuDeviceId);
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}
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}
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break;
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case amd::MemRangeAttribute::AccessedBy: {
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uint32_t entry = 0;
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uint32_t device_count = data_sizes[idx] / 4;
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// Make sure it's multiple of 4
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if (data_sizes[idx] % 4 != 0) {
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return false;
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}
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for (uint32_t att = 0; att < accessed_by; ++att) {
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const auto& it = attr[rocr_attr + att];
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if (entry >= device_count) {
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// The size of the array is less than the amount of available devices
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break;
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}
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switch (it.attribute) {
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case HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE:
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case HSA_AMD_SVM_ATTRIB_AGENT_NO_ACCESS:
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break;
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case HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE:
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reinterpret_cast<int32_t*>(data[idx])[entry] = static_cast<int32_t>(amd::InvalidDeviceId);
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// Find device agent returned by ROCr
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for (auto& device : devices()) {
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if (static_cast<Device*>(device)->getBackendDevice().handle == it.value) {
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reinterpret_cast<uint32_t*>(data[idx])[entry] = static_cast<uint32_t>(device->index());
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}
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}
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// Find CPU agent returned by ROCr
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for (auto& agent_info : getCpuAgents()) {
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if (agent_info.agent.handle == it.value) {
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reinterpret_cast<int32_t*>(data[idx])[entry] = static_cast<int32_t>(amd::CpuDeviceId);
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}
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}
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++entry;
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break;
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default:
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LogWarning("Unexpected result from HSA_AMD_SVM_ATTRIB_ACCESS_QUERY");
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break;
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}
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}
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rocr_attr += accessed_by;
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for (uint32_t idx = entry; idx < device_count; ++idx) {
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reinterpret_cast<int32_t*>(data[idx])[idx] = static_cast<int32_t>(amd::InvalidDeviceId);
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}
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break;
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}
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default:
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return false;
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break;
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}
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// Find the next location in the query
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++idx;
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}
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#endif // AMD_HMM_SUPPORT
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return true;
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}
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@@ -2428,35 +2439,42 @@ bool Device::GetSvmAttributes(void** data, size_t* data_sizes, int* attributes,
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bool Device::SvmAllocInit(void* memory, size_t size) const {
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amd::MemoryAdvice advice = amd::MemoryAdvice::SetAccessedBy;
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constexpr bool kFirstAlloc = true;
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SetSvmAttributesInt(memory, size, advice, kFirstAlloc);
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if (!SetSvmAttributesInt(memory, size, advice, kFirstAlloc)) {
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return false;
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}
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if (settings().hmmFlags_ & Settings::Hmm::EnableSystemMemory) {
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advice = amd::MemoryAdvice::UnsetPreferredLocation;
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SetSvmAttributesInt(memory, size, advice);
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if (!SetSvmAttributesInt(memory, size, advice)) {
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return false;
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}
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}
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if ((settings().hmmFlags_ & Settings::Hmm::EnableMallocPrefetch) == 0) {
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return true;
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}
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||||
#if AMD_HMM_SUPPORT
|
||||
// Initialize signal for the barrier
|
||||
hsa_signal_store_relaxed(prefetch_signal_, kInitSignalValueOne);
|
||||
if (info().hmmSupported_) {
|
||||
// Initialize signal for the barrier
|
||||
hsa_signal_store_relaxed(prefetch_signal_, kInitSignalValueOne);
|
||||
|
||||
// Initiate a prefetch command which should force memory update in HMM
|
||||
hsa_status_t status = hsa_amd_svm_prefetch_async(memory, size, getBackendDevice(),
|
||||
0, nullptr, prefetch_signal_);
|
||||
if (status != HSA_STATUS_SUCCESS) {
|
||||
LogError("hsa_amd_svm_attributes_get() failed");
|
||||
return false;
|
||||
// Initiate a prefetch command which should force memory update in HMM
|
||||
hsa_status_t status = hsa_amd_svm_prefetch_async(memory, size, getBackendDevice(),
|
||||
0, nullptr, prefetch_signal_);
|
||||
if (status != HSA_STATUS_SUCCESS) {
|
||||
LogError("hsa_amd_svm_prefetch_async() failed");
|
||||
return false;
|
||||
}
|
||||
|
||||
// Wait for the prefetch
|
||||
if (!WaitForSignal(prefetch_signal_)) {
|
||||
LogError("Barrier packet submission failed");
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
LogWarning("Early prefetch failed, because no HMM support");
|
||||
}
|
||||
|
||||
// Wait for the prefetch
|
||||
if (!WaitForSignal(prefetch_signal_)) {
|
||||
LogError("Barrier packet submission failed");
|
||||
return false;
|
||||
}
|
||||
#endif // AMD_HMM_SUPPORT
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user