Compiler warnings fix 2 (#1801)
* Changes to device code * Changes to src/misc * Changes to graph * src/include changes * src/transport changes * changes in init, enqueue, proxy * Changes to CMakeLists.txt * Additional changes to device code * Additional changes to net.cc * adding 'compiler warning' tag to ease upstream merge' * typo correction * Addessing comments * Additional changes for new commits
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@@ -119,14 +119,14 @@ bool isRankHere(const char* s, int start, int end, int rank) {
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ncclResult_t ncclTreeBasePostset(struct ncclComm* comm,
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struct ncclTopoGraph* treeGraph) {
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int x=0, y=0;
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int x=0;
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for (int i=0; treeGraph->treeBase[i][0]!=0; i++)
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{
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x=i+1;
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}
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if( treeGraph->treeBase[0][0] == 0) return ncclSuccess;
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int nChannels = comm->nChannels;
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int localRanks = comm->topo->nodes[GPU].count;
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//int localRanks = comm->topo->nodes[GPU].count; // unused variable - compiler warning
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//new tree
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for (int c=0; c<nChannels; c++) { // in here
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int buff = c%x;
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+6
-4
@@ -286,14 +286,17 @@ ncclResult_t ncclTopoCheckP2p(struct ncclComm* comm, struct ncclTopoSystem* syst
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// GPU not found, we can't use p2p.
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return ncclSuccess;
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}
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#if !defined(__HIP_PLATFORM_AMD__) && !defined(__HIPCC__)
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int intermediateIndex = -1;
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#endif
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// Set intermediate GPU rank, if routing through an intermediate GPU.
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struct ncclTopoLinkList* path = gpu1->paths[GPU]+g2;
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if (path->count == 2) {
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struct ncclTopoNode* intermediateNode = path->list[0]->remNode;
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if (intermediateNode->type == GPU) {
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#if !defined(__HIP_PLATFORM_AMD__) && !defined(__HIPCC__)
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intermediateIndex = intermediateNode - system->nodes[GPU].nodes;
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#endif
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if (intermediateRank) *intermediateRank = intermediateNode->gpu.rank;
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}
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}
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@@ -324,8 +327,7 @@ compare:
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// Compute the PCI distance and compare with the p2pLevel.
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if (path->type <= p2pLevel) *p2p = 1;
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#if defined(__HIP_PLATFORM_AMD__) || defined(__HIPCC__)
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#else
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#if !defined(__HIP_PLATFORM_AMD__) && !defined(__HIPCC__)
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if (*p2p == 1) {
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// NCCL_IGNORE_DISABLED_P2P=2 is used by unit tests that don't want to
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// validate against NVML at all since they are pretending to be on other hw.
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@@ -515,10 +517,10 @@ ncclResult_t ncclTopoNeedFlush(struct ncclComm* comm, int64_t netId, int netDev,
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int g;
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struct ncclTopoSystem* system = comm->topo;
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NCCLCHECK(ncclTopoRankToIndex(system, rank, &g));
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struct ncclTopoNode* gpu = system->nodes[GPU].nodes+g;
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#if defined(__HIP_PLATFORM_AMD__) || defined(__HIPCC__)
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*flush = 1;
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#else
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struct ncclTopoNode* gpu = system->nodes[GPU].nodes+g; // unused variable - compiler warning
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// Flush is required on Ampere and earlier
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if (gpu->gpu.cudaCompCap >= 90) *flush = 0;
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// On C2C platforms, data could go through a PCI switch while completions and
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@@ -1338,7 +1338,6 @@ end:
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*/
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ncclResult_t parseGraphLight(const char* str, struct ncclTopoSystem* system, struct ncclTopoGraph* graph, int* gpu_map) {
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int gpus[NCCL_TOPO_MAX_NODES]; //transcribe/change according to gpu_map
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int nChannels = 0;
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int gpu = 0;
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int offset = 0;
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int start_offset = offset;
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@@ -1348,7 +1347,7 @@ ncclResult_t parseGraphLight(const char* str, struct ncclTopoSystem* system, str
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}
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int status = 0; // 0 : between numbers, 1 : inside number
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int ngpus = system->nodes[GPU].count;
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int x=0, y=0;
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int x=0;
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do {
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int digit = str[offset] - '0';
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if (digit >= 0 && digit <= 9) {
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@@ -1855,7 +1854,6 @@ ncclResult_t parseA2a8P(struct ncclTopoSystem* system, struct ncclTopoGraph* gra
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bool isAlltoall = checkAlltoallWidth(&romeTopo);
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if (!isAlltoall) return ncclSuccess;
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int gcnt = 0;
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int *g8, n[NCCL_TOPO_MAX_NODES];
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int *all_gpu_permutations = (int *)malloc(TOTAL_PERMUTE_COUNT*NUMA_CPUS*NUMA_GPUS*sizeof(int));
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struct timeval tvs, tve;
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@@ -1878,7 +1876,6 @@ ncclResult_t parseA2a8P(struct ncclTopoSystem* system, struct ncclTopoGraph* gra
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}
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if (ngpusPerNuma == 0) continue;
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if (ngpusPerNuma != NUMA_GPUS) break;
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gcnt++;
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// init GPU mapping
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for (int k = 0; k < ngpus; k++) {
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if (romeTopo.gpuNuma[k] != j) continue;
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@@ -1927,7 +1924,6 @@ ncclResult_t parseA2a8P(struct ncclTopoSystem* system, struct ncclTopoGraph* gra
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if (p < TOTAL_PERMUTE_COUNT) break;
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}
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gettimeofday(&tve, NULL);
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float t = (tve.tv_sec - tvs.tv_sec)*1E3 + (tve.tv_usec - tvs.tv_usec)/1E3;
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if (i >= sizeof(romeTopoModels)/sizeof(romeTopoModels[0])) {
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//printf("No solution in %.2fms\n", t);
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return ncclSuccess;
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@@ -2035,7 +2031,6 @@ ncclResult_t parseRome4P2H(struct ncclTopoSystem* system, struct ncclTopoGraph*
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int i;
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int ngpus = system->nodes[GPU].count;
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int ncpus = system->nodes[CPU].count;
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int nnets = system->nodes[NET].count;
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// Only support ring and tree graphs
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@@ -2129,7 +2124,6 @@ ncclResult_t parseRome4P2H(struct ncclTopoSystem* system, struct ncclTopoGraph*
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}
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}
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gettimeofday(&tve, NULL);
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float t = (tve.tv_sec - tvs.tv_sec)*1E3 + (tve.tv_usec - tvs.tv_usec)/1E3;
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if (i >= sizeof(romeTopoModels)/sizeof(romeTopoModels[0])) {
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//printf("No solution in %.2fms (%d iter)\n", t, time);
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return ncclSuccess;
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@@ -2241,7 +2235,6 @@ ncclResult_t parse1H16P(struct ncclTopoSystem* system, struct ncclTopoGraph* gra
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// only match for system with 16 GPUs
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if (ngpus != 16 || ncpus != NUMA_CPUS) return ncclSuccess;
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int gcnt = 0;
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int *g16, n[NCCL_TOPO_MAX_NODES], rdm[NUMA_GPUS*NUMA_CPUS];
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int *all_gpu_permutations = (int *)malloc(TOTAL_PERMUTE_COUNT*NUMA_CPUS*NUMA_GPUS*sizeof(int));
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struct timeval tvs, tve;
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@@ -2262,7 +2255,6 @@ ncclResult_t parse1H16P(struct ncclTopoSystem* system, struct ncclTopoGraph* gra
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}
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if (ngpusPerNuma == 0) continue;
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if (ngpusPerNuma != NUMA_GPUS) break;
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gcnt++;
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// init GPU mapping
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for (int k = 0; k < ngpus; k++) {
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if (romeTopo.gpuNuma[k] != j) continue;
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@@ -2317,7 +2309,6 @@ ncclResult_t parse1H16P(struct ncclTopoSystem* system, struct ncclTopoGraph* gra
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if (p < TOTAL_PERMUTE_COUNT) break;
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}
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gettimeofday(&tve, NULL);
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float t = (tve.tv_sec - tvs.tv_sec)*1E3 + (tve.tv_usec - tvs.tv_usec)/1E3;
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if (i >= sizeof(romeTopoModels)/sizeof(romeTopoModels[0])) {
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//printf("No solution in %.2fms\n", t);
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return ncclSuccess;
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+11
-6
@@ -168,7 +168,7 @@ static struct tuningModel tuning_model_0 {
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{ 1.0, 0.8, 0.2, 1.0, 1.0, 0.3, 1.0, 0.1, 0.1, 0.2, 0.2, 0.1, 0.5, 1.0, 0.8, 0.8, 1.0, 0.9, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, },
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},
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.llProtoRanges = {RCCL_LL_LIMITS_UNDEFINED},
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.llProtoRanges = {{{RCCL_LL_LIMITS_UNDEFINED}}},
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};
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static struct tuningModel tuning_model_1 {
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@@ -200,7 +200,7 @@ static struct tuningModel tuning_model_1 {
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{ 0.3, 1.0, 0.3, 0.1, 0.1, 0.1, 0.3, 0.7, 1.0, 0.2, 0.1, 0.1, 0.1, 0.1, 0.1, 0.1, 0.1, 0.1, 0.1, 0.2, 0.3, 0.5, 0.9, 1.0, 1.0, 1.0, 1.0, },
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},
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.llProtoRanges = {RCCL_LL_LIMITS_UNDEFINED},
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.llProtoRanges = {{{RCCL_LL_LIMITS_UNDEFINED}}},
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};
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static struct tuningModel tuning_model_2 {
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@@ -232,7 +232,7 @@ static struct tuningModel tuning_model_2 {
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{ 0.1, 0.1, 0.1, 0.1, 0.1, 0.1, 0.1, 0.1, 1.0, 0.2, 0.2, 0.1, 0.1, 0.1, 0.1, 0.1, 0.2, 0.4, 0.5, 0.6, 0.9, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, },
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},
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.llProtoRanges = {RCCL_LL_LIMITS_UNDEFINED},
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.llProtoRanges = {{{RCCL_LL_LIMITS_UNDEFINED}}},
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};
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static struct tuningModel tuning_model_3 {
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@@ -264,7 +264,7 @@ static struct tuningModel tuning_model_3 {
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{ 0.1, 0.1, 0.1, 0.1, 0.1, 0.1, 0.1, 0.5, 1.0, 0.1, 0.3, 0.1, 0.1, 0.1, 0.2, 0.2, 0.2, 0.3, 0.4, 0.7, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, },
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},
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.llProtoRanges = {RCCL_LL_LIMITS_UNDEFINED},
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.llProtoRanges = {{{RCCL_LL_LIMITS_UNDEFINED}}},
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};
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static struct tuningModel tuning_model_4 {
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@@ -296,7 +296,7 @@ static struct tuningModel tuning_model_4 {
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{ 0.1, 0.1, 0.1, 0.1, 0.1, 0.1, 0.1, 0.1, 0.1, 1.0, 1.0, 0.8, 0.5, 0.1, 0.7, 0.2, 0.4, 0.4, 0.6, 0.7, 0.9, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, },
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},
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.llProtoRanges = {RCCL_LL_LIMITS_UNDEFINED},
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.llProtoRanges = {{{RCCL_LL_LIMITS_UNDEFINED}}},
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};
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static struct tuningModel tuning_model_5 {
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@@ -394,6 +394,7 @@ static struct tuningModel rcclTuningModel[] = {
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#define HOPPER_COMPCAP_IDX 2
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#define BLACKWELL_COMPCAP_IDX 3
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#if !defined(__HIP_PLATFORM_AMD__) && !defined(__HIPCC__)
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// LL128 max BW per channel
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static const double llMaxBws[][3] = {
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/* Volta-N1/Intel-N2/Intel-N4) */ {39.0, 39.0, 20.4},
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@@ -420,6 +421,7 @@ static const double perChMaxTreeBws[][3] = {
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/* Hopper (N1/N2/N4) */ {38.7, 41.4, 36.0},
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/* Blackwell (N1/N2/N4) */ {2*38.7, 2*41.4, 2*36.0},
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};
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#endif
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NCCL_PARAM(PatEnable, "PAT_ENABLE", 0);
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static int ncclPatEnable(struct ncclComm* comm) {
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@@ -470,7 +472,7 @@ ncclResult_t ncclTopoTuneModel(struct ncclComm* comm, int minCompCap, int maxCom
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int nNodes = comm->nNodes;
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int nRanks = comm->nRanks;
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if (nRanks <= 1) return ncclSuccess;
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#if !defined(__HIP_PLATFORM_AMD__) && !defined(__HIPCC__)
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int compCapIndex = minCompCap >= 100 ? BLACKWELL_COMPCAP_IDX : (minCompCap >= 90 ? HOPPER_COMPCAP_IDX : minCompCap >= 80 ? AMPERE_COMPCAP_IDX : VOLTA_COMPCAP_IDX);
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int index2 = nNodes <= 2 ? nNodes-1 : 2;
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// LL: for single node, we look at GPU type; for multi-node, we look at CPU type
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@@ -480,6 +482,7 @@ ncclResult_t ncclTopoTuneModel(struct ncclComm* comm, int minCompCap, int maxCom
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double perChMaxTreeBw = perChMaxTreeBws[compCapIndex][index2];
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double perChMaxRingLL128Bw = perChMaxRingLL128Bws[compCapIndex][index2];
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double perChMaxTreeLL128Bw = perChMaxTreeLL128Bws[compCapIndex][index2];
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#endif
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// De-penalize Tree/Simple latency on Power systems to favor Tree than Ring
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//if (comm->cpuArch == NCCL_TOPO_CPU_ARCH_POWER) hwLat[NCCL_HW_PCI][NCCL_ALGO_TREE][NCCL_PROTO_SIMPLE] = hwLat[NCCL_HW_PCI][NCCL_ALGO_RING][NCCL_PROTO_SIMPLE];
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float ppn = (float)nRanks / nNodes;
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@@ -805,11 +808,13 @@ ncclResult_t ncclTopoTuneModel(struct ncclComm* comm, int minCompCap, int maxCom
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// Trees are not perfectly sticking to the model for medium sizes. Applying a static correction
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// factor is not ideal but works quite well. Powers of two, 64 B to 256MB.
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#if !defined(__HIP_PLATFORM_AMD__) && !defined(__HIPCC__)
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static float treeCorrectionFactor[NCCL_NUM_PROTOCOLS][23] = {
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{ 1.0, 1.0, 1.0, 1.0, .9, .8, .7, .7, .7, .7, .6, .5, .4, .4, .5, .6, .7, .8, .9, 1.0, 1.0, 1.0, 1.0 },
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{ 1.0, 1.0, 1.0, 1.0, 1.0, .9, .8, .8, .8, .7, .6, .6, .6, .6, .6, .6, .8, .9, .9, .9, .9, 1.0, 1.0 },
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{ .9, .9, .9, .9, .9, .9, .9, .8, .7, .6, .6, .5, .5, .5, .5, .6, .7, .8, .7, .7, .8, .9, .9 }
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};
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#endif
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ncclResult_t ncclTopoGetAlgoTime(struct ncclComm* comm, int coll, int algorithm, int protocol, size_t nBytes, int numPipeOps, float* time) {
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float bw = comm->bandwidths[coll][algorithm][protocol];
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