AI/rocm-systems
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Revert "Implement memory fault analysis through context save area"

Browse Source 
This reverts commit 498f3a7188.

Change-Id: Ibf11b764b383b9be291f3009a30550e1a1e2d115


[ROCm/ROCR-Runtime commit: 5b4df54b10]
This commit is contained in:
Kenny Ho
2017-06-14 14:14:38 -04:00
parent 231d7e8608
commit 415027b89f
16 changed files with 89 additions and 663 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/rocr-runtime/runtime/hsa-runtime/core/inc/agent.h
-6
View File
@@ -218,12 +218,6 @@ class Agent : public Checked<0xF6BC25EB17E6F917> {
uint32_t group_segment_size,
Queue** queue) = 0;
virtual hsa_status_t HostQueueCreate(hsa_region_t region, uint32_t ring_size,
hsa_queue_type32_t type, uint32_t features,
hsa_signal_t doorbell_signal, Queue** queue) = 0;
virtual hsa_status_t QueueDestroy(Queue* queue) = 0;
// @brief Query the value of an attribute.
//
// @param [in] attribute Attribute to query.
projects/rocr-runtime/runtime/hsa-runtime/core/inc/amd_aql_queue.h
+1 -4
View File
@@ -44,13 +44,12 @@
#define HSA_RUNTIME_CORE_INC_AMD_HW_AQL_COMMAND_PROCESSOR_H_
#include "core/inc/runtime.h"
#include "core/inc/amd_gpu_agent.h"
#include "core/inc/signal.h"
#include "core/inc/queue.h"
#include "core/inc/amd_gpu_agent.h"
#include "core/util/locks.h"
namespace amd {
/// @brief Encapsulates HW Aql Command Processor functionality. It
/// provide the interface for things such as Doorbell register, read,
/// write pointers and a buffer.
@@ -185,8 +184,6 @@ class AqlQueue : public core::Queue, public core::Signal {
// @brief Submits a block of PM4 and waits until it has been executed.
void ExecutePM4(uint32_t* cmd_data, size_t cmd_size_b) override;
WaveStates GetWaveStates();
/// @brief This operation is illegal
hsa_signal_value_t LoadRelaxed() override {
assert(false);
projects/rocr-runtime/runtime/hsa-runtime/core/inc/amd_cpu_agent.h
-10
View File
@@ -45,8 +45,6 @@
#ifndef HSA_RUNTIME_CORE_INC_AMD_CPU_AGENT_H_
#define HSA_RUNTIME_CORE_INC_AMD_CPU_AGENT_H_
#include <list>
#include <memory>
#include <vector>
#include "hsakmt.h"
@@ -105,12 +103,6 @@ class CpuAgent : public core::Agent {
uint32_t group_segment_size,
core::Queue** queue) override;
hsa_status_t HostQueueCreate(hsa_region_t region, uint32_t ring_size, hsa_queue_type32_t type,
uint32_t features, hsa_signal_t doorbell_signal,
core::Queue** queue) override;
hsa_status_t QueueDestroy(core::Queue* queue) override;
// @brief Returns number of data caches.
__forceinline size_t num_cache() const { return cache_props_.size(); }
@@ -162,8 +154,6 @@ class CpuAgent : public core::Agent {
// @brief Array of regions owned by this agent.
std::vector<const core::MemoryRegion*> regions_;
std::list<std::unique_ptr<core::Queue>> queues_;
DISALLOW_COPY_AND_ASSIGN(CpuAgent);
};
projects/rocr-runtime/runtime/hsa-runtime/core/inc/amd_debugger.h
-57
View File
@@ -1,57 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
//
// The University of Illinois/NCSA
// Open Source License (NCSA)
//
// Copyright (c) 2014-2015, Advanced Micro Devices, Inc. All rights reserved.
//
// Developed by:
//
// AMD Research and AMD HSA Software Development
//
// Advanced Micro Devices, Inc.
//
// www.amd.com
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to
// deal with the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimers.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimers in
// the documentation and/or other materials provided with the distribution.
// - Neither the names of Advanced Micro Devices, Inc,
// nor the names of its contributors may be used to endorse or promote
// products derived from this Software without specific prior written
// permission.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS WITH THE SOFTWARE.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef HSA_RUNTIME_CORE_INC_AMD_DEBUGGER_H_
#define HSA_RUNTIME_CORE_INC_AMD_DEBUGGER_H_
#include "core/inc/amd_gpu_agent.h"
#include "hsakmt.h"
namespace amd {
class Debugger {
public:
static void HandleFault(const HsaMemoryAccessFault& fault, GpuAgentInt* agent);
};
}
#endif
projects/rocr-runtime/runtime/hsa-runtime/core/inc/amd_gpu_agent.h
+7 -55
View File
@@ -45,8 +45,6 @@
#ifndef HSA_RUNTIME_CORE_INC_AMD_GPU_AGENT_H_
#define HSA_RUNTIME_CORE_INC_AMD_GPU_AGENT_H_
#include <list>
#include <memory>
#include <vector>
#include "hsakmt.h"
@@ -61,42 +59,6 @@
namespace amd {
class MemoryRegion;
class AqlQueue;
struct WaveState {
// Number of SGPRs allocated per wavefront.
uint32_t num_sgprs;
// Array of packed SGPR data.
uint32_t* sgprs;
// Number of VGPRs allocated per wavefront.
uint32_t num_vgprs;
// Number of lanes in each VGPR.
uint32_t num_vgpr_lanes;
// Array of packed VGPR data.
// VGPR value = vgprs[(vgpr_idx * num_vgpr_lanes) + lane_idx]
uint32_t* vgprs;
// Data for miscellaneous registers.
struct {
uint64_t pc;
uint64_t exec;
uint32_t status;
uint32_t trapsts;
uint32_t m0;
} regs;
// LDS allocation size for the work group, in 32-bit words.
uint32_t lds_size_dw;
// Packed LDS data for the work group.
uint32_t* lds;
};
typedef std::vector<WaveState> WaveStates;
// @brief Contains scratch memory information.
struct ScratchInfo {
@@ -113,14 +75,6 @@ class GpuAgentInt : public core::Agent {
GpuAgentInt(uint32_t node_id)
: core::Agent(node_id, core::Agent::DeviceType::kAmdGpuDevice) {}
// @brief GpuAgent does not support HostQueueCreation.
hsa_status_t HostQueueCreate(hsa_region_t region, uint32_t ring_size, hsa_queue_type32_t type,
uint32_t features, hsa_signal_t doorbell_signal,
core::Queue** queue) override {
assert(false && "GpuAgent::HostQueueCreate not implemented");
return HSA_STATUS_ERROR_INVALID_AGENT;
}
// @brief Initialize DMA queue.
//
// @retval HSA_STATUS_SUCCESS DMA queue initialization is successful.
@@ -186,8 +140,6 @@ class GpuAgentInt : public core::Agent {
// @brief Invalidate caches on the agent which may hold code object data.
virtual void InvalidateCodeCaches() = 0;
virtual WaveStates GetWaveStates() = 0;
// @brief Sets the coherency type of this agent.
//
// @param [in] type New coherency type.
@@ -300,8 +252,6 @@ class GpuAgent : public GpuAgentInt {
uint32_t group_segment_size,
core::Queue** queue) override;
hsa_status_t QueueDestroy(core::Queue* queue) override;
// @brief Override from amd::GpuAgentInt.
void AcquireQueueScratch(ScratchInfo& scratch) override;
@@ -318,8 +268,6 @@ class GpuAgent : public GpuAgentInt {
// @brief Override from amd::GpuAgentInt.
void InvalidateCodeCaches() override;
WaveStates GetWaveStates() override;
// @brief Override from amd::GpuAgentInt.
bool current_coherency_type(hsa_amd_coherency_type_t type) override;
@@ -430,10 +378,14 @@ class GpuAgent : public GpuAgentInt {
core::Blit* blits_[BlitCount];
std::list<std::unique_ptr<AqlQueue>> queues_;
// @brief AQL queues for cache management and blit compute usage.
enum QueueEnum {
QueueUtility, // Cache management and device to {host,device} blit compute
QueueBlitOnly, // Host to device blit
QueueCount
};
core::Queue* queue_util_;
core::Queue* queue_blit_;
core::Queue* queues_[QueueCount];
// @brief Mutex to protect the update to coherency type.
KernelMutex coherency_lock_;
projects/rocr-runtime/runtime/hsa-runtime/core/inc/host_queue.h
+1 -1
View File
@@ -51,7 +51,7 @@
namespace core {
class HostQueue : public Queue {
public:
HostQueue(Agent& agent, hsa_region_t region, uint32_t ring_size, hsa_queue_type32_t type,
HostQueue(hsa_region_t region, uint32_t ring_size, hsa_queue_type32_t type,
uint32_t features, hsa_signal_t doorbell_signal);
~HostQueue();
projects/rocr-runtime/runtime/hsa-runtime/core/inc/queue.h
+1 -8
View File
@@ -45,7 +45,6 @@
#ifndef HSA_RUNTME_CORE_INC_COMMAND_QUEUE_H_
#define HSA_RUNTME_CORE_INC_COMMAND_QUEUE_H_
#include <sstream>
#include <vector>
#include "core/common/shared.h"
@@ -56,8 +55,6 @@
#include "inc/amd_hsa_queue.h"
namespace core {
class Agent;
struct AqlPacket {
union {
@@ -140,7 +137,7 @@ All funtions other than Convert and public_handle must be virtual.
class Queue : public Checked<0xFA3906A679F9DB49>,
public Shared<SharedQueue, AMD_QUEUE_ALIGN_BYTES> {
public:
explicit Queue(Agent& agent) : Shared(), amd_queue_(shared_object()->amd_queue), agent_(agent) {
Queue() : Shared(), amd_queue_(shared_object()->amd_queue) {
if (!Shared::IsSharedObjectAllocationValid()) {
return;
}
@@ -311,8 +308,6 @@ class Queue : public Checked<0xFA3906A679F9DB49>,
hsa_queue_t* public_handle() const { return public_handle_; }
Agent& agent() { return agent_; }
protected:
static void set_public_handle(Queue* ptr, hsa_queue_t* handle) {
ptr->do_set_public_handle(handle);
@@ -322,8 +317,6 @@ class Queue : public Checked<0xFA3906A679F9DB49>,
}
hsa_queue_t* public_handle_;
Agent& agent_;
private:
DISALLOW_COPY_AND_ASSIGN(Queue);
};