From 446c5e9672ee94228738cd1c118d64aa03966766 Mon Sep 17 00:00:00 2001 From: Graham Sider Date: Mon, 18 Oct 2021 18:21:31 -0400 Subject: [PATCH] Add gfx1100 support Signed-off-by: Graham Sider Change-Id: Ic5d5559e43df5c73409ba900a42c6901aabae661 --- rocrtst/suites/test_common/CMakeLists.txt | 2 +- runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp | 5 ++++- runtime/hsa-runtime/core/runtime/isa.cpp | 1 + runtime/hsa-runtime/image/blit_kernel.cpp | 3 +++ runtime/hsa-runtime/image/blit_src/CMakeLists.txt | 2 +- runtime/hsa-runtime/inc/amd_hsa_elf.h | 2 +- runtime/hsa-runtime/libamdhsacode/amd_hsa_code.cpp | 3 +++ 7 files changed, 14 insertions(+), 4 deletions(-) diff --git a/rocrtst/suites/test_common/CMakeLists.txt b/rocrtst/suites/test_common/CMakeLists.txt index 1151324c06..a7b4df6008 100755 --- a/rocrtst/suites/test_common/CMakeLists.txt +++ b/rocrtst/suites/test_common/CMakeLists.txt @@ -49,7 +49,7 @@ set ( CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/RadeonOpenCompute/ROCR-R set ( CPACK_PACKAGE_HOMEPAGE_URL "https://github.com/RadeonOpenCompute/ROCR-Runtime" ) -set(DEFAULT_TARGETS "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810;gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx1010;gfx1011;gfx1012;gfx1013;gfx1030;gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036") +set(DEFAULT_TARGETS "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810;gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx1010;gfx1011;gfx1012;gfx1013;gfx1030;gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036;gfx1100") # # Currently support for Windows platform is not present diff --git a/runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp b/runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp index b5a3843773..50a319e480 100644 --- a/runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp +++ b/runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp @@ -605,6 +605,9 @@ core::Blit* GpuAgent::CreateBlitSdma(bool use_xgmi) { case 10: sdma = new BlitSdmaV5(); break; + case 11: + sdma = new BlitSdmaV5(); + break; default: assert(false && "Unexpected device major version."); return nullptr; @@ -1543,7 +1546,7 @@ void GpuAgent::InvalidateCodeCaches() { // Microcode is handling code cache invalidation. return; } - } else if (isa_->GetMajorVersion() > 10) { + } else if (isa_->GetMajorVersion() > 11) { assert(false && "Code cache invalidation not implemented for this agent"); } diff --git a/runtime/hsa-runtime/core/runtime/isa.cpp b/runtime/hsa-runtime/core/runtime/isa.cpp index af34f45a15..ed61eccca8 100755 --- a/runtime/hsa-runtime/core/runtime/isa.cpp +++ b/runtime/hsa-runtime/core/runtime/isa.cpp @@ -315,6 +315,7 @@ constexpr size_t hsa_name_size = 63; ISAREG_ENTRY_GEN("gfx1034", 10, 3, 4, unsupported, unsupported) ISAREG_ENTRY_GEN("gfx1035", 10, 3, 5, unsupported, unsupported) ISAREG_ENTRY_GEN("gfx1036", 10, 3, 6, unsupported, unsupported) + ISAREG_ENTRY_GEN("gfx1100", 11, 0, 0, unsupported, unsupported) #undef ISAREG_ENTRY_GEN return supported_isas; } diff --git a/runtime/hsa-runtime/image/blit_kernel.cpp b/runtime/hsa-runtime/image/blit_kernel.cpp index a5b43784e4..62d6f01f32 100644 --- a/runtime/hsa-runtime/image/blit_kernel.cpp +++ b/runtime/hsa-runtime/image/blit_kernel.cpp @@ -96,6 +96,7 @@ extern uint8_t ocl_blit_object_gfx1033[]; extern uint8_t ocl_blit_object_gfx1034[]; extern uint8_t ocl_blit_object_gfx1035[]; extern uint8_t ocl_blit_object_gfx1036[]; +extern uint8_t ocl_blit_object_gfx1100[]; // Arguments inserted by OCL compiler, all zero here. struct OCLHiddenArgs { @@ -1025,6 +1026,8 @@ hsa_status_t BlitKernel::GetPatchedBlitObject(const char* agent_name, *blit_code_object = ocl_blit_object_gfx1035; } else if (sname == "gfx1036") { *blit_code_object = ocl_blit_object_gfx1036; + } else if (sname == "gfx1100") { + *blit_code_object = ocl_blit_object_gfx1100; } else { return HSA_STATUS_ERROR_INVALID_ISA_NAME; } diff --git a/runtime/hsa-runtime/image/blit_src/CMakeLists.txt b/runtime/hsa-runtime/image/blit_src/CMakeLists.txt index 71fa1b0a79..d8135d9606 100644 --- a/runtime/hsa-runtime/image/blit_src/CMakeLists.txt +++ b/runtime/hsa-runtime/image/blit_src/CMakeLists.txt @@ -47,7 +47,7 @@ find_package(Clang REQUIRED HINTS ${CMAKE_PREFIX_PATH}/llvm PATHS /opt/rocm/llvm # Determine the target devices if not specified if (NOT DEFINED TARGET_DEVICES) - set (TARGET_DEVICES "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810;gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx1010;gfx1011;gfx1012;gfx1013;gfx1030;gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036") + set (TARGET_DEVICES "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810;gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx1010;gfx1011;gfx1012;gfx1013;gfx1030;gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036;gfx1100") endif() set( TARGET_DEVICES ${TARGET_DEVICES} CACHE STRING "Build targets" FORCE ) diff --git a/runtime/hsa-runtime/inc/amd_hsa_elf.h b/runtime/hsa-runtime/inc/amd_hsa_elf.h index c42c5a4d00..f9ad738fe5 100644 --- a/runtime/hsa-runtime/inc/amd_hsa_elf.h +++ b/runtime/hsa-runtime/inc/amd_hsa_elf.h @@ -120,7 +120,7 @@ enum : unsigned { EF_AMDGPU_MACH_AMDGCN_GFX1034 = 0x03e, EF_AMDGPU_MACH_AMDGCN_GFX90A = 0x03f, EF_AMDGPU_MACH_AMDGCN_RESERVED_0X40 = 0x040, - EF_AMDGPU_MACH_AMDGCN_RESERVED_0X41 = 0x041, + EF_AMDGPU_MACH_AMDGCN_GFX1100 = 0x041, EF_AMDGPU_MACH_AMDGCN_GFX1013 = 0x042, EF_AMDGPU_MACH_AMDGCN_GFX1036 = 0x045, diff --git a/runtime/hsa-runtime/libamdhsacode/amd_hsa_code.cpp b/runtime/hsa-runtime/libamdhsacode/amd_hsa_code.cpp index 01e7b96717..d405030bca 100644 --- a/runtime/hsa-runtime/libamdhsacode/amd_hsa_code.cpp +++ b/runtime/hsa-runtime/libamdhsacode/amd_hsa_code.cpp @@ -585,6 +585,7 @@ namespace code { case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: name = "gfx1034"; xnack_supported = false; sramecc_supported = false; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035: name = "gfx1035"; xnack_supported = false; sramecc_supported = false; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036: name = "gfx1036"; xnack_supported = false; sramecc_supported = false; break; + case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100: name = "gfx1100"; xnack_supported = false; sramecc_supported = false; break; default: return false; } return true; @@ -633,6 +634,8 @@ namespace code { mach = ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; else if (old_name == "AMD:AMDGPU:9:0:12") mach = ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C; + else if (old_name == "AMD:AMDGPU:11:0:0") + mach = ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100; else { // Code object v2 only supports asics up to gfx906 plus gfx90c. Do NOT // add handling of new asics into this if-else-if* block.