diff --git a/rocclr/runtime/device/pal/palvirtual.cpp b/rocclr/runtime/device/pal/palvirtual.cpp
index f90981dd26..a40d2f1e44 100644
--- a/rocclr/runtime/device/pal/palvirtual.cpp
+++ b/rocclr/runtime/device/pal/palvirtual.cpp
@@ -759,12 +759,13 @@ bool VirtualGPU::create(bool profiling, uint deviceQueueSize, uint rtCUs,
     return false;
   }
 
+  const uint firstQueue = (dev().numComputeEngines() > 2) ? 1 : 0;
+  uint idx = index() % (dev().numComputeEngines() - firstQueue);
+
   if (dev().numComputeEngines()) {
     //! @todo There is a hang with a mix of user and non user queues.
     //! Currently there is no simple way to detect which queue is what.
     //! Disable first for now.
-    const uint firstQueue = (dev().numComputeEngines() > 2) ? 1 : 0;
-    uint idx = index() % (dev().numComputeEngines() - firstQueue);
 
     // hwRing_ should be set 0 if forced to have single scratch buffer
     hwRing_ = (dev().settings().useSingleScratch_) ? 0 : idx;
@@ -776,7 +777,7 @@ bool VirtualGPU::create(bool profiling, uint deviceQueueSize, uint rtCUs,
     }
 
     // Check if device has SDMA engines
-    if (dev().numDMAEngines() != 0) {
+    if (dev().numDMAEngines() != 0 && !PAL_DISABLE_SDMA) {
       uint sdma;
       // If only 1 DMA engine is available then use that one
       if ((dev().numDMAEngines() < 2) || ((idx & 0x1) && !dev().settings().svmFineGrainSystem_)) {
@@ -792,7 +793,11 @@ bool VirtualGPU::create(bool profiling, uint deviceQueueSize, uint rtCUs,
         return false;
       }
     } else {
-      Unimplemented();
+        queues_[SdmaEngine] = Queue::Create(dev().iDev(), Pal::QueueTypeCompute,
+            idx, cmdAllocator_, rtCUs, amd::CommandQueue::Priority::Normal);
+        if (nullptr == queues_[SdmaEngine]) {
+            return false;
+        }
     }
   } else {
     Unimplemented();
diff --git a/rocclr/runtime/utils/flags.hpp b/rocclr/runtime/utils/flags.hpp
index 94b5215150..576730d751 100644
--- a/rocclr/runtime/utils/flags.hpp
+++ b/rocclr/runtime/utils/flags.hpp
@@ -209,6 +209,8 @@ release(bool, OCL_CODE_CACHE_RESET, false,                                    \
         "1 =  Reset the compiler code cache storage")                         \
 release(bool, GPU_VEGA10_ONLY, VEGA10_ONLY,                                   \
         "1 = Report vega10 only on OCL/ROCR")                                 \
+release_on_stg(bool, PAL_DISABLE_SDMA, false,                                 \
+        "1 = Disable SDMA for PAL")                                           \
 
 namespace amd {