From 4d6ec86edf715619df9c0e182dff3d1540b11bee Mon Sep 17 00:00:00 2001
From: "Xie,AlexBin" <AlexBin.Xie@amd.com>
Date: Fri, 17 Feb 2023 18:49:15 -0500
Subject: [PATCH] SWDEV-378367 - Observed performance drop for Geekbench5

Change-Id: I0beabc6e3bec095574c8168fcf52af1e94105792


[ROCm/clr commit: 97243ff7556cd01ad36150fc865451047aed528b]
---
 projects/clr/rocclr/device/pal/palsettings.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/projects/clr/rocclr/device/pal/palsettings.cpp b/projects/clr/rocclr/device/pal/palsettings.cpp
index b85a2df037..080654c1cf 100644
--- a/projects/clr/rocclr/device/pal/palsettings.cpp
+++ b/projects/clr/rocclr/device/pal/palsettings.cpp
@@ -78,9 +78,10 @@ Settings::Settings() {
 
   // By default use host blit
   blitEngine_ = BlitEngineHost;
-  pinnedXferSize_ = GPU_PINNED_MIN_XFER_SIZE * Mi;
+  pinnedXferSize_ = GPU_PINNED_XFER_SIZE * Mi;
+  size_t defaultMinXferSize = amd::IS_HIP ? 128: 4;
   pinnedMinXferSize_ = flagIsDefault(GPU_PINNED_MIN_XFER_SIZE)
-    ? 128 * Mi : GPU_PINNED_MIN_XFER_SIZE * Mi;
+    ? defaultMinXferSize * Mi : GPU_PINNED_MIN_XFER_SIZE * Mi;
 
   // Disable FP_FAST_FMA defines by default
   reportFMAF_ = false;