SWDEV-279885 - correct HIP doc for managed memory

Change-Id: I94bb307dbe12692eb60cce744424fb18deea28ba
Tá an tiomantas seo le fáil i:
jujiang
2021-06-02 17:15:22 -04:00
tiomanta ag Julia Jiang
tuismitheoir 118714d1b6
tiomantas 52b4faef3b
D'athraigh 2 comhad le 13 breiseanna agus 3 scriosta
+11 -1
Féach ar an gComhad
@@ -25,7 +25,7 @@ Numa distance is the measurement of how far between GPU and CPU devices.
By default, each GPU selects a Numa CPU node that has the least Numa distance between them, that is, host memory will be automatically allocated closest on the memory pool of Numa node of the current GPU device. Using hipSetDevice API to a different GPU will still be able to access the host allocation, but can have longer Numa distance.
### Managed memory allocation
Managed memory, including the `__managed__` keyword, are supported in HIP combined host/device compilation.
Managed memory, except the `__managed__` keyword, are supported in HIP combined host/device compilation.
The allocation will be automatically managed by AMD HMM (Heterogeneous Memory Management).
In HIP application, there should be the capability check before make managed memory API call hipMallocManaged.
@@ -47,6 +47,16 @@ else {
```
For more details on managed memory APIs, please refer to the documentation HIP-API.pdf.
### HIP Stream Memory Operations
HIP supports Stream Memory Operations to enable direct synchronization between Network Nodes and GPU. Following new APIs are added,
hipStreamWaitValue32
hipStreamWaitValue64
hipStreamWriteValue32
hipStreamWriteValue64
For more details, please check the documentation HIP-API.pdf.
### Coherency Controls
ROCm defines two coherency options for host memory:
- Coherent memory : Supports fine-grain synchronization while the kernel is running.  For example, a kernel can perform atomic operations that are visible to the host CPU or to other (peer) GPUs.  Synchronization instructions include threadfence_system and C++11-style atomic operations. However, coherent memory cannot be cached by the GPU and thus may have lower performance.