diff --git a/src/argparser.py b/src/argparser.py index 438b49273f..abd0b9dd48 100644 --- a/src/argparser.py +++ b/src/argparser.py @@ -25,6 +25,27 @@ import argparse import shutil import os +import glob + +def load_avail_arch(omniperf_home): + ''' + Load list of avail archs by checking against defined implementations + ''' + matching_files=glob.glob(os.path.join(omniperf_home, 'omniperf_soc', 'soc_*.py')) + supported_arch=[] + # Load list of supported archs + for filepath in matching_files: + filename=os.path.basename(filepath) + postfix=filename[len('soc_'):-len('.py')] + # print(f"File: {filename}, Postfix: {postfix}") + if postfix != "base": + supported_arch.append(postfix) + return supported_arch +def print_avail_arch(avail_arch): + ret_str = "\t\tList all available metrics for analysis on specified arch:" + for arch in avail_arch: + ret_str += "\n\t\t {}".format(arch) + return ret_str def omniarg_parser(parser, omniperf_home, omniperf_version): # ----------------------------------------- @@ -389,8 +410,8 @@ def omniarg_parser(parser, omniperf_home, omniperf_version): analyze_group.add_argument( "--list-metrics", metavar="", - choices=["gfx906", "gfx908", "gfx90a"], - help="\t\tList all available metrics for analysis on specified arch:\n\t\t gfx906\n\t\t gfx908\n\t\t gfx90a", + choices=load_avail_arch(omniperf_home),#["gfx906", "gfx908", "gfx90a"], + help=print_avail_arch(load_avail_arch(omniperf_home)), ) analyze_group.add_argument( "-k", @@ -483,7 +504,7 @@ def omniarg_parser(parser, omniperf_home, omniperf_version): dest="config_dir", metavar="", help="\t\tSpecify the directory of customized configs.", - default=omniperf_home.joinpath("omniperf_analyze/configs"), + default=omniperf_home.joinpath("omniperf_soc/configs"), ) analyze_advanced_group.add_argument( "--save-dfs", diff --git a/src/omniperf_analyze/analysis_base.py b/src/omniperf_analyze/analysis_base.py index d16b0eef62..0a881f9e6b 100644 --- a/src/omniperf_analyze/analysis_base.py +++ b/src/omniperf_analyze/analysis_base.py @@ -23,22 +23,171 @@ ##############################################################################el from abc import ABC, abstractmethod +import os +import logging +import sys +import copy +from collections import OrderedDict +from pathlib import Path +from utils.utils import demarcate +from utils import schema, file_io, parser +import pandas as pd +from tabulate import tabulate class OmniAnalyze_Base(): def __init__(self,args,options): self.__args = args + self._runs = OrderedDict() #NB: I made this public so children can modify/add to obj properties + self._arch_configs = {} #NB: I made this public so children can modify/add to obj properties self.__options = options + self._output = None #NB: I made this public so children can modify/add to obj properties + def error(self,message): + logging.error("") + logging.error("[ERROR]: " + message) + logging.error("") + sys.exit(1) + def get_args(self): + return self.__args + + @demarcate + def generate_configs(self, arch, config_dir, list_kernels, filter_metrics): + single_panel_config = file_io.is_single_panel_config(Path(config_dir)) + + ac = schema.ArchConfig() + if list_kernels: + ac.panel_configs = file_io.top_stats_build_in_config + else: + arch_panel_config = ( + config_dir if single_panel_config else config_dir.joinpath(arch) + ) + ac.panel_configs = file_io.load_panel_configs(arch_panel_config) + + # TODO: filter_metrics should/might be one per arch + # print(ac) + + parser.build_dfs(ac, filter_metrics) + self._arch_configs[arch] = ac + return self._arch_configs + + @demarcate + def list_metrics(self): + args = self.__args + if args.list_metrics in file_io.supported_arch.keys(): + arch = args.list_metrics + if arch not in self._arch_configs.keys(): + self.generate_configs(arch, args.config_dir, args.list_kernels, args.filter_metrics) + print( + tabulate( + pd.DataFrame.from_dict( + self._arch_configs[args.list_metrics].metric_list, + orient="index", + columns=["Metric"], + ), + headers="keys", + tablefmt="fancy_grid" + ), + file=self._output + ) + sys.exit(0) + else: + self.error("Unsupported arch") + + @demarcate + def load_options(self, normalization_filter): + if not normalization_filter: + for k, v in self._arch_configs.items(): + parser.build_metric_value_string(v.dfs, v.dfs_type, self.__args.normal_unit) + else: + for k, v in self._arch_configs.items(): + parser.build_metric_value_string(v.dfs, v.dfs_type, normalization_filter) + + args = self.__args + # Error checking for multiple runs and multiple gpu_kernel filters + if args.gpu_kernel and (len(args.path) != len(args.gpu_kernel)): + if len(args.gpu_kernel) == 1: + for i in range(len(args.path) - 1): + args.gpu_kernel.extend(args.gpu_kernel) + else: + self.error("Error: the number of --filter-kernels doesn't match the number of --dir.") + + @demarcate + def initalize_runs(self, avail_socs, normalization_filter=None): + if self.__args.list_metrics: + self.list_metrics() + + # load required configs + for d in self.__args.path: + sys_info = file_io.load_sys_info(Path(d[0], "sysinfo.csv")) + arch = sys_info.iloc[0]["gpu_soc"] + args = self.__args + self.generate_configs(arch, args.config_dir, args.list_kernels, args.filter_metrics) + + self.load_options(normalization_filter) + + for d in self.__args.path: + w = schema.Workload() + w.sys_info = file_io.load_sys_info(Path(d[0], "sysinfo.csv")) + w.avail_ips = w.sys_info["ip_blocks"].item().split("|") + arch = w.sys_info.iloc[0]["gpu_soc"] + w.dfs = copy.deepcopy(self._arch_configs[arch].dfs) + w.dfs_type = self._arch_configs[arch].dfs_type + w.soc_spec = avail_socs[arch].get_soc_param() + self._runs[d[0]] = w + + return self._runs + + + @demarcate + def sanitize(self): + """Perform sanitization of inputs + """ + if not self.__args.list_metrics and not self.__args.path: + self.error("The following arguments are required: -p/--path") + # verify not accessing parent directories + if ".." in str(self.__args.path): + self.error("Access denied. Cannot access parent directories in path (i.e. ../)") + # ensure absolute path + for dir in self.__args.path: + full_path = os.path.abspath(dir[0]) + dir[0] = full_path + if not os.path.isdir(dir[0]): + self.error("Invalid directory {}\nPlease try again.".format(dir[0])) + + #---------------------------------------------------- # Required methods to be implemented by child classes + #---------------------------------------------------- @abstractmethod - def pre_processing(self): + def pre_processing(self, omni_socs: set): """Perform initialization prior to analysis. """ - pass + logging.debug("[analysis] prepping to do some analysis") + logging.info("[analysis] deriving Omniperf metrics...") + # initalize output file + self._output = open(self.__args.output_file, "w+") if self.__args.output_file else sys.stdout + + # initalize runs + self._runs = self.initalize_runs(omni_socs) + + # set filters + if self.__args.gpu_kernel: + for d, gk in zip(self.__args.path, self.__args.gpu_kernel): + self._runs[d[0]].filter_kernel_ids = gk + if self.__args.gpu_id: + if len(self.__args.gpu_id) == 1 and len(self.__args.path) != 1: + for i in range(len(self.__args.path) - 1): + self.__args.gpu_id.extend(self.__args.gpu_id) + for d, gi in zip(self.__args.path, self.__args.gpu_id): + self._runs[d[0]].filter_gpu_ids = gi + if self.__args.gpu_dispatch_id: + if len(self.__args.gpu_dispatch_id) == 1 and len(self.__args.path) != 1: + for i in range(len(self.__args.path) - 1): + self.__args.gpu_dispatch_id.extend(self.__args.gpu_dispatch_id) + for d, gd in zip(self.__args.path, self.__args.gpu_dispatch_id): + self._runs[d[0]].filter_dispatch_ids = gd @abstractmethod def run_analysis(self): """Run analysis. """ - pass - + logging.debug("[analysis] generating analysis") diff --git a/src/omniperf_analyze/analysis_cli.py b/src/omniperf_analyze/analysis_cli.py index a7a10e636d..81d0df2e61 100644 --- a/src/omniperf_analyze/analysis_cli.py +++ b/src/omniperf_analyze/analysis_cli.py @@ -22,21 +22,60 @@ # SOFTWARE. ##############################################################################el -import logging from omniperf_analyze.analysis_base import OmniAnalyze_Base from utils.utils import demarcate +from utils import file_io, parser, tty +from utils.csv_processor import kernel_name_shortener class cli_analysis(OmniAnalyze_Base): + #----------------------- # Required child methods + #----------------------- @demarcate - def pre_processing(self): + def pre_processing(self, omni_soc): """Perform any pre-processing steps prior to analysis. """ - logging.debug("[analysis] prepping to do some analysis") + super().pre_processing(omni_soc) + if self.get_args().random_port: + self.error("--gui flag is required to enable --random-port") + for d in self.get_args().path: + # demangle and overwrite original 'KernelName' + kernel_name_shortener(d[0], self.get_args().kernel_verbose) + + file_io.create_df_kernel_top_stats( + d[0], + self._runs[d[0]].filter_gpu_ids, + self._runs[d[0]].filter_dispatch_ids, + self.get_args().time_unit, + self.get_args().max_kernel_num + ) + # create 'mega dataframe' + self._runs[d[0]].raw_pmc = file_io.create_df_pmc( + d[0], self.get_args().verbose + ) + is_gui = False + # create the loaded table + parser.load_table_data( + self._runs[d[0]], d[0], is_gui, self.get_args().g, self.get_args().verbose + ) + @demarcate def run_analysis(self): """Run CLI analysis. """ - logging.debug("[analysis] check out this wicked cli ascii art") + if self.get_args().list_kernels: + tty.show_kernels( + self.get_args(), + self._runs, + self._arch_configs[self._runs[self.get_args().path[0][0]].sys_info.iloc[0]["gpu_soc"]], + self._output + ) + else: + tty.show_all( + self.get_args(), + self._runs, + self._arch_configs[self._runs[self.get_args().path[0][0]].sys_info.iloc[0]["gpu_soc"]], + self._output + ) diff --git a/src/omniperf_analyze/analysis_webui.py b/src/omniperf_analyze/analysis_webui.py index bd2b655be8..c145e62fcc 100644 --- a/src/omniperf_analyze/analysis_webui.py +++ b/src/omniperf_analyze/analysis_webui.py @@ -28,7 +28,9 @@ from utils.utils import demarcate class webui_analysis(OmniAnalyze_Base): + #----------------------- # Required child methods + #----------------------- @demarcate def pre_processing(self): """Perform any pre-processing steps prior to analysis. diff --git a/src/omniperf_base.py b/src/omniperf_base.py index d1a6e010bc..7524dfb2ed 100644 --- a/src/omniperf_base.py +++ b/src/omniperf_base.py @@ -32,13 +32,15 @@ from utils.specs import get_machine_specs from utils.utils import demarcate, trace_logger, get_version, get_version_display, detect_rocprof from argparser import omniarg_parser import config +import pandas as pd class Omniperf: def __init__(self): self.__args = None self.__profiler_mode = None - self.__soc_name = None - self.__soc = None + self.__analyze_mode = None + self.__soc_name = set() #TODO: Should we make this a list? To accommodate analyze mode + self.__soc = dict() # set of key, value pairs. Where arch->OmniSoc() obj self.__version = { "ver": None, "ver_pretty": None, @@ -53,9 +55,8 @@ class Omniperf: if self.__mode == "profile": self.detect_profiler() - - # self.__analyze_mode = "cli" - # self.__analyze_mode = "webui" + elif self.__mode == "analyze": + self.detect_analyze() logging.info("Execution mode = %s" % self.__mode) @@ -128,46 +129,50 @@ class Omniperf: rocprof_cmd = detect_rocprof() self.__profiler_mode = "rocprofv1" return - + def detect_analyze(self): + if self.__args.gui: + self.__analyze_mode = "web_ui" + else: + self.__analyze_mode = "cli" + return @demarcate - def detect_soc(self): - mspec = get_machine_specs(0) + def detect_soc(self, arch=None): + if not arch: + mspec = get_machine_specs(0) + arch = mspec.GPU target="" - if mspec.GPU == "gfx900": - target = "vega10" - elif mspec.GPU == "gfx906": + if arch == "gfx906": target = "mi50" - elif mspec.GPU == "gfx908": + elif arch == "gfx908": target = "mi100" - elif mspec.GPU == "gfx90a": + elif arch == "gfx90a": target = "mi200" else: - self.error("Unsupported SoC -> %s" % mspec.GPU) + self.error("Unsupported SoC -> %s" % arch) - self.__soc_name = target - self.__args.target = target + self.__soc_name.add(target) + if hasattr(self.__args, 'target'): + self.__args.target = target # instantiate underlying SoC support class - if self.__soc_name == "vega10": - from omniperf_soc.soc_gfx900 import gfx900_soc - self.__soc = gfx900_soc(self.__args) - elif self.__soc_name == "mi50": + # in case of analyze mode, __soc can accomadate multiple archs + if target == "mi50": from omniperf_soc.soc_gfx906 import gfx906_soc - self.__soc = gfx906_soc(self.__args) - elif self.__soc_name == "mi100": + self.__soc[arch] = gfx906_soc(self.__args) + elif target == "mi100": from omniperf_soc.soc_gfx908 import gfx908_soc - self.__soc = gfx908_soc(self.__args) - elif self.__soc_name == "mi200": + self.__soc[arch] = gfx908_soc(self.__args) + elif target == "mi200": from omniperf_soc.soc_gfx90a import gfx90a_soc - self.__soc = gfx90a_soc(self.__args) + self.__soc[arch] = gfx90a_soc(self.__args) else: - self.error("Unsupported SoC") + logging.error("Unsupported SoC") sys.exit(1) logging.info("SoC = %s" % self.__soc_name) - return + return arch @demarcate def parse_args(self): @@ -191,7 +196,7 @@ class Omniperf: @demarcate def run_profiler(self): self.print_graphic() - self.detect_soc() + targ_arch = self.detect_soc() # Update default path if self.__args.path == os.path.join(os.getcwd(), "workloads"): @@ -216,12 +221,11 @@ class Omniperf: #----------------------- # run profiling workflow #----------------------- - - self.__soc.profiling_setup() + self.__soc[targ_arch].profiling_setup() profiler.pre_processing() profiler.run_profiling(self.__version["ver"], config.prog) profiler.post_processing() - self.__soc.post_profiling() + self.__soc[targ_arch].post_profiling() return @@ -234,15 +238,14 @@ class Omniperf: @demarcate def run_analysis(self): self.print_graphic() - self.detect_soc() #NB: See comment in detect_profiler() to explain why this is here - logging.info("Analysis mode choie = %s" % self.__analyze_mode) + logging.info("Analysis mode = %s" % self.__analyze_mode) if self.__analyze_mode == "cli": - from analyze.analysis_cli import cli_analysis + from omniperf_analyze.analysis_cli import cli_analysis analyzer = cli_analysis(self.__args,self.__options) elif self.__analyze_mode == "webui": - from analyze.analysis_webui import webui_analysis + from omniperf_analyze.analysis_webui import webui_analysis analyzer = webui_analysis(self.__args,self.__options) else: self.error("Unsupported anlaysis mode -> %s" % self.__analyze_mode) @@ -251,8 +254,16 @@ class Omniperf: # run analysis workflow #----------------------- - self.__soc.analysis_setup() - analyzer.pre_processing() + analyzer.sanitize() + # Load required SoC(s) from input + for d in analyzer.get_args().path: + sys_info = pd.read_csv(Path(d[0], "sysinfo.csv")) + arch = sys_info.iloc[0]["gpu_soc"] + # Create and load new SoC object + self.detect_soc(arch) + + analyzer.pre_processing(self.__soc) analyzer.run_analysis() return + diff --git a/src/omniperf_profile/profiler_base.py b/src/omniperf_profile/profiler_base.py index 1a81deb7b6..8324f3fb60 100644 --- a/src/omniperf_profile/profiler_base.py +++ b/src/omniperf_profile/profiler_base.py @@ -47,7 +47,9 @@ class OmniProfiler_Base(): def get_args(self): return self.__args + #---------------------------------------------------- # Required methods to be implemented by child classes + #---------------------------------------------------- @abstractmethod def pre_processing(self): """Perform any pre-processing steps prior to profiling. diff --git a/src/omniperf_profile/profiler_rocprof_v1.py b/src/omniperf_profile/profiler_rocprof_v1.py index 0ce5ef5d55..c49c555454 100644 --- a/src/omniperf_profile/profiler_rocprof_v1.py +++ b/src/omniperf_profile/profiler_rocprof_v1.py @@ -39,8 +39,9 @@ class rocprof_v1_profiler(OmniProfiler_Base): self.ready_to_run = (self.get_args().roof_only and not os.path.isfile(os.path.join(self.get_args().path, "pmc_perf.csv")) or not self.get_args().roof_only) - + #----------------------- # Required child methods + #----------------------- @demarcate def pre_processing(self): """Perform any pre-processing steps prior to profiling. diff --git a/src/omniperf_profile/profiler_rocprof_v2.py b/src/omniperf_profile/profiler_rocprof_v2.py index 3bcd3bfe16..35249bfeaa 100644 --- a/src/omniperf_profile/profiler_rocprof_v2.py +++ b/src/omniperf_profile/profiler_rocprof_v2.py @@ -30,7 +30,9 @@ class rocprof_v2_profiler(OmniProfiler_Base): def __init__(self,profiling_args,profiler_mode,soc): super().__init__(profiling_args,profiler_mode,soc) + #----------------------- # Required child methods + #----------------------- @demarcate def pre_processing(self): """Perform any pre-processing steps prior to profiling. diff --git a/src/omniperf_profile/profiler_rocscope.py b/src/omniperf_profile/profiler_rocscope.py index e8a42848e5..69e2b9c336 100644 --- a/src/omniperf_profile/profiler_rocscope.py +++ b/src/omniperf_profile/profiler_rocscope.py @@ -30,7 +30,9 @@ class rocscope_profiler(OmniProfiler_Base): def __init__(self,profiling_args,profiler_mode,soc): super().__init__(profiling_args,profiler_mode,soc) + #----------------------- # Required child methods + #----------------------- @demarcate def pre_processing(self): """Perform any pre-processing steps prior to profiling. diff --git a/src/omniperf_soc/configs/gfx906/0000_top_stat.yaml b/src/omniperf_soc/configs/gfx906/0000_top_stat.yaml new file mode 100644 index 0000000000..077004080f --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/0000_top_stat.yaml @@ -0,0 +1,8 @@ +--- +Panel Config: + id: 000 + title: Top Stat + data source: + - raw_csv_table: + id: 001 + source: pmc_kernel_top.csv diff --git a/src/omniperf_soc/configs/gfx906/0100_system_info.yaml b/src/omniperf_soc/configs/gfx906/0100_system_info.yaml new file mode 100644 index 0000000000..b7ec29eaf9 --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/0100_system_info.yaml @@ -0,0 +1,9 @@ +--- +Panel Config: + id: 100 + title: System Info + data source: + - raw_csv_table: + id: 101 + source: sysinfo.csv + columnwise: True diff --git a/src/omniperf_soc/configs/gfx906/0200_system-speed-of-light.yaml b/src/omniperf_soc/configs/gfx906/0200_system-speed-of-light.yaml new file mode 100644 index 0000000000..986b2f0aec --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/0200_system-speed-of-light.yaml @@ -0,0 +1,230 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + SALU: &SALU_anchor Scalar Arithmetic Logic Unit + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 200 + title: System Speed-of-Light + data source: + - metric_table: + id: 201 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + peak: Peak + pop: PoP + tips: Tips + metric: + VALU FLOPs: + value: None # No perf counter + unit: GFLOPs + peak: (((($sclk * $numCU) * 64) * 2) / 1000) + pop: None # No perf counter + tips: + VALU IOPs: + value: None # No perf counter + unit: GOPs + peak: (((($sclk * $numCU) * 64) * 2) / 1000) + pop: None # No perf counter + tips: + MFMA FLOPs (BF16): + value: None # No perf counter + unit: GFLOPs + peak: ((($sclk * $numCU) * 512) / 1000) + pop: None # No perf counter + tips: + MFMA FLOPs (F16): + value: None # No perf counter + unit: GFLOPs + peak: ((($sclk * $numCU) * 1024) / 1000) + pop: None # No perf counter + tips: + MFMA FLOPs (F32): + value: None # No perf counter + unit: GFLOPs + peak: ((($sclk * $numCU) * 256) / 1000) + pop: None # No perf counter + tips: + MFMA FLOPs (F64): + value: None # No perf counter + unit: GFLOPs + peak: ((($sclk * $numCU) * 256) / 1000) + pop: None # No perf counter + tips: + MFMA IOPs (Int8): + value: None # No perf counter + unit: GOPs + peak: ((($sclk * $numCU) * 1024) / 1000) + pop: None # No perf counter + tips: + Active CUs: + value: $numActiveCUs + unit: CUs + peak: $numCU + pop: ((100 * $numActiveCUs) / $numCU) + tips: + SALU Util: + value: AVG(((100 * SQ_ACTIVE_INST_SCA) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + peak: 100 + pop: AVG(((100 * SQ_ACTIVE_INST_SCA) / (GRBM_GUI_ACTIVE * $numCU))) + tips: + VALU Util: + value: AVG(((100 * SQ_ACTIVE_INST_VALU) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + peak: 100 + pop: AVG(((100 * SQ_ACTIVE_INST_VALU) / (GRBM_GUI_ACTIVE * $numCU))) + tips: + MFMA Util: + value: None # No HW module + unit: pct + peak: 100 + pop: None # No HW module + tips: + VALU Active Threads/Wave: + value: AVG(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + unit: Threads + peak: 64 + pop: (AVG(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) * 1.5625) + tips: + IPC - Issue: + value: AVG(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM) + + SQ_INSTS_GDS) + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED) + / SQ_ACTIVE_INST_ANY)) + unit: Instr/cycle + peak: 5 + pop: ((100 * AVG(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM) + + SQ_INSTS_GDS) + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED) + / SQ_ACTIVE_INST_ANY))) / 5) + tips: + LDS BW: + value: AVG(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / (EndNs - BeginNs))) + unit: GB/sec + peak: (($sclk * $numCU) * 0.128) + pop: AVG((((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / (EndNs - BeginNs)) / (($sclk * $numCU) * 0.00128))) + tips: + LDS Bank Conflict: + value: AVG(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + unit: Conflicts/access + peak: 32 + pop: ((100 * AVG(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None))) / 32) + tips: + Instr Cache Hit Rate: + value: AVG(((100 * SQC_ICACHE_HITS) / (SQC_ICACHE_HITS + SQC_ICACHE_MISSES))) + unit: pct + peak: 100 + pop: AVG(((100 * SQC_ICACHE_HITS) / (SQC_ICACHE_HITS + SQC_ICACHE_MISSES))) + tips: + Instr Cache BW: + value: AVG(((SQC_ICACHE_REQ / (EndNs - BeginNs)) * 64)) + unit: GB/s + peak: ((($sclk / 1000) * 64) * $numSQC) + pop: ((100 * AVG(((SQC_ICACHE_REQ / (EndNs - BeginNs)) * 64))) / ((($sclk + / 1000) * 64) * $numSQC)) + tips: + Scalar L1D Cache Hit Rate: + value: AVG((((100 * SQC_DCACHE_HITS) / (SQC_DCACHE_HITS + SQC_DCACHE_MISSES)) + if ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) != 0) else None)) + unit: pct + peak: 100 + pop: AVG((((100 * SQC_DCACHE_HITS) / (SQC_DCACHE_HITS + SQC_DCACHE_MISSES)) + if ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) != 0) else None)) + tips: + Scalar L1D Cache BW: + value: AVG(((SQC_DCACHE_REQ / (EndNs - BeginNs)) * 64)) + unit: GB/s + peak: ((($sclk / 1000) * 64) * $numSQC) + pop: ((100 * AVG(((SQC_DCACHE_REQ / (EndNs - BeginNs)) * 64))) / ((($sclk + / 1000) * 64) * $numSQC)) + tips: + Vector L1D Cache Hit Rate: + value: AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + unit: pct + peak: 100 + pop: AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / + TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + tips: + Vector L1D Cache BW: + value: AVG(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs))) + unit: GB/s + peak: ((($sclk / 1000) * 64) * $numCU) + pop: ((100 * AVG(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs)))) + / ((($sclk / 1000) * 64) * $numCU)) + tips: + L2 Cache Hit Rate: + value: AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + unit: pct + peak: 100 + pop: AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + tips: + L2-Fabric Read BW: + value: AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / (EndNs - BeginNs))) + unit: GB/s + peak: $hbmBW + pop: ((100 * AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / (EndNs - BeginNs)))) / $hbmBW) + tips: + L2-Fabric Write BW: + value: AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / (EndNs - BeginNs))) + unit: GB/s + peak: $hbmBW + pop: ((100 * AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / (EndNs - BeginNs)))) / $hbmBW) + tips: + L2-Fabric Read Latency: + value: AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum + != 0) else None)) + unit: Cycles + peak: '' + pop: '' + tips: + L2-Fabric Write Latency: + value: AVG(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum + != 0) else None)) + unit: Cycles + peak: '' + pop: '' + tips: + Wave Occupancy: + value: AVG((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE)) + unit: Wavefronts + peak: ($maxWavesPerCU * $numCU) + pop: (100 * AVG(((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE) / ($maxWavesPerCU + * $numCU)))) + coll_level: SQ_LEVEL_WAVES + tips: + Instr Fetch BW: + value: AVG(((SQ_IFETCH / (EndNs - BeginNs)) * 32)) + unit: GB/s + peak: ((($sclk / 1000) * 32) * $numSQC) + pop: ((100 * AVG(((SQ_IFETCH / (EndNs - BeginNs)) * 32))) / ($numSQC + * (($sclk / 1000) * 32))) + coll_level: SQ_IFETCH_LEVEL + tips: + Instr Fetch Latency: + value: AVG((SQ_ACCUM_PREV_HIRES / SQ_IFETCH)) + unit: Cycles + peak: '' + pop: '' + coll_level: SQ_IFETCH_LEVEL + tips: diff --git a/src/omniperf_soc/configs/gfx906/0500_command-processor.yaml b/src/omniperf_soc/configs/gfx906/0500_command-processor.yaml new file mode 100644 index 0000000000..5250918799 --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/0500_command-processor.yaml @@ -0,0 +1,180 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 500 + title: Command Processor (CPC/CPF) + data source: + - metric_table: + id: 501 + title: Command Processor Fetcher + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + GPU Busy Cycles: + avg: AVG(GRBM_GUI_ACTIVE) + min: MIN(GRBM_GUI_ACTIVE) + max: MAX(GRBM_GUI_ACTIVE) + unit: Cycles/Kernel + tips: + CPF Busy: + avg: AVG(CPF_CPF_STAT_BUSY) + min: MIN(CPF_CPF_STAT_BUSY) + max: MAX(CPF_CPF_STAT_BUSY) + unit: Cycles/Kernel + tips: + CPF Util: + avg: AVG((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) + if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) + min: MIN((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) + if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) + max: MAX((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) + if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) + unit: pct + tips: + CPF Stall: + avg: AVG((((100 * CPF_CPF_STAT_STALL) / CPF_CPF_STAT_BUSY) if (CPF_CPF_STAT_BUSY + != 0) else None)) + min: MIN((((100 * CPF_CPF_STAT_STALL) / CPF_CPF_STAT_BUSY) if (CPF_CPF_STAT_BUSY + != 0) else None)) + max: MAX((((100 * CPF_CPF_STAT_STALL) / CPF_CPF_STAT_BUSY) if (CPF_CPF_STAT_BUSY + != 0) else None)) + unit: Cycles/Kernel + tips: + L2Cache Intf Busy: + avg: AVG(CPF_CPF_TCIU_BUSY) + min: MIN(CPF_CPF_TCIU_BUSY) + max: MAX(CPF_CPF_TCIU_BUSY) + unit: Cycles/Kernel + tips: + L2Cache Intf Util: + avg: AVG((((100 * CPF_CPF_TCIU_BUSY) / (CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE)) + if ((CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE) != 0) else None)) + min: MIN((((100 * CPF_CPF_TCIU_BUSY) / (CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE)) + if ((CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE) != 0) else None)) + max: MAX((((100 * CPF_CPF_TCIU_BUSY) / (CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE)) + if ((CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE) != 0) else None)) + unit: pct + tips: + L2Cache Intf Stall: + avg: AVG((((100 * CPF_CPF_TCIU_STALL) / CPF_CPF_TCIU_BUSY) if (CPF_CPF_TCIU_BUSY + != 0) else None)) + min: MIN((((100 * CPF_CPF_TCIU_STALL) / CPF_CPF_TCIU_BUSY) if (CPF_CPF_TCIU_BUSY + != 0) else None)) + max: MAX((((100 * CPF_CPF_TCIU_STALL) / CPF_CPF_TCIU_BUSY) if (CPF_CPF_TCIU_BUSY + != 0) else None)) + unit: pct + tips: + UTCL1 Stall: + avg: AVG(CPF_CMP_UTCL1_STALL_ON_TRANSLATION) + min: MIN(CPF_CMP_UTCL1_STALL_ON_TRANSLATION) + max: MAX(CPF_CMP_UTCL1_STALL_ON_TRANSLATION) + unit: Cycles/Kernel + tips: + + - metric_table: + id: 502 + title: Command Processor Compute + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + GPU Busy Cycles: + avg: AVG(GRBM_GUI_ACTIVE) + min: MIN(GRBM_GUI_ACTIVE) + max: MAX(GRBM_GUI_ACTIVE) + unit: Cycles + tips: + CPC Busy Cycles: + avg: AVG(CPC_CPC_STAT_BUSY) + min: MIN(CPC_CPC_STAT_BUSY) + max: MAX(CPC_CPC_STAT_BUSY) + unit: Cycles + tips: + CPC Util: + avg: AVG((((100 * CPC_CPC_STAT_BUSY) / (CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE)) + if ((CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE) != 0) else None)) + min: MIN((((100 * CPC_CPC_STAT_BUSY) / (CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE)) + if ((CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE) != 0) else None)) + max: MAX((((100 * CPC_CPC_STAT_BUSY) / (CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE)) + if ((CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE) != 0) else None)) + unit: pct + tips: + CPC Stall Cycles: + avg: AVG(CPC_CPC_STAT_STALL) + min: MIN(CPC_CPC_STAT_STALL) + max: MAX(CPC_CPC_STAT_STALL) + unit: Cycles + tips: + CPC Stall Rate: + avg: AVG((((100 * CPC_CPC_STAT_STALL) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + min: MIN((((100 * CPC_CPC_STAT_STALL) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + max: MAX((((100 * CPC_CPC_STAT_STALL) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + unit: pct + tips: + CPC Packet Decoding: + avg: AVG(CPC_ME1_BUSY_FOR_PACKET_DECODE) + min: MIN(CPC_ME1_BUSY_FOR_PACKET_DECODE) + max: MAX(CPC_ME1_BUSY_FOR_PACKET_DECODE) + unit: Cycles + tips: + SPI Intf Busy Cycles: + avg: AVG(CPC_ME1_DC0_SPI_BUSY) + min: MIN(CPC_ME1_DC0_SPI_BUSY) + max: MAX(CPC_ME1_DC0_SPI_BUSY) + unit: Cycles + tips: + SPI Intf Util: + avg: AVG((((100 * CPC_ME1_DC0_SPI_BUSY) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + min: MIN((((100 * CPC_ME1_DC0_SPI_BUSY) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + max: MAX((((100 * CPC_ME1_DC0_SPI_BUSY) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + unit: pct + tips: + L2Cache Intf Util: + avg: AVG((((100 * CPC_CPC_TCIU_BUSY) / (CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE)) + if ((CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE) != 0) else None)) + min: MIN((((100 * CPC_CPC_TCIU_BUSY) / (CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE)) + if ((CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE) != 0) else None)) + max: MAX((((100 * CPC_CPC_TCIU_BUSY) / (CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE)) + if ((CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE) != 0) else None)) + unit: pct + tips: + UTCL1 Stall Cycles: + avg: AVG(CPC_UTCL1_STALL_ON_TRANSLATION) + min: MIN(CPC_UTCL1_STALL_ON_TRANSLATION) + max: MAX(CPC_UTCL1_STALL_ON_TRANSLATION) + unit: Cycles + tips: + UTCL2 Intf Busy Cycles: + avg: AVG(CPC_CPC_UTCL2IU_BUSY) + min: MIN(CPC_CPC_UTCL2IU_BUSY) + max: MAX(CPC_CPC_UTCL2IU_BUSY) + unit: Cycles + tips: + UTCL2 Intf Util: + avg: AVG((((100 * CPC_CPC_UTCL2IU_BUSY) / (CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE)) + if ((CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE) != 0) else None)) + min: MIN((((100 * CPC_CPC_UTCL2IU_BUSY) / (CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE)) + if ((CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE) != 0) else None)) + max: MAX((((100 * CPC_CPC_UTCL2IU_BUSY) / (CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE)) + if ((CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE) != 0) else None)) + unit: pct + tips: diff --git a/src/omniperf_soc/configs/gfx906/0600_shader-processor-input.yaml b/src/omniperf_soc/configs/gfx906/0600_shader-processor-input.yaml new file mode 100644 index 0000000000..bab48700ac --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/0600_shader-processor-input.yaml @@ -0,0 +1,174 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 600 + title: Shader Processor Input (SPI) + data source: + - metric_table: + id: 601 + title: SPI Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + GPU Busy: + avg: AVG(GRBM_GUI_ACTIVE) + min: MIN(GRBM_GUI_ACTIVE) + max: MAX(GRBM_GUI_ACTIVE) + unit: Cycles + tips: + CS Busy: + avg: AVG(SPI_CSN_BUSY) + min: MIN(SPI_CSN_BUSY) + max: MAX(SPI_CSN_BUSY) + unit: Cycles + tips: + SPI Busy: + avg: AVG(GRBM_SPI_BUSY) + min: MIN(GRBM_SPI_BUSY) + max: MAX(GRBM_SPI_BUSY) + unit: Cycles + tips: + SQ Busy: + avg: AVG(SQ_BUSY_CYCLES) + min: MIN(SQ_BUSY_CYCLES) + max: MAX(SQ_BUSY_CYCLES) + unit: Cycles + tips: + Dispatched Workgroups: + avg: AVG(SPI_CSN_NUM_THREADGROUPS) + min: MIN(SPI_CSN_NUM_THREADGROUPS) + max: MAX(SPI_CSN_NUM_THREADGROUPS) + unit: Workgroups + tips: + Dispatched Wavefronts: + avg: AVG(SPI_CSN_WAVE) + min: MIN(SPI_CSN_WAVE) + max: MAX(SPI_CSN_WAVE) + unit: Wavefronts + tips: + Wave Alloc Failed: + avg: AVG(SPI_RA_REQ_NO_ALLOC) + min: MIN(SPI_RA_REQ_NO_ALLOC) + max: MAX(SPI_RA_REQ_NO_ALLOC) + unit: Cycles + tips: + Wave Alloc Failed - CS: + avg: AVG(SPI_RA_REQ_NO_ALLOC_CSN) + min: MIN(SPI_RA_REQ_NO_ALLOC_CSN) + max: MAX(SPI_RA_REQ_NO_ALLOC_CSN) + unit: Cycles + tips: + + - metric_table: + id: 602 + title: SPI Resource Allocation + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Wave request Failed (CS): + avg: AVG(SPI_RA_REQ_NO_ALLOC_CSN) + min: MIN(SPI_RA_REQ_NO_ALLOC_CSN) + max: MAX(SPI_RA_REQ_NO_ALLOC_CSN) + unit: Cycles + tips: + CS Stall: + avg: AVG(SPI_RA_RES_STALL_CSN) + min: MIN(SPI_RA_RES_STALL_CSN) + max: MAX(SPI_RA_RES_STALL_CSN) + unit: Cycles + tips: + CS Stall Rate: + avg: AVG((((100 * SPI_RA_RES_STALL_CSN) / GRBM_SPI_BUSY) if (GRBM_SPI_BUSY != + 0) else None)) + min: MIN((((100 * SPI_RA_RES_STALL_CSN) / GRBM_SPI_BUSY) if (GRBM_SPI_BUSY != + 0) else None)) + max: MAX((((100 * SPI_RA_RES_STALL_CSN) / GRBM_SPI_BUSY) if (GRBM_SPI_BUSY != + 0) else None)) + unit: pct + tips: + Scratch Stall: + avg: AVG(SPI_RA_TMP_STALL_CSN) + min: MIN(SPI_RA_TMP_STALL_CSN) + max: MAX(SPI_RA_TMP_STALL_CSN) + unit: Cycles + tips: + Insufficient SIMD Waveslots: + avg: AVG(SPI_RA_WAVE_SIMD_FULL_CSN) + min: MIN(SPI_RA_WAVE_SIMD_FULL_CSN) + max: MAX(SPI_RA_WAVE_SIMD_FULL_CSN) + unit: SIMD + tips: + Insufficient SIMD VGPRs: + avg: AVG(SPI_RA_VGPR_SIMD_FULL_CSN) + min: MIN(SPI_RA_VGPR_SIMD_FULL_CSN) + max: MAX(SPI_RA_VGPR_SIMD_FULL_CSN) + unit: SIMD + tips: + Insufficient SIMD SGPRs: + avg: AVG(SPI_RA_SGPR_SIMD_FULL_CSN) + min: MIN(SPI_RA_SGPR_SIMD_FULL_CSN) + max: MAX(SPI_RA_SGPR_SIMD_FULL_CSN) + unit: SIMD + tips: + Insufficient CU LDS: + avg: AVG(SPI_RA_LDS_CU_FULL_CSN) + min: MIN(SPI_RA_LDS_CU_FULL_CSN) + max: MAX(SPI_RA_LDS_CU_FULL_CSN) + unit: CU + tips: + Insufficient CU Barries: + avg: AVG(SPI_RA_BAR_CU_FULL_CSN) + min: MIN(SPI_RA_BAR_CU_FULL_CSN) + max: MAX(SPI_RA_BAR_CU_FULL_CSN) + unit: CU + tips: + Insufficient Bulky Resource: + avg: AVG(SPI_RA_BULKY_CU_FULL_CSN) + min: MIN(SPI_RA_BULKY_CU_FULL_CSN) + max: MAX(SPI_RA_BULKY_CU_FULL_CSN) + unit: CU + tips: + Reach CU Threadgroups Limit: + avg: AVG(SPI_RA_TGLIM_CU_FULL_CSN) + min: MIN(SPI_RA_TGLIM_CU_FULL_CSN) + max: MAX(SPI_RA_TGLIM_CU_FULL_CSN) + unit: Cycles + tips: + Reach CU Wave Limit: + avg: AVG(SPI_RA_WVLIM_STALL_CSN) + min: MIN(SPI_RA_WVLIM_STALL_CSN) + max: MAX(SPI_RA_WVLIM_STALL_CSN) + unit: Cycles + tips: + VGPR Writes: + avg: AVG((((4 * SPI_VWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + min: MIN((((4 * SPI_VWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + max: MAX((((4 * SPI_VWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + unit: Cycles/wave + tips: + SGPR Writes: + avg: AVG((((1 * SPI_SWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + min: MIN((((1 * SPI_SWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + max: MAX((((1 * SPI_SWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + unit: Cycles/wave + tips: diff --git a/src/omniperf_soc/configs/gfx906/0700_wavefront-launch.yaml b/src/omniperf_soc/configs/gfx906/0700_wavefront-launch.yaml new file mode 100644 index 0000000000..70141193e6 --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/0700_wavefront-launch.yaml @@ -0,0 +1,142 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 700 + title: Wavefront + data source: + - metric_table: + id: 701 + title: Wavefront Launch Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Grid Size: + avg: AVG(grd) + min: MIN(grd) + max: MAX(grd) + unit: Work Items + tips: + Workgroup Size: + avg: AVG(wgr) + min: MIN(wgr) + max: MAX(wgr) + unit: Work Items + tips: + Total Wavefronts: + avg: AVG(SPI_CSN_WAVE) + min: MIN(SPI_CSN_WAVE) + max: MAX(SPI_CSN_WAVE) + unit: Wavefronts + tips: + Saved Wavefronts: + avg: AVG(SQ_WAVES_SAVED) + min: MIN(SQ_WAVES_SAVED) + max: MAX(SQ_WAVES_SAVED) + unit: Wavefronts + tips: + Restored Wavefronts: + avg: AVG(SQ_WAVES_RESTORED) + min: MIN(SQ_WAVES_RESTORED) + max: MAX(SQ_WAVES_RESTORED) + unit: Wavefronts + tips: + VGPRs: + avg: AVG(arch_vgpr) + min: MIN(arch_vgpr) + max: MAX(arch_vgpr) + unit: Registers + tips: + AGPRs: + avg: AVG(accum_vgpr) + min: MIN(accum_vgpr) + max: MAX(accum_vgpr) + unit: Registers + tips: + SGPRs: + avg: AVG(sgpr) + min: MIN(sgpr) + max: MAX(sgpr) + unit: Registers + tips: + LDS Allocation: + avg: AVG(lds) + min: MIN(lds) + max: MAX(lds) + unit: Bytes + tips: + Scratch Allocation: + avg: AVG(scr) + min: MIN(scr) + max: MAX(scr) + unit: Bytes + tips: + + - metric_table: + id: 702 + title: Wavefront Runtime Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Kernel Time (Nanosec): + avg: AVG((EndNs - BeginNs)) + min: MIN((EndNs - BeginNs)) + max: MAX((EndNs - BeginNs)) + unit: ns + tips: + Kernel Time (Cycles): + avg: AVG(GRBM_GUI_ACTIVE) + min: MIN(GRBM_GUI_ACTIVE) + max: MAX(GRBM_GUI_ACTIVE) + unit: Cycle + tips: + Instr/wavefront: + avg: AVG((SQ_INSTS / SQ_WAVES)) + min: MIN((SQ_INSTS / SQ_WAVES)) + max: MAX((SQ_INSTS / SQ_WAVES)) + unit: Instr/wavefront + tips: + Wave Cycles: + avg: AVG(((4 * SQ_WAVE_CYCLES) / $denom)) + min: MIN(((4 * SQ_WAVE_CYCLES) / $denom)) + max: MAX(((4 * SQ_WAVE_CYCLES) / $denom)) + unit: (Cycles + $normUnit) + tips: + Dependency Wait Cycles: + avg: AVG(((4 * SQ_WAIT_ANY) / $denom)) + min: MIN(((4 * SQ_WAIT_ANY) / $denom)) + max: MAX(((4 * SQ_WAIT_ANY) / $denom)) + unit: (Cycles + $normUnit) + tips: + Issue Wait Cycles: + avg: AVG(((4 * SQ_WAIT_INST_ANY) / $denom)) + min: MIN(((4 * SQ_WAIT_INST_ANY) / $denom)) + max: MAX(((4 * SQ_WAIT_INST_ANY) / $denom)) + unit: (Cycles + $normUnit) + tips: + Active Cycles: + avg: AVG(((4 * SQ_ACTIVE_INST_ANY) / $denom)) + min: MIN(((4 * SQ_ACTIVE_INST_ANY) / $denom)) + max: MAX(((4 * SQ_ACTIVE_INST_ANY) / $denom)) + unit: (Cycles + $normUnit) + tips: + Wavefront Occupancy: + avg: AVG((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE)) + min: MIN((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE)) + max: MAX((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE)) + unit: Wavefronts + coll_level: SQ_LEVEL_WAVES + tips: diff --git a/src/omniperf_soc/configs/gfx906/1000_compute-unit-instruction-mix.yaml b/src/omniperf_soc/configs/gfx906/1000_compute-unit-instruction-mix.yaml new file mode 100644 index 0000000000..679acc34d1 --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/1000_compute-unit-instruction-mix.yaml @@ -0,0 +1,234 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1000 + title: Compute Units - Instruction Mix + data source: + - metric_table: + id: 1001 + title: Instruction Mix + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + style: + type: simple_bar + label_txt: (# of instr + $normUnit) + metric: + VALU - Vector: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + VMEM: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + LDS: + avg: AVG((SQ_INSTS_LDS / $denom)) + min: MIN((SQ_INSTS_LDS / $denom)) + max: MAX((SQ_INSTS_LDS / $denom)) + unit: (instr + $normUnit) + tips: + VALU - MFMA: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + SALU: + avg: AVG((SQ_INSTS_SALU / $denom)) + min: MIN((SQ_INSTS_SALU / $denom)) + max: MAX((SQ_INSTS_SALU / $denom)) + unit: (instr + $normUnit) + tips: + SMEM: + avg: AVG((SQ_INSTS_SMEM / $denom)) + min: MIN((SQ_INSTS_SMEM / $denom)) + max: MAX((SQ_INSTS_SMEM / $denom)) + unit: (instr + $normUnit) + tips: + Branch: + avg: AVG((SQ_INSTS_BRANCH / $denom)) + min: MIN((SQ_INSTS_BRANCH / $denom)) + max: MAX((SQ_INSTS_BRANCH / $denom)) + unit: (instr + $normUnit) + tips: + GDS: + avg: AVG((SQ_INSTS_GDS / $denom)) + min: MIN((SQ_INSTS_GDS / $denom)) + max: MAX((SQ_INSTS_GDS / $denom)) + unit: (instr + $normUnit) + tips: + + - metric_table: + id: 1002 + title: VALU Arithmetic Instr Mix + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + style: + type: simple_bar + label_txt: (# of instr + $normUnit) + metric: + INT-32: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + INT-64: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + F16-ADD: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + F16-Mult: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + F16-FMA: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + F16-Trans: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + F32-ADD: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + F32-Mult: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + F32-FMA: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + F32-Trans: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + F64-ADD: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + F64-Mult: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + F64-FMA: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + F64-Trans: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + Conversion: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + + - metric_table: + id: 1003 + title: VMEM Instr Mix + header: + type: Type + count: Count + tips: Tips + metric: + Buffer Instr: + count: AVG((TA_BUFFER_WAVEFRONTS_sum / $denom)) + tips: + Buffer Read: + count: AVG((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) + tips: + Buffer Write: + count: AVG((TA_BUFFER_WRITE_WAVEFRONTS_sum / $denom)) + tips: + Buffer Atomic: + count: AVG((TA_BUFFER_ATOMIC_WAVEFRONTS_sum / $denom)) + tips: + Flat Instr: + count: AVG((TA_FLAT_WAVEFRONTS_sum / $denom)) + tips: + Flat Read: + count: AVG((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) + tips: + Flat Write: + count: AVG((TA_FLAT_WRITE_WAVEFRONTS_sum / $denom)) + tips: + Flat Atomic: + count: AVG((TA_FLAT_ATOMIC_WAVEFRONTS_sum / $denom)) + tips: + + - metric_table: + id: 1004 + title: MFMA Arithmetic Instr Mix + header: + type: Type + count: Count + tips: Tips + metric: + MFMA-I8: + count: None # No HW module + tips: + MFMA-F16: + count: None # No HW module + tips: + MFMA-BF16: + count: None # No HW module + tips: + MFMA-F32: + count: None # No HW module + tips: + MFMA-F64: + count: None # No HW module + tips: diff --git a/src/omniperf_soc/configs/gfx906/1100_compute-unit-compute-pipeline.yaml b/src/omniperf_soc/configs/gfx906/1100_compute-unit-compute-pipeline.yaml new file mode 100644 index 0000000000..8cffb24c7e --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/1100_compute-unit-compute-pipeline.yaml @@ -0,0 +1,154 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1100 + title: Compute Units - Compute Pipeline + data source: + - metric_table: + id: 1101 + title: Speed-of-Light + header: + metric: Metric + value: Value + tips: Tips + style: + type: simple_bar + range_color: [1, 100] + label_txt: (%) + xrange: [0, 110] + metric: + valu_flops_pop: + value: None # No perf counter + tips: + mfma_flops_bf16_pop: + value: None # No perf counter + tips: + mfma_flops_f16_pop: + value: None # No perf counter + tips: + mfma_flops_f32_pop: + value: None # No perf counter + tips: + mfma_flops_f64_pop: + value: None # No perf counter + tips: + mfma_flops_i8_pop: + value: None # No perf counter + tips: + + - metric_table: + id: 1102 + title: Pipeline Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + IPC (Avg): + avg: AVG((SQ_INSTS / SQ_BUSY_CU_CYCLES)) + min: MIN((SQ_INSTS / SQ_BUSY_CU_CYCLES)) + max: MAX((SQ_INSTS / SQ_BUSY_CU_CYCLES)) + unit: Instr/cycle + tips: + IPC (Issue): + avg: AVG(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM) + + SQ_INSTS_GDS) + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED) + / SQ_ACTIVE_INST_ANY)) + min: MIN(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM) + + SQ_INSTS_GDS) + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED) + / SQ_ACTIVE_INST_ANY)) + max: MAX(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM) + + SQ_INSTS_GDS) + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED) + / SQ_ACTIVE_INST_ANY)) + unit: Instr/cycle + tips: + SALU Util: + avg: AVG((((100 * SQ_ACTIVE_INST_SCA) / GRBM_GUI_ACTIVE) / $numCU)) + min: MIN((((100 * SQ_ACTIVE_INST_SCA) / GRBM_GUI_ACTIVE) / $numCU)) + max: MAX((((100 * SQ_ACTIVE_INST_SCA) / GRBM_GUI_ACTIVE) / $numCU)) + unit: pct + tips: + VALU Util: + avg: AVG((((100 * SQ_ACTIVE_INST_VALU) / GRBM_GUI_ACTIVE) / $numCU)) + min: MIN((((100 * SQ_ACTIVE_INST_VALU) / GRBM_GUI_ACTIVE) / $numCU)) + max: MAX((((100 * SQ_ACTIVE_INST_VALU) / GRBM_GUI_ACTIVE) / $numCU)) + unit: pct + tips: + VALU Active Threads: + avg: AVG(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + min: MIN(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + max: MAX(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + unit: Threads + tips: + MFMA Util: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: pct + tips: + MFMA Instr Cycles: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: cycles/instr + tips: + + - metric_table: + id: 1103 + title: Arithmetic Operations + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + FLOPs (Total): + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (OPs + $normUnit) + tips: + INT8 OPs: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (OPs + $normUnit) + tips: + F16 OPs: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (OPs + $normUnit) + tips: + BF16 OPs: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (OPs + $normUnit) + tips: + F32 OPs: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (OPs + $normUnit) + tips: + F64 OPs: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (OPs + $normUnit) + tips: + + diff --git a/src/omniperf_soc/configs/gfx906/1200_lds.yaml b/src/omniperf_soc/configs/gfx906/1200_lds.yaml new file mode 100644 index 0000000000..3fd52c3b1b --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/1200_lds.yaml @@ -0,0 +1,121 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1200 + title: Local Data Share (LDS) + data source: + - metric_table: + id: 1201 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + range_color: [1, 100] + label_txt: (%) + xrange: [0, 110] + metric: + Utilization: + value: AVG(((100 * SQ_LDS_IDX_ACTIVE) / (GRBM_GUI_ACTIVE * $numCU))) + unit: Pct of Peak + tips: + Access Rate: + value: AVG(((200 * SQ_ACTIVE_INST_LDS) / (GRBM_GUI_ACTIVE * $numCU))) + unit: Pct of Peak + tips: + Bandwidth (Pct-of-Peak): + value: AVG((((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / (EndNs - BeginNs)) / (($sclk * $numCU) * 0.00128))) + unit: Pct of Peak + tips: + Bank Conflict Rate: + value: AVG((((SQ_LDS_BANK_CONFLICT * 3.125) / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + unit: Pct of Peak + tips: + + - metric_table: + id: 1202 + title: LDS Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + LDS Instrs: + avg: AVG((SQ_INSTS_LDS / $denom)) + min: MIN((SQ_INSTS_LDS / $denom)) + max: MAX((SQ_INSTS_LDS / $denom)) + unit: (Instr + $normUnit) + tips: + Bandwidth: + avg: AVG(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / $denom)) + min: MIN(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / $denom)) + max: MAX(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / $denom)) + unit: (Bytes + $normUnit) + tips: + Bank Conficts/Access: + avg: AVG(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + min: MIN(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + max: MAX(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + unit: Conflicts/Access + tips: + Index Accesses: + avg: AVG((SQ_LDS_IDX_ACTIVE / $denom)) + min: MIN((SQ_LDS_IDX_ACTIVE / $denom)) + max: MAX((SQ_LDS_IDX_ACTIVE / $denom)) + unit: (Cycles + $normUnit) + tips: + Atomic Cycles: + avg: AVG((SQ_LDS_ATOMIC_RETURN / $denom)) + min: MIN((SQ_LDS_ATOMIC_RETURN / $denom)) + max: MAX((SQ_LDS_ATOMIC_RETURN / $denom)) + unit: (Cycles + $normUnit) + tips: + Bank Conflict: + avg: AVG((SQ_LDS_BANK_CONFLICT / $denom)) + min: MIN((SQ_LDS_BANK_CONFLICT / $denom)) + max: MAX((SQ_LDS_BANK_CONFLICT / $denom)) + unit: (Cycles + $normUnit) + tips: + Addr Conflict: + avg: AVG((SQ_LDS_ADDR_CONFLICT / $denom)) + min: MIN((SQ_LDS_ADDR_CONFLICT / $denom)) + max: MAX((SQ_LDS_ADDR_CONFLICT / $denom)) + unit: (Cycles + $normUnit) + tips: + Unaligned Stall: + avg: AVG((SQ_LDS_UNALIGNED_STALL / $denom)) + min: MIN((SQ_LDS_UNALIGNED_STALL / $denom)) + max: MAX((SQ_LDS_UNALIGNED_STALL / $denom)) + unit: (Cycles + $normUnit) + tips: + Mem Violations: + avg: AVG((SQ_LDS_MEM_VIOLATIONS / $denom)) + min: MIN((SQ_LDS_MEM_VIOLATIONS / $denom)) + max: MAX((SQ_LDS_MEM_VIOLATIONS / $denom)) + unit: ( + $normUnit) + tips: + LDS Latency: + avg: AVG(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)) + min: MIN(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)) + max: MAX(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)) + unit: Cycles + coll_level: SQ_INST_LEVEL_LDS + tips: diff --git a/src/omniperf_soc/configs/gfx906/1300_instruction-cache.yaml b/src/omniperf_soc/configs/gfx906/1300_instruction-cache.yaml new file mode 100644 index 0000000000..05dc759803 --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/1300_instruction-cache.yaml @@ -0,0 +1,79 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1300 + title: Instruction Cache + data source: + - metric_table: + id: 1301 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + range_color: [1, 100] + label_txt: (%) + xrange: [0, 110] + metric: + Bandwidth: + value: AVG(((SQC_ICACHE_REQ * 100000) / (($sclk * $numSQC) + * (EndNs - BeginNs)))) + unit: Pct of Peak + tips: + Cache Hit: + value: AVG(((SQC_ICACHE_HITS * 100) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + unit: Pct of Peak + tips: + + - metric_table: + id: 1302 + title: Instruction Cache Accesses + header: + metric: L1I Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Req: + avg: AVG((SQC_ICACHE_REQ / $denom)) + min: MIN((SQC_ICACHE_REQ / $denom)) + max: MAX((SQC_ICACHE_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Hits: + avg: AVG((SQC_ICACHE_HITS / $denom)) + min: MIN((SQC_ICACHE_HITS / $denom)) + max: MAX((SQC_ICACHE_HITS / $denom)) + unit: (Hits + $normUnit) + tips: + Misses - Non Duplicated: + avg: AVG((SQC_ICACHE_MISSES / $denom)) + min: MIN((SQC_ICACHE_MISSES / $denom)) + max: MAX((SQC_ICACHE_MISSES / $denom)) + unit: (Misses + $normUnit) + tips: + Misses - Duplicated: + avg: AVG((SQC_ICACHE_MISSES_DUPLICATE / $denom)) + min: MIN((SQC_ICACHE_MISSES_DUPLICATE / $denom)) + max: MAX((SQC_ICACHE_MISSES_DUPLICATE / $denom)) + unit: (Misses + $normUnit) + tips: + Cache Hit: + avg: AVG(((100 * SQC_ICACHE_HITS) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + min: MIN(((100 * SQC_ICACHE_HITS) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + max: MAX(((100 * SQC_ICACHE_HITS) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + unit: pct + tips: diff --git a/src/omniperf_soc/configs/gfx906/1400_constant-cache.yaml b/src/omniperf_soc/configs/gfx906/1400_constant-cache.yaml new file mode 100644 index 0000000000..563caad13f --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/1400_constant-cache.yaml @@ -0,0 +1,164 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1400 + title: Scalar L1 Data Cache + data source: + - metric_table: + id: 1401 + title: Speed-of-Light + header: + mertic: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + range_color: [1, 100] + label_txt: (%) + xrange: [0, 110] + metric: + Bandwidth: + value: AVG(((SQC_DCACHE_REQ * 100000) / (($sclk * $numSQC) + * (EndNs - BeginNs)))) + unit: Pct of Peak + tips: + Cache Hit: + value: + AVG((((SQC_DCACHE_HITS * 100) / (SQC_DCACHE_HITS + SQC_DCACHE_MISSES + SQC_DCACHE_MISSES_DUPLICATE)) + if ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + unit: Pct of Peak + tips: + + - metric_table: + id: 1402 + title: Scalar L1D Cache Accesses + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Req: + avg: AVG((SQC_DCACHE_REQ / $denom)) + min: MIN((SQC_DCACHE_REQ / $denom)) + max: MAX((SQC_DCACHE_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Hits: + avg: AVG((SQC_DCACHE_HITS / $denom)) + min: MIN((SQC_DCACHE_HITS / $denom)) + max: MAX((SQC_DCACHE_HITS / $denom)) + unit: (Req + $normUnit) + tips: + Misses - Non Duplicated: + avg: AVG((SQC_DCACHE_MISSES / $denom)) + min: MIN((SQC_DCACHE_MISSES / $denom)) + max: MAX((SQC_DCACHE_MISSES / $denom)) + unit: (Req + $normUnit) + tips: + Misses- Duplicated: + avg: AVG((SQC_DCACHE_MISSES_DUPLICATE / $denom)) + min: MIN((SQC_DCACHE_MISSES_DUPLICATE / $denom)) + max: MAX((SQC_DCACHE_MISSES_DUPLICATE / $denom)) + unit: (Req + $normUnit) + tips: + Cache Hit: + avg: AVG((((100 * SQC_DCACHE_HITS) / ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE)) if (((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + min: MIN((((100 * SQC_DCACHE_HITS) / ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE)) if (((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + max: MAX((((100 * SQC_DCACHE_HITS) / ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE)) if (((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + unit: pct + tips: + Read Req (Total): + avg: AVG((((((SQC_DCACHE_REQ_READ_1 + SQC_DCACHE_REQ_READ_2) + SQC_DCACHE_REQ_READ_4) + + SQC_DCACHE_REQ_READ_8) + SQC_DCACHE_REQ_READ_16) / $denom)) + min: MIN((((((SQC_DCACHE_REQ_READ_1 + SQC_DCACHE_REQ_READ_2) + SQC_DCACHE_REQ_READ_4) + + SQC_DCACHE_REQ_READ_8) + SQC_DCACHE_REQ_READ_16) / $denom)) + max: MAX((((((SQC_DCACHE_REQ_READ_1 + SQC_DCACHE_REQ_READ_2) + SQC_DCACHE_REQ_READ_4) + + SQC_DCACHE_REQ_READ_8) + SQC_DCACHE_REQ_READ_16) / $denom)) + unit: (Req + $normUnit) + tips: + Atomic Req: + avg: AVG((SQC_DCACHE_ATOMIC / $denom)) + min: MIN((SQC_DCACHE_ATOMIC / $denom)) + max: MAX((SQC_DCACHE_ATOMIC / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (1 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_1 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_1 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_1 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (2 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_2 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_2 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_2 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (4 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_4 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_4 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_4 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (8 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_8 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_8 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_8 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (16 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_16 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_16 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_16 / $denom)) + unit: (Req + $normUnit) + tips: + + - metric_table: + id: 1403 + title: Scalar L1D Cache - L2 Interface + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Read Req: + avg: AVG((SQC_TC_DATA_READ_REQ / $denom)) + min: MIN((SQC_TC_DATA_READ_REQ / $denom)) + max: MAX((SQC_TC_DATA_READ_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Write Req: + avg: AVG((SQC_TC_DATA_WRITE_REQ / $denom)) + min: MIN((SQC_TC_DATA_WRITE_REQ / $denom)) + max: MAX((SQC_TC_DATA_WRITE_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Atomic Req: + avg: AVG((SQC_TC_DATA_ATOMIC_REQ / $denom)) + min: MIN((SQC_TC_DATA_ATOMIC_REQ / $denom)) + max: MAX((SQC_TC_DATA_ATOMIC_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Stall: + avg: AVG((SQC_TC_STALL / $denom)) + min: MIN((SQC_TC_STALL / $denom)) + max: MAX((SQC_TC_STALL / $denom)) + unit: (Cycles + $normUnit) + tips: diff --git a/src/omniperf_soc/configs/gfx906/1500_TA_and_TD.yaml b/src/omniperf_soc/configs/gfx906/1500_TA_and_TD.yaml new file mode 100644 index 0000000000..8f71cedc99 --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/1500_TA_and_TD.yaml @@ -0,0 +1,174 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1500 + title: Texture Addresser and Texture Data (TA/TD) + data source: + - metric_table: + id: 1501 + title: TA + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + TA Busy: + avg: AVG(((100 * TA_TA_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TA_TA_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TA_TA_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + TC2TA Addr Stall: + avg: AVG(((100 * TA_ADDR_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TA_ADDR_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TA_ADDR_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + TC2TA Data Stall: + avg: AVG(((100 * TA_DATA_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TA_DATA_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TA_DATA_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + TD2TA Addr Stall: + avg: AVG(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + Total Instructions: + avg: AVG((TA_TOTAL_WAVEFRONTS_sum / $denom)) + min: MIN((TA_TOTAL_WAVEFRONTS_sum / $denom)) + max: MAX((TA_TOTAL_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Flat Instr: + avg: AVG((TA_FLAT_WAVEFRONTS_sum / $denom)) + min: MIN((TA_FLAT_WAVEFRONTS_sum / $denom)) + max: MAX((TA_FLAT_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Flat Read Instr: + avg: AVG((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) + min: MIN((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) + max: MAX((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Flat Write Instr: + avg: AVG((TA_FLAT_WRITE_WAVEFRONTS_sum / $denom)) + min: MIN((TA_FLAT_WRITE_WAVEFRONTS_sum / $denom)) + max: MAX((TA_FLAT_WRITE_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Flat Atomic Instr: + avg: AVG((TA_FLAT_ATOMIC_WAVEFRONTS_sum / $denom)) + min: MIN((TA_FLAT_ATOMIC_WAVEFRONTS_sum / $denom)) + max: MAX((TA_FLAT_ATOMIC_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Buffer Instr: + avg: AVG((TA_BUFFER_WAVEFRONTS_sum / $denom)) + min: MIN((TA_BUFFER_WAVEFRONTS_sum / $denom)) + max: MAX((TA_BUFFER_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Buffer Read Instr: + avg: AVG((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) + min: MIN((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) + max: MAX((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Buffer Write Instr: + avg: AVG((TA_BUFFER_WRITE_WAVEFRONTS_sum / $denom)) + min: MIN((TA_BUFFER_WRITE_WAVEFRONTS_sum / $denom)) + max: MAX((TA_BUFFER_WRITE_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Buffer Atomic Instr: + avg: AVG((TA_BUFFER_ATOMIC_WAVEFRONTS_sum / $denom)) + min: MIN((TA_BUFFER_ATOMIC_WAVEFRONTS_sum / $denom)) + max: MAX((TA_BUFFER_ATOMIC_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Buffer Total Cylces: + avg: AVG((TA_BUFFER_TOTAL_CYCLES_sum / $denom)) + min: MIN((TA_BUFFER_TOTAL_CYCLES_sum / $denom)) + max: MAX((TA_BUFFER_TOTAL_CYCLES_sum / $denom)) + unit: (Cycles + $normUnit) + tips: + Buffer Coalesced Read: + avg: AVG((TA_BUFFER_COALESCED_READ_CYCLES_sum / $denom)) + min: MIN((TA_BUFFER_COALESCED_READ_CYCLES_sum / $denom)) + max: MAX((TA_BUFFER_COALESCED_READ_CYCLES_sum / $denom)) + unit: (Cycles + $normUnit) + tips: + Buffer Coalesced Write: + avg: AVG((TA_BUFFER_COALESCED_WRITE_CYCLES_sum / $denom)) + min: MIN((TA_BUFFER_COALESCED_WRITE_CYCLES_sum / $denom)) + max: MAX((TA_BUFFER_COALESCED_WRITE_CYCLES_sum / $denom)) + unit: (Cycles + $normUnit) + tips: + + - metric_table: + id: 1502 + title: TD + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + TD Busy: + avg: AVG(((100 * TD_TD_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TD_TD_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TD_TD_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + TC2TD Stall: + avg: AVG(((100 * TD_TC_STALL_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TD_TC_STALL_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TD_TC_STALL_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + SPI2TD Stall: + avg: # No perf counter + min: # No perf counter + max: # No perf counter + unit: pct + tips: + Coalescable Instr: + avg: AVG((TD_COALESCABLE_WAVEFRONT_sum / $denom)) + min: MIN((TD_COALESCABLE_WAVEFRONT_sum / $denom)) + max: MAX((TD_COALESCABLE_WAVEFRONT_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Load Instr: + avg: AVG((((TD_LOAD_WAVEFRONT_sum - TD_STORE_WAVEFRONT_sum) - TD_ATOMIC_WAVEFRONT_sum) + / $denom)) + min: MIN((((TD_LOAD_WAVEFRONT_sum - TD_STORE_WAVEFRONT_sum) - TD_ATOMIC_WAVEFRONT_sum) + / $denom)) + max: MAX((((TD_LOAD_WAVEFRONT_sum - TD_STORE_WAVEFRONT_sum) - TD_ATOMIC_WAVEFRONT_sum) + / $denom)) + unit: (Instr + $normUnit) + tips: + Store Instr: + avg: AVG((TD_STORE_WAVEFRONT_sum / $denom)) + min: MIN((TD_STORE_WAVEFRONT_sum / $denom)) + max: MAX((TD_STORE_WAVEFRONT_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Atomic Instr: + avg: AVG((TD_ATOMIC_WAVEFRONT_sum / $denom)) + min: MIN((TD_ATOMIC_WAVEFRONT_sum / $denom)) + max: MAX((TD_ATOMIC_WAVEFRONT_sum / $denom)) + unit: (Instr + $normUnit) + tips: diff --git a/src/omniperf_soc/configs/gfx906/1600_L1_cache.yaml b/src/omniperf_soc/configs/gfx906/1600_L1_cache.yaml new file mode 100644 index 0000000000..01e6d29d71 --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/1600_L1_cache.yaml @@ -0,0 +1,404 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1600 + title: Vector L1 Data Cache + data source: + - metric_table: + id: 1601 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + range_color: [1, 100] + label_txt: (%) + xrange: [0, 110] + metric: + Buffer Coalescing: + value: AVG(((((TA_TOTAL_WAVEFRONTS_sum * 64) * 100) / (TCP_TOTAL_ACCESSES_sum + * 4)) if (TCP_TOTAL_ACCESSES_sum != 0) else None)) + unit: Pct of Peak + tips: + Cache Util: + value: AVG((((TCP_GATE_EN2_sum * 100) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + unit: Pct of Peak + tips: + Cache BW: + value: ((100 * AVG(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs)))) + / ((($sclk / 1000) * 64) * $numCU)) + unit: Pct of Peak + tips: + Cache Hit: + value: AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + unit: Pct of Peak + tips: + + - metric_table: + id: 1602 + title: L1D Cache Stalls + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Stalled on L2 Data: + avg: AVG((((100 * TCP_PENDING_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + min: MIN((((100 * TCP_PENDING_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + max: MAX((((100 * TCP_PENDING_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + unit: pct + tips: + Stalled on L2 Req: + avg: AVG((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + min: MIN((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + max: MAX((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + unit: pct + tips: + Tag RAM Stall (Read): + avg: AVG((((100 * TCP_READ_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + min: MIN((((100 * TCP_READ_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + max: MAX((((100 * TCP_READ_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + unit: pct + tips: + Tag RAM Stall (Write): + avg: AVG((((100 * TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + min: MIN((((100 * TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + max: MAX((((100 * TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + unit: pct + tips: + Tag RAM Stall (Atomic): + avg: AVG((((100 * TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + min: MIN((((100 * TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + max: MAX((((100 * TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + unit: pct + tips: + + - metric_table: + id: 1603 + title: L1D Cache Accesses + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Total Req: + avg: AVG((TCP_TOTAL_ACCESSES_sum / $denom)) + min: MIN((TCP_TOTAL_ACCESSES_sum / $denom)) + max: MAX((TCP_TOTAL_ACCESSES_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read Req: + avg: AVG((TCP_TOTAL_READ_sum / $denom)) + min: MIN((TCP_TOTAL_READ_sum / $denom)) + max: MAX((TCP_TOTAL_READ_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write Req: + avg: AVG((TCP_TOTAL_WRITE_sum / $denom)) + min: MIN((TCP_TOTAL_WRITE_sum / $denom)) + max: MAX((TCP_TOTAL_WRITE_sum / $denom)) + unit: (Req + $normUnit) + tips: + Atomic Req: + avg: AVG(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) + / $denom)) + min: MIN(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) + / $denom)) + max: MAX(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) + / $denom)) + unit: (Req + $normUnit) + tips: + Cache BW: + avg: AVG(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs))) + min: MIN(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs))) + max: MAX(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs))) + unit: GB/s + tips: + Cache Accesses: + avg: AVG((TCP_TOTAL_CACHE_ACCESSES_sum / $denom)) + min: MIN((TCP_TOTAL_CACHE_ACCESSES_sum / $denom)) + max: MAX((TCP_TOTAL_CACHE_ACCESSES_sum / $denom)) + unit: (Req + $normUnit) + tips: + Cache Hits: + avg: AVG(((TCP_TOTAL_CACHE_ACCESSES_sum - (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / $denom)) + min: MIN(((TCP_TOTAL_CACHE_ACCESSES_sum - (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / $denom)) + max: MAX(((TCP_TOTAL_CACHE_ACCESSES_sum - (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / $denom)) + unit: (Req + $normUnit) + tips: + Cache Hit Rate: + avg: AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / + TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + min: MIN(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / + TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + max: MAX(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / + TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + unit: pct + tips: + Invalidate: + avg: AVG((TCP_TOTAL_WRITEBACK_INVALIDATES_sum / $denom)) + min: MIN((TCP_TOTAL_WRITEBACK_INVALIDATES_sum / $denom)) + max: MAX((TCP_TOTAL_WRITEBACK_INVALIDATES_sum / $denom)) + unit: ( + $normUnit) + tips: + L1-L2 BW: + avg: AVG(((64 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / $denom)) + min: AVG(((64 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / $denom)) + max: AVG(((64 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / $denom)) + unit: (Bytes + $normUnit) + tips: + L1-L2 Read: + avg: AVG((TCP_TCC_READ_REQ_sum / $denom)) + min: MIN((TCP_TCC_READ_REQ_sum / $denom)) + max: MAX((TCP_TCC_READ_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + L1-L2 Write: + avg: AVG((TCP_TCC_WRITE_REQ_sum / $denom)) + min: MIN((TCP_TCC_WRITE_REQ_sum / $denom)) + max: MAX((TCP_TCC_WRITE_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + L1-L2 Atomic: + avg: AVG(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + / $denom)) + min: MIN(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + / $denom)) + max: MAX(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + / $denom)) + unit: (Req + $normUnit) + tips: + L1 Access Latency: + avg: AVG(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum + != 0) else None)) + min: MIN(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum + != 0) else None)) + max: MAX(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum + != 0) else None)) + unit: Cycles + tips: + L1-L2 Read Latency: + avg: AVG(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) + if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)) + min: MIN(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) + if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)) + max: MAX(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) + if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)) + unit: Cycles + tips: + L1-L2 Write Latency: + avg: AVG(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) != 0) else + None)) + min: MIN(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) != 0) else + None)) + max: MAX(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) != 0) else + None)) + unit: Cycles + tips: + + - metric_table: + id: 1604 + title: L1D - L2 Transactions + header: + metric: Metric + xfer: Xfer + coherency: Coherency + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + style: + type: simple_multi_bar + metric: + NC - Read: + xfer: Read + coherency: NC + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Req + $normUnit) + tips: + UC - Read: + xfer: Read + coherency: UC + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Req + $normUnit) + tips: + CC - Read: + xfer: Read + coherency: CC + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Req + $normUnit) + tips: + RW - Read: + xfer: Read + coherency: RW + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Req + $normUnit) + tips: + RW - Write: + xfer: Write + coherency: RW + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Req + $normUnit) + tips: + NC - Write: + xfer: Write + coherency: NC + avg: AVG((TCP_TCC_NC_WRITE_REQ_sum / $denom)) + min: MIN((TCP_TCC_NC_WRITE_REQ_sum / $denom)) + max: MAX((TCP_TCC_NC_WRITE_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + CC - Write: + xfer: Write + coherency: CC + avg: AVG((TCP_TCC_CC_WRITE_REQ_sum / $denom)) + min: MIN((TCP_TCC_CC_WRITE_REQ_sum / $denom)) + max: MAX((TCP_TCC_CC_WRITE_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + UC - Write: + xfer: Write + coherency: UC + avg: AVG((TCP_TCC_UC_WRITE_REQ_sum / $denom)) + min: MIN((TCP_TCC_UC_WRITE_REQ_sum / $denom)) + max: MAX((TCP_TCC_UC_WRITE_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + NC - Atomic: + xfer: Atomic + coherency: NC + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Req + $normUnit) + tips: + UC - Atomic: + xfer: Atomic + coherency: UC + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Req + $normUnit) + tips: + CC - Atomic: + xfer: Atomic + coherency: CC + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Req + $normUnit) + tips: + RW - Atomic: + xfer: Atomic + coherency: RW + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Req + $normUnit) + tips: + + - metric_table: + id: 1605 + title: L1D Addr Translation + header: + metric: Metric + avg: Avg + min: Min + max: Max + units: Units + tips: Tips + metric: + Req: + avg: AVG((TCP_UTCL1_REQUEST_sum / $denom)) + min: MIN((TCP_UTCL1_REQUEST_sum / $denom)) + max: MAX((TCP_UTCL1_REQUEST_sum / $denom)) + units: (Req + $normUnit) + tips: + Hit Ratio: + avg: AVG((((100 * TCP_UTCL1_TRANSLATION_HIT_sum) / TCP_UTCL1_REQUEST_sum) if + (TCP_UTCL1_REQUEST_sum != 0) else None)) + min: MIN((((100 * TCP_UTCL1_TRANSLATION_HIT_sum) / TCP_UTCL1_REQUEST_sum) if + (TCP_UTCL1_REQUEST_sum != 0) else None)) + max: MAX((((100 * TCP_UTCL1_TRANSLATION_HIT_sum) / TCP_UTCL1_REQUEST_sum) if + (TCP_UTCL1_REQUEST_sum != 0) else None)) + units: pct + tips: + Hits: + avg: AVG((TCP_UTCL1_TRANSLATION_HIT_sum / $denom)) + min: MIN((TCP_UTCL1_TRANSLATION_HIT_sum / $denom)) + max: MAX((TCP_UTCL1_TRANSLATION_HIT_sum / $denom)) + units: (Hits + $normUnit) + tips: + Misses (Translation): + avg: AVG((TCP_UTCL1_TRANSLATION_MISS_sum / $denom)) + min: MIN((TCP_UTCL1_TRANSLATION_MISS_sum / $denom)) + max: MAX((TCP_UTCL1_TRANSLATION_MISS_sum / $denom)) + units: (Misses + $normUnit) + tips: + Misses (Permission): + avg: AVG((TCP_UTCL1_PERMISSION_MISS_sum / $denom)) + min: MIN((TCP_UTCL1_PERMISSION_MISS_sum / $denom)) + max: MAX((TCP_UTCL1_PERMISSION_MISS_sum / $denom)) + units: (Misses + $normUnit) + tips: diff --git a/src/omniperf_soc/configs/gfx906/1700_L2_cache.yaml b/src/omniperf_soc/configs/gfx906/1700_L2_cache.yaml new file mode 100644 index 0000000000..0b5f5e827a --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/1700_L2_cache.yaml @@ -0,0 +1,364 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1700 + title: L2 Cache + data source: + - metric_table: + id: 1701 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + metric: + L2 Util: + value: AVG(((TCC_BUSY_sum * 100) / (TO_INT($L2Banks) * GRBM_GUI_ACTIVE))) + unit: pct + tips: + Cache Hit: + value: AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else 0)) + unit: pct + tips: + L2-EA Rd BW: + value: AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / (EndNs - BeginNs))) + unit: GB/s + tips: + L2-EA Wr BW: + value: AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / (EndNs - BeginNs))) + unit: GB/s + tips: + + - metric_table: + id: 1702 + title: L2 - Fabric Transactions + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Read BW: + avg: AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / $denom)) + min: MIN((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / $denom)) + max: MAX((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / $denom)) + unit: (Bytes + $normUnit) + tips: + Write BW: + avg: AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / $denom)) + min: MIN((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / $denom)) + max: MAX((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / $denom)) + unit: (Bytes + $normUnit) + tips: + Read (32B): + avg: AVG((TCC_EA_RDREQ_32B_sum / $denom)) + min: MIN((TCC_EA_RDREQ_32B_sum / $denom)) + max: MAX((TCC_EA_RDREQ_32B_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read (Uncached 32B): + avg: AVG((TCC_EA_RD_UNCACHED_32B_sum / $denom)) + min: MIN((TCC_EA_RD_UNCACHED_32B_sum / $denom)) + max: MAX((TCC_EA_RD_UNCACHED_32B_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read (64B): + avg: AVG(((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) / $denom)) + min: MIN(((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) / $denom)) + max: MAX(((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) / $denom)) + unit: (Req + $normUnit) + tips: + HBM Read: + avg: AVG((TCC_EA_RDREQ_DRAM_sum / $denom)) + min: MIN((TCC_EA_RDREQ_DRAM_sum / $denom)) + max: MAX((TCC_EA_RDREQ_DRAM_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write (32B): + avg: AVG(((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) / $denom)) + min: MIN(((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) / $denom)) + max: MAX(((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) / $denom)) + unit: (Req + $normUnit) + tips: + Write (Uncached 32B): + avg: AVG((TCC_EA_WR_UNCACHED_32B_sum / $denom)) + min: MIN((TCC_EA_WR_UNCACHED_32B_sum / $denom)) + max: MAX((TCC_EA_WR_UNCACHED_32B_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write (64B): + avg: AVG((TCC_EA_WRREQ_64B_sum / $denom)) + min: MIN((TCC_EA_WRREQ_64B_sum / $denom)) + max: MAX((TCC_EA_WRREQ_64B_sum / $denom)) + unit: (Req + $normUnit) + tips: + HBM Write: + avg: AVG((TCC_EA_WRREQ_DRAM_sum / $denom)) + min: MIN((TCC_EA_WRREQ_DRAM_sum / $denom)) + max: MAX((TCC_EA_WRREQ_DRAM_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read Latency: + avg: AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum != + 0) else None)) + min: MIN(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum != + 0) else None)) + max: MAX(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum != + 0) else None)) + unit: Cycles + tips: + Write Latency: + avg: AVG(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum != + 0) else None)) + min: MIN(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum != + 0) else None)) + max: MAX(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum != + 0) else None)) + unit: Cycles + tips: + Atomic Latency: + avg: AVG(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum + != 0) else None)) + min: MIN(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum + != 0) else None)) + max: MAX(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum + != 0) else None)) + unit: Cycles + tips: + Read Stall: + avg: AVG((((100 * ((TCC_EA_RDREQ_IO_CREDIT_STALL_sum + TCC_EA_RDREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + min: MIN((((100 * ((TCC_EA_RDREQ_IO_CREDIT_STALL_sum + TCC_EA_RDREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + max: MAX((((100 * ((TCC_EA_RDREQ_IO_CREDIT_STALL_sum + TCC_EA_RDREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + unit: pct + tips: + Write Stall: + avg: AVG((((100 * ((TCC_EA_WRREQ_IO_CREDIT_STALL_sum + TCC_EA_WRREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + min: MIN((((100 * ((TCC_EA_WRREQ_IO_CREDIT_STALL_sum + TCC_EA_WRREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + max: MAX((((100 * ((TCC_EA_WRREQ_IO_CREDIT_STALL_sum + TCC_EA_WRREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + unit: pct + tips: + + - metric_table: + id: 1703 + title: L2 Cache Accesses + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Req: + avg: AVG((TCC_REQ_sum / $denom)) + min: MIN((TCC_REQ_sum / $denom)) + max: MAX((TCC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + Streaming Req: + avg: AVG((TCC_STREAMING_REQ_sum / $denom)) + min: MIN((TCC_STREAMING_REQ_sum / $denom)) + max: MAX((TCC_STREAMING_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read Req: + avg: AVG((TCC_READ_sum / $denom)) + min: MIN((TCC_READ_sum / $denom)) + max: MAX((TCC_READ_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write Req: + avg: AVG((TCC_WRITE_sum / $denom)) + min: MIN((TCC_WRITE_sum / $denom)) + max: MAX((TCC_WRITE_sum / $denom)) + unit: (Req + $normUnit) + tips: + Atomic Req: + avg: AVG((TCC_ATOMIC_sum / $denom)) + min: MIN((TCC_ATOMIC_sum / $denom)) + max: MAX((TCC_ATOMIC_sum / $denom)) + unit: (Req + $normUnit) + tips: + Probe Req: + avg: AVG((TCC_PROBE_sum / $denom)) + min: MIN((TCC_PROBE_sum / $denom)) + max: MAX((TCC_PROBE_sum / $denom)) + unit: (Req + $normUnit) + tips: + Hits: + avg: AVG((TCC_HIT_sum / $denom)) + min: MIN((TCC_HIT_sum / $denom)) + max: MAX((TCC_HIT_sum / $denom)) + unit: (Hits + $normUnit) + tips: + Misses: + avg: AVG((TCC_MISS_sum / $denom)) + min: MIN((TCC_MISS_sum / $denom)) + max: MAX((TCC_MISS_sum / $denom)) + unit: (Misses + $normUnit) + tips: + Cache Hit: + avg: AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + min: MIN((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + max: MAX((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + unit: pct + tips: + Writeback: + avg: AVG((TCC_WRITEBACK_sum / $denom)) + min: MIN((TCC_WRITEBACK_sum / $denom)) + max: MAX((TCC_WRITEBACK_sum / $denom)) + unit: ( + $normUnit) + tips: + NC Req: + avg: AVG((TCC_NC_REQ_sum / $denom)) + min: MIN((TCC_NC_REQ_sum / $denom)) + max: MAX((TCC_NC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + UC Req: + avg: AVG((TCC_UC_REQ_sum / $denom)) + min: MIN((TCC_UC_REQ_sum / $denom)) + max: MAX((TCC_UC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + CC Req: + avg: AVG((TCC_CC_REQ_sum / $denom)) + min: MIN((TCC_CC_REQ_sum / $denom)) + max: MAX((TCC_CC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + RW Req: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (Req + $normUnit) + tips: + Writeback (Normal): + avg: AVG((TCC_NORMAL_WRITEBACK_sum / $denom)) + min: MIN((TCC_NORMAL_WRITEBACK_sum / $denom)) + max: MAX((TCC_NORMAL_WRITEBACK_sum / $denom)) + unit: ( + $normUnit) + tips: + Writeback (TC Req): + avg: AVG((TCC_ALL_TC_OP_WB_WRITEBACK_sum / $denom)) + min: MIN((TCC_ALL_TC_OP_WB_WRITEBACK_sum / $denom)) + max: MAX((TCC_ALL_TC_OP_WB_WRITEBACK_sum / $denom)) + unit: ( + $normUnit) + tips: + Evict (Normal): + avg: AVG((TCC_NORMAL_EVICT_sum / $denom)) + min: MIN((TCC_NORMAL_EVICT_sum / $denom)) + max: MAX((TCC_NORMAL_EVICT_sum / $denom)) + unit: ( + $normUnit) + tips: + Evict (TC Req): + avg: AVG((TCC_ALL_TC_OP_INV_EVICT_sum / $denom)) + min: MIN((TCC_ALL_TC_OP_INV_EVICT_sum / $denom)) + max: MAX((TCC_ALL_TC_OP_INV_EVICT_sum / $denom)) + unit: ( + $normUnit) + tips: + + - metric_table: + id: 1704 + title: L2 - EA Interface Stalls + header: + metric: Metric + type: Type + transaction: Transaction + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + style: + type: simple_multi_bar + metric: + Read - Remote Socket Stall: + type: Remote Socket Stall + transaction: Read + avg: AVG((TCC_EA_RDREQ_IO_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_RDREQ_IO_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_RDREQ_IO_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read - Peer GCD Stall: + type: Peer GCD Stall + transaction: Read + avg: AVG((TCC_EA_RDREQ_GMI_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_RDREQ_GMI_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_RDREQ_GMI_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read - HBM Stall: + type: HBM Stall + transaction: Read + avg: AVG((TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write - Remote Socket Stall: + type: Remote Socket Stall + transaction: Write + avg: AVG((TCC_EA_WRREQ_IO_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_WRREQ_IO_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_WRREQ_IO_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write - Peer GCD Stall: + type: Peer GCD Stall + transaction: Write + avg: AVG((TCC_EA_WRREQ_GMI_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_WRREQ_GMI_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_WRREQ_GMI_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write - HBM Stall: + type: HBM Stall + transaction: Write + avg: AVG((TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write - Credit Starvation: + type: Credit Starvation + transaction: Write + avg: AVG((TCC_TOO_MANY_EA_WRREQS_STALL_sum / $denom)) + min: MIN((TCC_TOO_MANY_EA_WRREQS_STALL_sum / $denom)) + max: MAX((TCC_TOO_MANY_EA_WRREQS_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: diff --git a/src/omniperf_soc/configs/gfx906/1800_L2_cache_per_channel.yaml b/src/omniperf_soc/configs/gfx906/1800_L2_cache_per_channel.yaml new file mode 100644 index 0000000000..7a808c5b82 --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/1800_L2_cache_per_channel.yaml @@ -0,0 +1,1721 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1800 + title: L2 Cache (per Channel) + data source: + - metric_table: + id: 1801 + title: Aggregate Stats (All 32 channels) + header: + metric: Metric + avg: Mean + std dev: Std Dev + min: Min + max: Max + unit: Unit + tips: Tips + metric: + L2 Cache Hit Rate: + avg: AVG(((((((((((((((((((((((((((((((((((100 * TCC_HIT[0]) + (100 * TCC_HIT[1])) + + (100 * TCC_HIT[2])) + (100 * TCC_HIT[3])) + (100 * TCC_HIT[4])) + (100 * + TCC_HIT[5])) + (100 * TCC_HIT[6])) + (100 * TCC_HIT[7])) + (100 * TCC_HIT[8])) + + (100 * TCC_HIT[9])) + (100 * TCC_HIT[10])) + (100 * TCC_HIT[11])) + (100 + * TCC_HIT[12])) + (100 * TCC_HIT[13])) + (100 * TCC_HIT[14])) + (100 * TCC_HIT[15])) + + (100 * TCC_HIT[16])) + (100 * TCC_HIT[17])) + (100 * TCC_HIT[18])) + (100 + * TCC_HIT[19])) + (100 * TCC_HIT[20])) + (100 * TCC_HIT[21])) + (100 * TCC_HIT[22])) + + (100 * TCC_HIT[23])) + (100 * TCC_HIT[24])) + (100 * TCC_HIT[25])) + (100 + * TCC_HIT[26])) + (100 * TCC_HIT[27])) + (100 * TCC_HIT[28])) + (100 * TCC_HIT[29])) + + (100 * TCC_HIT[30])) + (100 * TCC_HIT[31])) / ((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31]))) if (((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[29] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31])) != 0) else None)) + std dev: STD(((((((((((((((((((((((((((((((((((100 * TCC_HIT[0]) + (100 * TCC_HIT[1])) + + (100 * TCC_HIT[2])) + (100 * TCC_HIT[3])) + (100 * TCC_HIT[4])) + (100 * + TCC_HIT[5])) + (100 * TCC_HIT[6])) + (100 * TCC_HIT[7])) + (100 * TCC_HIT[8])) + + (100 * TCC_HIT[9])) + (100 * TCC_HIT[10])) + (100 * TCC_HIT[11])) + (100 + * TCC_HIT[12])) + (100 * TCC_HIT[13])) + (100 * TCC_HIT[14])) + (100 * TCC_HIT[15])) + + (100 * TCC_HIT[16])) + (100 * TCC_HIT[17])) + (100 * TCC_HIT[18])) + (100 + * TCC_HIT[19])) + (100 * TCC_HIT[20])) + (100 * TCC_HIT[21])) + (100 * TCC_HIT[22])) + + (100 * TCC_HIT[23])) + (100 * TCC_HIT[24])) + (100 * TCC_HIT[25])) + (100 + * TCC_HIT[26])) + (100 * TCC_HIT[27])) + (100 * TCC_HIT[28])) + (100 * TCC_HIT[29])) + + (100 * TCC_HIT[30])) + (100 * TCC_HIT[31])) / ((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31]))) if (((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31])) != 0) else None)) + min: MIN(((((((((((((((((((((((((((((((((((100 * TCC_HIT[0]) + (100 * TCC_HIT[1])) + + (100 * TCC_HIT[2])) + (100 * TCC_HIT[3])) + (100 * TCC_HIT[4])) + (100 * + TCC_HIT[5])) + (100 * TCC_HIT[6])) + (100 * TCC_HIT[7])) + (100 * TCC_HIT[8])) + + (100 * TCC_HIT[9])) + (100 * TCC_HIT[10])) + (100 * TCC_HIT[11])) + (100 + * TCC_HIT[12])) + (100 * TCC_HIT[13])) + (100 * TCC_HIT[14])) + (100 * TCC_HIT[15])) + + (100 * TCC_HIT[16])) + (100 * TCC_HIT[17])) + (100 * TCC_HIT[18])) + (100 + * TCC_HIT[19])) + (100 * TCC_HIT[20])) + (100 * TCC_HIT[21])) + (100 * TCC_HIT[22])) + + (100 * TCC_HIT[23])) + (100 * TCC_HIT[24])) + (100 * TCC_HIT[25])) + (100 + * TCC_HIT[26])) + (100 * TCC_HIT[27])) + (100 * TCC_HIT[28])) + (100 * TCC_HIT[29])) + + (100 * TCC_HIT[30])) + (100 * TCC_HIT[31])) / ((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31]))) if (((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31])) != 0) else None)) + max: MAX(((((((((((((((((((((((((((((((((((100 * TCC_HIT[0]) + (100 * TCC_HIT[1])) + + (100 * TCC_HIT[2])) + (100 * TCC_HIT[3])) + (100 * TCC_HIT[4])) + (100 * + TCC_HIT[5])) + (100 * TCC_HIT[6])) + (100 * TCC_HIT[7])) + (100 * TCC_HIT[8])) + + (100 * TCC_HIT[9])) + (100 * TCC_HIT[10])) + (100 * TCC_HIT[11])) + (100 + * TCC_HIT[12])) + (100 * TCC_HIT[13])) + (100 * TCC_HIT[14])) + (100 * TCC_HIT[15])) + + (100 * TCC_HIT[16])) + (100 * TCC_HIT[17])) + (100 * TCC_HIT[18])) + (100 + * TCC_HIT[19])) + (100 * TCC_HIT[20])) + (100 * TCC_HIT[21])) + (100 * TCC_HIT[22])) + + (100 * TCC_HIT[23])) + (100 * TCC_HIT[24])) + (100 * TCC_HIT[25])) + (100 + * TCC_HIT[26])) + (100 * TCC_HIT[27])) + (100 * TCC_HIT[28])) + (100 * TCC_HIT[29])) + + (100 * TCC_HIT[30])) + (100 * TCC_HIT[31])) / ((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31]))) if (((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31])) != 0) else None)) + unit: pct + tips: + Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) + + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) + + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) + + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) + + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) + + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) + + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) + + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) + + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) + + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) + + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) + + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) + + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) + + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) + + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) + + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) + + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) + + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) + + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) + + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) + + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) + + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) + + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) + + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) + + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) + + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) + + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) + + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) + + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) + + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) + + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) + + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) + + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L1 - L2 Read Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) + + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) + + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) + + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + + TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) + + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + + TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) + + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + + TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) + + TO_INT(TCC_READ[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) + + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) + + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) + + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + + TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) + + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + + TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) + + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + + TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) + + TO_INT(TCC_READ[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) + + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) + + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) + + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + + TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) + + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + + TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) + + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + + TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) + + TO_INT(TCC_READ[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) + + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) + + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) + + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + + TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) + + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + + TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) + + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + + TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) + + TO_INT(TCC_READ[31])) / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L1 - L2 Write Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) + + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + + TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) + + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) + + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) + + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) + + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) + + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) + + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) + + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) + + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) + + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + + TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) + + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) + + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) + + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) + + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) + + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) + + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) + + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) + + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) + + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + + TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) + + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) + + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) + + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) + + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) + + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) + + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) + + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) + + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) + + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + + TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) + + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) + + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) + + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) + + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) + + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) + + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) + + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) + + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L1 - L2 Atomic Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) + + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) + + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) + + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) + + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) + + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) + + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) + + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) + + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) + + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) + + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) + / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) + + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) + + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) + + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) + + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) + + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) + + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) + + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) + + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) + + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) + + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) + / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) + + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) + + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) + + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) + + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) + + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) + + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) + + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) + + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) + + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) + + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) + / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) + + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) + + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) + + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) + + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) + + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) + + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) + + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) + + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) + + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) + + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) + / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L2 - EA Read Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) + + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) + + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) + + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) + + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) + + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) + + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) + + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) + + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) + + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) + + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) + / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) + + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) + + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) + + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) + + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) + + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) + + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) + + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) + + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) + + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) + + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) + / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) + + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) + + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) + + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) + + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) + + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) + + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) + + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) + + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) + + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) + + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) + / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) + + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) + + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) + + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) + + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) + + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) + + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) + + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) + + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) + + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) + + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) + / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L2 - EA Write Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) + + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) + + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) + + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) + + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) + + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) + + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) + + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) + + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) + + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) + + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) + / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) + + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) + + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) + + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) + + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) + + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) + + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) + + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) + + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) + + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) + + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) + / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) + + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) + + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) + + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) + + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) + + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) + + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) + + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) + + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) + + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) + + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) + / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) + + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) + + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) + + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) + + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) + + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) + + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) + + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) + + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) + + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) + + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) + / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L2 - EA Atomic Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) + + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) + + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) + + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) + + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) + + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) + + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) + + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) + + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) + + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) + + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) + / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) + + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) + + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) + + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) + + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) + + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) + + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) + + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) + + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) + + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) + + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) + / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) + + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) + + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) + + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) + + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) + + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) + + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) + + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) + + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) + + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) + + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) + / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) + + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) + + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) + + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) + + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) + + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) + + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) + + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) + + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) + + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) + + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) + / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L2 - EA Read Lat: + avg: AVG((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) + + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) + + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) + + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) + + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) + + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) + + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) + + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) + + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) + + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) + + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) + std dev: STD((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) + + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) + + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) + + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) + + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) + + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) + + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) + + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) + + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) + + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) + + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) + min: MIN((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) + + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) + + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) + + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) + + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) + + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) + + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) + + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) + + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) + + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) + + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) + max: MAX((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) + + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) + + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) + + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) + + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) + + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) + + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) + + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) + + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) + + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) + + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) + unit: Cycles + tips: + L2 - EA Write Lat: + avg: AVG((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) + + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) + + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) + + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) + + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) + + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) + + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) + + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) + + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) + + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) + + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) + std dev: STD((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) + + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) + + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) + + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) + + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) + + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) + + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) + + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) + + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) + + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) + + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) + min: MIN((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) + + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) + + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) + + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) + + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) + + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) + + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) + + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) + + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) + + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) + + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) + max: MAX((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) + + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) + + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) + + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) + + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) + + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) + + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) + + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) + + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) + + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) + + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) + unit: Cycles + tips: + L2 - EA Atomic Lat: + avg: AVG((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) + + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) + + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) + + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) + + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) + + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) + + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) + + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) + + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) + + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) + + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else + None)) + std dev: STD((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) + + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) + + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) + + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) + + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) + + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) + + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) + + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) + + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) + + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) + + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else + None)) + min: MIN((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) + + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) + + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) + + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) + + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) + + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) + + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) + + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) + + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) + + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) + + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else + None)) + max: MAX((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) + + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) + + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) + + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) + + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) + + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) + + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) + + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) + + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) + + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) + + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else + None)) + unit: Cycles + tips: + L2 - EA Read Stall (IO): + avg: None # No perf counter + std dev: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Cycles + $normUnit) + tips: + L2 - EA Read Stall (GMI): + avg: None # No perf counter + std dev: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Cycles + $normUnit) + tips: + L2 - EA Read Stall (DRAM): + avg: None # No perf counter + std dev: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Cycles + $normUnit) + tips: + L2 - EA Write Stall (IO): + avg: None # No perf counter + std dev: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Cycles + $normUnit) + tips: + L2 - EA Write Stall (GMI): + avg: None # No perf counter + std dev: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Cycles + $normUnit) + tips: + L2 - EA Write Stall (DRAM): + avg: None # No perf counter + std dev: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Cycles + $normUnit) + tips: + L2 - EA Write Starve: + avg: None # No perf counter + std dev: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (Cycles + $normUnit) + tips: + - metric_table: + id: 1802 + title: Channel 0-15 + columnwise: True + header: + channel: Channel + hit rate: L2 Cache Hit Rate (%) + req: Requests (Requests) + read req: L1-L2 Read (Requests) + write req: L1-L2 Write (Requests) + atomic req: L1-L2 Atomic (Requests) + ea read req: L2-EA Read (Requests) + ea write req: L2-EA Write (Requests) + ea atomic req: L2-EA Atomic (Requests) + ea read lat - cycles: L2-EA Read Latency (Cycles) + ea write lat - cycles: L2-EA Write Latency (Cycles) + ea atomic lat - cycles: L2-EA Atomic Latency (Cycles) + ea read stall - io: L2-EA Read Stall - IO (Cycles per) + ea read stall - gmi: L2-EA Read Stall - GMI (Cycles per) + ea read stall - dram: L2-EA Read Stall - DRAM (Cycles per) + ea write stall - io: L2-EA Write Stall - IO (Cycles per) + ea write stall - gmi: L2-EA Write Stall - GMI (Cycles per) + ea write stall - dram: L2-EA Write Stall - DRAM (Cycles per) + ea write stall - starve: L2-EA Write Stall - Starve (Cycles per) + tips: Tips + metric: + "0": + hit rate: + AVG((((100 * TCC_HIT[0]) / (TCC_HIT[0] + TCC_MISS[0])) if ((TCC_HIT[0] + + TCC_MISS[0]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[0]) / $denom)) + read req: AVG((TO_INT(TCC_READ[0]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[0]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[0]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[0]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[0]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[0]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[0] / TCC_EA_RDREQ[0]) if (TCC_EA_RDREQ[0] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[0] / TCC_EA_WRREQ[0]) if (TCC_EA_WRREQ[0] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[0] / TCC_EA_ATOMIC[0]) if + (TCC_EA_ATOMIC[0] != 0) else 0)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "1": + hit rate: + AVG((((100 * TCC_HIT[1]) / (TCC_HIT[1] + TCC_MISS[1])) if ((TCC_HIT[1] + + TCC_MISS[1]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[1]) / $denom)) + read req: AVG((TO_INT(TCC_READ[1]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[1]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[1]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[1]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[1]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[1]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[1] / TCC_EA_RDREQ[1]) if (TCC_EA_RDREQ[1] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[1] / TCC_EA_WRREQ[1]) if (TCC_EA_WRREQ[1] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[1] / TCC_EA_ATOMIC[1]) if + (TCC_EA_ATOMIC[1] != 0) else None)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "2": + hit rate: + AVG((((100 * TCC_HIT[2]) / (TCC_HIT[2] + TCC_MISS[2])) if ((TCC_HIT[2] + + TCC_MISS[2]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[2]) / $denom)) + read req: AVG((TO_INT(TCC_READ[2]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[2]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[2]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[2]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[2]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[2]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[2] / TCC_EA_RDREQ[2]) if (TCC_EA_RDREQ[2] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[2] / TCC_EA_WRREQ[2]) if (TCC_EA_WRREQ[2] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[2] / TCC_EA_ATOMIC[2]) if + (TCC_EA_ATOMIC[2] != 0) else None)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "3": + hit rate: + AVG((((100 * TCC_HIT[3]) / (TCC_HIT[3] + TCC_MISS[3])) if ((TCC_HIT[3] + + TCC_MISS[3]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[3]) / $denom)) + read req: AVG((TO_INT(TCC_READ[3]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[3]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[3]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[3]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[3]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[3]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[3] / TCC_EA_RDREQ[3]) if (TCC_EA_RDREQ[3] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[3] / TCC_EA_WRREQ[3]) if (TCC_EA_WRREQ[3] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[3] / TCC_EA_ATOMIC[3]) if + (TCC_EA_ATOMIC[3] != 0) else None)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "4": + hit rate: + AVG((((100 * TCC_HIT[4]) / (TCC_HIT[4] + TCC_MISS[4])) if ((TCC_HIT[4] + + TCC_MISS[4]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[4]) / $denom)) + read req: AVG((TO_INT(TCC_READ[4]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[4]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[4]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[4]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[4]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[4]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[4] / TCC_EA_RDREQ[4]) if (TCC_EA_RDREQ[4] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[4] / TCC_EA_WRREQ[4]) if (TCC_EA_WRREQ[4] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[4] / TCC_EA_ATOMIC[4]) if + (TCC_EA_ATOMIC[4] != 0) else None)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "5": + hit rate: + AVG((((100 * TCC_HIT[5]) / (TCC_HIT[5] + TCC_MISS[5])) if ((TCC_HIT[5] + + TCC_MISS[5]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[5]) / $denom)) + read req: AVG((TO_INT(TCC_READ[5]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[5]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[5]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[5]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[5]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[5]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[5] / TCC_EA_RDREQ[5]) if (TCC_EA_RDREQ[5] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[5] / TCC_EA_WRREQ[5]) if (TCC_EA_WRREQ[5] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[5] / TCC_EA_ATOMIC[5]) if + (TCC_EA_ATOMIC[5] != 0) else None)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "6": + hit rate: + AVG((((100 * TCC_HIT[6]) / (TCC_HIT[6] + TCC_MISS[6])) if ((TCC_HIT[6] + + TCC_MISS[6]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[6]) / $denom)) + read req: AVG((TO_INT(TCC_READ[6]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[6]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[6]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[6]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[6]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[6]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[6] / TCC_EA_RDREQ[6]) if (TCC_EA_RDREQ[6] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[6] / TCC_EA_WRREQ[6]) if (TCC_EA_WRREQ[6] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[6] / TCC_EA_ATOMIC[6]) if + (TCC_EA_ATOMIC[6] != 0) else None)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "7": + hit rate: + AVG((((100 * TCC_HIT[7]) / (TCC_HIT[7] + TCC_MISS[7])) if ((TCC_HIT[7] + + TCC_MISS[7]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[7]) / $denom)) + read req: AVG((TO_INT(TCC_READ[7]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[7]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[7]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[7]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[7]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[7]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[7] / TCC_EA_RDREQ[7]) if (TCC_EA_RDREQ[7] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[7] / TCC_EA_WRREQ[7]) if (TCC_EA_WRREQ[7] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[7] / TCC_EA_ATOMIC[7]) if + (TCC_EA_ATOMIC[7] != 0) else None)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "8": + hit rate: + AVG((((100 * TCC_HIT[8]) / (TCC_HIT[8] + TCC_MISS[8])) if ((TCC_HIT[8] + + TCC_MISS[8]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[8]) / $denom)) + read req: AVG((TO_INT(TCC_READ[8]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[8]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[8]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[8]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[8]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[8]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[8] / TCC_EA_RDREQ[8]) if (TCC_EA_RDREQ[8] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[8] / TCC_EA_WRREQ[8]) if (TCC_EA_WRREQ[8] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[8] / TCC_EA_ATOMIC[8]) if + (TCC_EA_ATOMIC[8] != 0) else None)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "9": + hit rate: + AVG((((100 * TCC_HIT[9]) / (TCC_HIT[9] + TCC_MISS[9])) if ((TCC_HIT[9] + + TCC_MISS[9]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[9]) / $denom)) + read req: AVG((TO_INT(TCC_READ[9]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[9]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[9]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[9]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[9]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[9]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[9] / TCC_EA_RDREQ[9]) if (TCC_EA_RDREQ[9] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[9] / TCC_EA_WRREQ[9]) if (TCC_EA_WRREQ[9] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[9] / TCC_EA_ATOMIC[9]) if + (TCC_EA_ATOMIC[9] != 0) else None)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "10": + hit rate: + AVG((((100 * TCC_HIT[10]) / (TCC_HIT[10] + TCC_MISS[10])) if ((TCC_HIT[10] + + TCC_MISS[10]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[10]) / $denom)) + read req: AVG((TO_INT(TCC_READ[10]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[10]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[10]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[10]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[10]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[10]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[10] / TCC_EA_RDREQ[10]) if (TCC_EA_RDREQ[10] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[10] / TCC_EA_WRREQ[10]) if (TCC_EA_WRREQ[10] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[10] / TCC_EA_ATOMIC[10]) if + (TCC_EA_ATOMIC[10] != 0) else None)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "11": + hit rate: + AVG((((100 * TCC_HIT[11]) / (TCC_HIT[11] + TCC_MISS[11])) if ((TCC_HIT[11] + + TCC_MISS[11]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[11]) / $denom)) + read req: AVG((TO_INT(TCC_READ[11]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[11]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[11]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[11]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[11]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[11]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[11] / TCC_EA_RDREQ[11]) if (TCC_EA_RDREQ[11] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[11] / TCC_EA_WRREQ[11]) if (TCC_EA_WRREQ[11] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[11] / TCC_EA_ATOMIC[11]) if + (TCC_EA_ATOMIC[11] != 0) else None)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "12": + hit rate: + AVG((((100 * TCC_HIT[12]) / (TCC_HIT[12] + TCC_MISS[12])) if ((TCC_HIT[12] + + TCC_MISS[12]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[12]) / $denom)) + read req: AVG((TO_INT(TCC_READ[12]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[12]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[12]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[12]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[12]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[12]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[12] / TCC_EA_RDREQ[12]) if (TCC_EA_RDREQ[12] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[12] / TCC_EA_WRREQ[12]) if (TCC_EA_WRREQ[12] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[12] / TCC_EA_ATOMIC[12]) if + (TCC_EA_ATOMIC[12] != 0) else None)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "13": + hit rate: + AVG((((100 * TCC_HIT[13]) / (TCC_HIT[13] + TCC_MISS[13])) if ((TCC_HIT[13] + + TCC_MISS[13]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[13]) / $denom)) + read req: AVG((TO_INT(TCC_READ[13]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[13]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[13]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[13]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[13]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[13]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[13] / TCC_EA_RDREQ[13]) if (TCC_EA_RDREQ[13] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[13] / TCC_EA_WRREQ[13]) if (TCC_EA_WRREQ[13] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[13] / TCC_EA_ATOMIC[13]) if + (TCC_EA_ATOMIC[13] != 0) else None)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "14": + hit rate: + AVG((((100 * TCC_HIT[14]) / (TCC_HIT[14] + TCC_MISS[14])) if ((TCC_HIT[14] + + TCC_MISS[14]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[14]) / $denom)) + read req: AVG((TO_INT(TCC_READ[14]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[14]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[14]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[14]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[14]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[14]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[14] / TCC_EA_RDREQ[14]) if (TCC_EA_RDREQ[14] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[14] / TCC_EA_WRREQ[14]) if (TCC_EA_WRREQ[14] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[14] / TCC_EA_ATOMIC[14]) if + (TCC_EA_ATOMIC[14] != 0) else None)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "15": + hit rate: + AVG((((100 * TCC_HIT[15]) / (TCC_HIT[15] + TCC_MISS[15])) if ((TCC_HIT[15] + + TCC_MISS[15]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[15]) / $denom)) + read req: AVG((TO_INT(TCC_READ[15]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[15]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[15]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[15]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[15]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[15]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[15] / TCC_EA_RDREQ[15]) if (TCC_EA_RDREQ[15] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[15] / TCC_EA_WRREQ[15]) if (TCC_EA_WRREQ[15] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[15] / TCC_EA_ATOMIC[15]) if + (TCC_EA_ATOMIC[15] != 0) else None)) + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + + - metric_table: + id: 1803 + title: Channel 16-31 + columnwise: True + header: + channel: Channel + hit rate: L2 Cache Hit Rate (%) + req: Requests (Requests) + read req: L1-L2 Read (Requests) + write req: L1-L2 Write (Requests) + atomic req: L1-L2 Atomic (Requests) + ea read req: L2-EA Read (Requests) + ea write req: L2-EA Write (Requests) + ea atomic req: L2-EA Atomic (Requests) + ea read lat - cycles: L2-EA Read Latency (Cycles) + ea write lat - cycles: L2-EA Write Latency (Cycles) + ea atomic lat - cycles: L2-EA Atomic Latency (Cycles) + ea read stall - io: L2-EA Read Stall - IO (Cycles per) + ea read stall - gmi: L2-EA Read Stall - GMI (Cycles per) + ea read stall - dram: L2-EA Read Stall - DRAM (Cycles per) + ea write stall - io: L2-EA Write Stall - IO (Cycles per) + ea write stall - gmi: L2-EA Write Stall - GMI (Cycles per) + ea write stall - dram: L2-EA Write Stall - DRAM (Cycles per) + ea write stall - starve: L2-EA Write Stall - Starve (Cycles per) + tips: Tips + metric: + "16": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "17": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "18": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "19": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "20": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "21": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "22": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "23": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "24": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "25": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "26": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "27": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "28": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "29": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "30": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: + "31": + hit rate: None # No perf counter + req: None # No perf counter + read req: None # No perf counter + write req: None # No perf counter + atomic req: None # No perf counter + ea read req: None # No perf counter + ea write req: None # No perf counter + ea atomic req: None # No perf counter + ea read lat - cycles: None # No perf counter + ea write lat - cycles: None # No perf counter + ea atomic lat - cycles: None # No perf counter + ea read stall - io: None # No perf counter + ea read stall - gmi: None # No perf counter + ea read stall - dram: None # No perf counter + ea write stall - io: None # No perf counter + ea write stall - gmi: None # No perf counter + ea write stall - dram: None # No perf counter + ea write stall - starve: None # No perf counter + tips: diff --git a/src/omniperf_soc/configs/gfx906/1900_memory_chart.yaml b/src/omniperf_soc/configs/gfx906/1900_memory_chart.yaml new file mode 100644 index 0000000000..905204601d --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/1900_memory_chart.yaml @@ -0,0 +1,259 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1900 + title: Memory Chart Analysis + data source: + - metric_table: + id: 1901 + title: # subtitle for this table(optional) + header: + metric: Metric + value: Value + alias: Alias + tips: Tips + metric: + Wave Life: + value: ROUND(AVG(((4 * (SQ_WAVE_CYCLES / SQ_WAVES)) if (SQ_WAVES != 0) else + None)), 0) + alias: wave_life_ + tips: + Active CUs: + value: CONCAT(CONCAT($numActiveCUs, "/"), $numCU) + alias: active_cu_ + tips: + SALU: + value: ROUND(AVG((SQ_INSTS_SALU / $denom)), 0) + alias: salu_ + tips: + SMEM: + value: ROUND(AVG((SQ_INSTS_SMEM / $denom)), 0) + alias: smem_ + tips: + VALU: + value: ROUND(AVG((SQ_INSTS_VALU / $denom)), 0) + alias: valu_ + tips: + MFMA: + value: None # No perf counter + alias: mfma_ + tips: + VMEM: + value: ROUND(AVG((SQ_INSTS_VMEM / $denom)), 0) + alias: vmem_ + tips: + LDS: + value: ROUND(AVG((SQ_INSTS_LDS / $denom)), 0) + alias: lds_ + tips: + GWS: + value: ROUND(AVG((SQ_INSTS_GDS / $denom)), 0) + alias: gws_ + tips: + BR: + value: ROUND(AVG((SQ_INSTS_BRANCH / $denom)), 0) + alias: br_ + tips: + VGPR: + value: ROUND(AVG(vgpr), 0) + alias: vgpr_ + tips: + SGPR: + value: ROUND(AVG(sgpr), 0) + alias: sgpr_ + tips: + LDS Allocation: + value: ROUND(AVG(lds), 0) + alias: lds_alloc_ + tips: + Scratch Allocation: + value: ROUND(AVG(scr), 0) + alias: scratch_alloc_ + tips: + Wavefronts: + value: ROUND(AVG(SPI_CSN_WAVE), 0) + alias: wavefronts_ + tips: + Workgroups: + value: ROUND(AVG(SPI_CSN_NUM_THREADGROUPS), 0) + alias: workgroups_ + tips: + LDS Req: + value: ROUND(AVG((SQ_INSTS_LDS / $denom)), 0) + alias: lds_req_ + tips: + IL1 Fetch: + value: ROUND(AVG((SQC_ICACHE_REQ / $denom)), 0) + alias: il1_fetch_ + tips: + IL1 Hit: + value: ROUND((AVG((SQC_ICACHE_HITS / SQC_ICACHE_REQ)) * 100), 0) + alias: il1_hit_ + tips: + IL1_L2 Rd: + value: ROUND(AVG((SQC_TC_INST_REQ / $denom)), 0) + alias: il1_l2_req_ + tips: + vL1D Rd: + value: ROUND(AVG((SQC_DCACHE_REQ / $denom)), 0) + alias: sl1_rd_ + tips: + vL1D Hit: + value: ROUND((AVG(((SQC_DCACHE_HITS / SQC_DCACHE_REQ) if (SQC_DCACHE_REQ != + 0) else None)) * 100), 0) + alias: sl1_hit_ + tips: + vL1D_L2 Rd: + value: ROUND(AVG((SQC_TC_DATA_READ_REQ / $denom)), 0) + alias: sl1_l2_rd_ + tips: + vL1D_L2 Wr: + value: ROUND(AVG((SQC_TC_DATA_WRITE_REQ / $denom)), 0) + alias: sl1_l2_wr_ + tips: + vL1D_L2 Atomic: + value: ROUND(AVG((SQC_TC_DATA_ATOMIC_REQ / $denom)), 0) + alias: sl1_l2_atom_ + tips: + VL1 Rd: + value: ROUND(AVG((TCP_TOTAL_READ_sum / $denom)), 0) + alias: vl1_rd_ + tips: + VL1 Wr: + value: ROUND(AVG((TCP_TOTAL_WRITE_sum / $denom)), 0) + alias: vl1_wr_ + tips: + VL1 Atomic: + value: ROUND(AVG(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) + / $denom)), 0) + alias: vl1_atom_ + tips: + VL1 Hit: + value: ROUND(AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)), 0) + alias: vl1_hit_ + tips: + VL1 Lat: + value: ROUND(AVG(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum + != 0) else None)), 0) + alias: vl1_lat_ + tips: + VL1_L2 Rd: + value: ROUND(AVG((TCP_TCC_READ_REQ_sum / $denom)), 0) + alias: vl1_l2_rd_ + tips: + VL1_L2 Wr: + value: ROUND(AVG((TCP_TCC_WRITE_REQ_sum / $denom)), 0) + alias: vl1_l2_wr_ + tips: + vL1_L2 Atomic: + value: ROUND(AVG(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + / $denom)), 0) + alias: vl1_l2_atom_ + tips: + L2 Rd: + value: ROUND(AVG((TCC_READ_sum / $denom)), 0) + alias: l2_rd_ + tips: + L2 Wr: + value: ROUND(AVG((TCC_WRITE_sum / $denom)), 0) + alias: l2_wr_ + tips: + L2 Atomic: + value: ROUND(AVG((TCC_ATOMIC_sum / $denom)), 0) + alias: l2_atom_ + tips: + L2 Hit: + value: ROUND(AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)), 0) + alias: l2_hit_ + tips: + L2 Rd Lat: + value: ROUND(AVG(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) + if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)), + 0) + alias: l2_rd_lat_ + tips: + L2 Wr Lat: + value: ROUND(AVG(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + != 0) else None)), 0) + alias: l2_wr_lat_ + tips: + Fabric Rd Lat: + value: ROUND(AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum + != 0) else None)), 0) + alias: fabric_rd_lat_ + tips: + Fabric Wr Lat: + value: ROUND(AVG(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum + != 0) else None)), 0) + alias: fabric_wr_lat_ + tips: + Fabric Atomic Lat: + value: ROUND(AVG(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum + != 0) else None)), 0) + alias: fabric_atom_lat_ + tips: + Fabric_L2 Rd: + value: ROUND(AVG((TCC_EA_RDREQ_sum / $denom)), 0) + alias: l2_fabric_rd_ + tips: + Fabric_L2 Wr: + value: ROUND(AVG((TCC_EA_WRREQ_sum / $denom)), 0) + alias: l2_fabric_wr_ + tips: + Fabric_l2 Atomic: + value: ROUND(AVG((TCC_EA_ATOMIC_sum / $denom)), 0) + alias: l2_fabric_atom_ + tips: + HBM Rd: + value: ROUND(AVG((TCC_EA_RDREQ_DRAM_sum / $denom)), 0) + alias: hbm_rd_ + tips: + HBM Wr: + value: ROUND(AVG((TCC_EA_WRREQ_DRAM_sum / $denom)), 0) + alias: hbm_wr_ + tips: + LDS Util: + value: ROUND(AVG(((100 * SQ_LDS_IDX_ACTIVE) / (GRBM_GUI_ACTIVE * $numCU))), + 0) + alias: lds_util_ + tips: + VL1 Coalesce: + value: ROUND(AVG(((((TA_TOTAL_WAVEFRONTS_sum * 64) * 100) / (TCP_TOTAL_ACCESSES_sum + * 4)) if (TCP_TOTAL_ACCESSES_sum != 0) else 0)), 0) + alias: vl1_coales_ + tips: + VL1 Stall: + value: ROUND(AVG((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)), 0) + alias: vl1_stall_ + tips: + LDS Lat: + value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) + if (SQ_INSTS_LDS != 0) else None)), 0) + alias: lds_lat_ + coll_level: SQ_INST_LEVEL_LDS + tips: + vL1D Lat: + value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQC_DCACHE_REQ) + if (SQC_DCACHE_REQ != 0) else None)), 0) + alias: sl1_lat_ + tips: + IL1 Lat: + value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQC_ICACHE_REQ) + if (SQC_ICACHE_REQ != 0) else None)), 0) + alias: il1_lat_ + tips: + Wave Occupancy: + value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE) / $numActiveCUs)), 0) + alias: wave_occ_ + coll_level: SQ_LEVEL_WAVES + tips: diff --git a/src/omniperf_soc/configs/gfx906/2000_kernels.yaml b/src/omniperf_soc/configs/gfx906/2000_kernels.yaml new file mode 100644 index 0000000000..ed566f75a2 --- /dev/null +++ b/src/omniperf_soc/configs/gfx906/2000_kernels.yaml @@ -0,0 +1,8 @@ +--- +Panel Config: + id: 2000 + title: Kernels + data source: + - raw_csv_table: + id: 2001 + source: pmc_dispatch_info.csv diff --git a/src/omniperf_soc/configs/gfx908/0000_top_stat.yaml b/src/omniperf_soc/configs/gfx908/0000_top_stat.yaml new file mode 100644 index 0000000000..077004080f --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/0000_top_stat.yaml @@ -0,0 +1,8 @@ +--- +Panel Config: + id: 000 + title: Top Stat + data source: + - raw_csv_table: + id: 001 + source: pmc_kernel_top.csv diff --git a/src/omniperf_soc/configs/gfx908/0100_system_info.yaml b/src/omniperf_soc/configs/gfx908/0100_system_info.yaml new file mode 100644 index 0000000000..b7ec29eaf9 --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/0100_system_info.yaml @@ -0,0 +1,9 @@ +--- +Panel Config: + id: 100 + title: System Info + data source: + - raw_csv_table: + id: 101 + source: sysinfo.csv + columnwise: True diff --git a/src/omniperf_soc/configs/gfx908/0200_system-speed-of-light.yaml b/src/omniperf_soc/configs/gfx908/0200_system-speed-of-light.yaml new file mode 100644 index 0000000000..986b2f0aec --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/0200_system-speed-of-light.yaml @@ -0,0 +1,230 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + SALU: &SALU_anchor Scalar Arithmetic Logic Unit + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 200 + title: System Speed-of-Light + data source: + - metric_table: + id: 201 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + peak: Peak + pop: PoP + tips: Tips + metric: + VALU FLOPs: + value: None # No perf counter + unit: GFLOPs + peak: (((($sclk * $numCU) * 64) * 2) / 1000) + pop: None # No perf counter + tips: + VALU IOPs: + value: None # No perf counter + unit: GOPs + peak: (((($sclk * $numCU) * 64) * 2) / 1000) + pop: None # No perf counter + tips: + MFMA FLOPs (BF16): + value: None # No perf counter + unit: GFLOPs + peak: ((($sclk * $numCU) * 512) / 1000) + pop: None # No perf counter + tips: + MFMA FLOPs (F16): + value: None # No perf counter + unit: GFLOPs + peak: ((($sclk * $numCU) * 1024) / 1000) + pop: None # No perf counter + tips: + MFMA FLOPs (F32): + value: None # No perf counter + unit: GFLOPs + peak: ((($sclk * $numCU) * 256) / 1000) + pop: None # No perf counter + tips: + MFMA FLOPs (F64): + value: None # No perf counter + unit: GFLOPs + peak: ((($sclk * $numCU) * 256) / 1000) + pop: None # No perf counter + tips: + MFMA IOPs (Int8): + value: None # No perf counter + unit: GOPs + peak: ((($sclk * $numCU) * 1024) / 1000) + pop: None # No perf counter + tips: + Active CUs: + value: $numActiveCUs + unit: CUs + peak: $numCU + pop: ((100 * $numActiveCUs) / $numCU) + tips: + SALU Util: + value: AVG(((100 * SQ_ACTIVE_INST_SCA) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + peak: 100 + pop: AVG(((100 * SQ_ACTIVE_INST_SCA) / (GRBM_GUI_ACTIVE * $numCU))) + tips: + VALU Util: + value: AVG(((100 * SQ_ACTIVE_INST_VALU) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + peak: 100 + pop: AVG(((100 * SQ_ACTIVE_INST_VALU) / (GRBM_GUI_ACTIVE * $numCU))) + tips: + MFMA Util: + value: None # No HW module + unit: pct + peak: 100 + pop: None # No HW module + tips: + VALU Active Threads/Wave: + value: AVG(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + unit: Threads + peak: 64 + pop: (AVG(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) * 1.5625) + tips: + IPC - Issue: + value: AVG(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM) + + SQ_INSTS_GDS) + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED) + / SQ_ACTIVE_INST_ANY)) + unit: Instr/cycle + peak: 5 + pop: ((100 * AVG(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM) + + SQ_INSTS_GDS) + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED) + / SQ_ACTIVE_INST_ANY))) / 5) + tips: + LDS BW: + value: AVG(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / (EndNs - BeginNs))) + unit: GB/sec + peak: (($sclk * $numCU) * 0.128) + pop: AVG((((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / (EndNs - BeginNs)) / (($sclk * $numCU) * 0.00128))) + tips: + LDS Bank Conflict: + value: AVG(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + unit: Conflicts/access + peak: 32 + pop: ((100 * AVG(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None))) / 32) + tips: + Instr Cache Hit Rate: + value: AVG(((100 * SQC_ICACHE_HITS) / (SQC_ICACHE_HITS + SQC_ICACHE_MISSES))) + unit: pct + peak: 100 + pop: AVG(((100 * SQC_ICACHE_HITS) / (SQC_ICACHE_HITS + SQC_ICACHE_MISSES))) + tips: + Instr Cache BW: + value: AVG(((SQC_ICACHE_REQ / (EndNs - BeginNs)) * 64)) + unit: GB/s + peak: ((($sclk / 1000) * 64) * $numSQC) + pop: ((100 * AVG(((SQC_ICACHE_REQ / (EndNs - BeginNs)) * 64))) / ((($sclk + / 1000) * 64) * $numSQC)) + tips: + Scalar L1D Cache Hit Rate: + value: AVG((((100 * SQC_DCACHE_HITS) / (SQC_DCACHE_HITS + SQC_DCACHE_MISSES)) + if ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) != 0) else None)) + unit: pct + peak: 100 + pop: AVG((((100 * SQC_DCACHE_HITS) / (SQC_DCACHE_HITS + SQC_DCACHE_MISSES)) + if ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) != 0) else None)) + tips: + Scalar L1D Cache BW: + value: AVG(((SQC_DCACHE_REQ / (EndNs - BeginNs)) * 64)) + unit: GB/s + peak: ((($sclk / 1000) * 64) * $numSQC) + pop: ((100 * AVG(((SQC_DCACHE_REQ / (EndNs - BeginNs)) * 64))) / ((($sclk + / 1000) * 64) * $numSQC)) + tips: + Vector L1D Cache Hit Rate: + value: AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + unit: pct + peak: 100 + pop: AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / + TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + tips: + Vector L1D Cache BW: + value: AVG(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs))) + unit: GB/s + peak: ((($sclk / 1000) * 64) * $numCU) + pop: ((100 * AVG(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs)))) + / ((($sclk / 1000) * 64) * $numCU)) + tips: + L2 Cache Hit Rate: + value: AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + unit: pct + peak: 100 + pop: AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + tips: + L2-Fabric Read BW: + value: AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / (EndNs - BeginNs))) + unit: GB/s + peak: $hbmBW + pop: ((100 * AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / (EndNs - BeginNs)))) / $hbmBW) + tips: + L2-Fabric Write BW: + value: AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / (EndNs - BeginNs))) + unit: GB/s + peak: $hbmBW + pop: ((100 * AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / (EndNs - BeginNs)))) / $hbmBW) + tips: + L2-Fabric Read Latency: + value: AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum + != 0) else None)) + unit: Cycles + peak: '' + pop: '' + tips: + L2-Fabric Write Latency: + value: AVG(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum + != 0) else None)) + unit: Cycles + peak: '' + pop: '' + tips: + Wave Occupancy: + value: AVG((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE)) + unit: Wavefronts + peak: ($maxWavesPerCU * $numCU) + pop: (100 * AVG(((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE) / ($maxWavesPerCU + * $numCU)))) + coll_level: SQ_LEVEL_WAVES + tips: + Instr Fetch BW: + value: AVG(((SQ_IFETCH / (EndNs - BeginNs)) * 32)) + unit: GB/s + peak: ((($sclk / 1000) * 32) * $numSQC) + pop: ((100 * AVG(((SQ_IFETCH / (EndNs - BeginNs)) * 32))) / ($numSQC + * (($sclk / 1000) * 32))) + coll_level: SQ_IFETCH_LEVEL + tips: + Instr Fetch Latency: + value: AVG((SQ_ACCUM_PREV_HIRES / SQ_IFETCH)) + unit: Cycles + peak: '' + pop: '' + coll_level: SQ_IFETCH_LEVEL + tips: diff --git a/src/omniperf_soc/configs/gfx908/0500_command-processor.yaml b/src/omniperf_soc/configs/gfx908/0500_command-processor.yaml new file mode 100644 index 0000000000..5250918799 --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/0500_command-processor.yaml @@ -0,0 +1,180 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 500 + title: Command Processor (CPC/CPF) + data source: + - metric_table: + id: 501 + title: Command Processor Fetcher + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + GPU Busy Cycles: + avg: AVG(GRBM_GUI_ACTIVE) + min: MIN(GRBM_GUI_ACTIVE) + max: MAX(GRBM_GUI_ACTIVE) + unit: Cycles/Kernel + tips: + CPF Busy: + avg: AVG(CPF_CPF_STAT_BUSY) + min: MIN(CPF_CPF_STAT_BUSY) + max: MAX(CPF_CPF_STAT_BUSY) + unit: Cycles/Kernel + tips: + CPF Util: + avg: AVG((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) + if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) + min: MIN((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) + if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) + max: MAX((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) + if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) + unit: pct + tips: + CPF Stall: + avg: AVG((((100 * CPF_CPF_STAT_STALL) / CPF_CPF_STAT_BUSY) if (CPF_CPF_STAT_BUSY + != 0) else None)) + min: MIN((((100 * CPF_CPF_STAT_STALL) / CPF_CPF_STAT_BUSY) if (CPF_CPF_STAT_BUSY + != 0) else None)) + max: MAX((((100 * CPF_CPF_STAT_STALL) / CPF_CPF_STAT_BUSY) if (CPF_CPF_STAT_BUSY + != 0) else None)) + unit: Cycles/Kernel + tips: + L2Cache Intf Busy: + avg: AVG(CPF_CPF_TCIU_BUSY) + min: MIN(CPF_CPF_TCIU_BUSY) + max: MAX(CPF_CPF_TCIU_BUSY) + unit: Cycles/Kernel + tips: + L2Cache Intf Util: + avg: AVG((((100 * CPF_CPF_TCIU_BUSY) / (CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE)) + if ((CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE) != 0) else None)) + min: MIN((((100 * CPF_CPF_TCIU_BUSY) / (CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE)) + if ((CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE) != 0) else None)) + max: MAX((((100 * CPF_CPF_TCIU_BUSY) / (CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE)) + if ((CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE) != 0) else None)) + unit: pct + tips: + L2Cache Intf Stall: + avg: AVG((((100 * CPF_CPF_TCIU_STALL) / CPF_CPF_TCIU_BUSY) if (CPF_CPF_TCIU_BUSY + != 0) else None)) + min: MIN((((100 * CPF_CPF_TCIU_STALL) / CPF_CPF_TCIU_BUSY) if (CPF_CPF_TCIU_BUSY + != 0) else None)) + max: MAX((((100 * CPF_CPF_TCIU_STALL) / CPF_CPF_TCIU_BUSY) if (CPF_CPF_TCIU_BUSY + != 0) else None)) + unit: pct + tips: + UTCL1 Stall: + avg: AVG(CPF_CMP_UTCL1_STALL_ON_TRANSLATION) + min: MIN(CPF_CMP_UTCL1_STALL_ON_TRANSLATION) + max: MAX(CPF_CMP_UTCL1_STALL_ON_TRANSLATION) + unit: Cycles/Kernel + tips: + + - metric_table: + id: 502 + title: Command Processor Compute + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + GPU Busy Cycles: + avg: AVG(GRBM_GUI_ACTIVE) + min: MIN(GRBM_GUI_ACTIVE) + max: MAX(GRBM_GUI_ACTIVE) + unit: Cycles + tips: + CPC Busy Cycles: + avg: AVG(CPC_CPC_STAT_BUSY) + min: MIN(CPC_CPC_STAT_BUSY) + max: MAX(CPC_CPC_STAT_BUSY) + unit: Cycles + tips: + CPC Util: + avg: AVG((((100 * CPC_CPC_STAT_BUSY) / (CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE)) + if ((CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE) != 0) else None)) + min: MIN((((100 * CPC_CPC_STAT_BUSY) / (CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE)) + if ((CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE) != 0) else None)) + max: MAX((((100 * CPC_CPC_STAT_BUSY) / (CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE)) + if ((CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE) != 0) else None)) + unit: pct + tips: + CPC Stall Cycles: + avg: AVG(CPC_CPC_STAT_STALL) + min: MIN(CPC_CPC_STAT_STALL) + max: MAX(CPC_CPC_STAT_STALL) + unit: Cycles + tips: + CPC Stall Rate: + avg: AVG((((100 * CPC_CPC_STAT_STALL) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + min: MIN((((100 * CPC_CPC_STAT_STALL) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + max: MAX((((100 * CPC_CPC_STAT_STALL) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + unit: pct + tips: + CPC Packet Decoding: + avg: AVG(CPC_ME1_BUSY_FOR_PACKET_DECODE) + min: MIN(CPC_ME1_BUSY_FOR_PACKET_DECODE) + max: MAX(CPC_ME1_BUSY_FOR_PACKET_DECODE) + unit: Cycles + tips: + SPI Intf Busy Cycles: + avg: AVG(CPC_ME1_DC0_SPI_BUSY) + min: MIN(CPC_ME1_DC0_SPI_BUSY) + max: MAX(CPC_ME1_DC0_SPI_BUSY) + unit: Cycles + tips: + SPI Intf Util: + avg: AVG((((100 * CPC_ME1_DC0_SPI_BUSY) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + min: MIN((((100 * CPC_ME1_DC0_SPI_BUSY) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + max: MAX((((100 * CPC_ME1_DC0_SPI_BUSY) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + unit: pct + tips: + L2Cache Intf Util: + avg: AVG((((100 * CPC_CPC_TCIU_BUSY) / (CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE)) + if ((CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE) != 0) else None)) + min: MIN((((100 * CPC_CPC_TCIU_BUSY) / (CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE)) + if ((CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE) != 0) else None)) + max: MAX((((100 * CPC_CPC_TCIU_BUSY) / (CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE)) + if ((CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE) != 0) else None)) + unit: pct + tips: + UTCL1 Stall Cycles: + avg: AVG(CPC_UTCL1_STALL_ON_TRANSLATION) + min: MIN(CPC_UTCL1_STALL_ON_TRANSLATION) + max: MAX(CPC_UTCL1_STALL_ON_TRANSLATION) + unit: Cycles + tips: + UTCL2 Intf Busy Cycles: + avg: AVG(CPC_CPC_UTCL2IU_BUSY) + min: MIN(CPC_CPC_UTCL2IU_BUSY) + max: MAX(CPC_CPC_UTCL2IU_BUSY) + unit: Cycles + tips: + UTCL2 Intf Util: + avg: AVG((((100 * CPC_CPC_UTCL2IU_BUSY) / (CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE)) + if ((CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE) != 0) else None)) + min: MIN((((100 * CPC_CPC_UTCL2IU_BUSY) / (CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE)) + if ((CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE) != 0) else None)) + max: MAX((((100 * CPC_CPC_UTCL2IU_BUSY) / (CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE)) + if ((CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE) != 0) else None)) + unit: pct + tips: diff --git a/src/omniperf_soc/configs/gfx908/0600_shader-processor-input.yaml b/src/omniperf_soc/configs/gfx908/0600_shader-processor-input.yaml new file mode 100644 index 0000000000..38b81ed4fc --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/0600_shader-processor-input.yaml @@ -0,0 +1,174 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 600 + title: Shader Processor Input (SPI) + data source: + - metric_table: + id: 601 + title: SPI Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + GPU Busy: + avg: AVG(GRBM_GUI_ACTIVE) + min: MIN(GRBM_GUI_ACTIVE) + max: MAX(GRBM_GUI_ACTIVE) + unit: Cycles + tips: + CS Busy: + avg: AVG(SPI_CSN_BUSY) + min: MIN(SPI_CSN_BUSY) + max: MAX(SPI_CSN_BUSY) + unit: Cycles + tips: + SPI Busy: + avg: AVG(GRBM_SPI_BUSY) + min: MIN(GRBM_SPI_BUSY) + max: MAX(GRBM_SPI_BUSY) + unit: Cycles + tips: + SQ Busy: + avg: AVG(SQ_BUSY_CYCLES) + min: MIN(SQ_BUSY_CYCLES) + max: MAX(SQ_BUSY_CYCLES) + unit: Cycles + tips: + Dispatched Workgroups: + avg: AVG(SPI_CSN_NUM_THREADGROUPS) + min: MIN(SPI_CSN_NUM_THREADGROUPS) + max: MAX(SPI_CSN_NUM_THREADGROUPS) + unit: Workgroups + tips: + Dispatched Wavefronts: + avg: AVG(SPI_CSN_WAVE) + min: MIN(SPI_CSN_WAVE) + max: MAX(SPI_CSN_WAVE) + unit: Wavefronts + tips: + Wave Alloc Failed: + avg: AVG(SPI_RA_REQ_NO_ALLOC) + min: MIN(SPI_RA_REQ_NO_ALLOC) + max: MAX(SPI_RA_REQ_NO_ALLOC) + unit: Cycles + tips: + Wave Alloc Failed - CS: + avg: AVG(SPI_RA_REQ_NO_ALLOC_CSN) + min: MIN(SPI_RA_REQ_NO_ALLOC_CSN) + max: MAX(SPI_RA_REQ_NO_ALLOC_CSN) + unit: Cycles + tips: + + - metric_table: + id: 602 + title: SPI Resource Allocation + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Wave request Failed (CS): + avg: AVG(SPI_RA_REQ_NO_ALLOC_CSN) + min: MIN(SPI_RA_REQ_NO_ALLOC_CSN) + max: MAX(SPI_RA_REQ_NO_ALLOC_CSN) + unit: Cycles + tips: + CS Stall: + avg: AVG(SPI_RA_RES_STALL_CSN) + min: MIN(SPI_RA_RES_STALL_CSN) + max: MAX(SPI_RA_RES_STALL_CSN) + unit: Cycles + tips: + CS Stall Rate: + avg: AVG((((100 * SPI_RA_RES_STALL_CSN) / GRBM_SPI_BUSY) if (GRBM_SPI_BUSY != + 0) else None)) + min: MIN((((100 * SPI_RA_RES_STALL_CSN) / GRBM_SPI_BUSY) if (GRBM_SPI_BUSY != + 0) else None)) + max: MAX((((100 * SPI_RA_RES_STALL_CSN) / GRBM_SPI_BUSY) if (GRBM_SPI_BUSY != + 0) else None)) + unit: pct + tips: + Scratch Stall: + avg: AVG(SPI_RA_TMP_STALL_CSN) + min: MIN(SPI_RA_TMP_STALL_CSN) + max: MAX(SPI_RA_TMP_STALL_CSN) + unit: Cycles + tips: + Insufficient SIMD Waveslots: + avg: AVG(SPI_RA_WAVE_SIMD_FULL_CSN) + min: MIN(SPI_RA_WAVE_SIMD_FULL_CSN) + max: MAX(SPI_RA_WAVE_SIMD_FULL_CSN) + unit: SIMD + tips: + Insufficient SIMD VGPRs: + avg: AVG(SPI_RA_VGPR_SIMD_FULL_CSN) + min: MIN(SPI_RA_VGPR_SIMD_FULL_CSN) + max: MAX(SPI_RA_VGPR_SIMD_FULL_CSN) + unit: SIMD + tips: + Insufficient SIMD SGPRs: + avg: AVG(SPI_RA_SGPR_SIMD_FULL_CSN) + min: MIN(SPI_RA_SGPR_SIMD_FULL_CSN) + max: MAX(SPI_RA_SGPR_SIMD_FULL_CSN) + unit: SIMD + tips: + Insufficient CU LDS: + avg: AVG(SPI_RA_LDS_CU_FULL_CSN) + min: MIN(SPI_RA_LDS_CU_FULL_CSN) + max: MAX(SPI_RA_LDS_CU_FULL_CSN) + unit: CU + tips: + Insufficient CU Barries: + avg: AVG(SPI_RA_BAR_CU_FULL_CSN) + min: MIN(SPI_RA_BAR_CU_FULL_CSN) + max: MAX(SPI_RA_BAR_CU_FULL_CSN) + unit: CU + tips: + Insufficient Bulky Resource: + avg: AVG(SPI_RA_BULKY_CU_FULL_CSN) + min: MIN(SPI_RA_BULKY_CU_FULL_CSN) + max: MAX(SPI_RA_BULKY_CU_FULL_CSN) + unit: CU + tips: + Reach CU Threadgroups Limit: + avg: AVG(SPI_RA_TGLIM_CU_FULL_CSN) + min: MIN(SPI_RA_TGLIM_CU_FULL_CSN) + max: MAX(SPI_RA_TGLIM_CU_FULL_CSN) + unit: Cycles + tips: + Reach CU Wave Limit: + avg: AVG(SPI_RA_WVLIM_STALL_CSN) + min: MIN(SPI_RA_WVLIM_STALL_CSN) + max: MAX(SPI_RA_WVLIM_STALL_CSN) + unit: Cycles + tips: + VGPR Writes: + avg: AVG((((4 * SPI_VWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + min: MIN((((4 * SPI_VWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + max: MAX((((4 * SPI_VWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + unit: Cycles/wave + tips: + SGPR Writes: + avg: AVG((((1 * SPI_SWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + min: MIN((((1 * SPI_SWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + max: MAX((((1 * SPI_SWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + unit: Cycles/wave + tips: diff --git a/src/omniperf_soc/configs/gfx908/0700_wavefront-launch.yaml b/src/omniperf_soc/configs/gfx908/0700_wavefront-launch.yaml new file mode 100644 index 0000000000..70141193e6 --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/0700_wavefront-launch.yaml @@ -0,0 +1,142 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 700 + title: Wavefront + data source: + - metric_table: + id: 701 + title: Wavefront Launch Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Grid Size: + avg: AVG(grd) + min: MIN(grd) + max: MAX(grd) + unit: Work Items + tips: + Workgroup Size: + avg: AVG(wgr) + min: MIN(wgr) + max: MAX(wgr) + unit: Work Items + tips: + Total Wavefronts: + avg: AVG(SPI_CSN_WAVE) + min: MIN(SPI_CSN_WAVE) + max: MAX(SPI_CSN_WAVE) + unit: Wavefronts + tips: + Saved Wavefronts: + avg: AVG(SQ_WAVES_SAVED) + min: MIN(SQ_WAVES_SAVED) + max: MAX(SQ_WAVES_SAVED) + unit: Wavefronts + tips: + Restored Wavefronts: + avg: AVG(SQ_WAVES_RESTORED) + min: MIN(SQ_WAVES_RESTORED) + max: MAX(SQ_WAVES_RESTORED) + unit: Wavefronts + tips: + VGPRs: + avg: AVG(arch_vgpr) + min: MIN(arch_vgpr) + max: MAX(arch_vgpr) + unit: Registers + tips: + AGPRs: + avg: AVG(accum_vgpr) + min: MIN(accum_vgpr) + max: MAX(accum_vgpr) + unit: Registers + tips: + SGPRs: + avg: AVG(sgpr) + min: MIN(sgpr) + max: MAX(sgpr) + unit: Registers + tips: + LDS Allocation: + avg: AVG(lds) + min: MIN(lds) + max: MAX(lds) + unit: Bytes + tips: + Scratch Allocation: + avg: AVG(scr) + min: MIN(scr) + max: MAX(scr) + unit: Bytes + tips: + + - metric_table: + id: 702 + title: Wavefront Runtime Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Kernel Time (Nanosec): + avg: AVG((EndNs - BeginNs)) + min: MIN((EndNs - BeginNs)) + max: MAX((EndNs - BeginNs)) + unit: ns + tips: + Kernel Time (Cycles): + avg: AVG(GRBM_GUI_ACTIVE) + min: MIN(GRBM_GUI_ACTIVE) + max: MAX(GRBM_GUI_ACTIVE) + unit: Cycle + tips: + Instr/wavefront: + avg: AVG((SQ_INSTS / SQ_WAVES)) + min: MIN((SQ_INSTS / SQ_WAVES)) + max: MAX((SQ_INSTS / SQ_WAVES)) + unit: Instr/wavefront + tips: + Wave Cycles: + avg: AVG(((4 * SQ_WAVE_CYCLES) / $denom)) + min: MIN(((4 * SQ_WAVE_CYCLES) / $denom)) + max: MAX(((4 * SQ_WAVE_CYCLES) / $denom)) + unit: (Cycles + $normUnit) + tips: + Dependency Wait Cycles: + avg: AVG(((4 * SQ_WAIT_ANY) / $denom)) + min: MIN(((4 * SQ_WAIT_ANY) / $denom)) + max: MAX(((4 * SQ_WAIT_ANY) / $denom)) + unit: (Cycles + $normUnit) + tips: + Issue Wait Cycles: + avg: AVG(((4 * SQ_WAIT_INST_ANY) / $denom)) + min: MIN(((4 * SQ_WAIT_INST_ANY) / $denom)) + max: MAX(((4 * SQ_WAIT_INST_ANY) / $denom)) + unit: (Cycles + $normUnit) + tips: + Active Cycles: + avg: AVG(((4 * SQ_ACTIVE_INST_ANY) / $denom)) + min: MIN(((4 * SQ_ACTIVE_INST_ANY) / $denom)) + max: MAX(((4 * SQ_ACTIVE_INST_ANY) / $denom)) + unit: (Cycles + $normUnit) + tips: + Wavefront Occupancy: + avg: AVG((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE)) + min: MIN((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE)) + max: MAX((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE)) + unit: Wavefronts + coll_level: SQ_LEVEL_WAVES + tips: diff --git a/src/omniperf_soc/configs/gfx908/1000_compute-unit-instruction-mix.yaml b/src/omniperf_soc/configs/gfx908/1000_compute-unit-instruction-mix.yaml new file mode 100644 index 0000000000..13c27dd209 --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/1000_compute-unit-instruction-mix.yaml @@ -0,0 +1,234 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1000 + title: Compute Units - Instruction Mix + data source: + - metric_table: + id: 1001 + title: Instruction Mix + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + style: + type: simple_bar + label_txt: (# of instr + $normUnit) + metric: + VALU - Vector: + avg: AVG(((SQ_INSTS_VALU - SQ_INSTS_MFMA) / $denom)) + min: MIN(((SQ_INSTS_VALU - SQ_INSTS_MFMA) / $denom)) + max: MAX(((SQ_INSTS_VALU - SQ_INSTS_MFMA) / $denom)) + unit: (instr + $normUnit) + tips: + VMEM: + avg: AVG(((SQ_INSTS_VMEM - SQ_INSTS_FLAT_LDS_ONLY) / $denom)) + min: MIN(((SQ_INSTS_VMEM - SQ_INSTS_FLAT_LDS_ONLY) / $denom)) + max: MAX(((SQ_INSTS_VMEM - SQ_INSTS_FLAT_LDS_ONLY) / $denom)) + unit: (instr + $normUnit) + tips: + LDS: + avg: AVG((SQ_INSTS_LDS / $denom)) + min: MIN((SQ_INSTS_LDS / $denom)) + max: MAX((SQ_INSTS_LDS / $denom)) + unit: (instr + $normUnit) + tips: + VALU - MFMA: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: (instr + $normUnit) + tips: + SALU: + avg: AVG((SQ_INSTS_SALU / $denom)) + min: MIN((SQ_INSTS_SALU / $denom)) + max: MAX((SQ_INSTS_SALU / $denom)) + unit: (instr + $normUnit) + tips: + SMEM: + avg: AVG((SQ_INSTS_SMEM / $denom)) + min: MIN((SQ_INSTS_SMEM / $denom)) + max: MAX((SQ_INSTS_SMEM / $denom)) + unit: (instr + $normUnit) + tips: + Branch: + avg: AVG((SQ_INSTS_BRANCH / $denom)) + min: MIN((SQ_INSTS_BRANCH / $denom)) + max: MAX((SQ_INSTS_BRANCH / $denom)) + unit: (instr + $normUnit) + tips: + GDS: + avg: AVG((SQ_INSTS_GDS / $denom)) + min: MIN((SQ_INSTS_GDS / $denom)) + max: MAX((SQ_INSTS_GDS / $denom)) + unit: (instr + $normUnit) + tips: + + - metric_table: + id: 1002 + title: VALU Arithmetic Instr Mix + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + style: + type: simple_bar + label_txt: (# of instr + $normUnit) + metric: + INT-32: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (instr + $normUnit) + tips: + INT-64: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (instr + $normUnit) + tips: + F16-ADD: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (instr + $normUnit) + tips: + F16-Mult: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (instr + $normUnit) + tips: + F16-FMA: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (instr + $normUnit) + tips: + F16-Trans: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (instr + $normUnit) + tips: + F32-ADD: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (instr + $normUnit) + tips: + F32-Mult: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (instr + $normUnit) + tips: + F32-FMA: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (instr + $normUnit) + tips: + F32-Trans: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (instr + $normUnit) + tips: + F64-ADD: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (instr + $normUnit) + tips: + F64-Mult: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (instr + $normUnit) + tips: + F64-FMA: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (instr + $normUnit) + tips: + F64-Trans: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (instr + $normUnit) + tips: + Conversion: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (instr + $normUnit) + tips: + + - metric_table: + id: 1003 + title: VMEM Instr Mix + header: + type: Type + count: Count + tips: Tips + metric: + Buffer Instr: + count: AVG((TA_BUFFER_WAVEFRONTS_sum / $denom)) + tips: + Buffer Read: + count: AVG((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) + tips: + Buffer Write: + count: AVG((TA_BUFFER_WRITE_WAVEFRONTS_sum / $denom)) + tips: + Buffer Atomic: + count: AVG((TA_BUFFER_ATOMIC_WAVEFRONTS_sum / $denom)) + tips: + Flat Instr: + count: AVG((TA_FLAT_WAVEFRONTS_sum / $denom)) + tips: + Flat Read: + count: AVG((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) + tips: + Flat Write: + count: AVG((TA_FLAT_WRITE_WAVEFRONTS_sum / $denom)) + tips: + Flat Atomic: + count: AVG((TA_FLAT_ATOMIC_WAVEFRONTS_sum / $denom)) + tips: + + - metric_table: + id: 1004 + title: MFMA Arithmetic Instr Mix + header: + type: Type + count: Count + tips: Tips + metric: + MFMA-I8: + count: None # No HW module + tips: + MFMA-F16: + count: None # No HW module + tips: + MFMA-BF16: + count: None # No HW module + tips: + MFMA-F32: + count: None # No HW module + tips: + MFMA-F64: + count: None # No HW module + tips: diff --git a/src/omniperf_soc/configs/gfx908/1100_compute-unit-compute-pipeline.yaml b/src/omniperf_soc/configs/gfx908/1100_compute-unit-compute-pipeline.yaml new file mode 100644 index 0000000000..061311d62d --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/1100_compute-unit-compute-pipeline.yaml @@ -0,0 +1,155 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1100 + title: Compute Units - Compute Pipeline + data source: + - metric_table: + id: 1101 + title: Speed-of-Light + header: + metric: Metric + value: Value + tips: Tips + style: + type: simple_bar + range_color: [1, 100] + label_txt: (%) + xrange: [0, 110] + metric: + valu_flops_pop: + value: None # No perf counter + tips: + mfma_flops_bf16_pop: + value: None # No perf counter + tips: + mfma_flops_f16_pop: + value: None # No perf counter + tips: + mfma_flops_f32_pop: + value: None # No perf counter + tips: + mfma_flops_f64_pop: + value: None # No perf counter + tips: + mfma_flops_i8_pop: + value: None # No perf counter + tips: + + - metric_table: + id: 1102 + title: Pipeline Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + IPC (Avg): + avg: AVG((SQ_INSTS / SQ_BUSY_CU_CYCLES)) + min: MIN((SQ_INSTS / SQ_BUSY_CU_CYCLES)) + max: MAX((SQ_INSTS / SQ_BUSY_CU_CYCLES)) + unit: Instr/cycle + tips: + IPC (Issue): + avg: AVG(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM) + + SQ_INSTS_GDS) + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED) + / SQ_ACTIVE_INST_ANY)) + min: MIN(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM) + + SQ_INSTS_GDS) + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED) + / SQ_ACTIVE_INST_ANY)) + max: MAX(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM) + + SQ_INSTS_GDS) + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED) + / SQ_ACTIVE_INST_ANY)) + unit: Instr/cycle + tips: + SALU Util: + avg: AVG((((100 * SQ_ACTIVE_INST_SCA) / GRBM_GUI_ACTIVE) / $numCU)) + min: MIN((((100 * SQ_ACTIVE_INST_SCA) / GRBM_GUI_ACTIVE) / $numCU)) + max: MAX((((100 * SQ_ACTIVE_INST_SCA) / GRBM_GUI_ACTIVE) / $numCU)) + unit: pct + tips: + VALU Util: + avg: AVG((((100 * SQ_ACTIVE_INST_VALU) / GRBM_GUI_ACTIVE) / $numCU)) + min: MIN((((100 * SQ_ACTIVE_INST_VALU) / GRBM_GUI_ACTIVE) / $numCU)) + max: MAX((((100 * SQ_ACTIVE_INST_VALU) / GRBM_GUI_ACTIVE) / $numCU)) + unit: pct + tips: + VALU Active Threads: + avg: AVG(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + min: MIN(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + max: MAX(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + unit: Threads + tips: + MFMA Util: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: pct + tips: + MFMA Instr Cycles: + avg: None # No HW module + min: None # No HW module + max: None # No HW module + unit: cycles/instr + tips: + + - metric_table: + id: 1103 + title: Arithmetic Operations + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + FLOPs (Total): + #FIXME: double check what is available on MI100!!! + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (OPs + $normUnit) + tips: + INT8 OPs: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (OPs + $normUnit) + tips: + F16 OPs: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (OPs + $normUnit) + tips: + BF16 OPs: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (OPs + $normUnit) + tips: + F32 OPs: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (OPs + $normUnit) + tips: + F64 OPs: + avg: None # No perf counter + min: None # No perf counter + max: None # No perf counter + unit: (OPs + $normUnit) + tips: + + diff --git a/src/omniperf_soc/configs/gfx908/1200_lds.yaml b/src/omniperf_soc/configs/gfx908/1200_lds.yaml new file mode 100644 index 0000000000..3fd52c3b1b --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/1200_lds.yaml @@ -0,0 +1,121 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1200 + title: Local Data Share (LDS) + data source: + - metric_table: + id: 1201 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + range_color: [1, 100] + label_txt: (%) + xrange: [0, 110] + metric: + Utilization: + value: AVG(((100 * SQ_LDS_IDX_ACTIVE) / (GRBM_GUI_ACTIVE * $numCU))) + unit: Pct of Peak + tips: + Access Rate: + value: AVG(((200 * SQ_ACTIVE_INST_LDS) / (GRBM_GUI_ACTIVE * $numCU))) + unit: Pct of Peak + tips: + Bandwidth (Pct-of-Peak): + value: AVG((((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / (EndNs - BeginNs)) / (($sclk * $numCU) * 0.00128))) + unit: Pct of Peak + tips: + Bank Conflict Rate: + value: AVG((((SQ_LDS_BANK_CONFLICT * 3.125) / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + unit: Pct of Peak + tips: + + - metric_table: + id: 1202 + title: LDS Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + LDS Instrs: + avg: AVG((SQ_INSTS_LDS / $denom)) + min: MIN((SQ_INSTS_LDS / $denom)) + max: MAX((SQ_INSTS_LDS / $denom)) + unit: (Instr + $normUnit) + tips: + Bandwidth: + avg: AVG(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / $denom)) + min: MIN(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / $denom)) + max: MAX(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / $denom)) + unit: (Bytes + $normUnit) + tips: + Bank Conficts/Access: + avg: AVG(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + min: MIN(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + max: MAX(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + unit: Conflicts/Access + tips: + Index Accesses: + avg: AVG((SQ_LDS_IDX_ACTIVE / $denom)) + min: MIN((SQ_LDS_IDX_ACTIVE / $denom)) + max: MAX((SQ_LDS_IDX_ACTIVE / $denom)) + unit: (Cycles + $normUnit) + tips: + Atomic Cycles: + avg: AVG((SQ_LDS_ATOMIC_RETURN / $denom)) + min: MIN((SQ_LDS_ATOMIC_RETURN / $denom)) + max: MAX((SQ_LDS_ATOMIC_RETURN / $denom)) + unit: (Cycles + $normUnit) + tips: + Bank Conflict: + avg: AVG((SQ_LDS_BANK_CONFLICT / $denom)) + min: MIN((SQ_LDS_BANK_CONFLICT / $denom)) + max: MAX((SQ_LDS_BANK_CONFLICT / $denom)) + unit: (Cycles + $normUnit) + tips: + Addr Conflict: + avg: AVG((SQ_LDS_ADDR_CONFLICT / $denom)) + min: MIN((SQ_LDS_ADDR_CONFLICT / $denom)) + max: MAX((SQ_LDS_ADDR_CONFLICT / $denom)) + unit: (Cycles + $normUnit) + tips: + Unaligned Stall: + avg: AVG((SQ_LDS_UNALIGNED_STALL / $denom)) + min: MIN((SQ_LDS_UNALIGNED_STALL / $denom)) + max: MAX((SQ_LDS_UNALIGNED_STALL / $denom)) + unit: (Cycles + $normUnit) + tips: + Mem Violations: + avg: AVG((SQ_LDS_MEM_VIOLATIONS / $denom)) + min: MIN((SQ_LDS_MEM_VIOLATIONS / $denom)) + max: MAX((SQ_LDS_MEM_VIOLATIONS / $denom)) + unit: ( + $normUnit) + tips: + LDS Latency: + avg: AVG(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)) + min: MIN(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)) + max: MAX(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)) + unit: Cycles + coll_level: SQ_INST_LEVEL_LDS + tips: diff --git a/src/omniperf_soc/configs/gfx908/1300_instruction-cache.yaml b/src/omniperf_soc/configs/gfx908/1300_instruction-cache.yaml new file mode 100644 index 0000000000..05dc759803 --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/1300_instruction-cache.yaml @@ -0,0 +1,79 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1300 + title: Instruction Cache + data source: + - metric_table: + id: 1301 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + range_color: [1, 100] + label_txt: (%) + xrange: [0, 110] + metric: + Bandwidth: + value: AVG(((SQC_ICACHE_REQ * 100000) / (($sclk * $numSQC) + * (EndNs - BeginNs)))) + unit: Pct of Peak + tips: + Cache Hit: + value: AVG(((SQC_ICACHE_HITS * 100) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + unit: Pct of Peak + tips: + + - metric_table: + id: 1302 + title: Instruction Cache Accesses + header: + metric: L1I Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Req: + avg: AVG((SQC_ICACHE_REQ / $denom)) + min: MIN((SQC_ICACHE_REQ / $denom)) + max: MAX((SQC_ICACHE_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Hits: + avg: AVG((SQC_ICACHE_HITS / $denom)) + min: MIN((SQC_ICACHE_HITS / $denom)) + max: MAX((SQC_ICACHE_HITS / $denom)) + unit: (Hits + $normUnit) + tips: + Misses - Non Duplicated: + avg: AVG((SQC_ICACHE_MISSES / $denom)) + min: MIN((SQC_ICACHE_MISSES / $denom)) + max: MAX((SQC_ICACHE_MISSES / $denom)) + unit: (Misses + $normUnit) + tips: + Misses - Duplicated: + avg: AVG((SQC_ICACHE_MISSES_DUPLICATE / $denom)) + min: MIN((SQC_ICACHE_MISSES_DUPLICATE / $denom)) + max: MAX((SQC_ICACHE_MISSES_DUPLICATE / $denom)) + unit: (Misses + $normUnit) + tips: + Cache Hit: + avg: AVG(((100 * SQC_ICACHE_HITS) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + min: MIN(((100 * SQC_ICACHE_HITS) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + max: MAX(((100 * SQC_ICACHE_HITS) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + unit: pct + tips: diff --git a/src/omniperf_soc/configs/gfx908/1400_constant-cache.yaml b/src/omniperf_soc/configs/gfx908/1400_constant-cache.yaml new file mode 100644 index 0000000000..563caad13f --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/1400_constant-cache.yaml @@ -0,0 +1,164 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1400 + title: Scalar L1 Data Cache + data source: + - metric_table: + id: 1401 + title: Speed-of-Light + header: + mertic: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + range_color: [1, 100] + label_txt: (%) + xrange: [0, 110] + metric: + Bandwidth: + value: AVG(((SQC_DCACHE_REQ * 100000) / (($sclk * $numSQC) + * (EndNs - BeginNs)))) + unit: Pct of Peak + tips: + Cache Hit: + value: + AVG((((SQC_DCACHE_HITS * 100) / (SQC_DCACHE_HITS + SQC_DCACHE_MISSES + SQC_DCACHE_MISSES_DUPLICATE)) + if ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + unit: Pct of Peak + tips: + + - metric_table: + id: 1402 + title: Scalar L1D Cache Accesses + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Req: + avg: AVG((SQC_DCACHE_REQ / $denom)) + min: MIN((SQC_DCACHE_REQ / $denom)) + max: MAX((SQC_DCACHE_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Hits: + avg: AVG((SQC_DCACHE_HITS / $denom)) + min: MIN((SQC_DCACHE_HITS / $denom)) + max: MAX((SQC_DCACHE_HITS / $denom)) + unit: (Req + $normUnit) + tips: + Misses - Non Duplicated: + avg: AVG((SQC_DCACHE_MISSES / $denom)) + min: MIN((SQC_DCACHE_MISSES / $denom)) + max: MAX((SQC_DCACHE_MISSES / $denom)) + unit: (Req + $normUnit) + tips: + Misses- Duplicated: + avg: AVG((SQC_DCACHE_MISSES_DUPLICATE / $denom)) + min: MIN((SQC_DCACHE_MISSES_DUPLICATE / $denom)) + max: MAX((SQC_DCACHE_MISSES_DUPLICATE / $denom)) + unit: (Req + $normUnit) + tips: + Cache Hit: + avg: AVG((((100 * SQC_DCACHE_HITS) / ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE)) if (((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + min: MIN((((100 * SQC_DCACHE_HITS) / ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE)) if (((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + max: MAX((((100 * SQC_DCACHE_HITS) / ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE)) if (((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + unit: pct + tips: + Read Req (Total): + avg: AVG((((((SQC_DCACHE_REQ_READ_1 + SQC_DCACHE_REQ_READ_2) + SQC_DCACHE_REQ_READ_4) + + SQC_DCACHE_REQ_READ_8) + SQC_DCACHE_REQ_READ_16) / $denom)) + min: MIN((((((SQC_DCACHE_REQ_READ_1 + SQC_DCACHE_REQ_READ_2) + SQC_DCACHE_REQ_READ_4) + + SQC_DCACHE_REQ_READ_8) + SQC_DCACHE_REQ_READ_16) / $denom)) + max: MAX((((((SQC_DCACHE_REQ_READ_1 + SQC_DCACHE_REQ_READ_2) + SQC_DCACHE_REQ_READ_4) + + SQC_DCACHE_REQ_READ_8) + SQC_DCACHE_REQ_READ_16) / $denom)) + unit: (Req + $normUnit) + tips: + Atomic Req: + avg: AVG((SQC_DCACHE_ATOMIC / $denom)) + min: MIN((SQC_DCACHE_ATOMIC / $denom)) + max: MAX((SQC_DCACHE_ATOMIC / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (1 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_1 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_1 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_1 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (2 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_2 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_2 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_2 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (4 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_4 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_4 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_4 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (8 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_8 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_8 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_8 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (16 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_16 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_16 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_16 / $denom)) + unit: (Req + $normUnit) + tips: + + - metric_table: + id: 1403 + title: Scalar L1D Cache - L2 Interface + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Read Req: + avg: AVG((SQC_TC_DATA_READ_REQ / $denom)) + min: MIN((SQC_TC_DATA_READ_REQ / $denom)) + max: MAX((SQC_TC_DATA_READ_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Write Req: + avg: AVG((SQC_TC_DATA_WRITE_REQ / $denom)) + min: MIN((SQC_TC_DATA_WRITE_REQ / $denom)) + max: MAX((SQC_TC_DATA_WRITE_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Atomic Req: + avg: AVG((SQC_TC_DATA_ATOMIC_REQ / $denom)) + min: MIN((SQC_TC_DATA_ATOMIC_REQ / $denom)) + max: MAX((SQC_TC_DATA_ATOMIC_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Stall: + avg: AVG((SQC_TC_STALL / $denom)) + min: MIN((SQC_TC_STALL / $denom)) + max: MAX((SQC_TC_STALL / $denom)) + unit: (Cycles + $normUnit) + tips: diff --git a/src/omniperf_soc/configs/gfx908/1500_TA_and_TD.yaml b/src/omniperf_soc/configs/gfx908/1500_TA_and_TD.yaml new file mode 100644 index 0000000000..8f71cedc99 --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/1500_TA_and_TD.yaml @@ -0,0 +1,174 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1500 + title: Texture Addresser and Texture Data (TA/TD) + data source: + - metric_table: + id: 1501 + title: TA + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + TA Busy: + avg: AVG(((100 * TA_TA_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TA_TA_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TA_TA_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + TC2TA Addr Stall: + avg: AVG(((100 * TA_ADDR_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TA_ADDR_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TA_ADDR_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + TC2TA Data Stall: + avg: AVG(((100 * TA_DATA_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TA_DATA_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TA_DATA_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + TD2TA Addr Stall: + avg: AVG(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + Total Instructions: + avg: AVG((TA_TOTAL_WAVEFRONTS_sum / $denom)) + min: MIN((TA_TOTAL_WAVEFRONTS_sum / $denom)) + max: MAX((TA_TOTAL_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Flat Instr: + avg: AVG((TA_FLAT_WAVEFRONTS_sum / $denom)) + min: MIN((TA_FLAT_WAVEFRONTS_sum / $denom)) + max: MAX((TA_FLAT_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Flat Read Instr: + avg: AVG((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) + min: MIN((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) + max: MAX((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Flat Write Instr: + avg: AVG((TA_FLAT_WRITE_WAVEFRONTS_sum / $denom)) + min: MIN((TA_FLAT_WRITE_WAVEFRONTS_sum / $denom)) + max: MAX((TA_FLAT_WRITE_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Flat Atomic Instr: + avg: AVG((TA_FLAT_ATOMIC_WAVEFRONTS_sum / $denom)) + min: MIN((TA_FLAT_ATOMIC_WAVEFRONTS_sum / $denom)) + max: MAX((TA_FLAT_ATOMIC_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Buffer Instr: + avg: AVG((TA_BUFFER_WAVEFRONTS_sum / $denom)) + min: MIN((TA_BUFFER_WAVEFRONTS_sum / $denom)) + max: MAX((TA_BUFFER_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Buffer Read Instr: + avg: AVG((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) + min: MIN((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) + max: MAX((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Buffer Write Instr: + avg: AVG((TA_BUFFER_WRITE_WAVEFRONTS_sum / $denom)) + min: MIN((TA_BUFFER_WRITE_WAVEFRONTS_sum / $denom)) + max: MAX((TA_BUFFER_WRITE_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Buffer Atomic Instr: + avg: AVG((TA_BUFFER_ATOMIC_WAVEFRONTS_sum / $denom)) + min: MIN((TA_BUFFER_ATOMIC_WAVEFRONTS_sum / $denom)) + max: MAX((TA_BUFFER_ATOMIC_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Buffer Total Cylces: + avg: AVG((TA_BUFFER_TOTAL_CYCLES_sum / $denom)) + min: MIN((TA_BUFFER_TOTAL_CYCLES_sum / $denom)) + max: MAX((TA_BUFFER_TOTAL_CYCLES_sum / $denom)) + unit: (Cycles + $normUnit) + tips: + Buffer Coalesced Read: + avg: AVG((TA_BUFFER_COALESCED_READ_CYCLES_sum / $denom)) + min: MIN((TA_BUFFER_COALESCED_READ_CYCLES_sum / $denom)) + max: MAX((TA_BUFFER_COALESCED_READ_CYCLES_sum / $denom)) + unit: (Cycles + $normUnit) + tips: + Buffer Coalesced Write: + avg: AVG((TA_BUFFER_COALESCED_WRITE_CYCLES_sum / $denom)) + min: MIN((TA_BUFFER_COALESCED_WRITE_CYCLES_sum / $denom)) + max: MAX((TA_BUFFER_COALESCED_WRITE_CYCLES_sum / $denom)) + unit: (Cycles + $normUnit) + tips: + + - metric_table: + id: 1502 + title: TD + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + TD Busy: + avg: AVG(((100 * TD_TD_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TD_TD_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TD_TD_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + TC2TD Stall: + avg: AVG(((100 * TD_TC_STALL_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TD_TC_STALL_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TD_TC_STALL_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + SPI2TD Stall: + avg: # No perf counter + min: # No perf counter + max: # No perf counter + unit: pct + tips: + Coalescable Instr: + avg: AVG((TD_COALESCABLE_WAVEFRONT_sum / $denom)) + min: MIN((TD_COALESCABLE_WAVEFRONT_sum / $denom)) + max: MAX((TD_COALESCABLE_WAVEFRONT_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Load Instr: + avg: AVG((((TD_LOAD_WAVEFRONT_sum - TD_STORE_WAVEFRONT_sum) - TD_ATOMIC_WAVEFRONT_sum) + / $denom)) + min: MIN((((TD_LOAD_WAVEFRONT_sum - TD_STORE_WAVEFRONT_sum) - TD_ATOMIC_WAVEFRONT_sum) + / $denom)) + max: MAX((((TD_LOAD_WAVEFRONT_sum - TD_STORE_WAVEFRONT_sum) - TD_ATOMIC_WAVEFRONT_sum) + / $denom)) + unit: (Instr + $normUnit) + tips: + Store Instr: + avg: AVG((TD_STORE_WAVEFRONT_sum / $denom)) + min: MIN((TD_STORE_WAVEFRONT_sum / $denom)) + max: MAX((TD_STORE_WAVEFRONT_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Atomic Instr: + avg: AVG((TD_ATOMIC_WAVEFRONT_sum / $denom)) + min: MIN((TD_ATOMIC_WAVEFRONT_sum / $denom)) + max: MAX((TD_ATOMIC_WAVEFRONT_sum / $denom)) + unit: (Instr + $normUnit) + tips: diff --git a/src/omniperf_soc/configs/gfx908/1600_L1_cache.yaml b/src/omniperf_soc/configs/gfx908/1600_L1_cache.yaml new file mode 100644 index 0000000000..cac92b1f2b --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/1600_L1_cache.yaml @@ -0,0 +1,404 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1600 + title: Vector L1 Data Cache + data source: + - metric_table: + id: 1601 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + range_color: [1, 100] + label_txt: (%) + xrange: [0, 110] + metric: + Buffer Coalescing: + value: AVG(((((TA_TOTAL_WAVEFRONTS_sum * 64) * 100) / (TCP_TOTAL_ACCESSES_sum + * 4)) if (TCP_TOTAL_ACCESSES_sum != 0) else None)) + unit: Pct of Peak + tips: + Cache Util: + value: AVG((((TCP_GATE_EN2_sum * 100) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + unit: Pct of Peak + tips: + Cache BW: + value: ((100 * AVG(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs)))) + / ((($sclk / 1000) * 64) * $numCU)) + unit: Pct of Peak + tips: + Cache Hit: + value: AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + unit: Pct of Peak + tips: + + - metric_table: + id: 1602 + title: L1D Cache Stalls + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Stalled on L2 Data: + avg: AVG((((100 * TCP_PENDING_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + min: MIN((((100 * TCP_PENDING_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + max: MAX((((100 * TCP_PENDING_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + unit: pct + tips: + Stalled on L2 Req: + avg: AVG((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + min: MIN((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + max: MAX((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + unit: pct + tips: + Tag RAM Stall (Read): + avg: AVG((((100 * TCP_READ_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + min: MIN((((100 * TCP_READ_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + max: MAX((((100 * TCP_READ_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + unit: pct + tips: + Tag RAM Stall (Write): + avg: AVG((((100 * TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + min: MIN((((100 * TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + max: MAX((((100 * TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + unit: pct + tips: + Tag RAM Stall (Atomic): + avg: AVG((((100 * TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + min: MIN((((100 * TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + max: MAX((((100 * TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + unit: pct + tips: + + - metric_table: + id: 1603 + title: L1D Cache Accesses + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Total Req: + avg: AVG((TCP_TOTAL_ACCESSES_sum / $denom)) + min: MIN((TCP_TOTAL_ACCESSES_sum / $denom)) + max: MAX((TCP_TOTAL_ACCESSES_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read Req: + avg: AVG((TCP_TOTAL_READ_sum / $denom)) + min: MIN((TCP_TOTAL_READ_sum / $denom)) + max: MAX((TCP_TOTAL_READ_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write Req: + avg: AVG((TCP_TOTAL_WRITE_sum / $denom)) + min: MIN((TCP_TOTAL_WRITE_sum / $denom)) + max: MAX((TCP_TOTAL_WRITE_sum / $denom)) + unit: (Req + $normUnit) + tips: + Atomic Req: + avg: AVG(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) + / $denom)) + min: MIN(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) + / $denom)) + max: MAX(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) + / $denom)) + unit: (Req + $normUnit) + tips: + Cache BW: + avg: AVG(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs))) + min: MIN(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs))) + max: MAX(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs))) + unit: GB/s + tips: + Cache Accesses: + avg: AVG((TCP_TOTAL_CACHE_ACCESSES_sum / $denom)) + min: MIN((TCP_TOTAL_CACHE_ACCESSES_sum / $denom)) + max: MAX((TCP_TOTAL_CACHE_ACCESSES_sum / $denom)) + unit: (Req + $normUnit) + tips: + Cache Hits: + avg: AVG(((TCP_TOTAL_CACHE_ACCESSES_sum - (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / $denom)) + min: MIN(((TCP_TOTAL_CACHE_ACCESSES_sum - (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / $denom)) + max: MAX(((TCP_TOTAL_CACHE_ACCESSES_sum - (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / $denom)) + unit: (Req + $normUnit) + tips: + Cache Hit Rate: + avg: AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / + TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + min: MIN(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / + TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + max: MAX(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / + TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + unit: pct + tips: + Invalidate: + avg: AVG((TCP_TOTAL_WRITEBACK_INVALIDATES_sum / $denom)) + min: MIN((TCP_TOTAL_WRITEBACK_INVALIDATES_sum / $denom)) + max: MAX((TCP_TOTAL_WRITEBACK_INVALIDATES_sum / $denom)) + unit: ( + $normUnit) + tips: + L1-L2 BW: + avg: AVG(((64 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / $denom)) + min: AVG(((64 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / $denom)) + max: AVG(((64 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / $denom)) + unit: (Bytes + $normUnit) + tips: + L1-L2 Read: + avg: AVG((TCP_TCC_READ_REQ_sum / $denom)) + min: MIN((TCP_TCC_READ_REQ_sum / $denom)) + max: MAX((TCP_TCC_READ_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + L1-L2 Write: + avg: AVG((TCP_TCC_WRITE_REQ_sum / $denom)) + min: MIN((TCP_TCC_WRITE_REQ_sum / $denom)) + max: MAX((TCP_TCC_WRITE_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + L1-L2 Atomic: + avg: AVG(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + / $denom)) + min: MIN(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + / $denom)) + max: MAX(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + / $denom)) + unit: (Req + $normUnit) + tips: + L1 Access Latency: + avg: AVG(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum + != 0) else None)) + min: MIN(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum + != 0) else None)) + max: MAX(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum + != 0) else None)) + unit: Cycles + tips: + L1-L2 Read Latency: + avg: AVG(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) + if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)) + min: MIN(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) + if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)) + max: MAX(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) + if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)) + unit: Cycles + tips: + L1-L2 Write Latency: + avg: AVG(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) != 0) else + None)) + min: MIN(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) != 0) else + None)) + max: MAX(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) != 0) else + None)) + unit: Cycles + tips: + + - metric_table: + id: 1604 + title: L1D - L2 Transactions + header: + metric: Metric + xfer: Xfer + coherency: Coherency + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + style: + type: simple_multi_bar + metric: + NC - Read: + xfer: Read + coherency: NC + avg: AVG((TCP_TCC_NC_READ_REQ_sum / $denom)) + min: MIN((TCP_TCC_NC_READ_REQ_sum / $denom)) + max: MAX((TCP_TCC_NC_READ_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + UC - Read: + xfer: Read + coherency: UC + avg: AVG((TCP_TCC_UC_READ_REQ_sum / $denom)) + min: MIN((TCP_TCC_UC_READ_REQ_sum / $denom)) + max: MAX((TCP_TCC_UC_READ_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + CC - Read: + xfer: Read + coherency: CC + avg: AVG((TCP_TCC_CC_READ_REQ_sum / $denom)) + min: MIN((TCP_TCC_CC_READ_REQ_sum / $denom)) + max: MAX((TCP_TCC_CC_READ_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + RW - Read: + xfer: Read + coherency: RW + avg: AVG((TCP_TCC_RW_READ_REQ_sum / $denom)) + min: MIN((TCP_TCC_RW_READ_REQ_sum / $denom)) + max: MAX((TCP_TCC_RW_READ_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + RW - Write: + xfer: Write + coherency: RW + avg: AVG((TCP_TCC_RW_WRITE_REQ_sum / $denom)) + min: MIN((TCP_TCC_RW_WRITE_REQ_sum / $denom)) + max: MAX((TCP_TCC_RW_WRITE_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + NC - Write: + xfer: Write + coherency: NC + avg: AVG((TCP_TCC_NC_WRITE_REQ_sum / $denom)) + min: MIN((TCP_TCC_NC_WRITE_REQ_sum / $denom)) + max: MAX((TCP_TCC_NC_WRITE_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + UC - Write: + xfer: Write + coherency: UC + avg: AVG((TCP_TCC_UC_WRITE_REQ_sum / $denom)) + min: MIN((TCP_TCC_UC_WRITE_REQ_sum / $denom)) + max: MAX((TCP_TCC_UC_WRITE_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + CC - Write: + xfer: Write + coherency: CC + avg: AVG((TCP_TCC_CC_WRITE_REQ_sum / $denom)) + min: MIN((TCP_TCC_CC_WRITE_REQ_sum / $denom)) + max: MAX((TCP_TCC_CC_WRITE_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + NC - Atomic: + xfer: Atomic + coherency: NC + avg: AVG((TCP_TCC_NC_ATOMIC_REQ_sum / $denom)) + min: MIN((TCP_TCC_NC_ATOMIC_REQ_sum / $denom)) + max: MAX((TCP_TCC_NC_ATOMIC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + UC - Atomic: + xfer: Atomic + coherency: UC + avg: AVG((TCP_TCC_UC_ATOMIC_REQ_sum / $denom)) + min: MIN((TCP_TCC_UC_ATOMIC_REQ_sum / $denom)) + max: MAX((TCP_TCC_UC_ATOMIC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + CC - Atomic: + xfer: Atomic + coherency: CC + avg: AVG((TCP_TCC_CC_ATOMIC_REQ_sum / $denom)) + min: MIN((TCP_TCC_CC_ATOMIC_REQ_sum / $denom)) + max: MAX((TCP_TCC_CC_ATOMIC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + RW - Atomic: + xfer: Atomic + coherency: RW + avg: AVG((TCP_TCC_RW_ATOMIC_REQ_sum / $denom)) + min: MIN((TCP_TCC_RW_ATOMIC_REQ_sum / $denom)) + max: MAX((TCP_TCC_RW_ATOMIC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + + - metric_table: + id: 1605 + title: L1D Addr Translation + header: + metric: Metric + avg: Avg + min: Min + max: Max + units: Units + tips: Tips + metric: + Req: + avg: AVG((TCP_UTCL1_REQUEST_sum / $denom)) + min: MIN((TCP_UTCL1_REQUEST_sum / $denom)) + max: MAX((TCP_UTCL1_REQUEST_sum / $denom)) + units: (Req + $normUnit) + tips: + Hit Ratio: + avg: AVG((((100 * TCP_UTCL1_TRANSLATION_HIT_sum) / TCP_UTCL1_REQUEST_sum) if + (TCP_UTCL1_REQUEST_sum != 0) else None)) + min: MIN((((100 * TCP_UTCL1_TRANSLATION_HIT_sum) / TCP_UTCL1_REQUEST_sum) if + (TCP_UTCL1_REQUEST_sum != 0) else None)) + max: MAX((((100 * TCP_UTCL1_TRANSLATION_HIT_sum) / TCP_UTCL1_REQUEST_sum) if + (TCP_UTCL1_REQUEST_sum != 0) else None)) + units: pct + tips: + Hits: + avg: AVG((TCP_UTCL1_TRANSLATION_HIT_sum / $denom)) + min: MIN((TCP_UTCL1_TRANSLATION_HIT_sum / $denom)) + max: MAX((TCP_UTCL1_TRANSLATION_HIT_sum / $denom)) + units: (Hits + $normUnit) + tips: + Misses (Translation): + avg: AVG((TCP_UTCL1_TRANSLATION_MISS_sum / $denom)) + min: MIN((TCP_UTCL1_TRANSLATION_MISS_sum / $denom)) + max: MAX((TCP_UTCL1_TRANSLATION_MISS_sum / $denom)) + units: (Misses + $normUnit) + tips: + Misses (Permission): + avg: AVG((TCP_UTCL1_PERMISSION_MISS_sum / $denom)) + min: MIN((TCP_UTCL1_PERMISSION_MISS_sum / $denom)) + max: MAX((TCP_UTCL1_PERMISSION_MISS_sum / $denom)) + units: (Misses + $normUnit) + tips: diff --git a/src/omniperf_soc/configs/gfx908/1700_L2_cache.yaml b/src/omniperf_soc/configs/gfx908/1700_L2_cache.yaml new file mode 100644 index 0000000000..0c7b03811a --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/1700_L2_cache.yaml @@ -0,0 +1,364 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1700 + title: L2 Cache + data source: + - metric_table: + id: 1701 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + metric: + L2 Util: + value: AVG(((TCC_BUSY_sum * 100) / (TO_INT($L2Banks) * GRBM_GUI_ACTIVE))) + unit: pct + tips: + Cache Hit: + value: AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else 0)) + unit: pct + tips: + L2-EA Rd BW: + value: AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / (EndNs - BeginNs))) + unit: GB/s + tips: + L2-EA Wr BW: + value: AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / (EndNs - BeginNs))) + unit: GB/s + tips: + + - metric_table: + id: 1702 + title: L2 - Fabric Transactions + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Read BW: + avg: AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / $denom)) + min: MIN((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / $denom)) + max: MAX((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / $denom)) + unit: (Bytes + $normUnit) + tips: + Write BW: + avg: AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / $denom)) + min: MIN((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / $denom)) + max: MAX((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / $denom)) + unit: (Bytes + $normUnit) + tips: + Read (32B): + avg: AVG((TCC_EA_RDREQ_32B_sum / $denom)) + min: MIN((TCC_EA_RDREQ_32B_sum / $denom)) + max: MAX((TCC_EA_RDREQ_32B_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read (Uncached 32B): + avg: AVG((TCC_EA_RD_UNCACHED_32B_sum / $denom)) + min: MIN((TCC_EA_RD_UNCACHED_32B_sum / $denom)) + max: MAX((TCC_EA_RD_UNCACHED_32B_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read (64B): + avg: AVG(((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) / $denom)) + min: MIN(((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) / $denom)) + max: MAX(((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) / $denom)) + unit: (Req + $normUnit) + tips: + HBM Read: + avg: AVG((TCC_EA_RDREQ_DRAM_sum / $denom)) + min: MIN((TCC_EA_RDREQ_DRAM_sum / $denom)) + max: MAX((TCC_EA_RDREQ_DRAM_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write (32B): + avg: AVG(((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) / $denom)) + min: MIN(((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) / $denom)) + max: MAX(((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) / $denom)) + unit: (Req + $normUnit) + tips: + Write (Uncached 32B): + avg: AVG((TCC_EA_WR_UNCACHED_32B_sum / $denom)) + min: MIN((TCC_EA_WR_UNCACHED_32B_sum / $denom)) + max: MAX((TCC_EA_WR_UNCACHED_32B_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write (64B): + avg: AVG((TCC_EA_WRREQ_64B_sum / $denom)) + min: MIN((TCC_EA_WRREQ_64B_sum / $denom)) + max: MAX((TCC_EA_WRREQ_64B_sum / $denom)) + unit: (Req + $normUnit) + tips: + HBM Write: + avg: AVG((TCC_EA_WRREQ_DRAM_sum / $denom)) + min: MIN((TCC_EA_WRREQ_DRAM_sum / $denom)) + max: MAX((TCC_EA_WRREQ_DRAM_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read Latency: + avg: AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum != + 0) else None)) + min: MIN(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum != + 0) else None)) + max: MAX(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum != + 0) else None)) + unit: Cycles + tips: + Write Latency: + avg: AVG(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum != + 0) else None)) + min: MIN(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum != + 0) else None)) + max: MAX(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum != + 0) else None)) + unit: Cycles + tips: + Atomic Latency: + avg: AVG(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum + != 0) else None)) + min: MIN(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum + != 0) else None)) + max: MAX(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum + != 0) else None)) + unit: Cycles + tips: + Read Stall: + avg: AVG((((100 * ((TCC_EA_RDREQ_IO_CREDIT_STALL_sum + TCC_EA_RDREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + min: MIN((((100 * ((TCC_EA_RDREQ_IO_CREDIT_STALL_sum + TCC_EA_RDREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + max: MAX((((100 * ((TCC_EA_RDREQ_IO_CREDIT_STALL_sum + TCC_EA_RDREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + unit: pct + tips: + Write Stall: + avg: AVG((((100 * ((TCC_EA_WRREQ_IO_CREDIT_STALL_sum + TCC_EA_WRREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + min: MIN((((100 * ((TCC_EA_WRREQ_IO_CREDIT_STALL_sum + TCC_EA_WRREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + max: MAX((((100 * ((TCC_EA_WRREQ_IO_CREDIT_STALL_sum + TCC_EA_WRREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + unit: pct + tips: + + - metric_table: + id: 1703 + title: L2 Cache Accesses + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Req: + avg: AVG((TCC_REQ_sum / $denom)) + min: MIN((TCC_REQ_sum / $denom)) + max: MAX((TCC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + Streaming Req: + avg: AVG((TCC_STREAMING_REQ_sum / $denom)) + min: MIN((TCC_STREAMING_REQ_sum / $denom)) + max: MAX((TCC_STREAMING_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read Req: + avg: AVG((TCC_READ_sum / $denom)) + min: MIN((TCC_READ_sum / $denom)) + max: MAX((TCC_READ_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write Req: + avg: AVG((TCC_WRITE_sum / $denom)) + min: MIN((TCC_WRITE_sum / $denom)) + max: MAX((TCC_WRITE_sum / $denom)) + unit: (Req + $normUnit) + tips: + Atomic Req: + avg: AVG((TCC_ATOMIC_sum / $denom)) + min: MIN((TCC_ATOMIC_sum / $denom)) + max: MAX((TCC_ATOMIC_sum / $denom)) + unit: (Req + $normUnit) + tips: + Probe Req: + avg: AVG((TCC_PROBE_sum / $denom)) + min: MIN((TCC_PROBE_sum / $denom)) + max: MAX((TCC_PROBE_sum / $denom)) + unit: (Req + $normUnit) + tips: + Hits: + avg: AVG((TCC_HIT_sum / $denom)) + min: MIN((TCC_HIT_sum / $denom)) + max: MAX((TCC_HIT_sum / $denom)) + unit: (Hits + $normUnit) + tips: + Misses: + avg: AVG((TCC_MISS_sum / $denom)) + min: MIN((TCC_MISS_sum / $denom)) + max: MAX((TCC_MISS_sum / $denom)) + unit: (Misses + $normUnit) + tips: + Cache Hit: + avg: AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + min: MIN((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + max: MAX((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + unit: pct + tips: + Writeback: + avg: AVG((TCC_WRITEBACK_sum / $denom)) + min: MIN((TCC_WRITEBACK_sum / $denom)) + max: MAX((TCC_WRITEBACK_sum / $denom)) + unit: ( + $normUnit) + tips: + NC Req: + avg: AVG((TCC_NC_REQ_sum / $denom)) + min: MIN((TCC_NC_REQ_sum / $denom)) + max: MAX((TCC_NC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + UC Req: + avg: AVG((TCC_UC_REQ_sum / $denom)) + min: MIN((TCC_UC_REQ_sum / $denom)) + max: MAX((TCC_UC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + CC Req: + avg: AVG((TCC_CC_REQ_sum / $denom)) + min: MIN((TCC_CC_REQ_sum / $denom)) + max: MAX((TCC_CC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + RW Req: + avg: AVG((TCC_RW_REQ_sum / $denom)) + min: MIN((TCC_RW_REQ_sum / $denom)) + max: MAX((TCC_RW_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + Writeback (Normal): + avg: AVG((TCC_NORMAL_WRITEBACK_sum / $denom)) + min: MIN((TCC_NORMAL_WRITEBACK_sum / $denom)) + max: MAX((TCC_NORMAL_WRITEBACK_sum / $denom)) + unit: ( + $normUnit) + tips: + Writeback (TC Req): + avg: AVG((TCC_ALL_TC_OP_WB_WRITEBACK_sum / $denom)) + min: MIN((TCC_ALL_TC_OP_WB_WRITEBACK_sum / $denom)) + max: MAX((TCC_ALL_TC_OP_WB_WRITEBACK_sum / $denom)) + unit: ( + $normUnit) + tips: + Evict (Normal): + avg: AVG((TCC_NORMAL_EVICT_sum / $denom)) + min: MIN((TCC_NORMAL_EVICT_sum / $denom)) + max: MAX((TCC_NORMAL_EVICT_sum / $denom)) + unit: ( + $normUnit) + tips: + Evict (TC Req): + avg: AVG((TCC_ALL_TC_OP_INV_EVICT_sum / $denom)) + min: MIN((TCC_ALL_TC_OP_INV_EVICT_sum / $denom)) + max: MAX((TCC_ALL_TC_OP_INV_EVICT_sum / $denom)) + unit: ( + $normUnit) + tips: + + - metric_table: + id: 1704 + title: L2 - EA Interface Stalls + header: + metric: Metric + type: Type + transaction: Transaction + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + style: + type: simple_multi_bar + metric: + Read - Remote Socket Stall: + type: Remote Socket Stall + transaction: Read + avg: AVG((TCC_EA_RDREQ_IO_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_RDREQ_IO_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_RDREQ_IO_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read - Peer GCD Stall: + type: Peer GCD Stall + transaction: Read + avg: AVG((TCC_EA_RDREQ_GMI_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_RDREQ_GMI_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_RDREQ_GMI_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read - HBM Stall: + type: HBM Stall + transaction: Read + avg: AVG((TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write - Remote Socket Stall: + type: Remote Socket Stall + transaction: Write + avg: AVG((TCC_EA_WRREQ_IO_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_WRREQ_IO_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_WRREQ_IO_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write - Peer GCD Stall: + type: Peer GCD Stall + transaction: Write + avg: AVG((TCC_EA_WRREQ_GMI_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_WRREQ_GMI_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_WRREQ_GMI_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write - HBM Stall: + type: HBM Stall + transaction: Write + avg: AVG((TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write - Credit Starvation: + type: Credit Starvation + transaction: Write + avg: AVG((TCC_TOO_MANY_EA_WRREQS_STALL_sum / $denom)) + min: MIN((TCC_TOO_MANY_EA_WRREQS_STALL_sum / $denom)) + max: MAX((TCC_TOO_MANY_EA_WRREQS_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: diff --git a/src/omniperf_soc/configs/gfx908/1800_L2_cache_per_channel.yaml b/src/omniperf_soc/configs/gfx908/1800_L2_cache_per_channel.yaml new file mode 100644 index 0000000000..45f8abb413 --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/1800_L2_cache_per_channel.yaml @@ -0,0 +1,2297 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1800 + title: L2 Cache (per Channel) + data source: + - metric_table: + id: 1801 + title: Aggregate Stats (All 32 channels) + header: + metric: Metric + avg: Avg + std dev: Std Dev + min: Min + max: Max + unit: Unit + tips: Tips + metric: + L2 Cache Hit Rate: + avg: AVG(((((((((((((((((((((((((((((((((((100 * TCC_HIT[0]) + (100 * TCC_HIT[1])) + + (100 * TCC_HIT[2])) + (100 * TCC_HIT[3])) + (100 * TCC_HIT[4])) + (100 * + TCC_HIT[5])) + (100 * TCC_HIT[6])) + (100 * TCC_HIT[7])) + (100 * TCC_HIT[8])) + + (100 * TCC_HIT[9])) + (100 * TCC_HIT[10])) + (100 * TCC_HIT[11])) + (100 + * TCC_HIT[12])) + (100 * TCC_HIT[13])) + (100 * TCC_HIT[14])) + (100 * TCC_HIT[15])) + + (100 * TCC_HIT[16])) + (100 * TCC_HIT[17])) + (100 * TCC_HIT[18])) + (100 + * TCC_HIT[19])) + (100 * TCC_HIT[20])) + (100 * TCC_HIT[21])) + (100 * TCC_HIT[22])) + + (100 * TCC_HIT[23])) + (100 * TCC_HIT[24])) + (100 * TCC_HIT[25])) + (100 + * TCC_HIT[26])) + (100 * TCC_HIT[27])) + (100 * TCC_HIT[28])) + (100 * TCC_HIT[29])) + + (100 * TCC_HIT[30])) + (100 * TCC_HIT[31])) / ((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31]))) if (((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[29] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31])) != 0) else None)) + std dev: STD(((((((((((((((((((((((((((((((((((100 * TCC_HIT[0]) + (100 * TCC_HIT[1])) + + (100 * TCC_HIT[2])) + (100 * TCC_HIT[3])) + (100 * TCC_HIT[4])) + (100 * + TCC_HIT[5])) + (100 * TCC_HIT[6])) + (100 * TCC_HIT[7])) + (100 * TCC_HIT[8])) + + (100 * TCC_HIT[9])) + (100 * TCC_HIT[10])) + (100 * TCC_HIT[11])) + (100 + * TCC_HIT[12])) + (100 * TCC_HIT[13])) + (100 * TCC_HIT[14])) + (100 * TCC_HIT[15])) + + (100 * TCC_HIT[16])) + (100 * TCC_HIT[17])) + (100 * TCC_HIT[18])) + (100 + * TCC_HIT[19])) + (100 * TCC_HIT[20])) + (100 * TCC_HIT[21])) + (100 * TCC_HIT[22])) + + (100 * TCC_HIT[23])) + (100 * TCC_HIT[24])) + (100 * TCC_HIT[25])) + (100 + * TCC_HIT[26])) + (100 * TCC_HIT[27])) + (100 * TCC_HIT[28])) + (100 * TCC_HIT[29])) + + (100 * TCC_HIT[30])) + (100 * TCC_HIT[31])) / ((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31]))) if (((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31])) != 0) else None)) + min: MIN(((((((((((((((((((((((((((((((((((100 * TCC_HIT[0]) + (100 * TCC_HIT[1])) + + (100 * TCC_HIT[2])) + (100 * TCC_HIT[3])) + (100 * TCC_HIT[4])) + (100 * + TCC_HIT[5])) + (100 * TCC_HIT[6])) + (100 * TCC_HIT[7])) + (100 * TCC_HIT[8])) + + (100 * TCC_HIT[9])) + (100 * TCC_HIT[10])) + (100 * TCC_HIT[11])) + (100 + * TCC_HIT[12])) + (100 * TCC_HIT[13])) + (100 * TCC_HIT[14])) + (100 * TCC_HIT[15])) + + (100 * TCC_HIT[16])) + (100 * TCC_HIT[17])) + (100 * TCC_HIT[18])) + (100 + * TCC_HIT[19])) + (100 * TCC_HIT[20])) + (100 * TCC_HIT[21])) + (100 * TCC_HIT[22])) + + (100 * TCC_HIT[23])) + (100 * TCC_HIT[24])) + (100 * TCC_HIT[25])) + (100 + * TCC_HIT[26])) + (100 * TCC_HIT[27])) + (100 * TCC_HIT[28])) + (100 * TCC_HIT[29])) + + (100 * TCC_HIT[30])) + (100 * TCC_HIT[31])) / ((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31]))) if (((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31])) != 0) else None)) + max: MAX(((((((((((((((((((((((((((((((((((100 * TCC_HIT[0]) + (100 * TCC_HIT[1])) + + (100 * TCC_HIT[2])) + (100 * TCC_HIT[3])) + (100 * TCC_HIT[4])) + (100 * + TCC_HIT[5])) + (100 * TCC_HIT[6])) + (100 * TCC_HIT[7])) + (100 * TCC_HIT[8])) + + (100 * TCC_HIT[9])) + (100 * TCC_HIT[10])) + (100 * TCC_HIT[11])) + (100 + * TCC_HIT[12])) + (100 * TCC_HIT[13])) + (100 * TCC_HIT[14])) + (100 * TCC_HIT[15])) + + (100 * TCC_HIT[16])) + (100 * TCC_HIT[17])) + (100 * TCC_HIT[18])) + (100 + * TCC_HIT[19])) + (100 * TCC_HIT[20])) + (100 * TCC_HIT[21])) + (100 * TCC_HIT[22])) + + (100 * TCC_HIT[23])) + (100 * TCC_HIT[24])) + (100 * TCC_HIT[25])) + (100 + * TCC_HIT[26])) + (100 * TCC_HIT[27])) + (100 * TCC_HIT[28])) + (100 * TCC_HIT[29])) + + (100 * TCC_HIT[30])) + (100 * TCC_HIT[31])) / ((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31]))) if (((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31])) != 0) else None)) + unit: pct + tips: + Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) + + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) + + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) + + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) + + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) + + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) + + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) + + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) + + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) + + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) + + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) + + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) + + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) + + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) + + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) + + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) + + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) + + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) + + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) + + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) + + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) + + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) + + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) + + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) + + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) + + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) + + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) + + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) + + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) + + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) + + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) + + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) + + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L1 - L2 Read Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) + + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) + + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) + + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + + TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) + + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + + TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) + + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + + TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) + + TO_INT(TCC_READ[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) + + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) + + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) + + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + + TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) + + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + + TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) + + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + + TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) + + TO_INT(TCC_READ[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) + + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) + + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) + + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + + TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) + + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + + TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) + + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + + TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) + + TO_INT(TCC_READ[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) + + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) + + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) + + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + + TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) + + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + + TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) + + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + + TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) + + TO_INT(TCC_READ[31])) / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L1 - L2 Write Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) + + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + + TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) + + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) + + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) + + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) + + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) + + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) + + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) + + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) + + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) + + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + + TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) + + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) + + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) + + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) + + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) + + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) + + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) + + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) + + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) + + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + + TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) + + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) + + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) + + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) + + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) + + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) + + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) + + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) + + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) + + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + + TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) + + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) + + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) + + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) + + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) + + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) + + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) + + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) + + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L1 - L2 Atomic Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) + + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) + + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) + + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) + + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) + + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) + + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) + + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) + + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) + + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) + + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) + / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) + + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) + + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) + + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) + + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) + + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) + + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) + + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) + + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) + + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) + + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) + / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) + + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) + + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) + + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) + + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) + + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) + + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) + + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) + + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) + + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) + + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) + / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) + + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) + + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) + + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) + + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) + + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) + + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) + + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) + + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) + + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) + + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) + / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L2 - EA Read Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) + + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) + + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) + + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) + + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) + + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) + + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) + + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) + + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) + + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) + + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) + / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) + + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) + + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) + + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) + + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) + + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) + + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) + + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) + + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) + + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) + + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) + / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) + + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) + + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) + + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) + + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) + + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) + + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) + + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) + + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) + + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) + + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) + / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) + + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) + + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) + + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) + + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) + + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) + + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) + + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) + + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) + + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) + + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) + / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L2 - EA Write Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) + + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) + + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) + + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) + + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) + + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) + + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) + + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) + + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) + + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) + + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) + / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) + + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) + + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) + + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) + + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) + + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) + + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) + + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) + + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) + + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) + + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) + / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) + + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) + + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) + + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) + + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) + + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) + + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) + + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) + + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) + + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) + + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) + / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) + + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) + + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) + + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) + + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) + + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) + + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) + + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) + + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) + + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) + + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) + / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L2 - EA Atomic Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) + + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) + + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) + + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) + + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) + + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) + + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) + + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) + + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) + + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) + + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) + / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) + + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) + + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) + + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) + + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) + + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) + + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) + + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) + + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) + + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) + + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) + / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) + + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) + + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) + + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) + + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) + + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) + + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) + + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) + + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) + + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) + + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) + / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) + + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) + + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) + + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) + + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) + + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) + + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) + + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) + + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) + + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) + + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) + / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L2 - EA Read Lat: + avg: AVG((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) + + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) + + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) + + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) + + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) + + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) + + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) + + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) + + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) + + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) + + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) + std dev: STD((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) + + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) + + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) + + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) + + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) + + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) + + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) + + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) + + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) + + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) + + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) + min: MIN((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) + + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) + + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) + + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) + + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) + + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) + + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) + + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) + + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) + + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) + + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) + max: MAX((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) + + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) + + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) + + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) + + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) + + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) + + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) + + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) + + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) + + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) + + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) + unit: Cycles + tips: + L2 - EA Write Lat: + avg: AVG((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) + + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) + + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) + + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) + + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) + + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) + + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) + + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) + + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) + + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) + + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) + std dev: STD((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) + + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) + + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) + + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) + + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) + + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) + + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) + + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) + + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) + + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) + + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) + min: MIN((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) + + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) + + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) + + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) + + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) + + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) + + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) + + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) + + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) + + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) + + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) + max: MAX((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) + + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) + + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) + + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) + + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) + + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) + + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) + + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) + + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) + + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) + + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) + unit: Cycles + tips: + L2 - EA Atomic Lat: + avg: AVG((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) + + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) + + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) + + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) + + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) + + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) + + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) + + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) + + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) + + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) + + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else + None)) + std dev: STD((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) + + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) + + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) + + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) + + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) + + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) + + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) + + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) + + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) + + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) + + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else + None)) + min: MIN((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) + + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) + + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) + + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) + + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) + + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) + + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) + + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) + + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) + + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) + + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else + None)) + max: MAX((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) + + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) + + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) + + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) + + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) + + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) + + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) + + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) + + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) + + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) + + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else + None)) + unit: Cycles + tips: + L2 - EA Read Stall (IO): + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + unit: (Cycles + $normUnit) + tips: + L2 - EA Read Stall (GMI): + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + unit: (Cycles + $normUnit) + tips: + L2 - EA Read Stall (DRAM): + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + unit: (Cycles + $normUnit) + tips: + L2 - EA Write Stall (IO): + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + unit: (Cycles + $normUnit) + tips: + L2 - EA Write Stall (GMI): + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + unit: (Cycles + $normUnit) + tips: + L2 - EA Write Stall (DRAM): + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + unit: (Cycles + $normUnit) + tips: + L2 - EA Write Starve: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) + unit: (Cycles + $normUnit) + tips: + - metric_table: + id: 1802 + title: Channel 0-15 + columnwise: True + header: + channel: Channel + hit rate: L2 Cache Hit Rate (%) + req: Requests (Requests) + read req: L1-L2 Read (Requests) + write req: L1-L2 Write (Requests) + atomic req: L1-L2 Atomic (Requests) + ea read req: L2-EA Read (Requests) + ea write req: L2-EA Write (Requests) + ea atomic req: L2-EA Atomic (Requests) + ea read lat - cycles: L2-EA Read Latency (Cycles) + ea write lat - cycles: L2-EA Write Latency (Cycles) + ea atomic lat - cycles: L2-EA Atomic Latency (Cycles) + ea read stall - io: L2-EA Read Stall - IO (Cycles per) + ea read stall - gmi: L2-EA Read Stall - GMI (Cycles per) + ea read stall - dram: L2-EA Read Stall - DRAM (Cycles per) + ea write stall - io: L2-EA Write Stall - IO (Cycles per) + ea write stall - gmi: L2-EA Write Stall - GMI (Cycles per) + ea write stall - dram: L2-EA Write Stall - DRAM (Cycles per) + ea write stall - starve: L2-EA Write Stall - Starve (Cycles per) + tips: Tips + metric: + "0": + hit rate: + AVG((((100 * TCC_HIT[0]) / (TCC_HIT[0] + TCC_MISS[0])) if ((TCC_HIT[0] + + TCC_MISS[0]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[0]) / $denom)) + read req: AVG((TO_INT(TCC_READ[0]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[0]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[0]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[0]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[0]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[0]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[0] / TCC_EA_RDREQ[0]) if (TCC_EA_RDREQ[0] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[0] / TCC_EA_WRREQ[0]) if (TCC_EA_WRREQ[0] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[0] / TCC_EA_ATOMIC[0]) if + (TCC_EA_ATOMIC[0] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) / $denom)) + tips: + "1": + hit rate: + AVG((((100 * TCC_HIT[1]) / (TCC_HIT[1] + TCC_MISS[1])) if ((TCC_HIT[1] + + TCC_MISS[1]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[1]) / $denom)) + read req: AVG((TO_INT(TCC_READ[1]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[1]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[1]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[1]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[1]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[1]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[1] / TCC_EA_RDREQ[1]) if (TCC_EA_RDREQ[1] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[1] / TCC_EA_WRREQ[1]) if (TCC_EA_WRREQ[1] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[1] / TCC_EA_ATOMIC[1]) if + (TCC_EA_ATOMIC[1] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1]) / $denom)) + tips: + "2": + hit rate: + AVG((((100 * TCC_HIT[2]) / (TCC_HIT[2] + TCC_MISS[2])) if ((TCC_HIT[2] + + TCC_MISS[2]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[2]) / $denom)) + read req: AVG((TO_INT(TCC_READ[2]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[2]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[2]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[2]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[2]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[2]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[2] / TCC_EA_RDREQ[2]) if (TCC_EA_RDREQ[2] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[2] / TCC_EA_WRREQ[2]) if (TCC_EA_WRREQ[2] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[2] / TCC_EA_ATOMIC[2]) if + (TCC_EA_ATOMIC[2] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2]) / $denom)) + tips: + "3": + hit rate: + AVG((((100 * TCC_HIT[3]) / (TCC_HIT[3] + TCC_MISS[3])) if ((TCC_HIT[3] + + TCC_MISS[3]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[3]) / $denom)) + read req: AVG((TO_INT(TCC_READ[3]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[3]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[3]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[3]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[3]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[3]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[3] / TCC_EA_RDREQ[3]) if (TCC_EA_RDREQ[3] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[3] / TCC_EA_WRREQ[3]) if (TCC_EA_WRREQ[3] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[3] / TCC_EA_ATOMIC[3]) if + (TCC_EA_ATOMIC[3] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3]) / $denom)) + tips: + "4": + hit rate: + AVG((((100 * TCC_HIT[4]) / (TCC_HIT[4] + TCC_MISS[4])) if ((TCC_HIT[4] + + TCC_MISS[4]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[4]) / $denom)) + read req: AVG((TO_INT(TCC_READ[4]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[4]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[4]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[4]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[4]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[4]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[4] / TCC_EA_RDREQ[4]) if (TCC_EA_RDREQ[4] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[4] / TCC_EA_WRREQ[4]) if (TCC_EA_WRREQ[4] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[4] / TCC_EA_ATOMIC[4]) if + (TCC_EA_ATOMIC[4] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4]) / $denom)) + tips: + "5": + hit rate: + AVG((((100 * TCC_HIT[5]) / (TCC_HIT[5] + TCC_MISS[5])) if ((TCC_HIT[5] + + TCC_MISS[5]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[5]) / $denom)) + read req: AVG((TO_INT(TCC_READ[5]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[5]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[5]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[5]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[5]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[5]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[5] / TCC_EA_RDREQ[5]) if (TCC_EA_RDREQ[5] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[5] / TCC_EA_WRREQ[5]) if (TCC_EA_WRREQ[5] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[5] / TCC_EA_ATOMIC[5]) if + (TCC_EA_ATOMIC[5] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5]) / $denom)) + tips: + "6": + hit rate: + AVG((((100 * TCC_HIT[6]) / (TCC_HIT[6] + TCC_MISS[6])) if ((TCC_HIT[6] + + TCC_MISS[6]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[6]) / $denom)) + read req: AVG((TO_INT(TCC_READ[6]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[6]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[6]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[6]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[6]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[6]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[6] / TCC_EA_RDREQ[6]) if (TCC_EA_RDREQ[6] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[6] / TCC_EA_WRREQ[6]) if (TCC_EA_WRREQ[6] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[6] / TCC_EA_ATOMIC[6]) if + (TCC_EA_ATOMIC[6] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6]) / $denom)) + tips: + "7": + hit rate: + AVG((((100 * TCC_HIT[7]) / (TCC_HIT[7] + TCC_MISS[7])) if ((TCC_HIT[7] + + TCC_MISS[7]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[7]) / $denom)) + read req: AVG((TO_INT(TCC_READ[7]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[7]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[7]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[7]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[7]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[7]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[7] / TCC_EA_RDREQ[7]) if (TCC_EA_RDREQ[7] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[7] / TCC_EA_WRREQ[7]) if (TCC_EA_WRREQ[7] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[7] / TCC_EA_ATOMIC[7]) if + (TCC_EA_ATOMIC[7] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7]) / $denom)) + tips: + "8": + hit rate: + AVG((((100 * TCC_HIT[8]) / (TCC_HIT[8] + TCC_MISS[8])) if ((TCC_HIT[8] + + TCC_MISS[8]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[8]) / $denom)) + read req: AVG((TO_INT(TCC_READ[8]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[8]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[8]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[8]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[8]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[8]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[8] / TCC_EA_RDREQ[8]) if (TCC_EA_RDREQ[8] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[8] / TCC_EA_WRREQ[8]) if (TCC_EA_WRREQ[8] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[8] / TCC_EA_ATOMIC[8]) if + (TCC_EA_ATOMIC[8] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8]) / $denom)) + tips: + "9": + hit rate: + AVG((((100 * TCC_HIT[9]) / (TCC_HIT[9] + TCC_MISS[9])) if ((TCC_HIT[9] + + TCC_MISS[9]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[9]) / $denom)) + read req: AVG((TO_INT(TCC_READ[9]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[9]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[9]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[9]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[9]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[9]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[9] / TCC_EA_RDREQ[9]) if (TCC_EA_RDREQ[9] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[9] / TCC_EA_WRREQ[9]) if (TCC_EA_WRREQ[9] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[9] / TCC_EA_ATOMIC[9]) if + (TCC_EA_ATOMIC[9] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9]) / $denom)) + tips: + "10": + hit rate: + AVG((((100 * TCC_HIT[10]) / (TCC_HIT[10] + TCC_MISS[10])) if ((TCC_HIT[10] + + TCC_MISS[10]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[10]) / $denom)) + read req: AVG((TO_INT(TCC_READ[10]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[10]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[10]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[10]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[10]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[10]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[10] / TCC_EA_RDREQ[10]) if (TCC_EA_RDREQ[10] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[10] / TCC_EA_WRREQ[10]) if (TCC_EA_WRREQ[10] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[10] / TCC_EA_ATOMIC[10]) if + (TCC_EA_ATOMIC[10] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10]) / $denom)) + tips: + "11": + hit rate: + AVG((((100 * TCC_HIT[11]) / (TCC_HIT[11] + TCC_MISS[11])) if ((TCC_HIT[11] + + TCC_MISS[11]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[11]) / $denom)) + read req: AVG((TO_INT(TCC_READ[11]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[11]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[11]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[11]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[11]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[11]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[11] / TCC_EA_RDREQ[11]) if (TCC_EA_RDREQ[11] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[11] / TCC_EA_WRREQ[11]) if (TCC_EA_WRREQ[11] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[11] / TCC_EA_ATOMIC[11]) if + (TCC_EA_ATOMIC[11] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11]) / $denom)) + tips: + "12": + hit rate: + AVG((((100 * TCC_HIT[12]) / (TCC_HIT[12] + TCC_MISS[12])) if ((TCC_HIT[12] + + TCC_MISS[12]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[12]) / $denom)) + read req: AVG((TO_INT(TCC_READ[12]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[12]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[12]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[12]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[12]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[12]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[12] / TCC_EA_RDREQ[12]) if (TCC_EA_RDREQ[12] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[12] / TCC_EA_WRREQ[12]) if (TCC_EA_WRREQ[12] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[12] / TCC_EA_ATOMIC[12]) if + (TCC_EA_ATOMIC[12] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12]) / $denom)) + tips: + "13": + hit rate: + AVG((((100 * TCC_HIT[13]) / (TCC_HIT[13] + TCC_MISS[13])) if ((TCC_HIT[13] + + TCC_MISS[13]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[13]) / $denom)) + read req: AVG((TO_INT(TCC_READ[13]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[13]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[13]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[13]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[13]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[13]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[13] / TCC_EA_RDREQ[13]) if (TCC_EA_RDREQ[13] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[13] / TCC_EA_WRREQ[13]) if (TCC_EA_WRREQ[13] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[13] / TCC_EA_ATOMIC[13]) if + (TCC_EA_ATOMIC[13] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13]) / $denom)) + tips: + "14": + hit rate: + AVG((((100 * TCC_HIT[14]) / (TCC_HIT[14] + TCC_MISS[14])) if ((TCC_HIT[14] + + TCC_MISS[14]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[14]) / $denom)) + read req: AVG((TO_INT(TCC_READ[14]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[14]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[14]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[14]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[14]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[14]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[14] / TCC_EA_RDREQ[14]) if (TCC_EA_RDREQ[14] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[14] / TCC_EA_WRREQ[14]) if (TCC_EA_WRREQ[14] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[14] / TCC_EA_ATOMIC[14]) if + (TCC_EA_ATOMIC[14] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14]) / $denom)) + tips: + "15": + hit rate: + AVG((((100 * TCC_HIT[15]) / (TCC_HIT[15] + TCC_MISS[15])) if ((TCC_HIT[15] + + TCC_MISS[15]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[15]) / $denom)) + read req: AVG((TO_INT(TCC_READ[15]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[15]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[15]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[15]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[15]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[15]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[15] / TCC_EA_RDREQ[15]) if (TCC_EA_RDREQ[15] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[15] / TCC_EA_WRREQ[15]) if (TCC_EA_WRREQ[15] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[15] / TCC_EA_ATOMIC[15]) if + (TCC_EA_ATOMIC[15] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15]) / $denom)) + tips: + + - metric_table: + id: 1803 + title: Channel 16-31 + columnwise: True + header: + channel: Channel + hit rate: L2 Cache Hit Rate (%) + req: Requests (Requests) + read req: L1-L2 Read (Requests) + write req: L1-L2 Write (Requests) + atomic req: L1-L2 Atomic (Requests) + ea read req: L2-EA Read (Requests) + ea write req: L2-EA Write (Requests) + ea atomic req: L2-EA Atomic (Requests) + ea read lat - cycles: L2-EA Read Latency (Cycles) + ea write lat - cycles: L2-EA Write Latency (Cycles) + ea atomic lat - cycles: L2-EA Atomic Latency (Cycles) + ea read stall - io: L2-EA Read Stall - IO (Cycles per) + ea read stall - gmi: L2-EA Read Stall - GMI (Cycles per) + ea read stall - dram: L2-EA Read Stall - DRAM (Cycles per) + ea write stall - io: L2-EA Write Stall - IO (Cycles per) + ea write stall - gmi: L2-EA Write Stall - GMI (Cycles per) + ea write stall - dram: L2-EA Write Stall - DRAM (Cycles per) + ea write stall - starve: L2-EA Write Stall - Starve (Cycles per) + tips: Tips + metric: + "16": + hit rate: + AVG((((100 * TCC_HIT[16]) / (TCC_HIT[16] + TCC_MISS[16])) if ((TCC_HIT[16] + + TCC_MISS[16]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[16]) / $denom)) + read req: AVG((TO_INT(TCC_READ[16]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[16]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[16]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[16]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[16]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[16]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[16] / TCC_EA_RDREQ[16]) if (TCC_EA_RDREQ[16] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[16] / TCC_EA_WRREQ[16]) if (TCC_EA_WRREQ[16] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[16] / TCC_EA_ATOMIC[16]) if + (TCC_EA_ATOMIC[16] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16]) / $denom)) + tips: + "17": + hit rate: + AVG((((100 * TCC_HIT[17]) / (TCC_HIT[17] + TCC_MISS[17])) if ((TCC_HIT[17] + + TCC_MISS[17]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[17]) / $denom)) + read req: AVG((TO_INT(TCC_READ[17]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[17]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[17]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[17]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[17]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[17]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[17] / TCC_EA_RDREQ[17]) if (TCC_EA_RDREQ[17] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[17] / TCC_EA_WRREQ[17]) if (TCC_EA_WRREQ[17] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[17] / TCC_EA_ATOMIC[17]) if + (TCC_EA_ATOMIC[17] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17]) / $denom)) + tips: + "18": + hit rate: + AVG((((100 * TCC_HIT[18]) / (TCC_HIT[18] + TCC_MISS[18])) if ((TCC_HIT[18] + + TCC_MISS[18]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[18]) / $denom)) + read req: AVG((TO_INT(TCC_READ[18]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[18]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[18]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[18]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[18]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[18]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[18] / TCC_EA_RDREQ[18]) if (TCC_EA_RDREQ[18] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[18] / TCC_EA_WRREQ[18]) if (TCC_EA_WRREQ[18] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[18] / TCC_EA_ATOMIC[18]) if + (TCC_EA_ATOMIC[18] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18]) / $denom)) + tips: + "19": + hit rate: + AVG((((100 * TCC_HIT[19]) / (TCC_HIT[19] + TCC_MISS[19])) if ((TCC_HIT[19] + + TCC_MISS[19]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[19]) / $denom)) + read req: AVG((TO_INT(TCC_READ[19]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[19]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[19]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[19]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[19]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[19]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[19] / TCC_EA_RDREQ[19]) if (TCC_EA_RDREQ[19] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[19] / TCC_EA_WRREQ[19]) if (TCC_EA_WRREQ[19] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[19] / TCC_EA_ATOMIC[19]) if + (TCC_EA_ATOMIC[19] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19]) / $denom)) + tips: + "20": + hit rate: + AVG((((100 * TCC_HIT[20]) / (TCC_HIT[20] + TCC_MISS[20])) if ((TCC_HIT[20] + + TCC_MISS[20]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[20]) / $denom)) + read req: AVG((TO_INT(TCC_READ[20]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[20]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[20]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[20]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[20]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[20]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[20] / TCC_EA_RDREQ[20]) if (TCC_EA_RDREQ[20] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[20] / TCC_EA_WRREQ[20]) if (TCC_EA_WRREQ[20] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[20] / TCC_EA_ATOMIC[20]) if + (TCC_EA_ATOMIC[20] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20]) / $denom)) + tips: + "21": + hit rate: + AVG((((100 * TCC_HIT[21]) / (TCC_HIT[21] + TCC_MISS[21])) if ((TCC_HIT[21] + + TCC_MISS[21]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[21]) / $denom)) + read req: AVG((TO_INT(TCC_READ[21]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[21]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[21]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[21]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[21]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[21]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[21] / TCC_EA_RDREQ[21]) if (TCC_EA_RDREQ[21] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[21] / TCC_EA_WRREQ[21]) if (TCC_EA_WRREQ[21] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[21] / TCC_EA_ATOMIC[21]) if + (TCC_EA_ATOMIC[21] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21]) / $denom)) + tips: + "22": + hit rate: + AVG((((100 * TCC_HIT[22]) / (TCC_HIT[22] + TCC_MISS[22])) if ((TCC_HIT[22] + + TCC_MISS[22]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[22]) / $denom)) + read req: AVG((TO_INT(TCC_READ[22]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[22]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[22]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[22]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[22]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[22]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[22] / TCC_EA_RDREQ[22]) if (TCC_EA_RDREQ[22] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[22] / TCC_EA_WRREQ[22]) if (TCC_EA_WRREQ[22] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[22] / TCC_EA_ATOMIC[22]) if + (TCC_EA_ATOMIC[22] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22]) / $denom)) + tips: + "23": + hit rate: + AVG((((100 * TCC_HIT[23]) / (TCC_HIT[23] + TCC_MISS[23])) if ((TCC_HIT[23] + + TCC_MISS[23]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[23]) / $denom)) + read req: AVG((TO_INT(TCC_READ[23]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[23]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[23]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[23]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[23]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[23]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[23] / TCC_EA_RDREQ[23]) if (TCC_EA_RDREQ[23] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[23] / TCC_EA_WRREQ[23]) if (TCC_EA_WRREQ[23] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[23] / TCC_EA_ATOMIC[23]) if + (TCC_EA_ATOMIC[23] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23]) / $denom)) + tips: + "24": + hit rate: + AVG((((100 * TCC_HIT[24]) / (TCC_HIT[24] + TCC_MISS[24])) if ((TCC_HIT[24] + + TCC_MISS[24]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[24]) / $denom)) + read req: AVG((TO_INT(TCC_READ[24]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[24]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[24]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[24]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[24]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[24]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[24] / TCC_EA_RDREQ[24]) if (TCC_EA_RDREQ[24] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[24] / TCC_EA_WRREQ[24]) if (TCC_EA_WRREQ[24] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[24] / TCC_EA_ATOMIC[24]) if + (TCC_EA_ATOMIC[24] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24]) / $denom)) + tips: + "25": + hit rate: + AVG((((100 * TCC_HIT[25]) / (TCC_HIT[25] + TCC_MISS[25])) if ((TCC_HIT[25] + + TCC_MISS[25]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[25]) / $denom)) + read req: AVG((TO_INT(TCC_READ[25]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[25]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[25]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[25]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[25]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[25]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[25] / TCC_EA_RDREQ[25]) if (TCC_EA_RDREQ[25] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[25] / TCC_EA_WRREQ[25]) if (TCC_EA_WRREQ[25] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[25] / TCC_EA_ATOMIC[25]) if + (TCC_EA_ATOMIC[25] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25]) / $denom)) + tips: + "26": + hit rate: + AVG((((100 * TCC_HIT[26]) / (TCC_HIT[26] + TCC_MISS[26])) if ((TCC_HIT[26] + + TCC_MISS[26]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[26]) / $denom)) + read req: AVG((TO_INT(TCC_READ[26]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[26]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[26]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[26]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[26]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[26]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[26] / TCC_EA_RDREQ[26]) if (TCC_EA_RDREQ[26] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[26] / TCC_EA_WRREQ[26]) if (TCC_EA_WRREQ[26] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[26] / TCC_EA_ATOMIC[26]) if + (TCC_EA_ATOMIC[26] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26]) / $denom)) + tips: + "27": + hit rate: + AVG((((100 * TCC_HIT[27]) / (TCC_HIT[27] + TCC_MISS[27])) if ((TCC_HIT[27] + + TCC_MISS[27]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[27]) / $denom)) + read req: AVG((TO_INT(TCC_READ[27]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[27]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[27]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[27]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[27]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[27]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[27] / TCC_EA_RDREQ[27]) if (TCC_EA_RDREQ[27] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[27] / TCC_EA_WRREQ[27]) if (TCC_EA_WRREQ[27] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[27] / TCC_EA_ATOMIC[27]) if + (TCC_EA_ATOMIC[27] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27]) / $denom)) + tips: + "28": + hit rate: + AVG((((100 * TCC_HIT[28]) / (TCC_HIT[28] + TCC_MISS[28])) if ((TCC_HIT[28] + + TCC_MISS[28]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[28]) / $denom)) + read req: AVG((TO_INT(TCC_READ[28]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[28]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[28]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[28]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[28]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[28]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[28] / TCC_EA_RDREQ[28]) if (TCC_EA_RDREQ[28] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[28] / TCC_EA_WRREQ[28]) if (TCC_EA_WRREQ[28] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[28] / TCC_EA_ATOMIC[28]) if + (TCC_EA_ATOMIC[28] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28]) / $denom)) + tips: + "29": + hit rate: + AVG((((100 * TCC_HIT[29]) / (TCC_HIT[29] + TCC_MISS[29])) if ((TCC_HIT[29] + + TCC_MISS[29]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[29]) / $denom)) + read req: AVG((TO_INT(TCC_READ[29]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[29]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[29]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[29]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[29]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[29]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[29] / TCC_EA_RDREQ[29]) if (TCC_EA_RDREQ[29] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[29] / TCC_EA_WRREQ[29]) if (TCC_EA_WRREQ[29] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[29] / TCC_EA_ATOMIC[29]) if + (TCC_EA_ATOMIC[29] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29]) / $denom)) + tips: + "30": + hit rate: + AVG((((100 * TCC_HIT[30]) / (TCC_HIT[30] + TCC_MISS[30])) if ((TCC_HIT[30] + + TCC_MISS[30]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[30]) / $denom)) + read req: AVG((TO_INT(TCC_READ[30]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[30]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[30]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[30]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[30]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[30]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[30] / TCC_EA_RDREQ[30]) if (TCC_EA_RDREQ[30] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[30] / TCC_EA_WRREQ[30]) if (TCC_EA_WRREQ[30] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[30] / TCC_EA_ATOMIC[30]) if + (TCC_EA_ATOMIC[30] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30]) / $denom)) + tips: + "31": + hit rate: + AVG((((100 * TCC_HIT[31]) / (TCC_HIT[31] + TCC_MISS[31])) if ((TCC_HIT[31] + + TCC_MISS[31]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[31]) / $denom)) + read req: AVG((TO_INT(TCC_READ[31]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[31]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[31]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[31]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[31]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[31]) / $denom)) + ea read lat - cycles: + AVG(((TCC_EA_RDREQ_LEVEL[31] / TCC_EA_RDREQ[31]) if (TCC_EA_RDREQ[31] + != 0) else None)) + ea write lat - cycles: + AVG(((TCC_EA_WRREQ_LEVEL[31] / TCC_EA_WRREQ[31]) if (TCC_EA_WRREQ[31] + != 0) else None)) + ea atomic lat - cycles: + AVG(((TCC_EA_ATOMIC_LEVEL[31] / TCC_EA_ATOMIC[31]) if + (TCC_EA_ATOMIC[31] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31]) / $denom)) + tips: diff --git a/src/omniperf_soc/configs/gfx908/1900_memory_chart.yaml b/src/omniperf_soc/configs/gfx908/1900_memory_chart.yaml new file mode 100644 index 0000000000..3728934e2b --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/1900_memory_chart.yaml @@ -0,0 +1,259 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1900 + title: Memory Chart Analysis + data source: + - metric_table: + id: 1901 + title: # subtitle for this table(optional) + header: + metric: Metric + value: Value + alias: Alias + tips: Tips + metric: + Wave Life: + value: ROUND(AVG(((4 * (SQ_WAVE_CYCLES / SQ_WAVES)) if (SQ_WAVES != 0) else + None)), 0) + alias: wave_life_ + tips: + Active CUs: + value: CONCAT(CONCAT($numActiveCUs, "/"), $numCU) + alias: active_cu_ + tips: + SALU: + value: ROUND(AVG((SQ_INSTS_SALU / $denom)), 0) + alias: salu_ + tips: + SMEM: + value: ROUND(AVG((SQ_INSTS_SMEM / $denom)), 0) + alias: smem_ + tips: + VALU: + value: ROUND(AVG((SQ_INSTS_VALU / $denom)), 0) + alias: valu_ + tips: + MFMA: + value: None # No perf counter + alias: mfma_ + tips: + VMEM: + value: ROUND(AVG((SQ_INSTS_VMEM / $denom)), 0) + alias: vmem_ + tips: + LDS: + value: ROUND(AVG((SQ_INSTS_LDS / $denom)), 0) + alias: lds_ + tips: + GWS: + value: ROUND(AVG((SQ_INSTS_GDS / $denom)), 0) + alias: gws_ + tips: + BR: + value: ROUND(AVG((SQ_INSTS_BRANCH / $denom)), 0) + alias: br_ + tips: + VGPR: + value: ROUND(AVG(vgpr), 0) + alias: vgpr_ + tips: + SGPR: + value: ROUND(AVG(sgpr), 0) + alias: sgpr_ + tips: + LDS Allocation: + value: ROUND(AVG(lds), 0) + alias: lds_alloc_ + tips: + Scratch Allocation: + value: ROUND(AVG(scr), 0) + alias: scratch_alloc_ + tips: + Wavefronts: + value: ROUND(AVG(SPI_CSN_WAVE), 0) + alias: wavefronts_ + tips: + Workgroups: + value: ROUND(AVG(SPI_CSN_NUM_THREADGROUPS), 0) + alias: workgroups_ + tips: + LDS Req: + value: ROUND(AVG((SQ_INSTS_LDS / $denom)), 0) + alias: lds_req_ + tips: + IL1 Fetch: + value: ROUND(AVG((SQC_ICACHE_REQ / $denom)), 0) + alias: il1_fetch_ + tips: + IL1 Hit: + value: ROUND((AVG((SQC_ICACHE_HITS / SQC_ICACHE_REQ)) * 100), 0) + alias: il1_hit_ + tips: + IL1_L2 Rd: + value: ROUND(AVG((SQC_TC_INST_REQ / $denom)), 0) + alias: il1_l2_req_ + tips: + vL1D Rd: + value: ROUND(AVG((SQC_DCACHE_REQ / $denom)), 0) + alias: sl1_rd_ + tips: + vL1D Hit: + value: ROUND((AVG(((SQC_DCACHE_HITS / SQC_DCACHE_REQ) if (SQC_DCACHE_REQ != + 0) else None)) * 100), 0) + alias: sl1_hit_ + tips: + vL1D_L2 Rd: + value: ROUND(AVG((SQC_TC_DATA_READ_REQ / $denom)), 0) + alias: sl1_l2_rd_ + tips: + vL1D_L2 Wr: + value: ROUND(AVG((SQC_TC_DATA_WRITE_REQ / $denom)), 0) + alias: sl1_l2_wr_ + tips: + vL1D_L2 Atomic: + value: ROUND(AVG((SQC_TC_DATA_ATOMIC_REQ / $denom)), 0) + alias: sl1_l2_atom_ + tips: + VL1 Rd: + value: ROUND(AVG((TCP_TOTAL_READ_sum / $denom)), 0) + alias: vl1_rd_ + tips: + VL1 Wr: + value: ROUND(AVG((TCP_TOTAL_WRITE_sum / $denom)), 0) + alias: vl1_wr_ + tips: + VL1 Atomic: + value: ROUND(AVG(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) + / $denom)), 0) + alias: vl1_atom_ + tips: + VL1 Hit: + value: ROUND(AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)), 0) + alias: vl1_hit_ + tips: + VL1 Lat: + value: ROUND(AVG(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum + != 0) else None)), 0) + alias: vl1_lat_ + tips: + VL1_L2 Rd: + value: ROUND(AVG((TCP_TCC_READ_REQ_sum / $denom)), 0) + alias: vl1_l2_rd_ + tips: + VL1_L2 Wr: + value: ROUND(AVG((TCP_TCC_WRITE_REQ_sum / $denom)), 0) + alias: vl1_l2_wr_ + tips: + vL1_L2 Atomic: + value: ROUND(AVG(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + / $denom)), 0) + alias: vl1_l2_atom_ + tips: + L2 Rd: + value: ROUND(AVG((TCC_READ_sum / $denom)), 0) + alias: l2_rd_ + tips: + L2 Wr: + value: ROUND(AVG((TCC_WRITE_sum / $denom)), 0) + alias: l2_wr_ + tips: + L2 Atomic: + value: ROUND(AVG((TCC_ATOMIC_sum / $denom)), 0) + alias: l2_atom_ + tips: + L2 Hit: + value: ROUND(AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)), 0) + alias: l2_hit_ + tips: + L2 Rd Lat: + value: ROUND(AVG(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) + if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)), + 0) + alias: l2_rd_lat_ + tips: + L2 Wr Lat: + value: ROUND(AVG(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + != 0) else None)), 0) + alias: l2_wr_lat_ + tips: + Fabric Rd Lat: + value: ROUND(AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum + != 0) else None)), 0) + alias: fabric_rd_lat_ + tips: + Fabric Wr Lat: + value: ROUND(AVG(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum + != 0) else None)), 0) + alias: fabric_wr_lat_ + tips: + Fabric Atomic Lat: + value: ROUND(AVG(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum + != 0) else None)), 0) + alias: fabric_atom_lat_ + tips: + Fabric_L2 Rd: + value: ROUND(AVG((TCC_EA_RDREQ_sum / $denom)), 0) + alias: l2_fabric_rd_ + tips: + Fabric_L2 Wr: + value: ROUND(AVG((TCC_EA_WRREQ_sum / $denom)), 0) + alias: l2_fabric_wr_ + tips: + Fabric_l2 Atomic: + value: ROUND(AVG((TCC_EA_ATOMIC_sum / $denom)), 0) + alias: l2_fabric_atom_ + tips: + HBM Rd: + value: ROUND(AVG((TCC_EA_RDREQ_DRAM_sum / $denom)), 0) + alias: hbm_rd_ + tips: + HBM Wr: + value: ROUND(AVG((TCC_EA_WRREQ_DRAM_sum / $denom)), 0) + alias: hbm_wr_ + tips: + LDS Util: + value: ROUND(AVG(((100 * SQ_LDS_IDX_ACTIVE) / (GRBM_GUI_ACTIVE * $numCU))), + 0) + alias: lds_util_ + tips: + VL1 Coalesce: + value: ROUND(AVG(((((TA_TOTAL_WAVEFRONTS_sum * 64) * 100) / (TCP_TOTAL_ACCESSES_sum + * 4)) if (TCP_TOTAL_ACCESSES_sum != 0) else 0)), 0) + alias: vl1_coales_ + tips: + VL1 Stall: + value: ROUND(AVG((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)), 0) + alias: vl1_stall_ + tips: + LDS Lat: + value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) + if (SQ_INSTS_LDS != 0) else None)), 0) + alias: lds_lat_ + coll_level: SQ_INST_LEVEL_LDS + tips: + vL1D Lat: + value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQC_DCACHE_REQ) + if (SQC_DCACHE_REQ != 0) else None)), 0) + alias: sl1_lat_ + tips: + IL1 Lat: + value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQC_ICACHE_REQ) + if (SQC_ICACHE_REQ != 0) else None)), 0) + alias: il1_lat_ + tips: + Wave Occupancy: + value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE) / $numActiveCUs)), 0) + alias: wave_occ_ + coll_level: SQ_LEVEL_WAVES + tips: diff --git a/src/omniperf_soc/configs/gfx908/2000_kernels.yaml b/src/omniperf_soc/configs/gfx908/2000_kernels.yaml new file mode 100644 index 0000000000..ed566f75a2 --- /dev/null +++ b/src/omniperf_soc/configs/gfx908/2000_kernels.yaml @@ -0,0 +1,8 @@ +--- +Panel Config: + id: 2000 + title: Kernels + data source: + - raw_csv_table: + id: 2001 + source: pmc_dispatch_info.csv diff --git a/src/omniperf_soc/configs/gfx90a/0000_top_stat.yaml b/src/omniperf_soc/configs/gfx90a/0000_top_stat.yaml new file mode 100644 index 0000000000..077004080f --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/0000_top_stat.yaml @@ -0,0 +1,8 @@ +--- +Panel Config: + id: 000 + title: Top Stat + data source: + - raw_csv_table: + id: 001 + source: pmc_kernel_top.csv diff --git a/src/omniperf_soc/configs/gfx90a/0100_system_info.yaml b/src/omniperf_soc/configs/gfx90a/0100_system_info.yaml new file mode 100644 index 0000000000..b7ec29eaf9 --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/0100_system_info.yaml @@ -0,0 +1,9 @@ +--- +Panel Config: + id: 100 + title: System Info + data source: + - raw_csv_table: + id: 101 + source: sysinfo.csv + columnwise: True diff --git a/src/omniperf_soc/configs/gfx90a/0200_system-speed-of-light.yaml b/src/omniperf_soc/configs/gfx90a/0200_system-speed-of-light.yaml new file mode 100644 index 0000000000..c197c0fc58 --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/0200_system-speed-of-light.yaml @@ -0,0 +1,247 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + SALU: &SALU_anchor Scalar Arithmetic Logic Unit + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 200 + title: System Speed-of-Light + data source: + - metric_table: + id: 201 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + peak: Peak + pop: PoP + tips: Tips + metric: + VALU FLOPs: + value: AVG(((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + + (2 * SQ_INSTS_VALU_FMA_F16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + + SQ_INSTS_VALU_TRANS_F32) + (2 * SQ_INSTS_VALU_FMA_F32)))) + (64 * (((SQ_INSTS_VALU_ADD_F64 + + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (2 * SQ_INSTS_VALU_FMA_F64)))) + / (EndNs - BeginNs))) + unit: GFLOP + peak: (((($sclk * $numCU) * 64) * 2) / 1000) + pop: ((100 * AVG(((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + + SQ_INSTS_VALU_TRANS_F16) + (2 * SQ_INSTS_VALU_FMA_F16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (2 * SQ_INSTS_VALU_FMA_F32)))) + + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (2 * SQ_INSTS_VALU_FMA_F64)))) / (EndNs - BeginNs)))) / (((($sclk + * $numCU) * 64) * 2) / 1000)) + tips: + VALU IOPs: + value: AVG(((64 * (SQ_INSTS_VALU_INT32 + SQ_INSTS_VALU_INT64)) / (EndNs - BeginNs))) + unit: GIOP + peak: (((($sclk * $numCU) * 64) * 2) / 1000) + pop: ((100 * AVG(((64 * (SQ_INSTS_VALU_INT32 + SQ_INSTS_VALU_INT64)) / (EndNs + - BeginNs)))) / (((($sclk * $numCU) * 64) * 2) / 1000)) + tips: + MFMA FLOPs (BF16): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) / (EndNs - BeginNs))) + unit: GFLOP + peak: ((($sclk * $numCU) * 1024) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) / (EndNs - BeginNs)))) + / ((($sclk * $numCU) * 1024) / 1000)) + tips: + MFMA FLOPs (F16): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (EndNs - BeginNs))) + unit: GFLOP + peak: ((($sclk * $numCU) * 1024) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (EndNs - BeginNs)))) + / ((($sclk * $numCU) * 1024) / 1000)) + tips: + MFMA FLOPs (F32): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) / (EndNs - BeginNs))) + unit: GFLOP + peak: ((($sclk * $numCU) * 256) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) / (EndNs - BeginNs)))) + / ((($sclk * $numCU) * 256) / 1000)) + tips: + MFMA FLOPs (F64): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (EndNs - BeginNs))) + unit: GFLOP + peak: ((($sclk * $numCU) * 256) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (EndNs - BeginNs)))) + / ((($sclk * $numCU) * 256) / 1000)) + tips: + MFMA IOPs (Int8): + value: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (EndNs - BeginNs))) + unit: GIOP + peak: ((($sclk * $numCU) * 1024) / 1000) + pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (EndNs - BeginNs)))) + / ((($sclk * $numCU) * 1024) / 1000)) + tips: + Active CUs: + value: $numActiveCUs + unit: CUs + peak: $numCU + pop: ((100 * $numActiveCUs) / $numCU) + tips: + SALU Util: + value: AVG(((100 * SQ_ACTIVE_INST_SCA) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + peak: 100 + pop: AVG(((100 * SQ_ACTIVE_INST_SCA) / (GRBM_GUI_ACTIVE * $numCU))) + tips: + VALU Util: + value: AVG(((100 * SQ_ACTIVE_INST_VALU) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + peak: 100 + pop: AVG(((100 * SQ_ACTIVE_INST_VALU) / (GRBM_GUI_ACTIVE * $numCU))) + tips: + MFMA Util: + value: AVG(((100 * SQ_VALU_MFMA_BUSY_CYCLES) / ((GRBM_GUI_ACTIVE * $numCU) + * 4))) + unit: pct + peak: 100 + pop: AVG(((100 * SQ_VALU_MFMA_BUSY_CYCLES) / ((GRBM_GUI_ACTIVE * $numCU) + * 4))) + tips: + VALU Active Threads/Wave: + value: AVG(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + unit: Threads + peak: 64 + pop: (AVG(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) * 1.5625) + tips: + IPC - Issue: + value: AVG(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM) + + SQ_INSTS_GDS) + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED) + / SQ_ACTIVE_INST_ANY)) + unit: Instr/cycle + peak: 5 + pop: ((100 * AVG(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM) + + SQ_INSTS_GDS) + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED) + / SQ_ACTIVE_INST_ANY))) / 5) + tips: + LDS BW: + value: AVG(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / (EndNs - BeginNs))) + unit: GB/sec + peak: (($sclk * $numCU) * 0.128) + pop: AVG((((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / (EndNs - BeginNs)) / (($sclk * $numCU) * 0.00128))) + tips: + LDS Bank Conflict: + value: AVG(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + unit: Conflicts/access + peak: 32 + pop: ((100 * AVG(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None))) / 32) + tips: + Instr Cache Hit Rate: + value: AVG(((100 * SQC_ICACHE_HITS) / (SQC_ICACHE_HITS + SQC_ICACHE_MISSES))) + unit: pct + peak: 100 + pop: AVG(((100 * SQC_ICACHE_HITS) / (SQC_ICACHE_HITS + SQC_ICACHE_MISSES))) + tips: + Instr Cache BW: + value: AVG(((SQC_ICACHE_REQ / (EndNs - BeginNs)) * 64)) + unit: GB/s + peak: ((($sclk / 1000) * 64) * $numSQC) + pop: ((100 * AVG(((SQC_ICACHE_REQ / (EndNs - BeginNs)) * 64))) / ((($sclk + / 1000) * 64) * $numSQC)) + tips: + Scalar L1D Cache Hit Rate: + value: AVG((((100 * SQC_DCACHE_HITS) / (SQC_DCACHE_HITS + SQC_DCACHE_MISSES)) + if ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) != 0) else None)) + unit: pct + peak: 100 + pop: AVG((((100 * SQC_DCACHE_HITS) / (SQC_DCACHE_HITS + SQC_DCACHE_MISSES)) + if ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) != 0) else None)) + tips: + Scalar L1D Cache BW: + value: AVG(((SQC_DCACHE_REQ / (EndNs - BeginNs)) * 64)) + unit: GB/s + peak: ((($sclk / 1000) * 64) * $numSQC) + pop: ((100 * AVG(((SQC_DCACHE_REQ / (EndNs - BeginNs)) * 64))) / ((($sclk + / 1000) * 64) * $numSQC)) + tips: + Vector L1D Cache Hit Rate: + value: AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + unit: pct + peak: 100 + pop: AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / + TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + tips: + Vector L1D Cache BW: + value: AVG(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs))) + unit: GB/s + peak: ((($sclk / 1000) * 64) * $numCU) + pop: ((100 * AVG(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs)))) + / ((($sclk / 1000) * 64) * $numCU)) + tips: + L2 Cache Hit Rate: + value: AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + unit: pct + peak: 100 + pop: AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + tips: + L2-Fabric Read BW: + value: AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / (EndNs - BeginNs))) + unit: GB/s + peak: $hbmBW + pop: ((100 * AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / (EndNs - BeginNs)))) / $hbmBW) + tips: + L2-Fabric Write BW: + value: AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / (EndNs - BeginNs))) + unit: GB/s + peak: $hbmBW + pop: ((100 * AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / (EndNs - BeginNs)))) / $hbmBW) + tips: + L2-Fabric Read Latency: + value: AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum + != 0) else None)) + unit: Cycles + peak: '' + pop: '' + tips: + L2-Fabric Write Latency: + value: AVG(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum + != 0) else None)) + unit: Cycles + peak: '' + pop: '' + tips: + Wave Occupancy: + value: AVG((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE)) + unit: Wavefronts + peak: ($maxWavesPerCU * $numCU) + pop: (100 * AVG(((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE) / ($maxWavesPerCU + * $numCU)))) + coll_level: SQ_LEVEL_WAVES + tips: + Instr Fetch BW: + value: AVG(((SQ_IFETCH / (EndNs - BeginNs)) * 32)) + unit: GB/s + peak: ((($sclk / 1000) * 32) * $numSQC) + pop: ((100 * AVG(((SQ_IFETCH / (EndNs - BeginNs)) * 32))) / ($numSQC + * (($sclk / 1000) * 32))) + coll_level: SQ_IFETCH_LEVEL + tips: + Instr Fetch Latency: + value: AVG((SQ_ACCUM_PREV_HIRES / SQ_IFETCH)) + unit: Cycles + peak: '' + pop: '' + coll_level: SQ_IFETCH_LEVEL + tips: diff --git a/src/omniperf_soc/configs/gfx90a/0500_command-processor.yaml b/src/omniperf_soc/configs/gfx90a/0500_command-processor.yaml new file mode 100644 index 0000000000..d954f61625 --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/0500_command-processor.yaml @@ -0,0 +1,180 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 500 + title: Command Processor (CPC/CPF) + data source: + - metric_table: + id: 501 + title: Command Processor Fetcher + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + GPU Busy Cycles: + avg: AVG(GRBM_GUI_ACTIVE) + min: MIN(GRBM_GUI_ACTIVE) + max: MAX(GRBM_GUI_ACTIVE) + unit: Cycles/Kernel + tips: + CPF Busy: + avg: AVG(CPF_CPF_STAT_BUSY) + min: MIN(CPF_CPF_STAT_BUSY) + max: MAX(CPF_CPF_STAT_BUSY) + unit: Cycles/Kernel + tips: + CPF Util: + avg: AVG((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) + if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) + min: MIN((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) + if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) + max: MAX((((100 * CPF_CPF_STAT_BUSY) / (CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE)) + if ((CPF_CPF_STAT_BUSY + CPF_CPF_STAT_IDLE) != 0) else None)) + unit: pct + tips: + CPF Stall: + avg: AVG((((100 * CPF_CPF_STAT_STALL) / CPF_CPF_STAT_BUSY) if (CPF_CPF_STAT_BUSY + != 0) else None)) + min: MIN((((100 * CPF_CPF_STAT_STALL) / CPF_CPF_STAT_BUSY) if (CPF_CPF_STAT_BUSY + != 0) else None)) + max: MAX((((100 * CPF_CPF_STAT_STALL) / CPF_CPF_STAT_BUSY) if (CPF_CPF_STAT_BUSY + != 0) else None)) + unit: Cycles/Kernel + tips: + L2Cache Intf Busy: + avg: AVG(CPF_CPF_TCIU_BUSY) + min: MIN(CPF_CPF_TCIU_BUSY) + max: MAX(CPF_CPF_TCIU_BUSY) + unit: Cycles/Kernel + tips: + L2Cache Intf Util: + avg: AVG((((100 * CPF_CPF_TCIU_BUSY) / (CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE)) + if ((CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE) != 0) else None)) + min: MIN((((100 * CPF_CPF_TCIU_BUSY) / (CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE)) + if ((CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE) != 0) else None)) + max: MAX((((100 * CPF_CPF_TCIU_BUSY) / (CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE)) + if ((CPF_CPF_TCIU_BUSY + CPF_CPF_TCIU_IDLE) != 0) else None)) + unit: pct + tips: + L2Cache Intf Stall: + avg: AVG((((100 * CPF_CPF_TCIU_STALL) / CPF_CPF_TCIU_BUSY) if (CPF_CPF_TCIU_BUSY + != 0) else None)) + min: MIN((((100 * CPF_CPF_TCIU_STALL) / CPF_CPF_TCIU_BUSY) if (CPF_CPF_TCIU_BUSY + != 0) else None)) + max: MAX((((100 * CPF_CPF_TCIU_STALL) / CPF_CPF_TCIU_BUSY) if (CPF_CPF_TCIU_BUSY + != 0) else None)) + unit: pct + tips: + UTCL1 Stall: + avg: AVG(CPF_CMP_UTCL1_STALL_ON_TRANSLATION) + min: MIN(CPF_CMP_UTCL1_STALL_ON_TRANSLATION) + max: MAX(CPF_CMP_UTCL1_STALL_ON_TRANSLATION) + unit: Cycles/Kernel + tips: + + - metric_table: + id: 502 + title: Command Processor Compute + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + GPU Busy Cycles: + avg: AVG(GRBM_GUI_ACTIVE) + min: MIN(GRBM_GUI_ACTIVE) + max: MAX(GRBM_GUI_ACTIVE) + unit: Cycles + tips: + CPC Busy Cycles: + avg: AVG(CPC_CPC_STAT_BUSY) + min: MIN(CPC_CPC_STAT_BUSY) + max: MAX(CPC_CPC_STAT_BUSY) + unit: Cycles + tips: + CPC Util: + avg: AVG((((100 * CPC_CPC_STAT_BUSY) / (CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE)) + if ((CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE) != 0) else None)) + min: MIN((((100 * CPC_CPC_STAT_BUSY) / (CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE)) + if ((CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE) != 0) else None)) + max: MAX((((100 * CPC_CPC_STAT_BUSY) / (CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE)) + if ((CPC_CPC_STAT_BUSY + CPC_CPC_STAT_IDLE) != 0) else None)) + unit: pct + tips: + CPC Stall Cycles: + avg: AVG(CPC_CPC_STAT_STALL) + min: MIN(CPC_CPC_STAT_STALL) + max: MAX(CPC_CPC_STAT_STALL) + unit: Cycles + tips: + CPC Stall Rate: + avg: AVG((((100 * CPC_CPC_STAT_STALL) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + min: MIN((((100 * CPC_CPC_STAT_STALL) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + max: MAX((((100 * CPC_CPC_STAT_STALL) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + unit: pct + tips: + CPC Packet Decoding: + avg: AVG(CPC_ME1_BUSY_FOR_PACKET_DECODE) + min: MIN(CPC_ME1_BUSY_FOR_PACKET_DECODE) + max: MAX(CPC_ME1_BUSY_FOR_PACKET_DECODE) + unit: Cycles + tips: + SPI Intf Busy Cycles: + avg: AVG(CPC_ME1_DC0_SPI_BUSY) + min: MIN(CPC_ME1_DC0_SPI_BUSY) + max: MAX(CPC_ME1_DC0_SPI_BUSY) + unit: Cycles + tips: + SPI Intf Util: + avg: AVG((((100 * CPC_ME1_DC0_SPI_BUSY) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + min: MIN((((100 * CPC_ME1_DC0_SPI_BUSY) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + max: MAX((((100 * CPC_ME1_DC0_SPI_BUSY) / CPC_CPC_STAT_BUSY) if (CPC_CPC_STAT_BUSY + != 0) else None)) + unit: pct + tips: + L2Cache Intf Util: + avg: AVG((((100 * CPC_CPC_TCIU_BUSY) / (CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE)) + if ((CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE) != 0) else None)) + min: MIN((((100 * CPC_CPC_TCIU_BUSY) / (CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE)) + if ((CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE) != 0) else None)) + max: MAX((((100 * CPC_CPC_TCIU_BUSY) / (CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE)) + if ((CPC_CPC_TCIU_BUSY + CPC_CPC_TCIU_IDLE) != 0) else None)) + unit: pct + tips: + UTCL1 Stall Cycles: + avg: AVG(CPC_UTCL1_STALL_ON_TRANSLATION) + min: MIN(CPC_UTCL1_STALL_ON_TRANSLATION) + max: MAX(CPC_UTCL1_STALL_ON_TRANSLATION) + unit: Cycles + tips: + UTCL2 Intf Busy Cycles: + avg: AVG(CPC_CPC_UTCL2IU_BUSY) + min: MIN(CPC_CPC_UTCL2IU_BUSY) + max: MAX(CPC_CPC_UTCL2IU_BUSY) + unit: Cycles + tips: + UTCL2 Intf Util: + avg: AVG((((100 * CPC_CPC_UTCL2IU_BUSY) / (CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE)) + if ((CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE) != 0) else None)) + min: MIN((((100 * CPC_CPC_UTCL2IU_BUSY) / (CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE)) + if ((CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE) != 0) else None)) + max: MAX((((100 * CPC_CPC_UTCL2IU_BUSY) / (CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE)) + if ((CPC_CPC_UTCL2IU_BUSY + CPC_CPC_UTCL2IU_IDLE) != 0) else None)) + unit: pct + tips: diff --git a/src/omniperf_soc/configs/gfx90a/0600_shader-processor-input.yaml b/src/omniperf_soc/configs/gfx90a/0600_shader-processor-input.yaml new file mode 100644 index 0000000000..bab48700ac --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/0600_shader-processor-input.yaml @@ -0,0 +1,174 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 600 + title: Shader Processor Input (SPI) + data source: + - metric_table: + id: 601 + title: SPI Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + GPU Busy: + avg: AVG(GRBM_GUI_ACTIVE) + min: MIN(GRBM_GUI_ACTIVE) + max: MAX(GRBM_GUI_ACTIVE) + unit: Cycles + tips: + CS Busy: + avg: AVG(SPI_CSN_BUSY) + min: MIN(SPI_CSN_BUSY) + max: MAX(SPI_CSN_BUSY) + unit: Cycles + tips: + SPI Busy: + avg: AVG(GRBM_SPI_BUSY) + min: MIN(GRBM_SPI_BUSY) + max: MAX(GRBM_SPI_BUSY) + unit: Cycles + tips: + SQ Busy: + avg: AVG(SQ_BUSY_CYCLES) + min: MIN(SQ_BUSY_CYCLES) + max: MAX(SQ_BUSY_CYCLES) + unit: Cycles + tips: + Dispatched Workgroups: + avg: AVG(SPI_CSN_NUM_THREADGROUPS) + min: MIN(SPI_CSN_NUM_THREADGROUPS) + max: MAX(SPI_CSN_NUM_THREADGROUPS) + unit: Workgroups + tips: + Dispatched Wavefronts: + avg: AVG(SPI_CSN_WAVE) + min: MIN(SPI_CSN_WAVE) + max: MAX(SPI_CSN_WAVE) + unit: Wavefronts + tips: + Wave Alloc Failed: + avg: AVG(SPI_RA_REQ_NO_ALLOC) + min: MIN(SPI_RA_REQ_NO_ALLOC) + max: MAX(SPI_RA_REQ_NO_ALLOC) + unit: Cycles + tips: + Wave Alloc Failed - CS: + avg: AVG(SPI_RA_REQ_NO_ALLOC_CSN) + min: MIN(SPI_RA_REQ_NO_ALLOC_CSN) + max: MAX(SPI_RA_REQ_NO_ALLOC_CSN) + unit: Cycles + tips: + + - metric_table: + id: 602 + title: SPI Resource Allocation + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Wave request Failed (CS): + avg: AVG(SPI_RA_REQ_NO_ALLOC_CSN) + min: MIN(SPI_RA_REQ_NO_ALLOC_CSN) + max: MAX(SPI_RA_REQ_NO_ALLOC_CSN) + unit: Cycles + tips: + CS Stall: + avg: AVG(SPI_RA_RES_STALL_CSN) + min: MIN(SPI_RA_RES_STALL_CSN) + max: MAX(SPI_RA_RES_STALL_CSN) + unit: Cycles + tips: + CS Stall Rate: + avg: AVG((((100 * SPI_RA_RES_STALL_CSN) / GRBM_SPI_BUSY) if (GRBM_SPI_BUSY != + 0) else None)) + min: MIN((((100 * SPI_RA_RES_STALL_CSN) / GRBM_SPI_BUSY) if (GRBM_SPI_BUSY != + 0) else None)) + max: MAX((((100 * SPI_RA_RES_STALL_CSN) / GRBM_SPI_BUSY) if (GRBM_SPI_BUSY != + 0) else None)) + unit: pct + tips: + Scratch Stall: + avg: AVG(SPI_RA_TMP_STALL_CSN) + min: MIN(SPI_RA_TMP_STALL_CSN) + max: MAX(SPI_RA_TMP_STALL_CSN) + unit: Cycles + tips: + Insufficient SIMD Waveslots: + avg: AVG(SPI_RA_WAVE_SIMD_FULL_CSN) + min: MIN(SPI_RA_WAVE_SIMD_FULL_CSN) + max: MAX(SPI_RA_WAVE_SIMD_FULL_CSN) + unit: SIMD + tips: + Insufficient SIMD VGPRs: + avg: AVG(SPI_RA_VGPR_SIMD_FULL_CSN) + min: MIN(SPI_RA_VGPR_SIMD_FULL_CSN) + max: MAX(SPI_RA_VGPR_SIMD_FULL_CSN) + unit: SIMD + tips: + Insufficient SIMD SGPRs: + avg: AVG(SPI_RA_SGPR_SIMD_FULL_CSN) + min: MIN(SPI_RA_SGPR_SIMD_FULL_CSN) + max: MAX(SPI_RA_SGPR_SIMD_FULL_CSN) + unit: SIMD + tips: + Insufficient CU LDS: + avg: AVG(SPI_RA_LDS_CU_FULL_CSN) + min: MIN(SPI_RA_LDS_CU_FULL_CSN) + max: MAX(SPI_RA_LDS_CU_FULL_CSN) + unit: CU + tips: + Insufficient CU Barries: + avg: AVG(SPI_RA_BAR_CU_FULL_CSN) + min: MIN(SPI_RA_BAR_CU_FULL_CSN) + max: MAX(SPI_RA_BAR_CU_FULL_CSN) + unit: CU + tips: + Insufficient Bulky Resource: + avg: AVG(SPI_RA_BULKY_CU_FULL_CSN) + min: MIN(SPI_RA_BULKY_CU_FULL_CSN) + max: MAX(SPI_RA_BULKY_CU_FULL_CSN) + unit: CU + tips: + Reach CU Threadgroups Limit: + avg: AVG(SPI_RA_TGLIM_CU_FULL_CSN) + min: MIN(SPI_RA_TGLIM_CU_FULL_CSN) + max: MAX(SPI_RA_TGLIM_CU_FULL_CSN) + unit: Cycles + tips: + Reach CU Wave Limit: + avg: AVG(SPI_RA_WVLIM_STALL_CSN) + min: MIN(SPI_RA_WVLIM_STALL_CSN) + max: MAX(SPI_RA_WVLIM_STALL_CSN) + unit: Cycles + tips: + VGPR Writes: + avg: AVG((((4 * SPI_VWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + min: MIN((((4 * SPI_VWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + max: MAX((((4 * SPI_VWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + unit: Cycles/wave + tips: + SGPR Writes: + avg: AVG((((1 * SPI_SWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + min: MIN((((1 * SPI_SWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + max: MAX((((1 * SPI_SWC_CSC_WR) / SPI_CSN_WAVE) if (SPI_CSN_WAVE != 0) else + None)) + unit: Cycles/wave + tips: diff --git a/src/omniperf_soc/configs/gfx90a/0700_wavefront-launch.yaml b/src/omniperf_soc/configs/gfx90a/0700_wavefront-launch.yaml new file mode 100644 index 0000000000..13ba5b8e16 --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/0700_wavefront-launch.yaml @@ -0,0 +1,142 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 700 + title: Wavefront + data source: + - metric_table: + id: 701 + title: Wavefront Launch Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Grid Size: + avg: AVG(grd) + min: MIN(grd) + max: MAX(grd) + unit: Work Items + tips: + Workgroup Size: + avg: AVG(wgr) + min: MIN(wgr) + max: MAX(wgr) + unit: Work Items + tips: + Total Wavefronts: + avg: AVG(SPI_CSN_WAVE) + min: MIN(SPI_CSN_WAVE) + max: MAX(SPI_CSN_WAVE) + unit: Wavefronts + tips: + Saved Wavefronts: + avg: AVG(SQ_WAVES_SAVED) + min: MIN(SQ_WAVES_SAVED) + max: MAX(SQ_WAVES_SAVED) + unit: Wavefronts + tips: + Restored Wavefronts: + avg: AVG(SQ_WAVES_RESTORED) + min: MIN(SQ_WAVES_RESTORED) + max: MAX(SQ_WAVES_RESTORED) + unit: Wavefronts + tips: + VGPRs: + avg: AVG(arch_vgpr) + min: MIN(arch_vgpr) + max: MAX(arch_vgpr) + unit: Registers + tips: + AGPRs: + avg: AVG(accum_vgpr) + min: MIN(accum_vgpr) + max: MAX(accum_vgpr) + unit: Registers + tips: + SGPRs: + avg: AVG(sgpr) + min: MIN(sgpr) + max: MAX(sgpr) + unit: Registers + tips: + LDS Allocation: + avg: AVG(lds) + min: MIN(lds) + max: MAX(lds) + unit: Bytes + tips: + Scratch Allocation: + avg: AVG(scr) + min: MIN(scr) + max: MAX(scr) + unit: Bytes + tips: + + - metric_table: + id: 702 + title: Wavefront Runtime Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Kernel Time (Nanosec): + avg: AVG((EndNs - BeginNs)) + min: MIN((EndNs - BeginNs)) + max: MAX((EndNs - BeginNs)) + unit: ns + tips: + Kernel Time (Cycles): + avg: AVG(GRBM_GUI_ACTIVE) + min: MIN(GRBM_GUI_ACTIVE) + max: MAX(GRBM_GUI_ACTIVE) + unit: Cycle + tips: + Instr/wavefront: + avg: AVG((SQ_INSTS / SQ_WAVES)) + min: MIN((SQ_INSTS / SQ_WAVES)) + max: MAX((SQ_INSTS / SQ_WAVES)) + unit: Instr/wavefront + tips: + Wave Cycles: + avg: AVG(((4 * SQ_WAVE_CYCLES) / $denom)) + min: MIN(((4 * SQ_WAVE_CYCLES) / $denom)) + max: MAX(((4 * SQ_WAVE_CYCLES) / $denom)) + unit: (Cycles + $normUnit) + tips: + Dependency Wait Cycles: + avg: AVG(((4 * SQ_WAIT_ANY) / $denom)) + min: MIN(((4 * SQ_WAIT_ANY) / $denom)) + max: MAX(((4 * SQ_WAIT_ANY) / $denom)) + unit: (Cycles + $normUnit) + tips: + Issue Wait Cycles: + avg: AVG(((4 * SQ_WAIT_INST_ANY) / $denom)) + min: MIN(((4 * SQ_WAIT_INST_ANY) / $denom)) + max: MAX(((4 * SQ_WAIT_INST_ANY) / $denom)) + unit: (Cycles + $normUnit) + tips: + Active Cycles: + avg: AVG(((4 * SQ_ACTIVE_INST_ANY) / $denom)) + min: MIN(((4 * SQ_ACTIVE_INST_ANY) / $denom)) + max: MAX(((4 * SQ_ACTIVE_INST_ANY) / $denom)) + unit: (Cycles + $normUnit) + tips: + Wavefront Occupancy: + avg: AVG((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE)) + min: MIN((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE)) + max: MAX((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE)) + unit: Wavefronts + coll_level: SQ_LEVEL_WAVES + tips: diff --git a/src/omniperf_soc/configs/gfx90a/1000_compute-unit-instruction-mix.yaml b/src/omniperf_soc/configs/gfx90a/1000_compute-unit-instruction-mix.yaml new file mode 100644 index 0000000000..8ffd87d2c8 --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/1000_compute-unit-instruction-mix.yaml @@ -0,0 +1,234 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1000 + title: Compute Units - Instruction Mix + data source: + - metric_table: + id: 1001 + title: Instruction Mix + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + style: + type: simple_bar + label_txt: (# of instr + $normUnit) + metric: + VALU - Vector: + avg: AVG(((SQ_INSTS_VALU - SQ_INSTS_MFMA) / $denom)) + min: MIN(((SQ_INSTS_VALU - SQ_INSTS_MFMA) / $denom)) + max: MAX(((SQ_INSTS_VALU - SQ_INSTS_MFMA) / $denom)) + unit: (instr + $normUnit) + tips: + VMEM: + avg: AVG(((SQ_INSTS_VMEM - SQ_INSTS_FLAT_LDS_ONLY) / $denom)) + min: MIN(((SQ_INSTS_VMEM - SQ_INSTS_FLAT_LDS_ONLY) / $denom)) + max: MAX(((SQ_INSTS_VMEM - SQ_INSTS_FLAT_LDS_ONLY) / $denom)) + unit: (instr + $normUnit) + tips: + LDS: + avg: AVG((SQ_INSTS_LDS / $denom)) + min: MIN((SQ_INSTS_LDS / $denom)) + max: MAX((SQ_INSTS_LDS / $denom)) + unit: (instr + $normUnit) + tips: + VALU - MFMA: + avg: AVG((SQ_INSTS_MFMA / $denom)) + min: MIN((SQ_INSTS_MFMA / $denom)) + max: MAX((SQ_INSTS_MFMA / $denom)) + unit: (instr + $normUnit) + tips: + SALU: + avg: AVG((SQ_INSTS_SALU / $denom)) + min: MIN((SQ_INSTS_SALU / $denom)) + max: MAX((SQ_INSTS_SALU / $denom)) + unit: (instr + $normUnit) + tips: + SMEM: + avg: AVG((SQ_INSTS_SMEM / $denom)) + min: MIN((SQ_INSTS_SMEM / $denom)) + max: MAX((SQ_INSTS_SMEM / $denom)) + unit: (instr + $normUnit) + tips: + Branch: + avg: AVG((SQ_INSTS_BRANCH / $denom)) + min: MIN((SQ_INSTS_BRANCH / $denom)) + max: MAX((SQ_INSTS_BRANCH / $denom)) + unit: (instr + $normUnit) + tips: + GDS: + avg: AVG((SQ_INSTS_GDS / $denom)) + min: MIN((SQ_INSTS_GDS / $denom)) + max: MAX((SQ_INSTS_GDS / $denom)) + unit: (instr + $normUnit) + tips: + + - metric_table: + id: 1002 + title: VALU Arithmetic Instr Mix + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + style: + type: simple_bar + label_txt: (# of instr + $normUnit) + metric: + INT32: + avg: AVG((SQ_INSTS_VALU_INT32 / $denom)) + min: MIN((SQ_INSTS_VALU_INT32 / $denom)) + max: MAX((SQ_INSTS_VALU_INT32 / $denom)) + unit: (instr + $normUnit) + tips: + INT64: + avg: AVG((SQ_INSTS_VALU_INT64 / $denom)) + min: MIN((SQ_INSTS_VALU_INT64 / $denom)) + max: MAX((SQ_INSTS_VALU_INT64 / $denom)) + unit: (instr + $normUnit) + tips: + F16-ADD: + avg: AVG((SQ_INSTS_VALU_ADD_F16 / $denom)) + min: MIN((SQ_INSTS_VALU_ADD_F16 / $denom)) + max: MAX((SQ_INSTS_VALU_ADD_F16 / $denom)) + unit: (instr + $normUnit) + tips: + F16-MUL: + avg: AVG((SQ_INSTS_VALU_MUL_F16 / $denom)) + min: MIN((SQ_INSTS_VALU_MUL_F16 / $denom)) + max: MAX((SQ_INSTS_VALU_MUL_F16 / $denom)) + unit: (instr + $normUnit) + tips: + F16-FMA: + avg: AVG((SQ_INSTS_VALU_FMA_F16 / $denom)) + min: MIN((SQ_INSTS_VALU_FMA_F16 / $denom)) + max: MAX((SQ_INSTS_VALU_FMA_F16 / $denom)) + unit: (instr + $normUnit) + tips: + F16-Trans: + avg: AVG((SQ_INSTS_VALU_TRANS_F16 / $denom)) + min: MIN((SQ_INSTS_VALU_TRANS_F16 / $denom)) + max: MAX((SQ_INSTS_VALU_TRANS_F16 / $denom)) + unit: (instr + $normUnit) + tips: + F32-ADD: + avg: AVG((SQ_INSTS_VALU_ADD_F32 / $denom)) + min: MIN((SQ_INSTS_VALU_ADD_F32 / $denom)) + max: MAX((SQ_INSTS_VALU_ADD_F32 / $denom)) + unit: (instr + $normUnit) + tips: + F32-MUL: + avg: AVG((SQ_INSTS_VALU_MUL_F32 / $denom)) + min: MIN((SQ_INSTS_VALU_MUL_F32 / $denom)) + max: MAX((SQ_INSTS_VALU_MUL_F32 / $denom)) + unit: (instr + $normUnit) + tips: + F32-FMA: + avg: AVG((SQ_INSTS_VALU_FMA_F32 / $denom)) + min: MIN((SQ_INSTS_VALU_FMA_F32 / $denom)) + max: MAX((SQ_INSTS_VALU_FMA_F32 / $denom)) + unit: (instr + $normUnit) + tips: + F32-Trans: + avg: AVG((SQ_INSTS_VALU_TRANS_F32 / $denom)) + min: MIN((SQ_INSTS_VALU_TRANS_F32 / $denom)) + max: MAX((SQ_INSTS_VALU_TRANS_F32 / $denom)) + unit: (instr + $normUnit) + tips: + F64-ADD: + avg: AVG((SQ_INSTS_VALU_ADD_F64 / $denom)) + min: MIN((SQ_INSTS_VALU_ADD_F64 / $denom)) + max: MAX((SQ_INSTS_VALU_ADD_F64 / $denom)) + unit: (instr + $normUnit) + tips: + F64-MUL: + avg: AVG((SQ_INSTS_VALU_MUL_F64 / $denom)) + min: MIN((SQ_INSTS_VALU_MUL_F64 / $denom)) + max: MAX((SQ_INSTS_VALU_MUL_F64 / $denom)) + unit: (instr + $normUnit) + tips: + F64-FMA: + avg: AVG((SQ_INSTS_VALU_FMA_F64 / $denom)) + min: MIN((SQ_INSTS_VALU_FMA_F64 / $denom)) + max: MAX((SQ_INSTS_VALU_FMA_F64 / $denom)) + unit: (instr + $normUnit) + tips: + F64-Trans: + avg: AVG((SQ_INSTS_VALU_TRANS_F64 / $denom)) + min: MIN((SQ_INSTS_VALU_TRANS_F64 / $denom)) + max: MAX((SQ_INSTS_VALU_TRANS_F64 / $denom)) + unit: (instr + $normUnit) + tips: + Conversion: + avg: AVG((SQ_INSTS_VALU_CVT / $denom)) + min: MIN((SQ_INSTS_VALU_CVT / $denom)) + max: MAX((SQ_INSTS_VALU_CVT / $denom)) + unit: (instr + $normUnit) + tips: + + - metric_table: + id: 1003 + title: VMEM Instr Mix + header: + type: type + count: Count + tips: Tips + metric: + Buffer Instr: + count: AVG((TA_BUFFER_WAVEFRONTS_sum / $denom)) + tips: + Buffer Read: + count: AVG((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) + tips: + Buffer Write: + count: AVG((TA_BUFFER_WRITE_WAVEFRONTS_sum / $denom)) + tips: + Buffer Atomic: + count: AVG((TA_BUFFER_ATOMIC_WAVEFRONTS_sum / $denom)) + tips: + Flat Instr: + count: AVG((TA_FLAT_WAVEFRONTS_sum / $denom)) + tips: + Flat Read: + count: AVG((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) + tips: + Flat Write: + count: AVG((TA_FLAT_WRITE_WAVEFRONTS_sum / $denom)) + tips: + Flat Atomic: + count: AVG((TA_FLAT_ATOMIC_WAVEFRONTS_sum / $denom)) + tips: + + - metric_table: + id: 1004 + title: MFMA Arithmetic Instr Mix + header: + type: type + count: Count + tips: Tips + metric: + MFMA-I8: + count: AVG((SQ_INSTS_VALU_MFMA_I8 / $denom)) + tips: + MFMA-F16: + count: AVG((SQ_INSTS_VALU_MFMA_F16 / $denom)) + tips: + MFMA-BF16: + count: AVG((SQ_INSTS_VALU_MFMA_BF16 / $denom)) + tips: + MFMA-F32: + count: AVG((SQ_INSTS_VALU_MFMA_F32 / $denom)) + tips: + MFMA-F64: + count: AVG((SQ_INSTS_VALU_MFMA_F64 / $denom)) + tips: diff --git a/src/omniperf_soc/configs/gfx90a/1100_compute-unit-compute-pipeline.yaml b/src/omniperf_soc/configs/gfx90a/1100_compute-unit-compute-pipeline.yaml new file mode 100644 index 0000000000..5767fe771a --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/1100_compute-unit-compute-pipeline.yaml @@ -0,0 +1,202 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1100 + title: Compute Units - Compute Pipeline + data source: + - metric_table: + id: 1101 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + range_color: [1, 100] + label_txt: (%) + xrange: [0, 110] + metric: + valu_flops_pop: + value: ((100 * AVG(((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + + SQ_INSTS_VALU_TRANS_F16) + (2 * SQ_INSTS_VALU_FMA_F16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (2 * SQ_INSTS_VALU_FMA_F32)))) + + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (2 * SQ_INSTS_VALU_FMA_F64)))) / (EndNs - BeginNs)))) / (((($sclk + * $numCU) * 64) * 2) / 1000)) + unit: Pct of Peak + tips: + mfma_flops_bf16_pop: + value: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) / (EndNs - BeginNs)))) + / ((($sclk * $numCU) * 512) / 1000)) + unit: Pct of Peak + tips: + mfma_flops_f16_pop: + value: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (EndNs - BeginNs)))) + / ((($sclk * $numCU) * 1024) / 1000)) + unit: Pct of Peak + tips: + mfma_flops_f32_pop: + value: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) / (EndNs - BeginNs)))) + / ((($sclk * $numCU) * 256) / 1000)) + unit: Pct of Peak + tips: + mfma_flops_f64_pop: + value: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (EndNs - BeginNs)))) + / ((($sclk * $numCU) * 256) / 1000)) + unit: Pct of Peak + tips: + mfma_flops_i8_pop: + value: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (EndNs - BeginNs)))) + / ((($sclk * $numCU) * 1024) / 1000)) + unit: Pct of Peak + tips: + + - metric_table: + id: 1102 + title: Pipeline Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + IPC (Avg): + avg: AVG((SQ_INSTS / SQ_BUSY_CU_CYCLES)) + min: MIN((SQ_INSTS / SQ_BUSY_CU_CYCLES)) + max: MAX((SQ_INSTS / SQ_BUSY_CU_CYCLES)) + unit: Instr/cycle + tips: + IPC (Issue): + avg: AVG(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM) + + SQ_INSTS_GDS) + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED) + / SQ_ACTIVE_INST_ANY)) + min: MIN(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM) + + SQ_INSTS_GDS) + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED) + / SQ_ACTIVE_INST_ANY)) + max: MAX(((((((((SQ_INSTS_VALU + SQ_INSTS_VMEM) + SQ_INSTS_SALU) + SQ_INSTS_SMEM) + + SQ_INSTS_GDS) + SQ_INSTS_BRANCH) + SQ_INSTS_SENDMSG) + SQ_INSTS_VSKIPPED) + / SQ_ACTIVE_INST_ANY)) + unit: Instr/cycle + tips: + SALU Util: + avg: AVG((((100 * SQ_ACTIVE_INST_SCA) / GRBM_GUI_ACTIVE) / $numCU)) + min: MIN((((100 * SQ_ACTIVE_INST_SCA) / GRBM_GUI_ACTIVE) / $numCU)) + max: MAX((((100 * SQ_ACTIVE_INST_SCA) / GRBM_GUI_ACTIVE) / $numCU)) + unit: pct + tips: + VALU Util: + avg: AVG((((100 * SQ_ACTIVE_INST_VALU) / GRBM_GUI_ACTIVE) / $numCU)) + min: MIN((((100 * SQ_ACTIVE_INST_VALU) / GRBM_GUI_ACTIVE) / $numCU)) + max: MAX((((100 * SQ_ACTIVE_INST_VALU) / GRBM_GUI_ACTIVE) / $numCU)) + unit: pct + tips: + VALU Active Threads: + avg: AVG(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + min: MIN(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + max: MAX(((SQ_THREAD_CYCLES_VALU / SQ_ACTIVE_INST_VALU) if (SQ_ACTIVE_INST_VALU + != 0) else None)) + unit: Threads + tips: + MFMA Util: + avg: AVG(((100 * SQ_VALU_MFMA_BUSY_CYCLES) / ((4 * $numCU) * GRBM_GUI_ACTIVE))) + min: MIN(((100 * SQ_VALU_MFMA_BUSY_CYCLES) / ((4 * $numCU) * GRBM_GUI_ACTIVE))) + max: MAX(((100 * SQ_VALU_MFMA_BUSY_CYCLES) / ((4 * $numCU) * GRBM_GUI_ACTIVE))) + unit: pct + tips: + MFMA Instr Cycles: + avg: AVG(((SQ_VALU_MFMA_BUSY_CYCLES / SQ_INSTS_MFMA) if (SQ_INSTS_MFMA != 0) + else None)) + min: MIN(((SQ_VALU_MFMA_BUSY_CYCLES / SQ_INSTS_MFMA) if (SQ_INSTS_MFMA != 0) + else None)) + max: MAX(((SQ_VALU_MFMA_BUSY_CYCLES / SQ_INSTS_MFMA) if (SQ_INSTS_MFMA != 0) + else None)) + unit: cycles/instr + tips: + + - metric_table: + id: 1103 + title: Arithmetic Operations + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + FLOPs (Total): + avg: AVG((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 + * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64)) / + $denom)) + min: MIN((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 + * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64)) / + $denom)) + max: MAX((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 + * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64)) / + $denom)) + unit: (OPs + $normUnit) + tips: + INT8 OPs: + avg: AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / $denom)) + min: MIN(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / $denom)) + max: MAX(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / $denom)) + unit: (OPs + $normUnit) + tips: + F16 OPs: + avg: AVG(((((((64 * SQ_INSTS_VALU_ADD_F16) + (64 * SQ_INSTS_VALU_MUL_F16)) + + (64 * SQ_INSTS_VALU_TRANS_F16)) + (128 * SQ_INSTS_VALU_FMA_F16)) + (512 * + SQ_INSTS_VALU_MFMA_MOPS_F16)) / $denom)) + min: MIN(((((((64 * SQ_INSTS_VALU_ADD_F16) + (64 * SQ_INSTS_VALU_MUL_F16)) + + (64 * SQ_INSTS_VALU_TRANS_F16)) + (128 * SQ_INSTS_VALU_FMA_F16)) + (512 * + SQ_INSTS_VALU_MFMA_MOPS_F16)) / $denom)) + max: MAX(((((((64 * SQ_INSTS_VALU_ADD_F16) + (64 * SQ_INSTS_VALU_MUL_F16)) + + (64 * SQ_INSTS_VALU_TRANS_F16)) + (128 * SQ_INSTS_VALU_FMA_F16)) + (512 * + SQ_INSTS_VALU_MFMA_MOPS_F16)) / $denom)) + unit: (OPs + $normUnit) + tips: + BF16 OPs: + avg: AVG(((512 * SQ_INSTS_VALU_MFMA_MOPS_BF16) / $denom)) + min: MIN(((512 * SQ_INSTS_VALU_MFMA_MOPS_BF16) / $denom)) + max: MAX(((512 * SQ_INSTS_VALU_MFMA_MOPS_BF16) / $denom)) + unit: (OPs + $normUnit) + tips: + F32 OPs: + avg: AVG((((64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + + (SQ_INSTS_VALU_FMA_F32 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) / $denom)) + min: MIN((((64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + + (SQ_INSTS_VALU_FMA_F32 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) / $denom)) + max: MAX((((64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + + (SQ_INSTS_VALU_FMA_F32 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) / $denom)) + unit: (OPs + $normUnit) + tips: + F64 OPs: + avg: AVG((((64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (SQ_INSTS_VALU_FMA_F64 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64)) / $denom)) + min: MIN((((64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (SQ_INSTS_VALU_FMA_F64 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64)) / $denom)) + max: MAX((((64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + + (SQ_INSTS_VALU_FMA_F64 * 2))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64)) / $denom)) + unit: (OPs + $normUnit) + tips: \ No newline at end of file diff --git a/src/omniperf_soc/configs/gfx90a/1200_lds.yaml b/src/omniperf_soc/configs/gfx90a/1200_lds.yaml new file mode 100644 index 0000000000..3fd52c3b1b --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/1200_lds.yaml @@ -0,0 +1,121 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1200 + title: Local Data Share (LDS) + data source: + - metric_table: + id: 1201 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + range_color: [1, 100] + label_txt: (%) + xrange: [0, 110] + metric: + Utilization: + value: AVG(((100 * SQ_LDS_IDX_ACTIVE) / (GRBM_GUI_ACTIVE * $numCU))) + unit: Pct of Peak + tips: + Access Rate: + value: AVG(((200 * SQ_ACTIVE_INST_LDS) / (GRBM_GUI_ACTIVE * $numCU))) + unit: Pct of Peak + tips: + Bandwidth (Pct-of-Peak): + value: AVG((((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / (EndNs - BeginNs)) / (($sclk * $numCU) * 0.00128))) + unit: Pct of Peak + tips: + Bank Conflict Rate: + value: AVG((((SQ_LDS_BANK_CONFLICT * 3.125) / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + unit: Pct of Peak + tips: + + - metric_table: + id: 1202 + title: LDS Stats + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + LDS Instrs: + avg: AVG((SQ_INSTS_LDS / $denom)) + min: MIN((SQ_INSTS_LDS / $denom)) + max: MAX((SQ_INSTS_LDS / $denom)) + unit: (Instr + $normUnit) + tips: + Bandwidth: + avg: AVG(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / $denom)) + min: MIN(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / $denom)) + max: MAX(((((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) * 4) * TO_INT($LDSBanks)) + / $denom)) + unit: (Bytes + $normUnit) + tips: + Bank Conficts/Access: + avg: AVG(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + min: MIN(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + max: MAX(((SQ_LDS_BANK_CONFLICT / (SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT)) + if ((SQ_LDS_IDX_ACTIVE - SQ_LDS_BANK_CONFLICT) != 0) else None)) + unit: Conflicts/Access + tips: + Index Accesses: + avg: AVG((SQ_LDS_IDX_ACTIVE / $denom)) + min: MIN((SQ_LDS_IDX_ACTIVE / $denom)) + max: MAX((SQ_LDS_IDX_ACTIVE / $denom)) + unit: (Cycles + $normUnit) + tips: + Atomic Cycles: + avg: AVG((SQ_LDS_ATOMIC_RETURN / $denom)) + min: MIN((SQ_LDS_ATOMIC_RETURN / $denom)) + max: MAX((SQ_LDS_ATOMIC_RETURN / $denom)) + unit: (Cycles + $normUnit) + tips: + Bank Conflict: + avg: AVG((SQ_LDS_BANK_CONFLICT / $denom)) + min: MIN((SQ_LDS_BANK_CONFLICT / $denom)) + max: MAX((SQ_LDS_BANK_CONFLICT / $denom)) + unit: (Cycles + $normUnit) + tips: + Addr Conflict: + avg: AVG((SQ_LDS_ADDR_CONFLICT / $denom)) + min: MIN((SQ_LDS_ADDR_CONFLICT / $denom)) + max: MAX((SQ_LDS_ADDR_CONFLICT / $denom)) + unit: (Cycles + $normUnit) + tips: + Unaligned Stall: + avg: AVG((SQ_LDS_UNALIGNED_STALL / $denom)) + min: MIN((SQ_LDS_UNALIGNED_STALL / $denom)) + max: MAX((SQ_LDS_UNALIGNED_STALL / $denom)) + unit: (Cycles + $normUnit) + tips: + Mem Violations: + avg: AVG((SQ_LDS_MEM_VIOLATIONS / $denom)) + min: MIN((SQ_LDS_MEM_VIOLATIONS / $denom)) + max: MAX((SQ_LDS_MEM_VIOLATIONS / $denom)) + unit: ( + $normUnit) + tips: + LDS Latency: + avg: AVG(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)) + min: MIN(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)) + max: MAX(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) if (SQ_INSTS_LDS != 0) else None)) + unit: Cycles + coll_level: SQ_INST_LEVEL_LDS + tips: diff --git a/src/omniperf_soc/configs/gfx90a/1300_instruction-cache.yaml b/src/omniperf_soc/configs/gfx90a/1300_instruction-cache.yaml new file mode 100644 index 0000000000..329a7edbad --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/1300_instruction-cache.yaml @@ -0,0 +1,79 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1300 + title: Instruction Cache + data source: + - metric_table: + id: 1301 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + range_color: [1, 100] + label_txt: (%) + xrange: [0, 110] + metric: + Bandwidth: + value: AVG(((SQC_ICACHE_REQ * 100000) / (($sclk * $numSQC) + * (EndNs - BeginNs)))) + unit: Pct of Peak + tips: + Cache Hit: + value: AVG(((SQC_ICACHE_HITS * 100) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + unit: Pct of Peak + tips: + + - metric_table: + id: 1302 + title: Instruction Cache Accesses + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Req: + avg: AVG((SQC_ICACHE_REQ / $denom)) + min: MIN((SQC_ICACHE_REQ / $denom)) + max: MAX((SQC_ICACHE_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Hits: + avg: AVG((SQC_ICACHE_HITS / $denom)) + min: MIN((SQC_ICACHE_HITS / $denom)) + max: MAX((SQC_ICACHE_HITS / $denom)) + unit: (Hits + $normUnit) + tips: + Misses - Non Duplicated: + avg: AVG((SQC_ICACHE_MISSES / $denom)) + min: MIN((SQC_ICACHE_MISSES / $denom)) + max: MAX((SQC_ICACHE_MISSES / $denom)) + unit: (Misses + $normUnit) + tips: + Misses - Duplicated: + avg: AVG((SQC_ICACHE_MISSES_DUPLICATE / $denom)) + min: MIN((SQC_ICACHE_MISSES_DUPLICATE / $denom)) + max: MAX((SQC_ICACHE_MISSES_DUPLICATE / $denom)) + unit: (Misses + $normUnit) + tips: + Cache Hit: + avg: AVG(((100 * SQC_ICACHE_HITS) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + min: MIN(((100 * SQC_ICACHE_HITS) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + max: MAX(((100 * SQC_ICACHE_HITS) / ((SQC_ICACHE_HITS + SQC_ICACHE_MISSES) + + SQC_ICACHE_MISSES_DUPLICATE))) + unit: pct + tips: diff --git a/src/omniperf_soc/configs/gfx90a/1400_constant-cache.yaml b/src/omniperf_soc/configs/gfx90a/1400_constant-cache.yaml new file mode 100644 index 0000000000..563caad13f --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/1400_constant-cache.yaml @@ -0,0 +1,164 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1400 + title: Scalar L1 Data Cache + data source: + - metric_table: + id: 1401 + title: Speed-of-Light + header: + mertic: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + range_color: [1, 100] + label_txt: (%) + xrange: [0, 110] + metric: + Bandwidth: + value: AVG(((SQC_DCACHE_REQ * 100000) / (($sclk * $numSQC) + * (EndNs - BeginNs)))) + unit: Pct of Peak + tips: + Cache Hit: + value: + AVG((((SQC_DCACHE_HITS * 100) / (SQC_DCACHE_HITS + SQC_DCACHE_MISSES + SQC_DCACHE_MISSES_DUPLICATE)) + if ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + unit: Pct of Peak + tips: + + - metric_table: + id: 1402 + title: Scalar L1D Cache Accesses + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Req: + avg: AVG((SQC_DCACHE_REQ / $denom)) + min: MIN((SQC_DCACHE_REQ / $denom)) + max: MAX((SQC_DCACHE_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Hits: + avg: AVG((SQC_DCACHE_HITS / $denom)) + min: MIN((SQC_DCACHE_HITS / $denom)) + max: MAX((SQC_DCACHE_HITS / $denom)) + unit: (Req + $normUnit) + tips: + Misses - Non Duplicated: + avg: AVG((SQC_DCACHE_MISSES / $denom)) + min: MIN((SQC_DCACHE_MISSES / $denom)) + max: MAX((SQC_DCACHE_MISSES / $denom)) + unit: (Req + $normUnit) + tips: + Misses- Duplicated: + avg: AVG((SQC_DCACHE_MISSES_DUPLICATE / $denom)) + min: MIN((SQC_DCACHE_MISSES_DUPLICATE / $denom)) + max: MAX((SQC_DCACHE_MISSES_DUPLICATE / $denom)) + unit: (Req + $normUnit) + tips: + Cache Hit: + avg: AVG((((100 * SQC_DCACHE_HITS) / ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE)) if (((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + min: MIN((((100 * SQC_DCACHE_HITS) / ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE)) if (((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + max: MAX((((100 * SQC_DCACHE_HITS) / ((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE)) if (((SQC_DCACHE_HITS + SQC_DCACHE_MISSES) + + SQC_DCACHE_MISSES_DUPLICATE) != 0) else None)) + unit: pct + tips: + Read Req (Total): + avg: AVG((((((SQC_DCACHE_REQ_READ_1 + SQC_DCACHE_REQ_READ_2) + SQC_DCACHE_REQ_READ_4) + + SQC_DCACHE_REQ_READ_8) + SQC_DCACHE_REQ_READ_16) / $denom)) + min: MIN((((((SQC_DCACHE_REQ_READ_1 + SQC_DCACHE_REQ_READ_2) + SQC_DCACHE_REQ_READ_4) + + SQC_DCACHE_REQ_READ_8) + SQC_DCACHE_REQ_READ_16) / $denom)) + max: MAX((((((SQC_DCACHE_REQ_READ_1 + SQC_DCACHE_REQ_READ_2) + SQC_DCACHE_REQ_READ_4) + + SQC_DCACHE_REQ_READ_8) + SQC_DCACHE_REQ_READ_16) / $denom)) + unit: (Req + $normUnit) + tips: + Atomic Req: + avg: AVG((SQC_DCACHE_ATOMIC / $denom)) + min: MIN((SQC_DCACHE_ATOMIC / $denom)) + max: MAX((SQC_DCACHE_ATOMIC / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (1 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_1 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_1 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_1 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (2 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_2 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_2 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_2 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (4 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_4 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_4 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_4 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (8 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_8 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_8 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_8 / $denom)) + unit: (Req + $normUnit) + tips: + Read Req (16 DWord): + avg: AVG((SQC_DCACHE_REQ_READ_16 / $denom)) + min: MIN((SQC_DCACHE_REQ_READ_16 / $denom)) + max: MAX((SQC_DCACHE_REQ_READ_16 / $denom)) + unit: (Req + $normUnit) + tips: + + - metric_table: + id: 1403 + title: Scalar L1D Cache - L2 Interface + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Read Req: + avg: AVG((SQC_TC_DATA_READ_REQ / $denom)) + min: MIN((SQC_TC_DATA_READ_REQ / $denom)) + max: MAX((SQC_TC_DATA_READ_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Write Req: + avg: AVG((SQC_TC_DATA_WRITE_REQ / $denom)) + min: MIN((SQC_TC_DATA_WRITE_REQ / $denom)) + max: MAX((SQC_TC_DATA_WRITE_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Atomic Req: + avg: AVG((SQC_TC_DATA_ATOMIC_REQ / $denom)) + min: MIN((SQC_TC_DATA_ATOMIC_REQ / $denom)) + max: MAX((SQC_TC_DATA_ATOMIC_REQ / $denom)) + unit: (Req + $normUnit) + tips: + Stall: + avg: AVG((SQC_TC_STALL / $denom)) + min: MIN((SQC_TC_STALL / $denom)) + max: MAX((SQC_TC_STALL / $denom)) + unit: (Cycles + $normUnit) + tips: diff --git a/src/omniperf_soc/configs/gfx90a/1500_TA_and_TD.yaml b/src/omniperf_soc/configs/gfx90a/1500_TA_and_TD.yaml new file mode 100644 index 0000000000..03af854976 --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/1500_TA_and_TD.yaml @@ -0,0 +1,174 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1500 + title: Texture Addresser and Texture Data (TA/TD) + data source: + - metric_table: + id: 1501 + title: TA + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + TA Busy: + avg: AVG(((100 * TA_TA_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TA_TA_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TA_TA_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + TC2TA Addr Stall: + avg: AVG(((100 * TA_ADDR_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TA_ADDR_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TA_ADDR_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + TC2TA Data Stall: + avg: AVG(((100 * TA_DATA_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TA_DATA_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TA_DATA_STALLED_BY_TC_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + TD2TA Addr Stall: + avg: AVG(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TA_ADDR_STALLED_BY_TD_CYCLES_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + Total Instructions: + avg: AVG((TA_TOTAL_WAVEFRONTS_sum / $denom)) + min: MIN((TA_TOTAL_WAVEFRONTS_sum / $denom)) + max: MAX((TA_TOTAL_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Flat Instr: + avg: AVG((TA_FLAT_WAVEFRONTS_sum / $denom)) + min: MIN((TA_FLAT_WAVEFRONTS_sum / $denom)) + max: MAX((TA_FLAT_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Flat Read Instr: + avg: AVG((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) + min: MIN((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) + max: MAX((TA_FLAT_READ_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Flat Write Instr: + avg: AVG((TA_FLAT_WRITE_WAVEFRONTS_sum / $denom)) + min: MIN((TA_FLAT_WRITE_WAVEFRONTS_sum / $denom)) + max: MAX((TA_FLAT_WRITE_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Flat Atomic Instr: + avg: AVG((TA_FLAT_ATOMIC_WAVEFRONTS_sum / $denom)) + min: MIN((TA_FLAT_ATOMIC_WAVEFRONTS_sum / $denom)) + max: MAX((TA_FLAT_ATOMIC_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Buffer Instr: + avg: AVG((TA_BUFFER_WAVEFRONTS_sum / $denom)) + min: MIN((TA_BUFFER_WAVEFRONTS_sum / $denom)) + max: MAX((TA_BUFFER_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Buffer Read Instr: + avg: AVG((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) + min: MIN((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) + max: MAX((TA_BUFFER_READ_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Buffer Write Instr: + avg: AVG((TA_BUFFER_WRITE_WAVEFRONTS_sum / $denom)) + min: MIN((TA_BUFFER_WRITE_WAVEFRONTS_sum / $denom)) + max: MAX((TA_BUFFER_WRITE_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Buffer Atomic Instr: + avg: AVG((TA_BUFFER_ATOMIC_WAVEFRONTS_sum / $denom)) + min: MIN((TA_BUFFER_ATOMIC_WAVEFRONTS_sum / $denom)) + max: MAX((TA_BUFFER_ATOMIC_WAVEFRONTS_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Buffer Total Cylces: + avg: AVG((TA_BUFFER_TOTAL_CYCLES_sum / $denom)) + min: MIN((TA_BUFFER_TOTAL_CYCLES_sum / $denom)) + max: MAX((TA_BUFFER_TOTAL_CYCLES_sum / $denom)) + unit: (Cycles + $normUnit) + tips: + Buffer Coalesced Read: + avg: AVG((TA_BUFFER_COALESCED_READ_CYCLES_sum / $denom)) + min: MIN((TA_BUFFER_COALESCED_READ_CYCLES_sum / $denom)) + max: MAX((TA_BUFFER_COALESCED_READ_CYCLES_sum / $denom)) + unit: (Cycles + $normUnit) + tips: + Buffer Coalesced Write: + avg: AVG((TA_BUFFER_COALESCED_WRITE_CYCLES_sum / $denom)) + min: MIN((TA_BUFFER_COALESCED_WRITE_CYCLES_sum / $denom)) + max: MAX((TA_BUFFER_COALESCED_WRITE_CYCLES_sum / $denom)) + unit: (Cycles + $normUnit) + tips: + + - metric_table: + id: 1502 + title: TD + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + TD Busy: + avg: AVG(((100 * TD_TD_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TD_TD_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TD_TD_BUSY_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + TC2TD Stall: + avg: AVG(((100 * TD_TC_STALL_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TD_TC_STALL_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TD_TC_STALL_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + SPI2TD Stall: + avg: AVG(((100 * TD_SPI_STALL_sum) / (GRBM_GUI_ACTIVE * $numCU))) + min: MIN(((100 * TD_SPI_STALL_sum) / (GRBM_GUI_ACTIVE * $numCU))) + max: MAX(((100 * TD_SPI_STALL_sum) / (GRBM_GUI_ACTIVE * $numCU))) + unit: pct + tips: + Coalescable Instr: + avg: AVG((TD_COALESCABLE_WAVEFRONT_sum / $denom)) + min: MIN((TD_COALESCABLE_WAVEFRONT_sum / $denom)) + max: MAX((TD_COALESCABLE_WAVEFRONT_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Load Instr: + avg: AVG((((TD_LOAD_WAVEFRONT_sum - TD_STORE_WAVEFRONT_sum) - TD_ATOMIC_WAVEFRONT_sum) + / $denom)) + min: MIN((((TD_LOAD_WAVEFRONT_sum - TD_STORE_WAVEFRONT_sum) - TD_ATOMIC_WAVEFRONT_sum) + / $denom)) + max: MAX((((TD_LOAD_WAVEFRONT_sum - TD_STORE_WAVEFRONT_sum) - TD_ATOMIC_WAVEFRONT_sum) + / $denom)) + unit: (Instr + $normUnit) + tips: + Store Instr: + avg: AVG((TD_STORE_WAVEFRONT_sum / $denom)) + min: MIN((TD_STORE_WAVEFRONT_sum / $denom)) + max: MAX((TD_STORE_WAVEFRONT_sum / $denom)) + unit: (Instr + $normUnit) + tips: + Atomic Instr: + avg: AVG((TD_ATOMIC_WAVEFRONT_sum / $denom)) + min: MIN((TD_ATOMIC_WAVEFRONT_sum / $denom)) + max: MAX((TD_ATOMIC_WAVEFRONT_sum / $denom)) + unit: (Instr + $normUnit) + tips: diff --git a/src/omniperf_soc/configs/gfx90a/1600_L1_cache.yaml b/src/omniperf_soc/configs/gfx90a/1600_L1_cache.yaml new file mode 100644 index 0000000000..d9291de21d --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/1600_L1_cache.yaml @@ -0,0 +1,404 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1600 + title: Vector L1 Data Cache + data source: + - metric_table: + id: 1601 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + range_color: [1, 100] + label_txt: (%) + xrange: [0, 110] + metric: + Buffer Coalescing: + value: AVG(((((TA_TOTAL_WAVEFRONTS_sum * 64) * 100) / (TCP_TOTAL_ACCESSES_sum + * 4)) if (TCP_TOTAL_ACCESSES_sum != 0) else None)) + unit: Pct of Peak + tips: + Cache Util: + value: AVG((((TCP_GATE_EN2_sum * 100) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + unit: Pct of Peak + tips: + Cache BW: + value: ((100 * AVG(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs)))) + / ((($sclk / 1000) * 64) * $numCU)) + unit: Pct of Peak + tips: + Cache Hit: + value: AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + unit: Pct of Peak + tips: + + - metric_table: + id: 1602 + title: L1D Cache Stalls + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: unit + tips: Tips + metric: + Stalled on L2 Data: + avg: AVG((((100 * TCP_PENDING_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + min: MIN((((100 * TCP_PENDING_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + max: MAX((((100 * TCP_PENDING_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + unit: pct + tips: + Stalled on L2 Req: + avg: AVG((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + min: MIN((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + max: MAX((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum + != 0) else None)) + unit: pct + tips: + Tag RAM Stall (Read): + avg: AVG((((100 * TCP_READ_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + min: MIN((((100 * TCP_READ_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + max: MAX((((100 * TCP_READ_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + unit: pct + tips: + Tag RAM Stall (Write): + avg: AVG((((100 * TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + min: MIN((((100 * TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + max: MAX((((100 * TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + unit: pct + tips: + Tag RAM Stall (Atomic): + avg: AVG((((100 * TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + min: MIN((((100 * TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + max: MAX((((100 * TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)) + unit: pct + tips: + + - metric_table: + id: 1603 + title: L1D Cache Accesses + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Total Req: + avg: AVG((TCP_TOTAL_ACCESSES_sum / $denom)) + min: MIN((TCP_TOTAL_ACCESSES_sum / $denom)) + max: MAX((TCP_TOTAL_ACCESSES_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read Req: + avg: AVG((TCP_TOTAL_READ_sum / $denom)) + min: MIN((TCP_TOTAL_READ_sum / $denom)) + max: MAX((TCP_TOTAL_READ_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write Req: + avg: AVG((TCP_TOTAL_WRITE_sum / $denom)) + min: MIN((TCP_TOTAL_WRITE_sum / $denom)) + max: MAX((TCP_TOTAL_WRITE_sum / $denom)) + unit: (Req + $normUnit) + tips: + Atomic Req: + avg: AVG(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) + / $denom)) + min: MIN(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) + / $denom)) + max: MAX(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) + / $denom)) + unit: (Req + $normUnit) + tips: + Cache BW: + avg: AVG(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs))) + min: MIN(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs))) + max: MAX(((TCP_TOTAL_CACHE_ACCESSES_sum * 64) / (EndNs - BeginNs))) + unit: GB/s + tips: + Cache Accesses: + avg: AVG((TCP_TOTAL_CACHE_ACCESSES_sum / $denom)) + min: MIN((TCP_TOTAL_CACHE_ACCESSES_sum / $denom)) + max: MAX((TCP_TOTAL_CACHE_ACCESSES_sum / $denom)) + unit: (Req + $normUnit) + tips: + Cache Hits: + avg: AVG(((TCP_TOTAL_CACHE_ACCESSES_sum - (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / $denom)) + min: MIN(((TCP_TOTAL_CACHE_ACCESSES_sum - (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / $denom)) + max: MAX(((TCP_TOTAL_CACHE_ACCESSES_sum - (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / $denom)) + unit: (Req + $normUnit) + tips: + Cache Hit Rate: + avg: AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / + TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + min: MIN(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / + TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + max: MAX(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / + TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)) + unit: pct + tips: + Invalidate: + avg: AVG((TCP_TOTAL_WRITEBACK_INVALIDATES_sum / $denom)) + min: MIN((TCP_TOTAL_WRITEBACK_INVALIDATES_sum / $denom)) + max: MAX((TCP_TOTAL_WRITEBACK_INVALIDATES_sum / $denom)) + unit: (Req + $normUnit) + tips: + L1-L2 BW: + avg: AVG(((64 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / $denom)) + min: AVG(((64 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / $denom)) + max: AVG(((64 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) / $denom)) + unit: (Bytes + $normUnit) + tips: + L1-L2 Read: + avg: AVG((TCP_TCC_READ_REQ_sum / $denom)) + min: MIN((TCP_TCC_READ_REQ_sum / $denom)) + max: MAX((TCP_TCC_READ_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + L1-L2 Write: + avg: AVG((TCP_TCC_WRITE_REQ_sum / $denom)) + min: MIN((TCP_TCC_WRITE_REQ_sum / $denom)) + max: MAX((TCP_TCC_WRITE_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + L1-L2 Atomic: + avg: AVG(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + / $denom)) + min: MIN(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + / $denom)) + max: MAX(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + / $denom)) + unit: (Req + $normUnit) + tips: + L1 Access Latency: + avg: AVG(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum + != 0) else None)) + min: MIN(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum + != 0) else None)) + max: MAX(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum + != 0) else None)) + unit: Cycles + tips: + L1-L2 Read Latency: + avg: AVG(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) + if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)) + min: MIN(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) + if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)) + max: MAX(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) + if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)) + unit: Cycles + tips: + L1-L2 Write Latency: + avg: AVG(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) != 0) else + None)) + min: MIN(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) != 0) else + None)) + max: MAX(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) != 0) else + None)) + unit: Cycles + tips: + + - metric_table: + id: 1604 + title: L1D - L2 Transactions + header: + metric: Metric + xfer: Xfer + coherency: Coherency + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + style: + type: simple_multi_bar + metric: + NC - Read: + xfer: Read + coherency: NC + avg: AVG((TCP_TCC_NC_READ_REQ_sum / $denom)) + min: MIN((TCP_TCC_NC_READ_REQ_sum / $denom)) + max: MAX((TCP_TCC_NC_READ_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + UC - Read: + xfer: Read + coherency: UC + avg: AVG((TCP_TCC_UC_READ_REQ_sum / $denom)) + min: MIN((TCP_TCC_UC_READ_REQ_sum / $denom)) + max: MAX((TCP_TCC_UC_READ_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + CC - Read: + xfer: Read + coherency: CC + avg: AVG((TCP_TCC_CC_READ_REQ_sum / $denom)) + min: MIN((TCP_TCC_CC_READ_REQ_sum / $denom)) + max: MAX((TCP_TCC_CC_READ_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + RW - Read: + xfer: Read + coherency: RW + avg: AVG((TCP_TCC_RW_READ_REQ_sum / $denom)) + min: MIN((TCP_TCC_RW_READ_REQ_sum / $denom)) + max: MAX((TCP_TCC_RW_READ_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + RW - Write: + xfer: Write + coherency: RW + avg: AVG((TCP_TCC_RW_WRITE_REQ_sum / $denom)) + min: MIN((TCP_TCC_RW_WRITE_REQ_sum / $denom)) + max: MAX((TCP_TCC_RW_WRITE_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + NC - Write: + xfer: Write + coherency: NC + avg: AVG((TCP_TCC_NC_WRITE_REQ_sum / $denom)) + min: MIN((TCP_TCC_NC_WRITE_REQ_sum / $denom)) + max: MAX((TCP_TCC_NC_WRITE_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + UC - Write: + xfer: Write + coherency: UC + avg: AVG((TCP_TCC_UC_WRITE_REQ_sum / $denom)) + min: MIN((TCP_TCC_UC_WRITE_REQ_sum / $denom)) + max: MAX((TCP_TCC_UC_WRITE_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + CC - Write: + xfer: Write + coherency: CC + avg: AVG((TCP_TCC_CC_WRITE_REQ_sum / $denom)) + min: MIN((TCP_TCC_CC_WRITE_REQ_sum / $denom)) + max: MAX((TCP_TCC_CC_WRITE_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + NC - Atomic: + xfer: Atomic + coherency: NC + avg: AVG((TCP_TCC_NC_ATOMIC_REQ_sum / $denom)) + min: MIN((TCP_TCC_NC_ATOMIC_REQ_sum / $denom)) + max: MAX((TCP_TCC_NC_ATOMIC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + UC - Atomic: + xfer: Atomic + coherency: UC + avg: AVG((TCP_TCC_UC_ATOMIC_REQ_sum / $denom)) + min: MIN((TCP_TCC_UC_ATOMIC_REQ_sum / $denom)) + max: MAX((TCP_TCC_UC_ATOMIC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + CC - Atomic: + xfer: Atomic + coherency: CC + avg: AVG((TCP_TCC_CC_ATOMIC_REQ_sum / $denom)) + min: MIN((TCP_TCC_CC_ATOMIC_REQ_sum / $denom)) + max: MAX((TCP_TCC_CC_ATOMIC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + RW - Atomic: + xfer: Atomic + coherency: RW + avg: AVG((TCP_TCC_RW_ATOMIC_REQ_sum / $denom)) + min: MIN((TCP_TCC_RW_ATOMIC_REQ_sum / $denom)) + max: MAX((TCP_TCC_RW_ATOMIC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + + - metric_table: + id: 1605 + title: L1D Addr Translation + header: + metric: Metric + avg: Avg + min: Min + max: Max + units: Units + tips: Tips + metric: + Req: + avg: AVG((TCP_UTCL1_REQUEST_sum / $denom)) + min: MIN((TCP_UTCL1_REQUEST_sum / $denom)) + max: MAX((TCP_UTCL1_REQUEST_sum / $denom)) + units: (Req + $normUnit) + tips: + Hit Ratio: + avg: AVG((((100 * TCP_UTCL1_TRANSLATION_HIT_sum) / TCP_UTCL1_REQUEST_sum) if + (TCP_UTCL1_REQUEST_sum != 0) else None)) + min: MIN((((100 * TCP_UTCL1_TRANSLATION_HIT_sum) / TCP_UTCL1_REQUEST_sum) if + (TCP_UTCL1_REQUEST_sum != 0) else None)) + max: MAX((((100 * TCP_UTCL1_TRANSLATION_HIT_sum) / TCP_UTCL1_REQUEST_sum) if + (TCP_UTCL1_REQUEST_sum != 0) else None)) + units: pct + tips: + Hits: + avg: AVG((TCP_UTCL1_TRANSLATION_HIT_sum / $denom)) + min: MIN((TCP_UTCL1_TRANSLATION_HIT_sum / $denom)) + max: MAX((TCP_UTCL1_TRANSLATION_HIT_sum / $denom)) + units: (Hits + $normUnit) + tips: + Misses (Translation): + avg: AVG((TCP_UTCL1_TRANSLATION_MISS_sum / $denom)) + min: MIN((TCP_UTCL1_TRANSLATION_MISS_sum / $denom)) + max: MAX((TCP_UTCL1_TRANSLATION_MISS_sum / $denom)) + units: (Misses + $normUnit) + tips: + Misses (Permission): + avg: AVG((TCP_UTCL1_PERMISSION_MISS_sum / $denom)) + min: MIN((TCP_UTCL1_PERMISSION_MISS_sum / $denom)) + max: MAX((TCP_UTCL1_PERMISSION_MISS_sum / $denom)) + units: (Misses + $normUnit) + tips: diff --git a/src/omniperf_soc/configs/gfx90a/1700_L2_cache.yaml b/src/omniperf_soc/configs/gfx90a/1700_L2_cache.yaml new file mode 100644 index 0000000000..ddbaf91554 --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/1700_L2_cache.yaml @@ -0,0 +1,364 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1700 + title: L2 Cache + data source: + - metric_table: + id: 1701 + title: Speed-of-Light + header: + metric: Metric + value: Value + unit: Unit + tips: Tips + style: + type: simple_bar + metric: + L2 Util: + value: AVG(((TCC_BUSY_sum * 100) / (TO_INT($L2Banks) * GRBM_GUI_ACTIVE))) + unit: pct + tips: + Cache Hit: + value: AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else 0)) + unit: pct + tips: + L2-EA Rd BW: + value: AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / (EndNs - BeginNs))) + unit: GB/s + tips: + L2-EA Wr BW: + value: AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / (EndNs - BeginNs))) + unit: GB/s + tips: + + - metric_table: + id: 1702 + title: L2 - Fabric Transactions + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Read BW: + avg: AVG((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / $denom)) + min: MIN((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / $denom)) + max: MAX((((TCC_EA_RDREQ_32B_sum * 32) + ((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) + * 64)) / $denom)) + unit: (Bytes + $normUnit) + tips: + Write BW: + avg: AVG((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / $denom)) + min: MIN((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / $denom)) + max: MAX((((TCC_EA_WRREQ_64B_sum * 64) + ((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) + * 32)) / $denom)) + unit: (Bytes + $normUnit) + tips: + Read (32B): + avg: AVG((TCC_EA_RDREQ_32B_sum / $denom)) + min: MIN((TCC_EA_RDREQ_32B_sum / $denom)) + max: MAX((TCC_EA_RDREQ_32B_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read (Uncached 32B): + avg: AVG((TCC_EA_RD_UNCACHED_32B_sum / $denom)) + min: MIN((TCC_EA_RD_UNCACHED_32B_sum / $denom)) + max: MAX((TCC_EA_RD_UNCACHED_32B_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read (64B): + avg: AVG(((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) / $denom)) + min: MIN(((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) / $denom)) + max: MAX(((TCC_EA_RDREQ_sum - TCC_EA_RDREQ_32B_sum) / $denom)) + unit: (Req + $normUnit) + tips: + HBM Read: + avg: AVG((TCC_EA_RDREQ_DRAM_sum / $denom)) + min: MIN((TCC_EA_RDREQ_DRAM_sum / $denom)) + max: MAX((TCC_EA_RDREQ_DRAM_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write (32B): + avg: AVG(((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) / $denom)) + min: MIN(((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) / $denom)) + max: MAX(((TCC_EA_WRREQ_sum - TCC_EA_WRREQ_64B_sum) / $denom)) + unit: (Req + $normUnit) + tips: + Write (Uncached 32B): + avg: AVG((TCC_EA_WR_UNCACHED_32B_sum / $denom)) + min: MIN((TCC_EA_WR_UNCACHED_32B_sum / $denom)) + max: MAX((TCC_EA_WR_UNCACHED_32B_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write (64B): + avg: AVG((TCC_EA_WRREQ_64B_sum / $denom)) + min: MIN((TCC_EA_WRREQ_64B_sum / $denom)) + max: MAX((TCC_EA_WRREQ_64B_sum / $denom)) + unit: (Req + $normUnit) + tips: + HBM Write: + avg: AVG((TCC_EA_WRREQ_DRAM_sum / $denom)) + min: MIN((TCC_EA_WRREQ_DRAM_sum / $denom)) + max: MAX((TCC_EA_WRREQ_DRAM_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read Latency: + avg: AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum != + 0) else None)) + min: MIN(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum != + 0) else None)) + max: MAX(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum != + 0) else None)) + unit: Cycles + tips: + Write Latency: + avg: AVG(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum != + 0) else None)) + min: MIN(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum != + 0) else None)) + max: MAX(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum != + 0) else None)) + unit: Cycles + tips: + Atomic Latency: + avg: AVG(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum + != 0) else None)) + min: MIN(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum + != 0) else None)) + max: MAX(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum + != 0) else None)) + unit: Cycles + tips: + Read Stall: + avg: AVG((((100 * ((TCC_EA_RDREQ_IO_CREDIT_STALL_sum + TCC_EA_RDREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + min: MIN((((100 * ((TCC_EA_RDREQ_IO_CREDIT_STALL_sum + TCC_EA_RDREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + max: MAX((((100 * ((TCC_EA_RDREQ_IO_CREDIT_STALL_sum + TCC_EA_RDREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + unit: pct + tips: + Write Stall: + avg: AVG((((100 * ((TCC_EA_WRREQ_IO_CREDIT_STALL_sum + TCC_EA_WRREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + min: MIN((((100 * ((TCC_EA_WRREQ_IO_CREDIT_STALL_sum + TCC_EA_WRREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + max: MAX((((100 * ((TCC_EA_WRREQ_IO_CREDIT_STALL_sum + TCC_EA_WRREQ_GMI_CREDIT_STALL_sum) + + TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != + 0) else None)) + unit: pct + tips: + + - metric_table: + id: 1703 + title: L2 Cache Accesses + header: + metric: Metric + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + metric: + Req: + avg: AVG((TCC_REQ_sum / $denom)) + min: MIN((TCC_REQ_sum / $denom)) + max: MAX((TCC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + Streaming Req: + avg: AVG((TCC_STREAMING_REQ_sum / $denom)) + min: MIN((TCC_STREAMING_REQ_sum / $denom)) + max: MAX((TCC_STREAMING_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read Req: + avg: AVG((TCC_READ_sum / $denom)) + min: MIN((TCC_READ_sum / $denom)) + max: MAX((TCC_READ_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write Req: + avg: AVG((TCC_WRITE_sum / $denom)) + min: MIN((TCC_WRITE_sum / $denom)) + max: MAX((TCC_WRITE_sum / $denom)) + unit: (Req + $normUnit) + tips: + Atomic Req: + avg: AVG((TCC_ATOMIC_sum / $denom)) + min: MIN((TCC_ATOMIC_sum / $denom)) + max: MAX((TCC_ATOMIC_sum / $denom)) + unit: (Req + $normUnit) + tips: + Probe Req: + avg: AVG((TCC_PROBE_sum / $denom)) + min: MIN((TCC_PROBE_sum / $denom)) + max: MAX((TCC_PROBE_sum / $denom)) + unit: (Req + $normUnit) + tips: + Hits: + avg: AVG((TCC_HIT_sum / $denom)) + min: MIN((TCC_HIT_sum / $denom)) + max: MAX((TCC_HIT_sum / $denom)) + unit: (Hits + $normUnit) + tips: + Misses: + avg: AVG((TCC_MISS_sum / $denom)) + min: MIN((TCC_MISS_sum / $denom)) + max: MAX((TCC_MISS_sum / $denom)) + unit: (Misses + $normUnit) + tips: + Cache Hit: + avg: AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + min: MIN((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + max: MAX((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)) + unit: pct + tips: + Writeback: + avg: AVG((TCC_WRITEBACK_sum / $denom)) + min: MIN((TCC_WRITEBACK_sum / $denom)) + max: MAX((TCC_WRITEBACK_sum / $denom)) + unit: ( + $normUnit) + tips: + NC Req: + avg: AVG((TCC_NC_REQ_sum / $denom)) + min: MIN((TCC_NC_REQ_sum / $denom)) + max: MAX((TCC_NC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + UC Req: + avg: AVG((TCC_UC_REQ_sum / $denom)) + min: MIN((TCC_UC_REQ_sum / $denom)) + max: MAX((TCC_UC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + CC Req: + avg: AVG((TCC_CC_REQ_sum / $denom)) + min: MIN((TCC_CC_REQ_sum / $denom)) + max: MAX((TCC_CC_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + RW Req: + avg: AVG((TCC_RW_REQ_sum / $denom)) + min: MIN((TCC_RW_REQ_sum / $denom)) + max: MAX((TCC_RW_REQ_sum / $denom)) + unit: (Req + $normUnit) + tips: + Writeback (Normal): + avg: AVG((TCC_NORMAL_WRITEBACK_sum / $denom)) + min: MIN((TCC_NORMAL_WRITEBACK_sum / $denom)) + max: MAX((TCC_NORMAL_WRITEBACK_sum / $denom)) + unit: ( + $normUnit) + tips: + Writeback (TC Req): + avg: AVG((TCC_ALL_TC_OP_WB_WRITEBACK_sum / $denom)) + min: MIN((TCC_ALL_TC_OP_WB_WRITEBACK_sum / $denom)) + max: MAX((TCC_ALL_TC_OP_WB_WRITEBACK_sum / $denom)) + unit: ( + $normUnit) + tips: + Evict (Normal): + avg: AVG((TCC_NORMAL_EVICT_sum / $denom)) + min: MIN((TCC_NORMAL_EVICT_sum / $denom)) + max: MAX((TCC_NORMAL_EVICT_sum / $denom)) + unit: ( + $normUnit) + tips: + Evict (TC Req): + avg: AVG((TCC_ALL_TC_OP_INV_EVICT_sum / $denom)) + min: MIN((TCC_ALL_TC_OP_INV_EVICT_sum / $denom)) + max: MAX((TCC_ALL_TC_OP_INV_EVICT_sum / $denom)) + unit: ( + $normUnit) + tips: + + - metric_table: + id: 1704 + title: L2 - Fabric Interface Stalls + header: + metric: Metric + type: Type + transaction: Transaction + avg: Avg + min: Min + max: Max + unit: Unit + tips: Tips + style: + type: simple_multi_bar + metric: + Read - Remote Socket Stall: + type: Remote Socket Stall + transaction: Read + avg: AVG((TCC_EA_RDREQ_IO_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_RDREQ_IO_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_RDREQ_IO_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read - Peer GCD Stall: + type: Peer GCD Stall + transaction: Read + avg: AVG((TCC_EA_RDREQ_GMI_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_RDREQ_GMI_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_RDREQ_GMI_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Read - HBM Stall: + type: HBM Stall + transaction: Read + avg: AVG((TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write - Remote Socket Stall: + type: Remote Socket Stall + transaction: Write + avg: AVG((TCC_EA_WRREQ_IO_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_WRREQ_IO_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_WRREQ_IO_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write - Peer GCD Stall: + type: Peer GCD Stall + transaction: Write + avg: AVG((TCC_EA_WRREQ_GMI_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_WRREQ_GMI_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_WRREQ_GMI_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write - HBM Stall: + type: HBM Stall + transaction: Write + avg: AVG((TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum / $denom)) + min: MIN((TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum / $denom)) + max: MAX((TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: + Write - Credit Starvation: + type: Credit Starvation + transaction: Write + avg: AVG((TCC_TOO_MANY_EA_WRREQS_STALL_sum / $denom)) + min: MIN((TCC_TOO_MANY_EA_WRREQS_STALL_sum / $denom)) + max: MAX((TCC_TOO_MANY_EA_WRREQS_STALL_sum / $denom)) + unit: (Req + $normUnit) + tips: diff --git a/src/omniperf_soc/configs/gfx90a/1800_L2_cache_per_channel.yaml b/src/omniperf_soc/configs/gfx90a/1800_L2_cache_per_channel.yaml new file mode 100644 index 0000000000..c6d93aa61b --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/1800_L2_cache_per_channel.yaml @@ -0,0 +1,2168 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1800 + title: L2 Cache (per Channel) + data source: + - metric_table: + id: 1801 + title: Aggregate Stats (All 32 channels) + header: + metric: Metric + avg: Avg + std dev: Std Dev + min: Min + max: Max + unit: Unit + tips: Tips + metric: + L2 Cache Hit Rate: + avg: AVG(((((((((((((((((((((((((((((((((((100 * TCC_HIT[0]) + (100 * TCC_HIT[1])) + + (100 * TCC_HIT[2])) + (100 * TCC_HIT[3])) + (100 * TCC_HIT[4])) + (100 * + TCC_HIT[5])) + (100 * TCC_HIT[6])) + (100 * TCC_HIT[7])) + (100 * TCC_HIT[8])) + + (100 * TCC_HIT[9])) + (100 * TCC_HIT[10])) + (100 * TCC_HIT[11])) + (100 + * TCC_HIT[12])) + (100 * TCC_HIT[13])) + (100 * TCC_HIT[14])) + (100 * TCC_HIT[15])) + + (100 * TCC_HIT[16])) + (100 * TCC_HIT[17])) + (100 * TCC_HIT[18])) + (100 + * TCC_HIT[19])) + (100 * TCC_HIT[20])) + (100 * TCC_HIT[21])) + (100 * TCC_HIT[22])) + + (100 * TCC_HIT[23])) + (100 * TCC_HIT[24])) + (100 * TCC_HIT[25])) + (100 + * TCC_HIT[26])) + (100 * TCC_HIT[27])) + (100 * TCC_HIT[28])) + (100 * TCC_HIT[29])) + + (100 * TCC_HIT[30])) + (100 * TCC_HIT[31])) / ((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31]))) if (((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[29] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31])) != 0) else None)) + std dev: STD(((((((((((((((((((((((((((((((((((100 * TCC_HIT[0]) + (100 * TCC_HIT[1])) + + (100 * TCC_HIT[2])) + (100 * TCC_HIT[3])) + (100 * TCC_HIT[4])) + (100 * + TCC_HIT[5])) + (100 * TCC_HIT[6])) + (100 * TCC_HIT[7])) + (100 * TCC_HIT[8])) + + (100 * TCC_HIT[9])) + (100 * TCC_HIT[10])) + (100 * TCC_HIT[11])) + (100 + * TCC_HIT[12])) + (100 * TCC_HIT[13])) + (100 * TCC_HIT[14])) + (100 * TCC_HIT[15])) + + (100 * TCC_HIT[16])) + (100 * TCC_HIT[17])) + (100 * TCC_HIT[18])) + (100 + * TCC_HIT[19])) + (100 * TCC_HIT[20])) + (100 * TCC_HIT[21])) + (100 * TCC_HIT[22])) + + (100 * TCC_HIT[23])) + (100 * TCC_HIT[24])) + (100 * TCC_HIT[25])) + (100 + * TCC_HIT[26])) + (100 * TCC_HIT[27])) + (100 * TCC_HIT[28])) + (100 * TCC_HIT[29])) + + (100 * TCC_HIT[30])) + (100 * TCC_HIT[31])) / ((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31]))) if (((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31])) != 0) else None)) + min: MIN(((((((((((((((((((((((((((((((((((100 * TCC_HIT[0]) + (100 * TCC_HIT[1])) + + (100 * TCC_HIT[2])) + (100 * TCC_HIT[3])) + (100 * TCC_HIT[4])) + (100 * + TCC_HIT[5])) + (100 * TCC_HIT[6])) + (100 * TCC_HIT[7])) + (100 * TCC_HIT[8])) + + (100 * TCC_HIT[9])) + (100 * TCC_HIT[10])) + (100 * TCC_HIT[11])) + (100 + * TCC_HIT[12])) + (100 * TCC_HIT[13])) + (100 * TCC_HIT[14])) + (100 * TCC_HIT[15])) + + (100 * TCC_HIT[16])) + (100 * TCC_HIT[17])) + (100 * TCC_HIT[18])) + (100 + * TCC_HIT[19])) + (100 * TCC_HIT[20])) + (100 * TCC_HIT[21])) + (100 * TCC_HIT[22])) + + (100 * TCC_HIT[23])) + (100 * TCC_HIT[24])) + (100 * TCC_HIT[25])) + (100 + * TCC_HIT[26])) + (100 * TCC_HIT[27])) + (100 * TCC_HIT[28])) + (100 * TCC_HIT[29])) + + (100 * TCC_HIT[30])) + (100 * TCC_HIT[31])) / ((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31]))) if (((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31])) != 0) else None)) + max: MAX(((((((((((((((((((((((((((((((((((100 * TCC_HIT[0]) + (100 * TCC_HIT[1])) + + (100 * TCC_HIT[2])) + (100 * TCC_HIT[3])) + (100 * TCC_HIT[4])) + (100 * + TCC_HIT[5])) + (100 * TCC_HIT[6])) + (100 * TCC_HIT[7])) + (100 * TCC_HIT[8])) + + (100 * TCC_HIT[9])) + (100 * TCC_HIT[10])) + (100 * TCC_HIT[11])) + (100 + * TCC_HIT[12])) + (100 * TCC_HIT[13])) + (100 * TCC_HIT[14])) + (100 * TCC_HIT[15])) + + (100 * TCC_HIT[16])) + (100 * TCC_HIT[17])) + (100 * TCC_HIT[18])) + (100 + * TCC_HIT[19])) + (100 * TCC_HIT[20])) + (100 * TCC_HIT[21])) + (100 * TCC_HIT[22])) + + (100 * TCC_HIT[23])) + (100 * TCC_HIT[24])) + (100 * TCC_HIT[25])) + (100 + * TCC_HIT[26])) + (100 * TCC_HIT[27])) + (100 * TCC_HIT[28])) + (100 * TCC_HIT[29])) + + (100 * TCC_HIT[30])) + (100 * TCC_HIT[31])) / ((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31]))) if (((((((((((((((((((((((((((((((((TCC_MISS[0] + + TCC_HIT[0]) + (TCC_MISS[1] + TCC_HIT[1])) + (TCC_MISS[2] + TCC_HIT[2])) + + (TCC_MISS[3] + TCC_HIT[3])) + (TCC_MISS[4] + TCC_HIT[4])) + (TCC_MISS[5] + + TCC_HIT[5])) + (TCC_MISS[6] + TCC_HIT[6])) + (TCC_MISS[7] + TCC_HIT[7])) + + (TCC_MISS[8] + TCC_HIT[8])) + (TCC_MISS[9] + TCC_HIT[9])) + (TCC_MISS[10] + + TCC_HIT[10])) + (TCC_MISS[11] + TCC_HIT[11])) + (TCC_MISS[12] + TCC_HIT[12])) + + (TCC_MISS[13] + TCC_HIT[13])) + (TCC_MISS[14] + TCC_HIT[14])) + (TCC_MISS[15] + + TCC_HIT[15])) + (TCC_MISS[16] + TCC_HIT[16])) + (TCC_MISS[17] + TCC_HIT[17])) + + (TCC_MISS[18] + TCC_HIT[18])) + (TCC_MISS[19] + TCC_HIT[19])) + (TCC_MISS[20] + + TCC_HIT[20])) + (TCC_MISS[21] + TCC_HIT[21])) + (TCC_MISS[22] + TCC_HIT[22])) + + (TCC_MISS[23] + TCC_HIT[23])) + (TCC_MISS[24] + TCC_HIT[24])) + (TCC_MISS[25] + + TCC_HIT[25])) + (TCC_MISS[26] + TCC_HIT[26])) + (TCC_MISS[27] + TCC_HIT[27])) + + (TCC_MISS[28] + TCC_HIT[28])) + (TCC_MISS[28] + TCC_HIT[29])) + (TCC_MISS[30] + + TCC_HIT[30])) + (TCC_MISS[31] + TCC_HIT[31])) != 0) else None)) + unit: pct + tips: + Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) + + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) + + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) + + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) + + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) + + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) + + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) + + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) + + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) + + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) + + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) + + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) + + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) + + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) + + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) + + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) + + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) + + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) + + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) + + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) + + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) + + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) + + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) + + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) + + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_REQ[0]) + TO_INT(TCC_REQ[1])) + + TO_INT(TCC_REQ[2])) + TO_INT(TCC_REQ[3])) + TO_INT(TCC_REQ[4])) + TO_INT(TCC_REQ[5])) + + TO_INT(TCC_REQ[6])) + TO_INT(TCC_REQ[7])) + TO_INT(TCC_REQ[8])) + TO_INT(TCC_REQ[9])) + + TO_INT(TCC_REQ[10])) + TO_INT(TCC_REQ[11])) + TO_INT(TCC_REQ[12])) + TO_INT(TCC_REQ[13])) + + TO_INT(TCC_REQ[14])) + TO_INT(TCC_REQ[15])) + TO_INT(TCC_REQ[16])) + TO_INT(TCC_REQ[17])) + + TO_INT(TCC_REQ[18])) + TO_INT(TCC_REQ[19])) + TO_INT(TCC_REQ[20])) + TO_INT(TCC_REQ[21])) + + TO_INT(TCC_REQ[22])) + TO_INT(TCC_REQ[23])) + TO_INT(TCC_REQ[24])) + TO_INT(TCC_REQ[25])) + + TO_INT(TCC_REQ[26])) + TO_INT(TCC_REQ[27])) + TO_INT(TCC_REQ[28])) + TO_INT(TCC_REQ[29])) + + TO_INT(TCC_REQ[30])) + TO_INT(TCC_REQ[31])) / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L1 - L2 Read Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) + + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) + + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) + + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + + TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) + + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + + TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) + + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + + TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) + + TO_INT(TCC_READ[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) + + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) + + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) + + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + + TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) + + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + + TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) + + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + + TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) + + TO_INT(TCC_READ[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) + + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) + + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) + + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + + TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) + + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + + TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) + + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + + TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) + + TO_INT(TCC_READ[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_READ[0]) + TO_INT(TCC_READ[1])) + + TO_INT(TCC_READ[2])) + TO_INT(TCC_READ[3])) + TO_INT(TCC_READ[4])) + TO_INT(TCC_READ[5])) + + TO_INT(TCC_READ[6])) + TO_INT(TCC_READ[7])) + TO_INT(TCC_READ[8])) + TO_INT(TCC_READ[9])) + + TO_INT(TCC_READ[10])) + TO_INT(TCC_READ[11])) + TO_INT(TCC_READ[12])) + + TO_INT(TCC_READ[13])) + TO_INT(TCC_READ[14])) + TO_INT(TCC_READ[15])) + TO_INT(TCC_READ[16])) + + TO_INT(TCC_READ[17])) + TO_INT(TCC_READ[18])) + TO_INT(TCC_READ[19])) + + TO_INT(TCC_READ[20])) + TO_INT(TCC_READ[21])) + TO_INT(TCC_READ[22])) + TO_INT(TCC_READ[23])) + + TO_INT(TCC_READ[24])) + TO_INT(TCC_READ[25])) + TO_INT(TCC_READ[26])) + + TO_INT(TCC_READ[27])) + TO_INT(TCC_READ[28])) + TO_INT(TCC_READ[29])) + TO_INT(TCC_READ[30])) + + TO_INT(TCC_READ[31])) / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L1 - L2 Write Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) + + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + + TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) + + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) + + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) + + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) + + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) + + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) + + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) + + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) + + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) + + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + + TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) + + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) + + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) + + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) + + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) + + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) + + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) + + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) + + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) + + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + + TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) + + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) + + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) + + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) + + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) + + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) + + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) + + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) + + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_WRITE[0]) + TO_INT(TCC_WRITE[1])) + + TO_INT(TCC_WRITE[2])) + TO_INT(TCC_WRITE[3])) + TO_INT(TCC_WRITE[4])) + + TO_INT(TCC_WRITE[5])) + TO_INT(TCC_WRITE[6])) + TO_INT(TCC_WRITE[7])) + TO_INT(TCC_WRITE[8])) + + TO_INT(TCC_WRITE[9])) + TO_INT(TCC_WRITE[10])) + TO_INT(TCC_WRITE[11])) + + TO_INT(TCC_WRITE[12])) + TO_INT(TCC_WRITE[13])) + TO_INT(TCC_WRITE[14])) + + TO_INT(TCC_WRITE[15])) + TO_INT(TCC_WRITE[16])) + TO_INT(TCC_WRITE[17])) + + TO_INT(TCC_WRITE[18])) + TO_INT(TCC_WRITE[19])) + TO_INT(TCC_WRITE[20])) + + TO_INT(TCC_WRITE[21])) + TO_INT(TCC_WRITE[22])) + TO_INT(TCC_WRITE[23])) + + TO_INT(TCC_WRITE[24])) + TO_INT(TCC_WRITE[25])) + TO_INT(TCC_WRITE[26])) + + TO_INT(TCC_WRITE[27])) + TO_INT(TCC_WRITE[28])) + TO_INT(TCC_WRITE[29])) + + TO_INT(TCC_WRITE[30])) + TO_INT(TCC_WRITE[31])) / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L1 - L2 Atomic Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) + + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) + + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) + + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) + + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) + + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) + + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) + + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) + + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) + + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) + + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) + / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) + + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) + + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) + + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) + + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) + + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) + + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) + + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) + + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) + + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) + + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) + / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) + + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) + + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) + + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) + + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) + + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) + + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) + + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) + + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) + + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) + + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) + / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_ATOMIC[0]) + TO_INT(TCC_ATOMIC[1])) + + TO_INT(TCC_ATOMIC[2])) + TO_INT(TCC_ATOMIC[3])) + TO_INT(TCC_ATOMIC[4])) + + TO_INT(TCC_ATOMIC[5])) + TO_INT(TCC_ATOMIC[6])) + TO_INT(TCC_ATOMIC[7])) + + TO_INT(TCC_ATOMIC[8])) + TO_INT(TCC_ATOMIC[9])) + TO_INT(TCC_ATOMIC[10])) + + TO_INT(TCC_ATOMIC[11])) + TO_INT(TCC_ATOMIC[12])) + TO_INT(TCC_ATOMIC[13])) + + TO_INT(TCC_ATOMIC[14])) + TO_INT(TCC_ATOMIC[15])) + TO_INT(TCC_ATOMIC[16])) + + TO_INT(TCC_ATOMIC[17])) + TO_INT(TCC_ATOMIC[18])) + TO_INT(TCC_ATOMIC[19])) + + TO_INT(TCC_ATOMIC[20])) + TO_INT(TCC_ATOMIC[21])) + TO_INT(TCC_ATOMIC[22])) + + TO_INT(TCC_ATOMIC[23])) + TO_INT(TCC_ATOMIC[24])) + TO_INT(TCC_ATOMIC[25])) + + TO_INT(TCC_ATOMIC[26])) + TO_INT(TCC_ATOMIC[27])) + TO_INT(TCC_ATOMIC[28])) + + TO_INT(TCC_ATOMIC[29])) + TO_INT(TCC_ATOMIC[30])) + TO_INT(TCC_ATOMIC[31])) + / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L2 - EA Read Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) + + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) + + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) + + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) + + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) + + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) + + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) + + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) + + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) + + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) + + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) + / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) + + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) + + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) + + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) + + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) + + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) + + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) + + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) + + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) + + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) + + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) + / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) + + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) + + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) + + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) + + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) + + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) + + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) + + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) + + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) + + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) + + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) + / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ[0]) + TO_INT(TCC_EA_RDREQ[1])) + + TO_INT(TCC_EA_RDREQ[2])) + TO_INT(TCC_EA_RDREQ[3])) + TO_INT(TCC_EA_RDREQ[4])) + + TO_INT(TCC_EA_RDREQ[5])) + TO_INT(TCC_EA_RDREQ[6])) + TO_INT(TCC_EA_RDREQ[7])) + + TO_INT(TCC_EA_RDREQ[8])) + TO_INT(TCC_EA_RDREQ[9])) + TO_INT(TCC_EA_RDREQ[10])) + + TO_INT(TCC_EA_RDREQ[11])) + TO_INT(TCC_EA_RDREQ[12])) + TO_INT(TCC_EA_RDREQ[13])) + + TO_INT(TCC_EA_RDREQ[14])) + TO_INT(TCC_EA_RDREQ[15])) + TO_INT(TCC_EA_RDREQ[16])) + + TO_INT(TCC_EA_RDREQ[17])) + TO_INT(TCC_EA_RDREQ[18])) + TO_INT(TCC_EA_RDREQ[19])) + + TO_INT(TCC_EA_RDREQ[20])) + TO_INT(TCC_EA_RDREQ[21])) + TO_INT(TCC_EA_RDREQ[22])) + + TO_INT(TCC_EA_RDREQ[23])) + TO_INT(TCC_EA_RDREQ[24])) + TO_INT(TCC_EA_RDREQ[25])) + + TO_INT(TCC_EA_RDREQ[26])) + TO_INT(TCC_EA_RDREQ[27])) + TO_INT(TCC_EA_RDREQ[28])) + + TO_INT(TCC_EA_RDREQ[29])) + TO_INT(TCC_EA_RDREQ[30])) + TO_INT(TCC_EA_RDREQ[31])) + / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L2 - EA Write Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) + + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) + + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) + + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) + + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) + + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) + + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) + + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) + + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) + + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) + + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) + / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) + + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) + + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) + + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) + + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) + + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) + + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) + + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) + + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) + + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) + + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) + / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) + + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) + + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) + + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) + + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) + + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) + + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) + + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) + + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) + + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) + + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) + / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ[0]) + TO_INT(TCC_EA_WRREQ[1])) + + TO_INT(TCC_EA_WRREQ[2])) + TO_INT(TCC_EA_WRREQ[3])) + TO_INT(TCC_EA_WRREQ[4])) + + TO_INT(TCC_EA_WRREQ[5])) + TO_INT(TCC_EA_WRREQ[6])) + TO_INT(TCC_EA_WRREQ[7])) + + TO_INT(TCC_EA_WRREQ[8])) + TO_INT(TCC_EA_WRREQ[9])) + TO_INT(TCC_EA_WRREQ[10])) + + TO_INT(TCC_EA_WRREQ[11])) + TO_INT(TCC_EA_WRREQ[12])) + TO_INT(TCC_EA_WRREQ[13])) + + TO_INT(TCC_EA_WRREQ[14])) + TO_INT(TCC_EA_WRREQ[15])) + TO_INT(TCC_EA_WRREQ[16])) + + TO_INT(TCC_EA_WRREQ[17])) + TO_INT(TCC_EA_WRREQ[18])) + TO_INT(TCC_EA_WRREQ[19])) + + TO_INT(TCC_EA_WRREQ[20])) + TO_INT(TCC_EA_WRREQ[21])) + TO_INT(TCC_EA_WRREQ[22])) + + TO_INT(TCC_EA_WRREQ[23])) + TO_INT(TCC_EA_WRREQ[24])) + TO_INT(TCC_EA_WRREQ[25])) + + TO_INT(TCC_EA_WRREQ[26])) + TO_INT(TCC_EA_WRREQ[27])) + TO_INT(TCC_EA_WRREQ[28])) + + TO_INT(TCC_EA_WRREQ[29])) + TO_INT(TCC_EA_WRREQ[30])) + TO_INT(TCC_EA_WRREQ[31])) + / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L2 - EA Atomic Req: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) + + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) + + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) + + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) + + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) + + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) + + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) + + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) + + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) + + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) + + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) + / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) + + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) + + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) + + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) + + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) + + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) + + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) + + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) + + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) + + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) + + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) + / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) + + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) + + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) + + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) + + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) + + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) + + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) + + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) + + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) + + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) + + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) + / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_ATOMIC[0]) + TO_INT(TCC_EA_ATOMIC[1])) + + TO_INT(TCC_EA_ATOMIC[2])) + TO_INT(TCC_EA_ATOMIC[3])) + TO_INT(TCC_EA_ATOMIC[4])) + + TO_INT(TCC_EA_ATOMIC[5])) + TO_INT(TCC_EA_ATOMIC[6])) + TO_INT(TCC_EA_ATOMIC[7])) + + TO_INT(TCC_EA_ATOMIC[8])) + TO_INT(TCC_EA_ATOMIC[9])) + TO_INT(TCC_EA_ATOMIC[10])) + + TO_INT(TCC_EA_ATOMIC[11])) + TO_INT(TCC_EA_ATOMIC[12])) + TO_INT(TCC_EA_ATOMIC[13])) + + TO_INT(TCC_EA_ATOMIC[14])) + TO_INT(TCC_EA_ATOMIC[15])) + TO_INT(TCC_EA_ATOMIC[16])) + + TO_INT(TCC_EA_ATOMIC[17])) + TO_INT(TCC_EA_ATOMIC[18])) + TO_INT(TCC_EA_ATOMIC[19])) + + TO_INT(TCC_EA_ATOMIC[20])) + TO_INT(TCC_EA_ATOMIC[21])) + TO_INT(TCC_EA_ATOMIC[22])) + + TO_INT(TCC_EA_ATOMIC[23])) + TO_INT(TCC_EA_ATOMIC[24])) + TO_INT(TCC_EA_ATOMIC[25])) + + TO_INT(TCC_EA_ATOMIC[26])) + TO_INT(TCC_EA_ATOMIC[27])) + TO_INT(TCC_EA_ATOMIC[28])) + + TO_INT(TCC_EA_ATOMIC[29])) + TO_INT(TCC_EA_ATOMIC[30])) + TO_INT(TCC_EA_ATOMIC[31])) + / 32) / $denom)) + unit: (Req + $normUnit) + tips: + L2 - EA Read Lat: + avg: AVG((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) + + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) + + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) + + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) + + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) + + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) + + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) + + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) + + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) + + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) + + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) + std dev: STD((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) + + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) + + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) + + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) + + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) + + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) + + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) + + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) + + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) + + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) + + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) + min: MIN((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) + + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) + + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) + + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) + + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) + + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) + + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) + + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) + + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) + + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) + + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) + max: MAX((((((((((((((((((((((((((((((((((TCC_EA_RDREQ_LEVEL[0] + TCC_EA_RDREQ_LEVEL[1]) + + TCC_EA_RDREQ_LEVEL[2]) + TCC_EA_RDREQ_LEVEL[3]) + TCC_EA_RDREQ_LEVEL[4]) + + TCC_EA_RDREQ_LEVEL[5]) + TCC_EA_RDREQ_LEVEL[6]) + TCC_EA_RDREQ_LEVEL[7]) + + TCC_EA_RDREQ_LEVEL[8]) + TCC_EA_RDREQ_LEVEL[9]) + TCC_EA_RDREQ_LEVEL[10]) + + TCC_EA_RDREQ_LEVEL[11]) + TCC_EA_RDREQ_LEVEL[12]) + TCC_EA_RDREQ_LEVEL[13]) + + TCC_EA_RDREQ_LEVEL[14]) + TCC_EA_RDREQ_LEVEL[15]) + TCC_EA_RDREQ_LEVEL[16]) + + TCC_EA_RDREQ_LEVEL[17]) + TCC_EA_RDREQ_LEVEL[18]) + TCC_EA_RDREQ_LEVEL[19]) + + TCC_EA_RDREQ_LEVEL[20]) + TCC_EA_RDREQ_LEVEL[21]) + TCC_EA_RDREQ_LEVEL[22]) + + TCC_EA_RDREQ_LEVEL[23]) + TCC_EA_RDREQ_LEVEL[24]) + TCC_EA_RDREQ_LEVEL[25]) + + TCC_EA_RDREQ_LEVEL[26]) + TCC_EA_RDREQ_LEVEL[27]) + TCC_EA_RDREQ_LEVEL[28]) + + TCC_EA_RDREQ_LEVEL[29]) + TCC_EA_RDREQ_LEVEL[30]) + TCC_EA_RDREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + + TCC_EA_RDREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_RDREQ[0] + + TCC_EA_RDREQ[1]) + TCC_EA_RDREQ[2]) + TCC_EA_RDREQ[3]) + TCC_EA_RDREQ[4]) + + TCC_EA_RDREQ[5]) + TCC_EA_RDREQ[6]) + TCC_EA_RDREQ[7]) + TCC_EA_RDREQ[8]) + + TCC_EA_RDREQ[9]) + TCC_EA_RDREQ[10]) + TCC_EA_RDREQ[11]) + TCC_EA_RDREQ[12]) + + TCC_EA_RDREQ[13]) + TCC_EA_RDREQ[14]) + TCC_EA_RDREQ[15]) + TCC_EA_RDREQ[16]) + + TCC_EA_RDREQ[17]) + TCC_EA_RDREQ[18]) + TCC_EA_RDREQ[19]) + TCC_EA_RDREQ[20]) + + TCC_EA_RDREQ[21]) + TCC_EA_RDREQ[22]) + TCC_EA_RDREQ[23]) + TCC_EA_RDREQ[24]) + + TCC_EA_RDREQ[25]) + TCC_EA_RDREQ[26]) + TCC_EA_RDREQ[27]) + TCC_EA_RDREQ[28]) + + TCC_EA_RDREQ[29]) + TCC_EA_RDREQ[30]) + TCC_EA_RDREQ[31]) != 0) else None)) + unit: Cycles + tips: + L2 - EA Write Lat: + avg: AVG((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) + + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) + + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) + + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) + + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) + + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) + + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) + + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) + + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) + + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) + + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) + std dev: STD((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) + + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) + + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) + + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) + + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) + + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) + + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) + + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) + + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) + + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) + + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) + min: MIN((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) + + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) + + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) + + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) + + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) + + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) + + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) + + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) + + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) + + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) + + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) + max: MAX((((((((((((((((((((((((((((((((((TCC_EA_WRREQ_LEVEL[0] + TCC_EA_WRREQ_LEVEL[1]) + + TCC_EA_WRREQ_LEVEL[2]) + TCC_EA_WRREQ_LEVEL[3]) + TCC_EA_WRREQ_LEVEL[4]) + + TCC_EA_WRREQ_LEVEL[5]) + TCC_EA_WRREQ_LEVEL[6]) + TCC_EA_WRREQ_LEVEL[7]) + + TCC_EA_WRREQ_LEVEL[8]) + TCC_EA_WRREQ_LEVEL[9]) + TCC_EA_WRREQ_LEVEL[10]) + + TCC_EA_WRREQ_LEVEL[11]) + TCC_EA_WRREQ_LEVEL[12]) + TCC_EA_WRREQ_LEVEL[13]) + + TCC_EA_WRREQ_LEVEL[14]) + TCC_EA_WRREQ_LEVEL[15]) + TCC_EA_WRREQ_LEVEL[16]) + + TCC_EA_WRREQ_LEVEL[17]) + TCC_EA_WRREQ_LEVEL[18]) + TCC_EA_WRREQ_LEVEL[19]) + + TCC_EA_WRREQ_LEVEL[20]) + TCC_EA_WRREQ_LEVEL[21]) + TCC_EA_WRREQ_LEVEL[22]) + + TCC_EA_WRREQ_LEVEL[23]) + TCC_EA_WRREQ_LEVEL[24]) + TCC_EA_WRREQ_LEVEL[25]) + + TCC_EA_WRREQ_LEVEL[26]) + TCC_EA_WRREQ_LEVEL[27]) + TCC_EA_WRREQ_LEVEL[28]) + + TCC_EA_WRREQ_LEVEL[29]) + TCC_EA_WRREQ_LEVEL[30]) + TCC_EA_WRREQ_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + + TCC_EA_WRREQ[31])) if ((((((((((((((((((((((((((((((((TCC_EA_WRREQ[0] + + TCC_EA_WRREQ[1]) + TCC_EA_WRREQ[2]) + TCC_EA_WRREQ[3]) + TCC_EA_WRREQ[4]) + + TCC_EA_WRREQ[5]) + TCC_EA_WRREQ[6]) + TCC_EA_WRREQ[7]) + TCC_EA_WRREQ[8]) + + TCC_EA_WRREQ[9]) + TCC_EA_WRREQ[10]) + TCC_EA_WRREQ[11]) + TCC_EA_WRREQ[12]) + + TCC_EA_WRREQ[13]) + TCC_EA_WRREQ[14]) + TCC_EA_WRREQ[15]) + TCC_EA_WRREQ[16]) + + TCC_EA_WRREQ[17]) + TCC_EA_WRREQ[18]) + TCC_EA_WRREQ[19]) + TCC_EA_WRREQ[20]) + + TCC_EA_WRREQ[21]) + TCC_EA_WRREQ[22]) + TCC_EA_WRREQ[23]) + TCC_EA_WRREQ[24]) + + TCC_EA_WRREQ[25]) + TCC_EA_WRREQ[26]) + TCC_EA_WRREQ[27]) + TCC_EA_WRREQ[28]) + + TCC_EA_WRREQ[29]) + TCC_EA_WRREQ[30]) + TCC_EA_WRREQ[31]) != 0) else None)) + unit: Cycles + tips: + L2 - EA Atomic Lat: + avg: AVG((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) + + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) + + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) + + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) + + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) + + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) + + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) + + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) + + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) + + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) + + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else + None)) + std dev: STD((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) + + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) + + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) + + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) + + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) + + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) + + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) + + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) + + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) + + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) + + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else + None)) + min: MIN((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) + + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) + + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) + + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) + + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) + + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) + + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) + + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) + + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) + + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) + + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else + None)) + max: MAX((((((((((((((((((((((((((((((((((TCC_EA_ATOMIC_LEVEL[0] + TCC_EA_ATOMIC_LEVEL[1]) + + TCC_EA_ATOMIC_LEVEL[2]) + TCC_EA_ATOMIC_LEVEL[3]) + TCC_EA_ATOMIC_LEVEL[4]) + + TCC_EA_ATOMIC_LEVEL[5]) + TCC_EA_ATOMIC_LEVEL[6]) + TCC_EA_ATOMIC_LEVEL[7]) + + TCC_EA_ATOMIC_LEVEL[8]) + TCC_EA_ATOMIC_LEVEL[9]) + TCC_EA_ATOMIC_LEVEL[10]) + + TCC_EA_ATOMIC_LEVEL[11]) + TCC_EA_ATOMIC_LEVEL[12]) + TCC_EA_ATOMIC_LEVEL[13]) + + TCC_EA_ATOMIC_LEVEL[14]) + TCC_EA_ATOMIC_LEVEL[15]) + TCC_EA_ATOMIC_LEVEL[16]) + + TCC_EA_ATOMIC_LEVEL[17]) + TCC_EA_ATOMIC_LEVEL[18]) + TCC_EA_ATOMIC_LEVEL[19]) + + TCC_EA_ATOMIC_LEVEL[20]) + TCC_EA_ATOMIC_LEVEL[21]) + TCC_EA_ATOMIC_LEVEL[22]) + + TCC_EA_ATOMIC_LEVEL[23]) + TCC_EA_ATOMIC_LEVEL[24]) + TCC_EA_ATOMIC_LEVEL[25]) + + TCC_EA_ATOMIC_LEVEL[26]) + TCC_EA_ATOMIC_LEVEL[27]) + TCC_EA_ATOMIC_LEVEL[28]) + + TCC_EA_ATOMIC_LEVEL[29]) + TCC_EA_ATOMIC_LEVEL[30]) + TCC_EA_ATOMIC_LEVEL[31]) + / (((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + + TCC_EA_ATOMIC[31])) if ((((((((((((((((((((((((((((((((TCC_EA_ATOMIC[0] + + TCC_EA_ATOMIC[1]) + TCC_EA_ATOMIC[2]) + TCC_EA_ATOMIC[3]) + TCC_EA_ATOMIC[4]) + + TCC_EA_ATOMIC[5]) + TCC_EA_ATOMIC[6]) + TCC_EA_ATOMIC[7]) + TCC_EA_ATOMIC[8]) + + TCC_EA_ATOMIC[9]) + TCC_EA_ATOMIC[10]) + TCC_EA_ATOMIC[11]) + TCC_EA_ATOMIC[12]) + + TCC_EA_ATOMIC[13]) + TCC_EA_ATOMIC[14]) + TCC_EA_ATOMIC[15]) + TCC_EA_ATOMIC[16]) + + TCC_EA_ATOMIC[17]) + TCC_EA_ATOMIC[18]) + TCC_EA_ATOMIC[19]) + TCC_EA_ATOMIC[20]) + + TCC_EA_ATOMIC[21]) + TCC_EA_ATOMIC[22]) + TCC_EA_ATOMIC[23]) + TCC_EA_ATOMIC[24]) + + TCC_EA_ATOMIC[25]) + TCC_EA_ATOMIC[26]) + TCC_EA_ATOMIC[27]) + TCC_EA_ATOMIC[28]) + + TCC_EA_ATOMIC[29]) + TCC_EA_ATOMIC[30]) + TCC_EA_ATOMIC[31]) != 0) else + None)) + unit: Cycles + tips: + L2 - EA Read Stall (IO): + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + unit: (Cycles + $normUnit) + tips: + L2 - EA Read Stall (GMI): + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + unit: (Cycles + $normUnit) + tips: + L2 - EA Read Stall (DRAM): + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + unit: (Cycles + $normUnit) + tips: + L2 - EA Write Stall (IO): + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31])) / 32) / $denom)) + unit: (Cycles + $normUnit) + tips: + L2 - EA Write Stall (GMI): + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31])) / 32) / $denom)) + unit: (Cycles + $normUnit) + tips: + L2 - EA Write Stall (DRAM): + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29])) + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30])) + + TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31])) / 32) / $denom)) + unit: (Cycles + $normUnit) + tips: + L2 - EA Write Starve: + avg: AVG((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) + std dev: STD((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) + min: MIN((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) + max: MAX((((((((((((((((((((((((((((((((((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29])) + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30])) + + TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31])) / 32) / $denom)) + unit: (Cycles + $normUnit) + tips: + - metric_table: + id: 1802 + title: Channel 0-15 + columnwise: True + header: + channel: Channel + hit rate: L2 Cache Hit Rate (%) + req: Requests (Requests) + read req: L1-L2 Read (Requests) + write req: L1-L2 Write (Requests) + atomic req: L1-L2 Atomic (Requests) + ea read req: L2-EA Read (Requests) + ea write req: L2-EA Write (Requests) + ea atomic req: L2-EA Atomic (Requests) + ea read lat - cycles: L2-EA Read Latency (Cycles) + ea write lat - cycles: L2-EA Write Latency (Cycles) + ea atomic lat - cycles: L2-EA Atomic Latency (Cycles) + ea read stall - io: L2-EA Read Stall - IO (Cycles per) + ea read stall - gmi: L2-EA Read Stall - GMI (Cycles per) + ea read stall - dram: L2-EA Read Stall - DRAM (Cycles per) + ea write stall - io: L2-EA Write Stall - IO (Cycles per) + ea write stall - gmi: L2-EA Write Stall - GMI (Cycles per) + ea write stall - dram: L2-EA Write Stall - DRAM (Cycles per) + ea write stall - starve: L2-EA Write Stall - Starve (Cycles per) + tips: Tips + metric: + '0': + hit rate: AVG((((100 * TCC_HIT[0]) / (TCC_HIT[0] + TCC_MISS[0])) if ((TCC_HIT[0] + + TCC_MISS[0]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[0]) / $denom)) + read req: AVG((TO_INT(TCC_READ[0]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[0]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[0]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[0]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[0]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[0]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[0] / TCC_EA_RDREQ[0]) if (TCC_EA_RDREQ[0] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[0] / TCC_EA_WRREQ[0]) if (TCC_EA_WRREQ[0] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[0] / TCC_EA_ATOMIC[0]) if + (TCC_EA_ATOMIC[0] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[0]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[0]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[0]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[0]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[0]) / $denom)) + tips: + '1': + hit rate: AVG((((100 * TCC_HIT[1]) / (TCC_HIT[1] + TCC_MISS[1])) if ((TCC_HIT[1] + + TCC_MISS[1]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[1]) / $denom)) + read req: AVG((TO_INT(TCC_READ[1]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[1]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[1]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[1]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[1]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[1]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[1] / TCC_EA_RDREQ[1]) if (TCC_EA_RDREQ[1] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[1] / TCC_EA_WRREQ[1]) if (TCC_EA_WRREQ[1] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[1] / TCC_EA_ATOMIC[1]) if + (TCC_EA_ATOMIC[1] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[1]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[1]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[1]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[1]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[1]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[1]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[1]) / $denom)) + tips: + '2': + hit rate: AVG((((100 * TCC_HIT[2]) / (TCC_HIT[2] + TCC_MISS[2])) if ((TCC_HIT[2] + + TCC_MISS[2]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[2]) / $denom)) + read req: AVG((TO_INT(TCC_READ[2]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[2]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[2]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[2]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[2]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[2]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[2] / TCC_EA_RDREQ[2]) if (TCC_EA_RDREQ[2] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[2] / TCC_EA_WRREQ[2]) if (TCC_EA_WRREQ[2] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[2] / TCC_EA_ATOMIC[2]) if + (TCC_EA_ATOMIC[2] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[2]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[2]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[2]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[2]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[2]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[2]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[2]) / $denom)) + tips: + '3': + hit rate: AVG((((100 * TCC_HIT[3]) / (TCC_HIT[3] + TCC_MISS[3])) if ((TCC_HIT[3] + + TCC_MISS[3]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[3]) / $denom)) + read req: AVG((TO_INT(TCC_READ[3]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[3]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[3]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[3]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[3]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[3]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[3] / TCC_EA_RDREQ[3]) if (TCC_EA_RDREQ[3] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[3] / TCC_EA_WRREQ[3]) if (TCC_EA_WRREQ[3] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[3] / TCC_EA_ATOMIC[3]) if + (TCC_EA_ATOMIC[3] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[3]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[3]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[3]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[3]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[3]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[3]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[3]) / $denom)) + tips: + '4': + hit rate: AVG((((100 * TCC_HIT[4]) / (TCC_HIT[4] + TCC_MISS[4])) if ((TCC_HIT[4] + + TCC_MISS[4]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[4]) / $denom)) + read req: AVG((TO_INT(TCC_READ[4]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[4]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[4]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[4]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[4]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[4]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[4] / TCC_EA_RDREQ[4]) if (TCC_EA_RDREQ[4] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[4] / TCC_EA_WRREQ[4]) if (TCC_EA_WRREQ[4] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[4] / TCC_EA_ATOMIC[4]) if + (TCC_EA_ATOMIC[4] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[4]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[4]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[4]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[4]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[4]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[4]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[4]) / $denom)) + tips: + '5': + hit rate: AVG((((100 * TCC_HIT[5]) / (TCC_HIT[5] + TCC_MISS[5])) if ((TCC_HIT[5] + + TCC_MISS[5]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[5]) / $denom)) + read req: AVG((TO_INT(TCC_READ[5]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[5]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[5]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[5]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[5]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[5]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[5] / TCC_EA_RDREQ[5]) if (TCC_EA_RDREQ[5] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[5] / TCC_EA_WRREQ[5]) if (TCC_EA_WRREQ[5] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[5] / TCC_EA_ATOMIC[5]) if + (TCC_EA_ATOMIC[5] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[5]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[5]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[5]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[5]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[5]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[5]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[5]) / $denom)) + tips: + '6': + hit rate: AVG((((100 * TCC_HIT[6]) / (TCC_HIT[6] + TCC_MISS[6])) if ((TCC_HIT[6] + + TCC_MISS[6]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[6]) / $denom)) + read req: AVG((TO_INT(TCC_READ[6]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[6]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[6]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[6]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[6]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[6]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[6] / TCC_EA_RDREQ[6]) if (TCC_EA_RDREQ[6] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[6] / TCC_EA_WRREQ[6]) if (TCC_EA_WRREQ[6] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[6] / TCC_EA_ATOMIC[6]) if + (TCC_EA_ATOMIC[6] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[6]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[6]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[6]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[6]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[6]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[6]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[6]) / $denom)) + tips: + '7': + hit rate: AVG((((100 * TCC_HIT[7]) / (TCC_HIT[7] + TCC_MISS[7])) if ((TCC_HIT[7] + + TCC_MISS[7]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[7]) / $denom)) + read req: AVG((TO_INT(TCC_READ[7]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[7]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[7]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[7]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[7]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[7]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[7] / TCC_EA_RDREQ[7]) if (TCC_EA_RDREQ[7] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[7] / TCC_EA_WRREQ[7]) if (TCC_EA_WRREQ[7] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[7] / TCC_EA_ATOMIC[7]) if + (TCC_EA_ATOMIC[7] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[7]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[7]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[7]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[7]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[7]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[7]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[7]) / $denom)) + tips: + '8': + hit rate: AVG((((100 * TCC_HIT[8]) / (TCC_HIT[8] + TCC_MISS[8])) if ((TCC_HIT[8] + + TCC_MISS[8]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[8]) / $denom)) + read req: AVG((TO_INT(TCC_READ[8]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[8]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[8]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[8]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[8]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[8]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[8] / TCC_EA_RDREQ[8]) if (TCC_EA_RDREQ[8] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[8] / TCC_EA_WRREQ[8]) if (TCC_EA_WRREQ[8] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[8] / TCC_EA_ATOMIC[8]) if + (TCC_EA_ATOMIC[8] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[8]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[8]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[8]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[8]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[8]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[8]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[8]) / $denom)) + tips: + '9': + hit rate: AVG((((100 * TCC_HIT[9]) / (TCC_HIT[9] + TCC_MISS[9])) if ((TCC_HIT[9] + + TCC_MISS[9]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[9]) / $denom)) + read req: AVG((TO_INT(TCC_READ[9]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[9]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[9]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[9]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[9]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[9]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[9] / TCC_EA_RDREQ[9]) if (TCC_EA_RDREQ[9] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[9] / TCC_EA_WRREQ[9]) if (TCC_EA_WRREQ[9] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[9] / TCC_EA_ATOMIC[9]) if + (TCC_EA_ATOMIC[9] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[9]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[9]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[9]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[9]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[9]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[9]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[9]) / $denom)) + tips: + '10': + hit rate: AVG((((100 * TCC_HIT[10]) / (TCC_HIT[10] + TCC_MISS[10])) if ((TCC_HIT[10] + + TCC_MISS[10]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[10]) / $denom)) + read req: AVG((TO_INT(TCC_READ[10]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[10]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[10]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[10]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[10]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[10]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[10] / TCC_EA_RDREQ[10]) if (TCC_EA_RDREQ[10] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[10] / TCC_EA_WRREQ[10]) if (TCC_EA_WRREQ[10] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[10] / TCC_EA_ATOMIC[10]) if + (TCC_EA_ATOMIC[10] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[10]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[10]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[10]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[10]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[10]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[10]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[10]) / $denom)) + tips: + '11': + hit rate: AVG((((100 * TCC_HIT[11]) / (TCC_HIT[11] + TCC_MISS[11])) if ((TCC_HIT[11] + + TCC_MISS[11]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[11]) / $denom)) + read req: AVG((TO_INT(TCC_READ[11]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[11]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[11]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[11]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[11]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[11]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[11] / TCC_EA_RDREQ[11]) if (TCC_EA_RDREQ[11] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[11] / TCC_EA_WRREQ[11]) if (TCC_EA_WRREQ[11] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[11] / TCC_EA_ATOMIC[11]) if + (TCC_EA_ATOMIC[11] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[11]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[11]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[11]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[11]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[11]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[11]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[11]) / $denom)) + tips: + '12': + hit rate: AVG((((100 * TCC_HIT[12]) / (TCC_HIT[12] + TCC_MISS[12])) if ((TCC_HIT[12] + + TCC_MISS[12]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[12]) / $denom)) + read req: AVG((TO_INT(TCC_READ[12]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[12]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[12]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[12]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[12]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[12]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[12] / TCC_EA_RDREQ[12]) if (TCC_EA_RDREQ[12] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[12] / TCC_EA_WRREQ[12]) if (TCC_EA_WRREQ[12] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[12] / TCC_EA_ATOMIC[12]) if + (TCC_EA_ATOMIC[12] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[12]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[12]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[12]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[12]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[12]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[12]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[12]) / $denom)) + tips: + '13': + hit rate: AVG((((100 * TCC_HIT[13]) / (TCC_HIT[13] + TCC_MISS[13])) if ((TCC_HIT[13] + + TCC_MISS[13]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[13]) / $denom)) + read req: AVG((TO_INT(TCC_READ[13]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[13]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[13]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[13]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[13]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[13]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[13] / TCC_EA_RDREQ[13]) if (TCC_EA_RDREQ[13] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[13] / TCC_EA_WRREQ[13]) if (TCC_EA_WRREQ[13] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[13] / TCC_EA_ATOMIC[13]) if + (TCC_EA_ATOMIC[13] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[13]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[13]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[13]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[13]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[13]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[13]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[13]) / $denom)) + tips: + '14': + hit rate: AVG((((100 * TCC_HIT[14]) / (TCC_HIT[14] + TCC_MISS[14])) if ((TCC_HIT[14] + + TCC_MISS[14]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[14]) / $denom)) + read req: AVG((TO_INT(TCC_READ[14]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[14]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[14]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[14]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[14]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[14]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[14] / TCC_EA_RDREQ[14]) if (TCC_EA_RDREQ[14] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[14] / TCC_EA_WRREQ[14]) if (TCC_EA_WRREQ[14] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[14] / TCC_EA_ATOMIC[14]) if + (TCC_EA_ATOMIC[14] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[14]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[14]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[14]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[14]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[14]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[14]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[14]) / $denom)) + tips: + '15': + hit rate: AVG((((100 * TCC_HIT[15]) / (TCC_HIT[15] + TCC_MISS[15])) if ((TCC_HIT[15] + + TCC_MISS[15]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[15]) / $denom)) + read req: AVG((TO_INT(TCC_READ[15]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[15]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[15]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[15]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[15]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[15]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[15] / TCC_EA_RDREQ[15]) if (TCC_EA_RDREQ[15] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[15] / TCC_EA_WRREQ[15]) if (TCC_EA_WRREQ[15] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[15] / TCC_EA_ATOMIC[15]) if + (TCC_EA_ATOMIC[15] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[15]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[15]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[15]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[15]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[15]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[15]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[15]) / $denom)) + tips: + - metric_table: + id: 1803 + title: Channel 16-31 + columnwise: True + header: + channel: Channel + hit rate: L2 Cache Hit Rate (%) + req: Requests (Requests) + read req: L1-L2 Read (Requests) + write req: L1-L2 Write (Requests) + atomic req: L1-L2 Atomic (Requests) + ea read req: L2-EA Read (Requests) + ea write req: L2-EA Write (Requests) + ea atomic req: L2-EA Atomic (Requests) + ea read lat - cycles: L2-EA Read Latency (Cycles) + ea write lat - cycles: L2-EA Write Latency (Cycles) + ea atomic lat - cycles: L2-EA Atomic Latency (Cycles) + ea read stall - io: L2-EA Read Stall - IO (Cycles per) + ea read stall - gmi: L2-EA Read Stall - GMI (Cycles per) + ea read stall - dram: L2-EA Read Stall - DRAM (Cycles per) + ea write stall - io: L2-EA Write Stall - IO (Cycles per) + ea write stall - gmi: L2-EA Write Stall - GMI (Cycles per) + ea write stall - dram: L2-EA Write Stall - DRAM (Cycles per) + ea write stall - starve: L2-EA Write Stall - Starve (Cycles per) + tips: Tips + metric: + '16': + hit rate: AVG((((100 * TCC_HIT[16]) / (TCC_HIT[16] + TCC_MISS[16])) if ((TCC_HIT[16] + + TCC_MISS[16]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[16]) / $denom)) + read req: AVG((TO_INT(TCC_READ[16]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[16]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[16]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[16]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[16]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[16]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[16] / TCC_EA_RDREQ[16]) if (TCC_EA_RDREQ[16] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[16] / TCC_EA_WRREQ[16]) if (TCC_EA_WRREQ[16] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[16] / TCC_EA_ATOMIC[16]) if + (TCC_EA_ATOMIC[16] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[16]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[16]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[16]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[16]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[16]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[16]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[16]) / $denom)) + tips: + '17': + hit rate: AVG((((100 * TCC_HIT[17]) / (TCC_HIT[17] + TCC_MISS[17])) if ((TCC_HIT[17] + + TCC_MISS[17]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[17]) / $denom)) + read req: AVG((TO_INT(TCC_READ[17]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[17]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[17]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[17]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[17]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[17]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[17] / TCC_EA_RDREQ[17]) if (TCC_EA_RDREQ[17] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[17] / TCC_EA_WRREQ[17]) if (TCC_EA_WRREQ[17] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[17] / TCC_EA_ATOMIC[17]) if + (TCC_EA_ATOMIC[17] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[17]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[17]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[17]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[17]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[17]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[17]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[17]) / $denom)) + tips: + '18': + hit rate: AVG((((100 * TCC_HIT[18]) / (TCC_HIT[18] + TCC_MISS[18])) if ((TCC_HIT[18] + + TCC_MISS[18]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[18]) / $denom)) + read req: AVG((TO_INT(TCC_READ[18]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[18]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[18]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[18]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[18]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[18]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[18] / TCC_EA_RDREQ[18]) if (TCC_EA_RDREQ[18] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[18] / TCC_EA_WRREQ[18]) if (TCC_EA_WRREQ[18] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[18] / TCC_EA_ATOMIC[18]) if + (TCC_EA_ATOMIC[18] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[18]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[18]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[18]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[18]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[18]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[18]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[18]) / $denom)) + tips: + '19': + hit rate: AVG((((100 * TCC_HIT[19]) / (TCC_HIT[19] + TCC_MISS[19])) if ((TCC_HIT[19] + + TCC_MISS[19]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[19]) / $denom)) + read req: AVG((TO_INT(TCC_READ[19]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[19]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[19]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[19]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[19]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[19]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[19] / TCC_EA_RDREQ[19]) if (TCC_EA_RDREQ[19] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[19] / TCC_EA_WRREQ[19]) if (TCC_EA_WRREQ[19] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[19] / TCC_EA_ATOMIC[19]) if + (TCC_EA_ATOMIC[19] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[19]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[19]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[19]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[19]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[19]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[19]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[19]) / $denom)) + tips: + '20': + hit rate: AVG((((100 * TCC_HIT[20]) / (TCC_HIT[20] + TCC_MISS[20])) if ((TCC_HIT[20] + + TCC_MISS[20]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[20]) / $denom)) + read req: AVG((TO_INT(TCC_READ[20]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[20]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[20]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[20]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[20]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[20]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[20] / TCC_EA_RDREQ[20]) if (TCC_EA_RDREQ[20] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[20] / TCC_EA_WRREQ[20]) if (TCC_EA_WRREQ[20] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[20] / TCC_EA_ATOMIC[20]) if + (TCC_EA_ATOMIC[20] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[20]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[20]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[20]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[20]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[20]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[20]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[20]) / $denom)) + tips: + '21': + hit rate: AVG((((100 * TCC_HIT[21]) / (TCC_HIT[21] + TCC_MISS[21])) if ((TCC_HIT[21] + + TCC_MISS[21]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[21]) / $denom)) + read req: AVG((TO_INT(TCC_READ[21]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[21]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[21]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[21]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[21]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[21]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[21] / TCC_EA_RDREQ[21]) if (TCC_EA_RDREQ[21] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[21] / TCC_EA_WRREQ[21]) if (TCC_EA_WRREQ[21] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[21] / TCC_EA_ATOMIC[21]) if + (TCC_EA_ATOMIC[21] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[21]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[21]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[21]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[21]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[21]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[21]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[21]) / $denom)) + tips: + '22': + hit rate: AVG((((100 * TCC_HIT[22]) / (TCC_HIT[22] + TCC_MISS[22])) if ((TCC_HIT[22] + + TCC_MISS[22]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[22]) / $denom)) + read req: AVG((TO_INT(TCC_READ[22]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[22]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[22]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[22]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[22]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[22]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[22] / TCC_EA_RDREQ[22]) if (TCC_EA_RDREQ[22] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[22] / TCC_EA_WRREQ[22]) if (TCC_EA_WRREQ[22] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[22] / TCC_EA_ATOMIC[22]) if + (TCC_EA_ATOMIC[22] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[22]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[22]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[22]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[22]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[22]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[22]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[22]) / $denom)) + tips: + '23': + hit rate: AVG((((100 * TCC_HIT[23]) / (TCC_HIT[23] + TCC_MISS[23])) if ((TCC_HIT[23] + + TCC_MISS[23]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[23]) / $denom)) + read req: AVG((TO_INT(TCC_READ[23]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[23]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[23]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[23]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[23]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[23]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[23] / TCC_EA_RDREQ[23]) if (TCC_EA_RDREQ[23] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[23] / TCC_EA_WRREQ[23]) if (TCC_EA_WRREQ[23] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[23] / TCC_EA_ATOMIC[23]) if + (TCC_EA_ATOMIC[23] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[23]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[23]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[23]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[23]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[23]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[23]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[23]) / $denom)) + tips: + '24': + hit rate: AVG((((100 * TCC_HIT[24]) / (TCC_HIT[24] + TCC_MISS[24])) if ((TCC_HIT[24] + + TCC_MISS[24]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[24]) / $denom)) + read req: AVG((TO_INT(TCC_READ[24]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[24]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[24]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[24]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[24]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[24]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[24] / TCC_EA_RDREQ[24]) if (TCC_EA_RDREQ[24] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[24] / TCC_EA_WRREQ[24]) if (TCC_EA_WRREQ[24] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[24] / TCC_EA_ATOMIC[24]) if + (TCC_EA_ATOMIC[24] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[24]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[24]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[24]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[24]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[24]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[24]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[24]) / $denom)) + tips: + '25': + hit rate: AVG((((100 * TCC_HIT[25]) / (TCC_HIT[25] + TCC_MISS[25])) if ((TCC_HIT[25] + + TCC_MISS[25]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[25]) / $denom)) + read req: AVG((TO_INT(TCC_READ[25]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[25]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[25]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[25]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[25]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[25]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[25] / TCC_EA_RDREQ[25]) if (TCC_EA_RDREQ[25] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[25] / TCC_EA_WRREQ[25]) if (TCC_EA_WRREQ[25] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[25] / TCC_EA_ATOMIC[25]) if + (TCC_EA_ATOMIC[25] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[25]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[25]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[25]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[25]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[25]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[25]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[25]) / $denom)) + tips: + '26': + hit rate: AVG((((100 * TCC_HIT[26]) / (TCC_HIT[26] + TCC_MISS[26])) if ((TCC_HIT[26] + + TCC_MISS[26]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[26]) / $denom)) + read req: AVG((TO_INT(TCC_READ[26]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[26]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[26]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[26]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[26]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[26]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[26] / TCC_EA_RDREQ[26]) if (TCC_EA_RDREQ[26] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[26] / TCC_EA_WRREQ[26]) if (TCC_EA_WRREQ[26] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[26] / TCC_EA_ATOMIC[26]) if + (TCC_EA_ATOMIC[26] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[26]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[26]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[26]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[26]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[26]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[26]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[26]) / $denom)) + tips: + '27': + hit rate: AVG((((100 * TCC_HIT[27]) / (TCC_HIT[27] + TCC_MISS[27])) if ((TCC_HIT[27] + + TCC_MISS[27]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[27]) / $denom)) + read req: AVG((TO_INT(TCC_READ[27]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[27]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[27]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[27]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[27]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[27]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[27] / TCC_EA_RDREQ[27]) if (TCC_EA_RDREQ[27] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[27] / TCC_EA_WRREQ[27]) if (TCC_EA_WRREQ[27] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[27] / TCC_EA_ATOMIC[27]) if + (TCC_EA_ATOMIC[27] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[27]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[27]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[27]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[27]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[27]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[27]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[27]) / $denom)) + tips: + '28': + hit rate: AVG((((100 * TCC_HIT[28]) / (TCC_HIT[28] + TCC_MISS[28])) if ((TCC_HIT[28] + + TCC_MISS[28]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[28]) / $denom)) + read req: AVG((TO_INT(TCC_READ[28]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[28]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[28]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[28]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[28]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[28]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[28] / TCC_EA_RDREQ[28]) if (TCC_EA_RDREQ[28] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[28] / TCC_EA_WRREQ[28]) if (TCC_EA_WRREQ[28] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[28] / TCC_EA_ATOMIC[28]) if + (TCC_EA_ATOMIC[28] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[28]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[28]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[28]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[28]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[28]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[28]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[28]) / $denom)) + tips: + '29': + hit rate: AVG((((100 * TCC_HIT[29]) / (TCC_HIT[29] + TCC_MISS[29])) if ((TCC_HIT[29] + + TCC_MISS[29]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[29]) / $denom)) + read req: AVG((TO_INT(TCC_READ[29]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[29]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[29]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[29]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[29]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[29]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[29] / TCC_EA_RDREQ[29]) if (TCC_EA_RDREQ[29] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[29] / TCC_EA_WRREQ[29]) if (TCC_EA_WRREQ[29] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[29] / TCC_EA_ATOMIC[29]) if + (TCC_EA_ATOMIC[29] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[29]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[29]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[29]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[29]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[29]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[29]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[29]) / $denom)) + tips: + '30': + hit rate: AVG((((100 * TCC_HIT[30]) / (TCC_HIT[30] + TCC_MISS[30])) if ((TCC_HIT[30] + + TCC_MISS[30]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[30]) / $denom)) + read req: AVG((TO_INT(TCC_READ[30]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[30]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[30]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[30]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[30]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[30]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[30] / TCC_EA_RDREQ[30]) if (TCC_EA_RDREQ[30] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[30] / TCC_EA_WRREQ[30]) if (TCC_EA_WRREQ[30] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[30] / TCC_EA_ATOMIC[30]) if + (TCC_EA_ATOMIC[30] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[30]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[30]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[30]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[30]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[30]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[30]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[30]) / $denom)) + tips: + '31': + hit rate: AVG((((100 * TCC_HIT[31]) / (TCC_HIT[31] + TCC_MISS[31])) if ((TCC_HIT[31] + + TCC_MISS[31]) != 0) else None)) + req: AVG((TO_INT(TCC_REQ[31]) / $denom)) + read req: AVG((TO_INT(TCC_READ[31]) / $denom)) + write req: AVG((TO_INT(TCC_WRITE[31]) / $denom)) + atomic req: AVG((TO_INT(TCC_ATOMIC[31]) / $denom)) + ea read req: AVG((TO_INT(TCC_EA_RDREQ[31]) / $denom)) + ea write req: AVG((TO_INT(TCC_EA_WRREQ[31]) / $denom)) + ea atomic req: AVG((TO_INT(TCC_EA_ATOMIC[31]) / $denom)) + ea read lat - cycles: AVG(((TCC_EA_RDREQ_LEVEL[31] / TCC_EA_RDREQ[31]) if (TCC_EA_RDREQ[31] + != 0) else None)) + ea write lat - cycles: AVG(((TCC_EA_WRREQ_LEVEL[31] / TCC_EA_WRREQ[31]) if (TCC_EA_WRREQ[31] + != 0) else None)) + ea atomic lat - cycles: AVG(((TCC_EA_ATOMIC_LEVEL[31] / TCC_EA_ATOMIC[31]) if + (TCC_EA_ATOMIC[31] != 0) else None)) + ea read stall - io: AVG((TO_INT(TCC_EA_RDREQ_IO_CREDIT_STALL[31]) / $denom)) + ea read stall - gmi: AVG((TO_INT(TCC_EA_RDREQ_GMI_CREDIT_STALL[31]) / $denom)) + ea read stall - dram: AVG((TO_INT(TCC_EA_RDREQ_DRAM_CREDIT_STALL[31]) / $denom)) + ea write stall - io: AVG((TO_INT(TCC_EA_WRREQ_IO_CREDIT_STALL[31]) / $denom)) + ea write stall - gmi: AVG((TO_INT(TCC_EA_WRREQ_GMI_CREDIT_STALL[31]) / $denom)) + ea write stall - dram: AVG((TO_INT(TCC_EA_WRREQ_DRAM_CREDIT_STALL[31]) / $denom)) + ea write stall - starve: AVG((TO_INT(TCC_TOO_MANY_EA_WRREQS_STALL[31]) / $denom)) + tips: diff --git a/src/omniperf_soc/configs/gfx90a/1900_memory_chart.yaml b/src/omniperf_soc/configs/gfx90a/1900_memory_chart.yaml new file mode 100644 index 0000000000..c0d086f121 --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/1900_memory_chart.yaml @@ -0,0 +1,259 @@ +--- +# Add description/tips for each metric in this section. +# So it could be shown in hover. +Metric Description: + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 1900 + title: Memory Chart Analysis + data source: + - metric_table: + id: 1901 + title: # subtitle for this table(optional) + header: + metric: Metric + value: Value + alias: Alias + tips: Tips + metric: + Wave Life: + value: ROUND(AVG(((4 * (SQ_WAVE_CYCLES / SQ_WAVES)) if (SQ_WAVES != 0) else + None)), 0) + alias: wave_life_ + tips: + Active CUs: + value: CONCAT(CONCAT($numActiveCUs, "/"), $numCU) + alias: active_cu_ + tips: + SALU: + value: ROUND(AVG((SQ_INSTS_SALU / $denom)), 0) + alias: salu_ + tips: + SMEM: + value: ROUND(AVG((SQ_INSTS_SMEM / $denom)), 0) + alias: smem_ + tips: + VALU: + value: ROUND(AVG((SQ_INSTS_VALU / $denom)), 0) + alias: valu_ + tips: + MFMA: + value: ROUND(AVG((SQ_INSTS_MFMA / $denom)), 0) + alias: mfma_ + tips: + VMEM: + value: ROUND(AVG((SQ_INSTS_VMEM / $denom)), 0) + alias: vmem_ + tips: + LDS: + value: ROUND(AVG((SQ_INSTS_LDS / $denom)), 0) + alias: lds_ + tips: + GWS: + value: ROUND(AVG((SQ_INSTS_GDS / $denom)), 0) + alias: gws_ + tips: + BR: + value: ROUND(AVG((SQ_INSTS_BRANCH / $denom)), 0) + alias: br_ + tips: + VGPR: + value: ROUND(AVG(vgpr), 0) + alias: vgpr_ + tips: + SGPR: + value: ROUND(AVG(sgpr), 0) + alias: sgpr_ + tips: + LDS Allocation: + value: ROUND(AVG(lds), 0) + alias: lds_alloc_ + tips: + Scratch Allocation: + value: ROUND(AVG(scr), 0) + alias: scratch_alloc_ + tips: + Wavefronts: + value: ROUND(AVG(SPI_CSN_WAVE), 0) + alias: wavefronts_ + tips: + Workgroups: + value: ROUND(AVG(SPI_CSN_NUM_THREADGROUPS), 0) + alias: workgroups_ + tips: + LDS Req: + value: ROUND(AVG((SQ_INSTS_LDS / $denom)), 0) + alias: lds_req_ + tips: + IL1 Fetch: + value: ROUND(AVG((SQC_ICACHE_REQ / $denom)), 0) + alias: il1_fetch_ + tips: + IL1 Hit: + value: ROUND((AVG((SQC_ICACHE_HITS / SQC_ICACHE_REQ)) * 100), 0) + alias: il1_hit_ + tips: + IL1_L2 Rd: + value: ROUND(AVG((SQC_TC_INST_REQ / $denom)), 0) + alias: il1_l2_req_ + tips: + vL1D Rd: + value: ROUND(AVG((SQC_DCACHE_REQ / $denom)), 0) + alias: sl1_rd_ + tips: + vL1D Hit: + value: ROUND((AVG(((SQC_DCACHE_HITS / SQC_DCACHE_REQ) if (SQC_DCACHE_REQ != + 0) else None)) * 100), 0) + alias: sl1_hit_ + tips: + vL1D_L2 Rd: + value: ROUND(AVG((SQC_TC_DATA_READ_REQ / $denom)), 0) + alias: sl1_l2_rd_ + tips: + vL1D_L2 Wr: + value: ROUND(AVG((SQC_TC_DATA_WRITE_REQ / $denom)), 0) + alias: sl1_l2_wr_ + tips: + vL1D_L2 Atomic: + value: ROUND(AVG((SQC_TC_DATA_ATOMIC_REQ / $denom)), 0) + alias: sl1_l2_atom_ + tips: + VL1 Rd: + value: ROUND(AVG((TCP_TOTAL_READ_sum / $denom)), 0) + alias: vl1_rd_ + tips: + VL1 Wr: + value: ROUND(AVG((TCP_TOTAL_WRITE_sum / $denom)), 0) + alias: vl1_wr_ + tips: + VL1 Atomic: + value: ROUND(AVG(((TCP_TOTAL_ATOMIC_WITH_RET_sum + TCP_TOTAL_ATOMIC_WITHOUT_RET_sum) + / $denom)), 0) + alias: vl1_atom_ + tips: + VL1 Hit: + value: ROUND(AVG(((100 - ((100 * (((TCP_TCC_READ_REQ_sum + TCP_TCC_WRITE_REQ_sum) + + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) + / TCP_TOTAL_CACHE_ACCESSES_sum)) if (TCP_TOTAL_CACHE_ACCESSES_sum != 0) else + None)), 0) + alias: vl1_hit_ + tips: + VL1 Lat: + value: ROUND(AVG(((TCP_TCP_LATENCY_sum / TCP_TA_TCP_STATE_READ_sum) if (TCP_TA_TCP_STATE_READ_sum + != 0) else None)), 0) + alias: vl1_lat_ + tips: + VL1_L2 Rd: + value: ROUND(AVG((TCP_TCC_READ_REQ_sum / $denom)), 0) + alias: vl1_l2_rd_ + tips: + VL1_L2 Wr: + value: ROUND(AVG((TCP_TCC_WRITE_REQ_sum / $denom)), 0) + alias: vl1_l2_wr_ + tips: + vL1_L2 Atomic: + value: ROUND(AVG(((TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + / $denom)), 0) + alias: vl1_l2_atom_ + tips: + L2 Rd: + value: ROUND(AVG((TCC_READ_sum / $denom)), 0) + alias: l2_rd_ + tips: + L2 Wr: + value: ROUND(AVG((TCC_WRITE_sum / $denom)), 0) + alias: l2_wr_ + tips: + L2 Atomic: + value: ROUND(AVG((TCC_ATOMIC_sum / $denom)), 0) + alias: l2_atom_ + tips: + L2 Hit: + value: ROUND(AVG((((100 * TCC_HIT_sum) / (TCC_HIT_sum + TCC_MISS_sum)) if ((TCC_HIT_sum + + TCC_MISS_sum) != 0) else None)), 0) + alias: l2_hit_ + tips: + L2 Rd Lat: + value: ROUND(AVG(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) + if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)), + 0) + alias: l2_rd_lat_ + tips: + L2 Wr Lat: + value: ROUND(AVG(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) + != 0) else None)), 0) + alias: l2_wr_lat_ + tips: + Fabric Rd Lat: + value: ROUND(AVG(((TCC_EA_RDREQ_LEVEL_sum / TCC_EA_RDREQ_sum) if (TCC_EA_RDREQ_sum + != 0) else None)), 0) + alias: fabric_rd_lat_ + tips: + Fabric Wr Lat: + value: ROUND(AVG(((TCC_EA_WRREQ_LEVEL_sum / TCC_EA_WRREQ_sum) if (TCC_EA_WRREQ_sum + != 0) else None)), 0) + alias: fabric_wr_lat_ + tips: + Fabric Atomic Lat: + value: ROUND(AVG(((TCC_EA_ATOMIC_LEVEL_sum / TCC_EA_ATOMIC_sum) if (TCC_EA_ATOMIC_sum + != 0) else None)), 0) + alias: fabric_atom_lat_ + tips: + Fabric_L2 Rd: + value: ROUND(AVG((TCC_EA_RDREQ_sum / $denom)), 0) + alias: l2_fabric_rd_ + tips: + Fabric_L2 Wr: + value: ROUND(AVG((TCC_EA_WRREQ_sum / $denom)), 0) + alias: l2_fabric_wr_ + tips: + Fabric_l2 Atomic: + value: ROUND(AVG((TCC_EA_ATOMIC_sum / $denom)), 0) + alias: l2_fabric_atom_ + tips: + HBM Rd: + value: ROUND(AVG((TCC_EA_RDREQ_DRAM_sum / $denom)), 0) + alias: hbm_rd_ + tips: + HBM Wr: + value: ROUND(AVG((TCC_EA_WRREQ_DRAM_sum / $denom)), 0) + alias: hbm_wr_ + tips: + LDS Util: + value: ROUND(AVG(((100 * SQ_LDS_IDX_ACTIVE) / (GRBM_GUI_ACTIVE * $numCU))), + 0) + alias: lds_util_ + tips: + VL1 Coalesce: + value: ROUND(AVG(((((TA_TOTAL_WAVEFRONTS_sum * 64) * 100) / (TCP_TOTAL_ACCESSES_sum + * 4)) if (TCP_TOTAL_ACCESSES_sum != 0) else 0)), 0) + alias: vl1_coales_ + tips: + VL1 Stall: + value: ROUND(AVG((((100 * TCP_TCR_TCP_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) + if (TCP_GATE_EN1_sum != 0) else None)), 0) + alias: vl1_stall_ + tips: + LDS Lat: + value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQ_INSTS_LDS) + if (SQ_INSTS_LDS != 0) else None)), 0) + alias: lds_lat_ + coll_level: SQ_INST_LEVEL_LDS + tips: + vL1D Lat: + value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQC_DCACHE_REQ) + if (SQC_DCACHE_REQ != 0) else None)), 0) + alias: sl1_lat_ + tips: + IL1 Lat: + value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / SQC_ICACHE_REQ) + if (SQC_ICACHE_REQ != 0) else None)), 0) + alias: il1_lat_ + tips: + Wave Occupancy: + value: ROUND(AVG(((SQ_ACCUM_PREV_HIRES / GRBM_GUI_ACTIVE) / $numActiveCUs)), 0) + alias: wave_occ_ + coll_level: SQ_LEVEL_WAVES + tips: diff --git a/src/omniperf_soc/configs/gfx90a/2000_kernels.yaml b/src/omniperf_soc/configs/gfx90a/2000_kernels.yaml new file mode 100644 index 0000000000..ed566f75a2 --- /dev/null +++ b/src/omniperf_soc/configs/gfx90a/2000_kernels.yaml @@ -0,0 +1,8 @@ +--- +Panel Config: + id: 2000 + title: Kernels + data source: + - raw_csv_table: + id: 2001 + source: pmc_dispatch_info.csv diff --git a/src/omniperf_soc/configs/panel_config_template.yaml b/src/omniperf_soc/configs/panel_config_template.yaml new file mode 100644 index 0000000000..e241896b40 --- /dev/null +++ b/src/omniperf_soc/configs/panel_config_template.yaml @@ -0,0 +1,51 @@ +--- +# +# Rules to define a panel and its data sources: +# - Each panel has its own yaml file. +# - Each yaml file has 2 sections: (1) Description Details. (2) Panel Config. +# - id for each panel/ data_source has to be unique. +# - The data source of panel support only: raw_csv_table and metric_table for now. +# - For raw_csv_table, data will be loaded from the specified csv file directly, +# and may be sorted. +# - For metric_table, the number of entries of each metric must match of +# the number of entries of table header. The metric can be raw pmc counters +# or an expression derived from them. The key keyword of the metric has to be +# one defined in parser.supported_field, i.e. "Value", "Min", "Max", "Avg" etc. +# + +Metric Description: + METRIC01: &METRIC01_anchor Scalar Arithmetic Logic Unit + +# Define the panel properties and properties of each metric in the panel. +Panel Config: + id: 800 + title: # define panel title to display + data source: + # Metric table sample + - metric_table: + id: 801 + title: # subtitle for this table(optional) + header: + metric: Metric + value: Value + unit: Unit + peak: Peak + pop: PoP + tips: Tips + metric: + METRIC01: + value: AVG(100 * SQ_ACTIVE_INST_SCA / ( GRBM_GUI_ACTIVE * $numCU )) + unit: pct + peak: 100 + pop: AVG(100* SQ_ACTIVE_INST_SCA/(GRBM_GUI_ACTIVE*$numCU)) + tips: *METRIC01_anchor + METRIC02: + value: AVG(100 * SQ_ACTIVE_INST_VALU / ( GRBM_GUI_ACTIVE * $numCU)) + unit: pct + peak: 100 + pop: AVG(100* SQ_ACTIVE_INST_VALU/(GRBM_GUI_ACTIVE*$numCU)) + tips: + # CSV table sample + - raw_csv_table: + id: 802 + source: abc.csv diff --git a/src/omniperf_soc/soc_base.py b/src/omniperf_soc/soc_base.py index 94bd623c85..fe90c3d7c8 100644 --- a/src/omniperf_soc/soc_base.py +++ b/src/omniperf_soc/soc_base.py @@ -39,10 +39,17 @@ class OmniSoC_Base(): self.__soc = None self.__perfmon_dir = None self.__perfmon_config = {} # Per IP block max number of simulutaneous counters. GFX IP Blocks + self.__soc_params = {} # SoC specifications if self.__args.path == os.path.join(os.getcwd(), "workloads"): self.__workload_dir = os.path.join(self.__args.path, self.__args.name, self.__args.target) else: self.__workload_dir = self.__args.path + def __hash__(self): + return hash(self.__soc) + def __eq__(self, other): + if not isinstance(other, type(self)): + return NotImplemented + return self.__soc == other.get_soc() def error(self,message): logging.error("") @@ -53,6 +60,10 @@ class OmniSoC_Base(): self.__perfmon_dir = path def set_perfmon_config(self, config: dict): self.__perfmon_config = config + def set_soc_param(self, param: dict): + self.__soc_params = param + def get_soc_param(self): + return self.__soc_params def set_soc(self, soc: str): self.__soc = soc def get_soc(self): @@ -108,7 +119,9 @@ class OmniSoC_Base(): pmc_list = perfmon_coalesce(pmc_files_list, self.__perfmon_config, self.__workload_dir) perfmon_emit(pmc_list, self.__perfmon_config, self.__workload_dir) + #---------------------------------------------------- # Required methods to be implemented by child classes + #---------------------------------------------------- @abstractmethod def profiling_setup(self): """Perform any SoC-specific setup prior to profiling. @@ -127,6 +140,7 @@ class OmniSoC_Base(): """Perform any SoC-specific setup prior to analysis. """ logging.debug("[analysis] perform SoC analysis setup for %s" % self.__soc) + @demarcate def perfmon_coalesce(pmc_files_list, perfmon_config, workload_dir): diff --git a/src/omniperf_soc/soc_gfx900.py b/src/omniperf_soc/soc_gfx900.py deleted file mode 100644 index 997eb386c7..0000000000 --- a/src/omniperf_soc/soc_gfx900.py +++ /dev/null @@ -1,74 +0,0 @@ -##############################################################################bl -# MIT License -# -# Copyright (c) 2021 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all -# copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -# SOFTWARE. -##############################################################################el - -import os -import config -from omniperf_soc.soc_base import OmniSoC_Base -from utils.utils import demarcate - -class gfx900_soc (OmniSoC_Base): - def __init__(self,args): - super().__init__(args) - soc = "gfx900" - self.set_soc(soc) - self.set_perfmon_dir(os.path.join(str(config.omniperf_home), "perfmon_configs", soc)) #TODO: Improve extensibility - # Per IP block max number of simulutaneous counters. GFX IP Blocks - self.set_perfmon_config( - { - "SQ": 8, - "TA": 2, - "TD": 2, - "TCP": 4, - "TCC": 4, - "CPC": 2, - "CPF": 2, - "SPI": 2, - "GRBM": 2, - "GDS": 4, - "TCC_channels": 16, - } - ) - - # Required methods to be implemented by child classes - @demarcate - def profiling_setup(self): - """Perform any SoC-specific setup prior to profiling. - """ - super().profiling_setup() - if self.get_args().roof_only: - self.error("%s does not support roofline analysis" % self.get_soc()) - # Perfmon filtering - self.perfmon_filter() - - @demarcate - def post_profiling(self): - """Perform any SoC-specific post profiling activities. - """ - super().post_profiling() - - @demarcate - def analysis_setup(self): - """Perform any SoC-specific setup prior to analysis. - """ - super().analysis_setup() \ No newline at end of file diff --git a/src/omniperf_soc/soc_gfx906.py b/src/omniperf_soc/soc_gfx906.py index bf566ff2b8..cea494fa5e 100644 --- a/src/omniperf_soc/soc_gfx906.py +++ b/src/omniperf_soc/soc_gfx906.py @@ -49,8 +49,23 @@ class gfx906_soc (OmniSoC_Base): "TCC_channels": 16, } ) + self.set_soc_param( + { + "numSE": 4, + "numCU": 60, + "numSIMD": 240, + "numWavesPerCU": 40, + "numSQC": 15, + "L2Banks": 16, + "LDSBanks": 32, + "Freq": 1725, + "mclk": 1000 + } + ) - # Required methods to be implemented by child classes + #----------------------- + # Required child methods + #----------------------- @demarcate def profiling_setup(self): """Perform any SoC-specific setup prior to profiling. diff --git a/src/omniperf_soc/soc_gfx908.py b/src/omniperf_soc/soc_gfx908.py index cab8e36066..05b9d41d8c 100644 --- a/src/omniperf_soc/soc_gfx908.py +++ b/src/omniperf_soc/soc_gfx908.py @@ -49,9 +49,24 @@ class gfx908_soc (OmniSoC_Base): "TCC_channels": 32, } ) + self.set_soc_param( + { + "numSE": 8, + "numCU": 120, + "numSIMD": 480, + "numWavesPerCU": 40, + "numSQC": 30, + "L2Banks": 32, + "LDSBanks": 32, + "Freq": 1502, + "mclk": 1200 + } + ) - # Required methods to be implemented by child classes + #----------------------- + # Required child methods + #----------------------- @demarcate def profiling_setup(self): """Perform any SoC-specific setup prior to profiling. diff --git a/src/omniperf_soc/soc_gfx90a.py b/src/omniperf_soc/soc_gfx90a.py index 596a07d543..6098d4ac70 100644 --- a/src/omniperf_soc/soc_gfx90a.py +++ b/src/omniperf_soc/soc_gfx90a.py @@ -55,9 +55,24 @@ class gfx90a_soc (OmniSoC_Base): "TCC_channels": 32 } ) + self.set_soc_param( + { + "numSE": 8, + "numCU": 110, + "numSIMD": 440, + "numWavesPerCU": 32, + "numSQC": 56, + "L2Banks": 32, + "LDSBanks": 32, + "Freq": 1700, + "mclk": 1600 + } + ) self.roofline_obj = Roofline(args) - # Required methods to be implemented by child classes + #----------------------- + # Required child methods + #----------------------- @demarcate def profiling_setup(self): """Perform any SoC-specific setup prior to profiling. @@ -87,3 +102,4 @@ class gfx90a_soc (OmniSoC_Base): """ super().analysis_setup() + diff --git a/src/utils/file_io.py b/src/utils/file_io.py new file mode 100644 index 0000000000..366105e861 --- /dev/null +++ b/src/utils/file_io.py @@ -0,0 +1,256 @@ +##############################################################################bl +# MIT License +# +# Copyright (c) 2021 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +##############################################################################el + +import os +import sys +import pandas as pd +import re +import yaml + +import glob +import collections +from collections import OrderedDict +from pathlib import Path +from utils import schema +import config +import logging + +# TODO: use pandas chunksize or dask to read really large csv file +# from dask import dataframe as dd + +# the build-in config to list kernel names purpose only +top_stats_build_in_config = { + 0: { + "id": 0, + "title": "Top Stat", + "data source": [{"raw_csv_table": {"id": 1, "source": "pmc_kernel_top.csv"}}], + } +} + +time_units = {"s": 10**9, "ms": 10**6, "us": 10**3, "ns": 1} + +def load_sys_info(f): + """ + Load sys running info from csv file to a df. + """ + return pd.read_csv(f) + + +def load_soc_params(dir): + """ + Load soc params for all supported archs to a df. + """ + df = pd.DataFrame() + for root, dirs, files in os.walk(dir): + for f in files: + if f.endswith(".csv"): + tmp_df = pd.read_csv(os.path.join(root, f)) + df = pd.concat([tmp_df, df]) + df.set_index("name", inplace=True) + return df + +def load_panel_configs(dir): + """ + Load all panel configs from yaml file. + """ + d = {} + for root, dirs, files in os.walk(dir): + for f in files: + if f.endswith(".yaml"): + with open(os.path.join(root, f)) as file: + config = yaml.safe_load(file) + d[config["Panel Config"]["id"]] = config["Panel Config"] + + # TODO: sort metrics as the header order in case they are not defined in the same order + + od = OrderedDict(sorted(d.items())) + # for key, value in od.items(): + # print(key, value) + return od + + +def create_df_kernel_top_stats( + raw_data_dir, + filter_gpu_ids, + filter_dispatch_ids, + time_unit, + max_kernel_num, + sortby="sum", +): + """ + Create top stats info by grouping kernels with user's filters. + """ + # NB: + # We even don't have to create pmc_kernel_top.csv explictly + df = pd.read_csv(os.path.join(raw_data_dir, schema.pmc_perf_file_prefix + ".csv")) + + # The logic below for filters are the same as in parser.apply_filters(), + # which can be merged together if need it. + if filter_gpu_ids: + df = df.loc[df["gpu-id"].astype(str).isin([filter_gpu_ids])] + + if filter_dispatch_ids: + # NB: support ignoring the 1st n dispatched execution by '> n' + # The better way may be parsing python slice string + if ">" in filter_dispatch_ids[0]: + m = re.match("\> (\d+)", filter_dispatch_ids[0]) + df = df[df["Index"] > int(m.group(1))] + else: + df = df.loc[df["Index"].astype(str).isin(filter_dispatch_ids)] + + # First, create a dispatches file used to populate global vars + dispatch_info = df.loc[:, ["Index", "KernelName", "gpu-id"]] + dispatch_info.to_csv(os.path.join(raw_data_dir, "pmc_dispatch_info.csv"), index=False) + + time_stats = pd.concat( + [df["KernelName"], (df["EndNs"] - df["BeginNs"])], + keys=["KernelName", "ExeTime"], + axis=1, + ) + + grouped = time_stats.groupby(by=["KernelName"]).agg( + {"ExeTime": ["count", "sum", "mean", "median"]} + ) + + time_unit_str = "(" + time_unit + ")" + grouped.columns = [ + x.capitalize() + time_unit_str if x != "count" else x.capitalize() + for x in grouped.columns.get_level_values(1) + ] + + key = "Sum" + time_unit_str + grouped[key] = grouped[key].div(time_units[time_unit]) + key = "Mean" + time_unit_str + grouped[key] = grouped[key].div(time_units[time_unit]) + key = "Median" + time_unit_str + grouped[key] = grouped[key].div(time_units[time_unit]) + + grouped = grouped.reset_index() # Remove special group indexing + + key = "Sum" + time_unit_str + grouped["Pct"] = grouped[key] / grouped[key].sum() * 100 + + # NB: + # Sort by total time as default. + if sortby == "sum": + grouped = grouped.sort_values(by=("Sum" + time_unit_str), ascending=False) + + grouped = grouped.head(max_kernel_num) # Display only the top n results + + grouped.to_csv(os.path.join(raw_data_dir, "pmc_kernel_top.csv"), index=False) + elif sortby == "kernel": + grouped = grouped.sort_values("KernelName") + + grouped = grouped.head(max_kernel_num) # Display only the top n results + grouped.to_csv(os.path.join(raw_data_dir, "pmc_kernel_top.csv"), index=False) + + +def create_df_pmc(raw_data_dir, verbose): + """ + Load all raw pmc counters and join into one df. + """ + dfs = [] + coll_levels = [] + + df = pd.DataFrame() + new_df = pd.DataFrame() + for root, dirs, files in os.walk(raw_data_dir): + for f in files: + # print("file ", f) + if (f.endswith(".csv") and f.startswith("SQ")) or ( + f == schema.pmc_perf_file_prefix + ".csv" + ): + tmp_df = pd.read_csv(os.path.join(root, f)) + dfs.append(tmp_df) + coll_levels.append(f[:-4]) + final_df = pd.concat(dfs, keys=coll_levels, axis=1, copy=False) + # TODO: join instead of concat! + if verbose >= 2: + print("pmc_raw_data final_df ", final_df.info()) + return final_df + + +def collect_wave_occu_per_cu(in_dir, out_dir, numSE): + """ + Collect wave occupancy info from in_dir csv files + and consolidate into out_dir/wave_occu_per_cu.csv. + It depends highly on wave_occu_se*.csv format. + """ + + all = pd.DataFrame() + + for i in range(numSE): + p = Path(in_dir, "wave_occu_se" + str(i) + ".csv") + if p.exists(): + tmp_df = pd.read_csv(p) + SE_idx = "SE" + str(tmp_df.loc[0, "SE"]) + tmp_df.rename( + columns={ + "Dispatch": "Dispatch", + "SE": "SE", + "CU": "CU", + "Occupancy": SE_idx, + }, + inplace=True, + ) + + # TODO: join instead of concat! + if i == 0: + all = tmp_df[{"CU", SE_idx}] + all.sort_index(axis=1, inplace=True) + else: + all = pd.concat([all, tmp_df[SE_idx]], axis=1, copy=False) + + if not all.empty: + # print(all.transpose()) + all.to_csv(Path(out_dir, "wave_occu_per_cu.csv"), index=False) + + +def is_single_panel_config(root_dir): + """ + Check the root configs dir structure to decide using one config set for all + archs, or one for each arch. + """ + matching_files=glob.glob(os.path.join(config.omniperf_home, 'omniperf_soc', 'soc_*.py')) + supported_arch=[] + # Load list of supported archs + for filepath in matching_files: + filename=os.path.basename(filepath) + postfix=filename[len('soc_'):-len('.py')] + # print(f"File: {filename}, Postfix: {postfix}") + if postfix != "base": + supported_arch.append(postfix) + + # If not single config, verify all supported archs have defined configs + counter = 0 + for arch in supported_arch: + if root_dir.joinpath(arch).exists(): + counter += 1 + if counter == 0: + return True + elif counter == len(supported_arch): + return False + else: + logging.error("Found multiple panel config sets but incomplete for all archs!") + sys.exit(1) \ No newline at end of file diff --git a/src/utils/parser.py b/src/utils/parser.py new file mode 100644 index 0000000000..3d09aa8247 --- /dev/null +++ b/src/utils/parser.py @@ -0,0 +1,827 @@ +##############################################################################bl +# MIT License +# +# Copyright (c) 2021 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +##############################################################################el + +import ast +import sys +import astunparse +import re +import os +import pandas as pd +import numpy as np +from tabulate import tabulate +from utils import schema + +# ------------------------------------------------------------------------------ +# Internal global definitions + +# NB: +# Ammolite is unique gemstone from the Rocky Mountains. +# "ammolite__" is a special internal prefix to mark build-in global variables +# calculated or parsed from raw data sources. Its range is only in this file. +# Any other general prefixes string, like "buildin__", might be used by the +# editor. Whenever change it to a new one, replace all appearances in this file. + +# 001 is ID of pmc_kernel_top.csv table +pmc_kernel_top_table_id = 1 + +# Build-in $denom defined in mongodb query: +# "denom": { +# "$switch" : { +# "branches": [ +# { +# "case": { "$eq": [ $normUnit, "per Wave"]} , +# "then": "&SQ_WAVES" +# }, +# { +# "case": { "$eq": [ $normUnit, "per Cycle"]} , +# "then": "&GRBM_GUI_ACTIVE" +# }, +# { +# "case": { "$eq": [ $normUnit, "per Sec"]} , +# "then": {"$divide":[{"$subtract": ["&EndNs", "&BeginNs" ]}, 1000000000]} +# } +# ], +# "default": 1 +# } +# } +supported_denom = { + "per_wave": "SQ_WAVES", + "per_cycle": "GRBM_GUI_ACTIVE", + "per_second": "((EndNs - BeginNs) / 1000000000)", + "per_kernel": "1", +} + +# Build-in defined in mongodb variables: +build_in_vars = { + "numActiveCUs": "TO_INT(MIN((((ROUND(AVG(((4 * SQ_BUSY_CU_CYCLES) / GRBM_GUI_ACTIVE)), \ + 0) / $maxWavesPerCU) * 8) + MIN(MOD(ROUND(AVG(((4 * SQ_BUSY_CU_CYCLES) \ + / GRBM_GUI_ACTIVE)), 0), $maxWavesPerCU), 8)), $numCU))", + "kernelBusyCycles": "ROUND(AVG((((EndNs - BeginNs) / 1000) * $sclk)), 0)", +} + +supported_call = { + # If the below has single arg, like(expr), it is a aggr, in which turn to a pd function. + # If it has args like list [], in which turn to a python function. + "MIN": "to_min", + "MAX": "to_max", + # simple aggr + "AVG": "to_avg", + "MEDIAN": "to_median", + "STD": "to_std", + # functions apply to whole column of df or a single value + "TO_INT": "to_int", + # Support the below with 2 inputs + "ROUND": "to_round", + "MOD": "to_mod", + # Concat operation from the memory chart "active cus" + "CONCAT": "to_concat", +} + +# ------------------------------------------------------------------------------ + + +def to_min(*args): + if len(args) == 1 and isinstance(args[0], pd.core.series.Series): + return args[0].min() + elif min(args) == None: + return np.nan + else: + return min(args) + + +def to_max(*args): + if len(args) == 1 and isinstance(args[0], pd.core.series.Series): + return args[0].max() + elif max(args) == None: + return np.nan + else: + return max(args) + + +def to_avg(a): + if str(type(a)) == "": + return np.nan + elif a.empty: + return np.nan + elif isinstance(a, pd.core.series.Series): + return a.mean() + else: + raise Exception("to_avg: unsupported type.") + + +def to_median(a): + if isinstance(a, pd.core.series.Series): + return a.median() + else: + raise Exception("to_median: unsupported type.") + + +def to_std(a): + if isinstance(a, pd.core.series.Series): + return a.std() + else: + raise Exception("to_std: unsupported type.") + + +def to_int(a): + if str(type(a)) == "": + return np.nan + elif isinstance(a, (int, float, np.int64)): + return int(a) + elif isinstance(a, pd.core.series.Series): + return a.astype("Int64") + # Do we need it? + # elif isinstance(a, str): + # return int(a) + else: + raise Exception("to_int: unsupported type.") + + +def to_round(a, b): + if isinstance(a, pd.core.series.Series): + return a.round(b) + else: + return round(a, b) + + +def to_mod(a, b): + if isinstance(a, pd.core.series.Series): + return a.mod(b) + else: + return a % b + + +def to_concat(a, b): + return str(a) + str(b) + + +class CodeTransformer(ast.NodeTransformer): + """ + Python AST visitor to transform user defined equation string to df format + """ + + def visit_Call(self, node): + self.generic_visit(node) + # print("--- debug visit_Call --- ", node.args, node.func) + # print(astunparse.dump(node)) + # print(astunparse.unparse(node)) + if isinstance(node.func, ast.Name): + if node.func.id in supported_call: + node.func.id = supported_call[node.func.id] + else: + raise Exception( + "Unknown call:", node.func.id + ) # Could be removed if too strict + return node + + def visit_IfExp(self, node): + self.generic_visit(node) + # print("visit_IfExp", type(node.test), type(node.body), type(node.orelse), dir(node)) + + if isinstance(node.body, ast.Num): + raise Exception( + "Don't support body of IF with number only! Has to be expr with df['column']." + ) + + new_node = ast.Expr( + value=ast.Call( + func=ast.Attribute(value=node.body, attr="where", ctx=ast.Load()), + args=[node.test, node.orelse], + keywords=[], + ) + ) + # print("-------------") + # print(astunparse.dump(new_node)) + # print("-------------") + + return new_node + + # NB: + # visit_Name is for replacing HW counter to its df expr. In this way, we + # could support any HW counter names, which is easier than regex. + # + # There are 2 limitations: + # - It is not straightforward to support types other than simple column + # in df, such as [], (). If we need to support those, have to implement + # in correct way or work around. + # - The 'raw_pmc_df' is hack code. For other data sources, like wavefront + # data,We need to think about template or pass it as a parameter. + def visit_Name(self, node): + self.generic_visit(node) + # print("-------------", node.id) + if (not node.id.startswith("ammolite__")) and (not node.id in supported_call): + new_node = ast.Subscript( + value=ast.Name(id="raw_pmc_df", ctx=ast.Load()), + slice=ast.Index(value=ast.Str(s=node.id)), + ctx=ast.Load(), + ) + + node = new_node + return node + + +def build_eval_string(equation, coll_level): + """ + Convert user defined equation string to eval executable string + For example, + input: AVG(100 * SQ_ACTIVE_INST_SCA / ( GRBM_GUI_ACTIVE * $numCU )) + output: to_avg(100 * raw_pmc_df["pmc_perf"]["SQ_ACTIVE_INST_SCA"] / \ + (raw_pmc_df["pmc_perf"]["GRBM_GUI_ACTIVE"] * numCU)) + input: AVG(((TCC_EA_RDREQ_LEVEL_31 / TCC_EA_RDREQ_31) if (TCC_EA_RDREQ_31 != 0) else (0))) + output: to_avg((raw_pmc_df["pmc_perf"]["TCC_EA_RDREQ_LEVEL_31"] / raw_pmc_df["pmc_perf"]["TCC_EA_RDREQ_31"]).where(raw_pmc_df["pmc_perf"]["TCC_EA_RDREQ_31"] != 0, 0)) + We can not handle the below for now, + input: AVG((0 if (TCC_EA_RDREQ_31 == 0) else (TCC_EA_RDREQ_LEVEL_31 / TCC_EA_RDREQ_31))) + But potential workaound is, + output: to_avg(raw_pmc_df["pmc_perf"]["TCC_EA_RDREQ_31"].where(raw_pmc_df["pmc_perf"]["TCC_EA_RDREQ_31"] == 0, raw_pmc_df["pmc_perf"]["TCC_EA_RDREQ_LEVEL_31"] / raw_pmc_df["pmc_perf"]["TCC_EA_RDREQ_31"])) + """ + + if coll_level is None: + raise Exception("Error: coll_level can not be None.") + + if not equation: + return "" + + s = str(equation) + # print("input:", s) + + # build-in variable starts with '$', python can not handle it. + # replace '$' with 'ammolite__'. + # TODO: pre-check there is no "ammolite__" in all config files. + s = re.sub("\$", "ammolite__", s) + + # convert equation string to intermediate expression in df array format + ast_node = ast.parse(s) + # print(astunparse.dump(ast_node)) + transformer = CodeTransformer() + transformer.visit(ast_node) + + s = astunparse.unparse(ast_node) + + # correct column name/label in df with [], such as TCC_HIT[0], + # the target is df['TCC_HIT[0]'] + s = re.sub(r"\'\]\[(\d+)\]", r"[\g<1>]']", s) + # use .get() to catch any potential KeyErrors + s = re.sub("raw_pmc_df\['(.*?)']", r'raw_pmc_df.get("\1")', s) + # apply coll_level + s = re.sub(r"raw_pmc_df", "raw_pmc_df.get('" + coll_level + "')", s) + # print("--- build_eval_string, return: ", s) + return s + + +def update_denom_string(equation, unit): + """ + Update $denom in equation with runtime nomorlization unit. + """ + if not equation: + return "" + + s = str(equation) + + if unit in supported_denom.keys(): + s = re.sub(r"\$denom", supported_denom[unit], s) + + return s + + +def update_normUnit_string(equation, unit): + """ + Update $normUnit in equation with runtime nomorlization unit. + It is string replacement for display only. + """ + + # TODO: We might want to do it for subtitle contains $normUnit + if not equation: + return "" + + return re.sub( + "\((?P\w*)\s+\+\s+(\$normUnit\))", + "\g " + re.sub("_", " ", unit), + str(equation), + ).capitalize() + + +def gen_counter_list(formula): + function_filter = { + "MIN": None, + "MAX": None, + "AVG": None, + "ROUND": None, + "TO_INT": None, + "GB": None, + "STD": None, + "GFLOP": None, + "GOP": None, + "OP": None, + "CU": None, + "NC": None, + "UC": None, + "CC": None, + "RW": None, + "GIOP": None, + "GFLOPs": None, + "CONCAT": None, + "MOD": None, + } + + built_in_counter = [ + "lds", + "grd", + "wgr", + "arch_vgpr", + "accum_vgpr", + "sgpr", + "scr", + "BeginNs", + "EndNs", + ] + + visited = False + counters = [] + if not isinstance(formula, str): + return visited, counters + try: + tree = ast.parse( + formula.replace("$normUnit", "SQ_WAVES") + .replace("$denom", "SQ_WAVES") + .replace( + "$numActiveCUs", + "TO_INT(MIN((((ROUND(AVG(((4 * SQ_BUSY_CU_CYCLES) / GRBM_GUI_ACTIVE)), \ + 0) / $maxWavesPerCU) * 8) + MIN(MOD(ROUND(AVG(((4 * SQ_BUSY_CU_CYCLES) \ + / GRBM_GUI_ACTIVE)), 0), $maxWavesPerCU), 8)), $numCU))", + ) + .replace("$", "") + ) + for node in ast.walk(tree): + if isinstance(node, ast.Name): + val = str(node.id)[:-4] if str(node.id).endswith("_sum") else str(node.id) + if val.isupper() and val not in function_filter: + counters.append(val) + visited = True + if val in built_in_counter: + visited = True + except: + pass + + return visited, counters + + +def build_dfs(archConfigs, filter_metrics): + """ + - Build dataframe for each type of data source within each panel. + Each dataframe will be used as a template to load data with each run later. + For now, support "metric_table" and "raw_csv_table". Otherwise, put an empty df. + - Collect/build metric_list to suport customrized metrics profiling. + """ + + # TODO: more error checking for filter_metrics!! + # if filter_metrics: + # for metric in filter_metrics: + # if not metric in avail_ip_blocks: + # print("{} is not a valid metric to filter".format(metric)) + # exit(1) + d = {} + metric_list = {} + dfs_type = {} + metric_counters = {} + for panel_id, panel in archConfigs.panel_configs.items(): + panel_idx = str(panel_id // 100) + for data_source in panel["data source"]: + for type, data_config in data_source.items(): + if type == "metric_table": + metric_list[panel_idx] = panel["title"] + table_idx = panel_idx + "." + str(data_config["id"] % 100) + metric_list[table_idx] = data_config["title"] + + headers = ["Index"] + for key, tile in data_config["header"].items(): + if key != "tips": + headers.append(tile) + headers.append("coll_level") + + if "tips" in data_config["header"].keys(): + headers.append(data_config["header"]["tips"]) + + df = pd.DataFrame(columns=headers) + + i = 0 + for key, entries in data_config["metric"].items(): + metric_idx = table_idx + "." + str(i) + values = [] + eqn_content = [] + + if ( + (not filter_metrics) + or (metric_idx in filter_metrics) # no filter + or # metric in filter + # the whole table in filter + (table_idx in filter_metrics) + or + # the whole IP block in filter + (str(panel_id // 100) in filter_metrics) + ): + values.append(metric_idx) + values.append(key) + for k, v in entries.items(): + if k != "tips" and k != "coll_level" and k != "alias": + values.append(v) + eqn_content.append(v) + + if "alias" in entries.keys(): + values.append(entries["alias"]) + + if "coll_level" in entries.keys(): + values.append(entries["coll_level"]) + else: + values.append(schema.pmc_perf_file_prefix) + + if "tips" in entries.keys(): + values.append(entries["tips"]) + + # print(key, entries) + df_new_row = pd.DataFrame([values], columns=headers) + df = pd.concat([df, df_new_row]) + + # collect metric_list + metric_list[metric_idx] = key + # generate mapping of counters and metrics + filter = {} + _visited = False + for formula in eqn_content: + if formula is not None and formula != "None": + visited, counters = gen_counter_list(formula) + if visited: + _visited = True + for k in counters: + filter[k] = None + + if len(filter) > 0 or _visited: + metric_counters[key] = list(filter) + + i += 1 + + df.set_index("Index", inplace=True) + # df.set_index('Metric', inplace=True) + # print(tabulate(df, headers='keys', tablefmt='fancy_grid')) + elif type == "raw_csv_table": + data_source_idx = str(data_config["id"] // 100) + if ( + (not filter_metrics) + or (data_source_idx == "0") # no filter + or (data_source_idx in filter_metrics) + ): + if ( + "columnwise" in data_config + and data_config["columnwise"] == True + ): + df = pd.DataFrame( + [data_config["source"]], columns=["from_csv_columnwise"] + ) + else: + df = pd.DataFrame( + [data_config["source"]], columns=["from_csv"] + ) + metric_list[data_source_idx] = panel["title"] + else: + df = pd.DataFrame() + else: + df = pd.DataFrame() + + d[data_config["id"]] = df + dfs_type[data_config["id"]] = type + + setattr(archConfigs, "dfs", d) + setattr(archConfigs, "metric_list", metric_list) + setattr(archConfigs, "dfs_type", dfs_type) + setattr(archConfigs, "metric_counters", metric_counters) + + +def build_metric_value_string(dfs, dfs_type, normal_unit): + """ + Apply the real eval string to its field in the metric_table df. + """ + + for id, df in dfs.items(): + if dfs_type[id] == "metric_table": + for expr in df.columns: + if expr in schema.supported_field: + # NB: apply all build-in before building the whole string + df[expr] = df[expr].apply(update_denom_string, unit=normal_unit) + + # NB: there should be a faster way to do with single apply + if not df.empty: + for i in range(df.shape[0]): + row_idx_label = df.index.to_list()[i] + # print(i, "row_idx_label", row_idx_label, expr) + if expr.lower() != "alias": + df.at[row_idx_label, expr] = build_eval_string( + df.at[row_idx_label, expr], + df.at[row_idx_label, "coll_level"], + ) + + elif expr.lower() == "unit" or expr.lower() == "units": + df[expr] = df[expr].apply(update_normUnit_string, unit=normal_unit) + + # print(tabulate(df, headers='keys', tablefmt='fancy_grid')) + + +def eval_metric(dfs, dfs_type, sys_info, soc_spec, raw_pmc_df, debug): + """ + Execute the expr string for each metric in the df. + """ + + # confirm no illogical counter values (only consider non-roofline runs) + roof_only_run = sys_info.ip_blocks == "roofline" + rocscope_run = sys_info.ip_blocks == "rocscope" + if ( + not rocscope_run + and not roof_only_run + and (raw_pmc_df["pmc_perf"]["GRBM_GUI_ACTIVE"] == 0).any() + ): + print("WARNING: Dectected GRBM_GUI_ACTIVE == 0\nHaulting execution.") + sys.exit(1) + + # NB: + # Following with Omniperf 0.2.0, we are using HW spec from sys_info instead. + # The soc_spec is not in using right now, but can be used to do verification + # aganist sys_info, forced theoretical evaluation, or supporting tool-chains + # broken. + ammolite__numSE = sys_info.numSE + ammolite__numCU = sys_info.numCU + ammolite__numSIMD = sys_info.numSIMD + ammolite__numWavesPerCU = sys_info.maxWavesPerCU # todo: check do we still need it + ammolite__numSQC = sys_info.numSQC + ammolite__L2Banks = sys_info.L2Banks + ammolite__LDSBanks = ( + soc_spec['LDSBanks'] + ) # todo: eventually switch this over to sys_info. its a new spec so trying not to break compatibility + ammolite__freq = sys_info.cur_sclk # todo: check do we still need it + ammolite__mclk = sys_info.cur_mclk + ammolite__sclk = sys_info.sclk + ammolite__maxWavesPerCU = sys_info.maxWavesPerCU + ammolite__hbmBW = sys_info.hbmBW + + # TODO: fix all $normUnit in Unit column or title + + # build and eval all derived build-in global variables + ammolite__build_in = {} + for key, value in build_in_vars.items(): + # NB: assume all build in vars from pmc_perf.csv for now + s = build_eval_string(value, schema.pmc_perf_file_prefix) + try: + ammolite__build_in[key] = eval(compile(s, "", "eval")) + except TypeError: + ammolite__build_in[key] = None + except AttributeError as ae: + if ae == "'NoneType' object has no attribute 'get'": + ammolite__build_in[key] = None + + ammolite__numActiveCUs = ammolite__build_in["numActiveCUs"] + ammolite__kernelBusyCycles = ammolite__build_in["kernelBusyCycles"] + + # Hmmm... apply + lambda should just work + # df['Value'] = df['Value'].apply(lambda s: eval(compile(str(s), '', 'eval'))) + for id, df in dfs.items(): + if dfs_type[id] == "metric_table": + for idx, row in df.iterrows(): + for expr in df.columns: + if expr in schema.supported_field: + if expr.lower() != "alias": + if row[expr]: + if debug: # debug won't impact the regular calc + print("~" * 40 + "\nExpression:") + print(expr, "=", row[expr]) + print("Inputs:") + matched_vars = re.findall("ammolite__\w+", row[expr]) + if matched_vars: + for v in matched_vars: + print( + "Var ", + v, + ":", + eval(compile(v, "", "eval")), + ) + matched_cols = re.findall( + "raw_pmc_df\['\w+'\]\['\w+'\]", row[expr] + ) + if matched_cols: + for c in matched_cols: + m = re.match( + "raw_pmc_df\['(\w+)'\]\['(\w+)'\]", c + ) + t = raw_pmc_df[m.group(1)][ + m.group(2) + ].to_list() + print(c) + print( + raw_pmc_df[m.group(1)][ + m.group(2) + ].to_list() + ) + # print( + # tabulate(raw_pmc_df[m.group(1)][ + # m.group(2)], + # headers='keys', + # tablefmt='fancy_grid')) + print("\nOutput:") + try: + print( + eval(compile(row[expr], "", "eval")) + ) + print("~" * 40) + except TypeError: + print( + "skiping entry. Encounterd a missing counter" + ) + print(expr, " has been assigned to None") + print(np.nan) + except AttributeError as ae: + if ( + str(ae) + == "'NoneType' object has no attribute 'get'" + ): + print( + "skiping entry. Encounterd a missing csv" + ) + print(np.nan) + else: + print(ae) + sys.exit(1) + + # print("eval_metric", id, expr) + try: + out = eval(compile(row[expr], "", "eval")) + if row.name != "19.1.1" and np.isnan( + out + ): # Special exception for unique format of Active CUs in mem chart + row[expr] = "" + else: + row[expr] = out + except TypeError: + row[expr] = "" + except AttributeError as ae: + if ( + str(ae) + == "'NoneType' object has no attribute 'get'" + ): + row[expr] = "" + else: + print(ae) + sys.exit(1) + + else: + # If not insert nan, the whole col might be treated + # as string but not nubmer if there is NONE + row[expr] = "" + + # print(tabulate(df, headers='keys', tablefmt='fancy_grid')) + + +def apply_filters(workload, is_gui, debug): + """ + Apply user's filters to the raw_pmc df. + """ + + # TODO: error out properly if filters out of bound + ret_df = workload.raw_pmc + + if workload.filter_gpu_ids: + ret_df = ret_df.loc[ + ret_df[schema.pmc_perf_file_prefix]["gpu-id"] + .astype(str) + .isin([workload.filter_gpu_ids]) + ] + if ret_df.empty: + print("{} is an invalid gpu-id".format(workload.filter_gpu_ids)) + sys.exit(1) + + # NB: + # Kernel id is unique! + # We pick up kernel names from kerne ids first. + # Then filter valid entries with kernel names. + if workload.filter_kernel_ids: + # There are two ways Kernel filtering is done: + # 1) CLI accepts an array of ints, representing indexes of kernels from the pmc_kernel_top.csv + # 2) GUI will be passing an array of strs. The full names of kernels as selected from dropdown + if not is_gui: + if debug: + print("CLI kernel filtering") + kernels = [] + # NB: mark selected kernels with "*" + # Todo: fix it for unaligned comparison + kernel_top_df = workload.dfs[pmc_kernel_top_table_id] + kernel_top_df["S"] = "" + for kernel_id in workload.filter_kernel_ids: + # print("------- ", kernel_id) + kernels.append(kernel_top_df.loc[kernel_id, "KernelName"]) + kernel_top_df.loc[kernel_id, "S"] = "*" + + if kernels: + # print("fitlered df:", len(df.index)) + ret_df = ret_df.loc[ + ret_df[schema.pmc_perf_file_prefix]["KernelName"].isin(kernels) + ] + else: + if debug: + print("GUI kernel filtering") + ret_df = ret_df.loc[ + ret_df[schema.pmc_perf_file_prefix]["KernelName"].isin( + workload.filter_kernel_ids + ) + ] + + if workload.filter_dispatch_ids: + # NB: support ignoring the 1st n dispatched execution by '> n' + # The better way may be parsing python slice string + for d in workload.filter_dispatch_ids: + if int(d) >= len(ret_df): # subtract 2 bc of the two header rows + print("{} is an invalid dispatch id.".format(d)) + sys.exit(1) + if ">" in workload.filter_dispatch_ids[0]: + m = re.match("\> (\d+)", workload.filter_dispatch_ids[0]) + ret_df = ret_df[ + ret_df[schema.pmc_perf_file_prefix]["Index"] > int(m.group(1)) + ] + else: + dispatches = [int(x) for x in workload.filter_dispatch_ids] + ret_df = ret_df.loc[dispatches] + if debug: + print("~" * 40, "\nraw pmc df info:\n") + print(workload.raw_pmc.info()) + print("~" * 40, "\nfiltered pmc df info:") + print(ret_df.info()) + + return ret_df + + +def load_kernel_top(workload, dir): + # NB: + # - Do pmc_kernel_top.csv loading before eval_metric because we need the kernel names. + # - There might be a better way/timing to load raw_csv_table. + tmp = {} + for id, df in workload.dfs.items(): + if "from_csv" in df.columns: + tmp[id] = pd.read_csv(os.path.join(dir, df.loc[0, "from_csv"])) + elif "from_csv_columnwise" in df.columns: + # NB: + # Another way might be doing transpose in tty like metric_table. + # But we need to figure out headers and comparison properly. + tmp[id] = pd.read_csv( + os.path.join(dir, df.loc[0, "from_csv_columnwise"]) + ).transpose() + # NB: + # All transposed columns should be marked with a general header, + # so tty could detect them and show them correctly in comparison. + tmp[id].columns = ["Info"] + workload.dfs.update(tmp) + + +def load_table_data(workload, dir, is_gui, debug, verbose, skipKernelTop=False): + """ + Load data for all "raw_csv_table". + Calculate mertric value for all "metric_table". + """ + if not skipKernelTop: + load_kernel_top(workload, dir) + + eval_metric( + workload.dfs, + workload.dfs_type, + workload.sys_info.iloc[0], + workload.soc_spec, + apply_filters(workload, is_gui, debug), + debug, + ) + + +def build_comparable_columns(time_unit): + """ + Build comparable columns/headers for display + """ + comparable_columns = schema.supported_field + top_stat_base = ["Count", "Sum", "Mean", "Median", "Standard Deviation"] + + for h in top_stat_base: + comparable_columns.append(h + "(" + time_unit + ")") + + return comparable_columns diff --git a/src/utils/schema.py b/src/utils/schema.py new file mode 100644 index 0000000000..e060ff6ab1 --- /dev/null +++ b/src/utils/schema.py @@ -0,0 +1,113 @@ +##############################################################################bl +# MIT License +# +# Copyright (c) 2021 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +##############################################################################el + +# +# Define all common data storage classes, +# predifned dict and global functions. +# + +import pandas as pd +from typing import Dict, List, Mapping, Generator +from dataclasses import dataclass, field +from collections import OrderedDict + + +@dataclass +class ArchConfig: + # [id: panel_config] pairs + panel_configs: OrderedDict = field(default=dict) + + # [id: df] pairs + dfs: Dict[int, pd.DataFrame] = field(default_factory=dict) + + # NB: + # dfs_type should be a meta info embeded into df. + # pandas.DataFrame.attrs is experimental and may change without warning. + # So do it as below for now. + + # [id: df_type] pairs + dfs_type: Dict[int, str] = field(default_factory=dict) + + # [Index: Metric name] pairs + metric_list: Dict[str, str] = field(default_factory=dict) + + # [Metric name: Counters] pairs + metric_counters: Dict[str, list] = field(default_factory=dict) + + +@dataclass +class Workload: + sys_info: pd.DataFrame = None + soc_spec: dict = None # TODO: might move it to ArchConfig + raw_pmc: pd.DataFrame = None + dfs: Dict[int, pd.DataFrame] = field(default_factory=dict) + dfs_type: Dict[int, str] = field(default_factory=dict) + filter_kernel_ids: List[int] = field(default_factory=list) + filter_gpu_ids: List[int] = field(default_factory=list) + filter_dispatch_ids: List[int] = field(default_factory=list) + avail_ips: List[int] = field(default_factory=list) + + +# Metrics will be calculated ONLY when the header(key) is in below list +supported_field = [ + "Value", + "Minimum", + "Maximum", + "Average", + "Median", + "Min", + "Max", + "Avg", + "PoP", + "Peak", + "Count", + "Mean", + "Pct", + "Std Dev", + # Special keywords for Memory chart + "Alias", + # Special keywords for L2 channel + "Channel", + "L2 Cache Hit Rate (%)", + "Requests (Requests)", + "L1-L2 Read (Requests)", + "L1-L2 Write (Requests)", + "L1-L2 Atomic (Requests)", + "L2-EA Read (Requests)", + "L2-EA Write (Requests)", + "L2-EA Atomic (Requests)", + "L2-EA Read Latency (Cycles)", + "L2-EA Write Latency (Cycles)", + "L2-EA Atomic Latency (Cycles)", + "L2-EA Read Stall - IO (Cycles per)", + "L2-EA Read Stall - GMI (Cycles per)", + "L2-EA Read Stall - DRAM (Cycles per)", + "L2-EA Write Stall - IO (Cycles per)", + "L2-EA Write Stall - GMI (Cycles per)", + "L2-EA Write Stall - DRAM (Cycles per)", + "L2-EA Write Stall - Starve (Cycles per)", +] + +# The prefix of raw pmc_perf.csv +pmc_perf_file_prefix = "pmc_perf" diff --git a/src/utils/tty.py b/src/utils/tty.py new file mode 100644 index 0000000000..668567ac08 --- /dev/null +++ b/src/utils/tty.py @@ -0,0 +1,247 @@ +##############################################################################bl +# MIT License +# +# Copyright (c) 2021 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +##############################################################################el + +import pandas as pd +from pathlib import Path +from tabulate import tabulate +import sys +import copy + +from utils import parser + +hidden_columns = ["Tips", "coll_level"] +hidden_sections = [1900, 2000] + + +def string_multiple_lines(source, width, max_rows): + """ + Adjust string with multiple lines by inserting '\n' + """ + idx = 0 + lines = [] + while idx < len(source) and len(lines) < max_rows: + lines.append(source[idx : idx + width]) + idx += width + + if idx < len(source): + last = lines[-1] + lines[-1] = last[0:-3] + "..." + return "\n".join(lines) + + +def show_all(args, runs, archConfigs, output): + """ + Show all panels with their data in plain text mode. + """ + comparable_columns = parser.build_comparable_columns(args.time_unit) + + for panel_id, panel in archConfigs.panel_configs.items(): + # Skip panels that don't support baseline comparison + if panel_id in hidden_sections: + continue + ss = "" # store content of all data_source from one pannel + + for data_source in panel["data source"]: + for type, table_config in data_source.items(): + # take the 1st run as baseline + base_run, base_data = next(iter(runs.items())) + base_df = base_data.dfs[table_config["id"]] + + df = pd.DataFrame(index=base_df.index) + + for header in list(base_df.keys()): + if ( + (not args.cols) + or (args.cols and base_df.columns.get_loc(header) in args.cols) + or (type == "raw_csv_table") + ): + if header in hidden_columns: + pass + elif header not in comparable_columns: + if ( + type == "raw_csv_table" + and table_config["source"] == "pmc_kernel_top.csv" + and header == "KernelName" + ): + # NB: the width of kernel name might depend on the header of the table. + adjusted_name = base_df["KernelName"].apply( + lambda x: string_multiple_lines(x, 40, 3) + ) + df = pd.concat([df, adjusted_name], axis=1) + elif type == "raw_csv_table" and header == "Info": + for run, data in runs.items(): + cur_df = data.dfs[table_config["id"]] + df = pd.concat([df, cur_df[header]], axis=1) + else: + df = pd.concat([df, base_df[header]], axis=1) + else: + for run, data in runs.items(): + cur_df = data.dfs[table_config["id"]] + if (type == "raw_csv_table") or ( + type == "metric_table" + and (not header in hidden_columns) + ): + if run != base_run: + # calc percentage over the baseline + base_df[header] = [ + float(x) if x != "" else float(0) + for x in base_df[header] + ] + cur_df[header] = [ + float(x) if x != "" else float(0) + for x in cur_df[header] + ] + t_df = pd.concat( + [ + base_df[header], + cur_df[header], + ], + axis=1, + ) + diff = t_df.iloc[:, 1] - t_df.iloc[:, 0] + t_df = diff / t_df.iloc[:, 0].replace(0, 1) + if args.verbose >= 2: + print("---------", header, t_df) + + t_df_pretty = ( + t_df.astype(float) + .mul(100) + .round(args.decimal) + ) + # show value + percentage + # TODO: better alignment + t_df = ( + cur_df[header] + .astype(float) + .round(args.decimal) + .map(str) + + " (" + + t_df_pretty.map(str) + + "%)" + ) + df = pd.concat([df, t_df], axis=1) + + # DEBUG: When in a CI setting and flag is set, + # then verify metrics meet threshold requirement + if args.report_diff: + if ( + t_df_pretty.abs() + .gt(args.report_diff) + .any() + ): + violation_idx = t_df_pretty.index[t_df_pretty.abs() > args.report_diff] + print( + "DEBUG ERROR: Dataframe diff exceeds {} threshold requirement\nSee metric {}".format( + str(args.report_diff) + "%", + violation_idx.to_numpy() + ) + ) + print(df) + sys.exit(1) + else: + cur_df_copy = copy.deepcopy(cur_df) + cur_df_copy[header] = [ + round(float(x), args.decimal) + if x != "" + else x + for x in base_df[header] + ] + df = pd.concat([df, cur_df_copy[header]], axis=1) + + if not df.empty: + # subtitle for each table in a panel if existing + table_id_str = ( + str(table_config["id"] // 100) + + "." + + str(table_config["id"] % 100) + ) + + if "title" in table_config and table_config["title"]: + ss += table_id_str + " " + table_config["title"] + "\n" + + if args.df_file_dir: + p = Path(args.df_file_dir) + if not p.exists(): + p.mkdir() + if p.is_dir(): + if "title" in table_config and table_config["title"]: + table_id_str += "_" + table_config["title"] + df.to_csv( + p.joinpath(table_id_str.replace(" ", "_") + ".csv"), + index=False, + ) + + # NB: + # "columnwise: True" is a special attr of a table/df + # For raw_csv_table, such as system_info, we transpose the + # df when load it, because we need those items in column. + # For metric_table, we only need to show the data in column + # fash for now. + ss += ( + tabulate( + df.transpose() + if type != "raw_csv_table" + and "columnwise" in table_config + and table_config["columnwise"] == True + else df, + headers="keys", + tablefmt="fancy_grid", + floatfmt="." + str(args.decimal) + "f", + ) + + "\n" + ) + + if ss: + print("\n" + "-" * 80, file=output) + print(str(panel_id // 100) + ". " + panel["title"], file=output) + print(ss, file=output) + + +def show_kernels(args, runs, archConfigs, output): + """ + Show the kernels from top stats. + """ + print("\n" + "-" * 80, file=output) + print("Detected Kernels", file=output) + + df = pd.DataFrame() + for panel_id, panel in archConfigs.panel_configs.items(): + for data_source in panel["data source"]: + for type, table_config in data_source.items(): + for run, data in runs.items(): + single_df = data.dfs[table_config["id"]] + # NB: + # For pmc_kernel_top.csv, have to sort here if not + # sorted when load_table_data. + df = pd.concat([df, single_df["KernelName"]], axis=1) + + print( + tabulate( + df, + headers="keys", + tablefmt="fancy_grid", + floatfmt="." + str(args.decimal) + "f", + ), + file=output, + )