From 63b4fe36dd992ce89bc3a716690a11c141782e93 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Tue, 14 Dec 2021 11:14:15 -0500 Subject: [PATCH] Add new ImageManager for GFX11 Adding new ImageManager class for GFX11 GPUs ImageManagerGfx11 functions copied from ImageManagerNv. Register descriptions in resource_gfx11.h updated for gfx11. Signed-off-by: David Yat Sin Change-Id: I48b39f6a633aef14aa829f7240a43fe0feb1c290 [ROCm/ROCR-Runtime commit: 907e05c1b3c0d80e63c8df4a46331524dc1b8556] --- .../runtime/hsa-runtime/CMakeLists.txt | 1 + .../hsa-runtime/image/image_manager_gfx11.cpp | 790 ++++++++++++++++ .../hsa-runtime/image/image_manager_gfx11.h | 98 ++ .../hsa-runtime/image/image_runtime.cpp | 5 +- .../hsa-runtime/image/resource_gfx11.h | 871 ++++++++++++++++++ 5 files changed, 1764 insertions(+), 1 deletion(-) create mode 100644 projects/rocr-runtime/runtime/hsa-runtime/image/image_manager_gfx11.cpp create mode 100755 projects/rocr-runtime/runtime/hsa-runtime/image/image_manager_gfx11.h create mode 100755 projects/rocr-runtime/runtime/hsa-runtime/image/resource_gfx11.h diff --git a/projects/rocr-runtime/runtime/hsa-runtime/CMakeLists.txt b/projects/rocr-runtime/runtime/hsa-runtime/CMakeLists.txt index a0f08ae9cd..6a047c1855 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/CMakeLists.txt +++ b/projects/rocr-runtime/runtime/hsa-runtime/CMakeLists.txt @@ -235,6 +235,7 @@ if(${IMAGE_SUPPORT}) image/image_manager_kv.cpp image/image_manager_ai.cpp image/image_manager_nv.cpp + image/image_manager_gfx11.cpp image/image_lut_kv.cpp image/blit_object_gfx7xx.cpp image/blit_object_gfx8xx.cpp diff --git a/projects/rocr-runtime/runtime/hsa-runtime/image/image_manager_gfx11.cpp b/projects/rocr-runtime/runtime/hsa-runtime/image/image_manager_gfx11.cpp new file mode 100644 index 0000000000..a2ac0a3c23 --- /dev/null +++ b/projects/rocr-runtime/runtime/hsa-runtime/image/image_manager_gfx11.cpp @@ -0,0 +1,790 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// The University of Illinois/NCSA +// Open Source License (NCSA) +// +// Copyright (c) 2014-2021, Advanced Micro Devices, Inc. All rights reserved. +// +// Developed by: +// +// AMD Research and AMD HSA Software Development +// +// Advanced Micro Devices, Inc. +// +// www.amd.com +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to +// deal with the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimers. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimers in +// the documentation and/or other materials provided with the distribution. +// - Neither the names of Advanced Micro Devices, Inc, +// nor the names of its contributors may be used to endorse or promote +// products derived from this Software without specific prior written +// permission. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS WITH THE SOFTWARE. +// +//////////////////////////////////////////////////////////////////////////////// + +#define NOMINMAX +#include "image_manager_gfx11.h" + +#include + +#include +#include + +#include "inc/hsa_ext_amd.h" +#include "core/inc/hsa_internal.h" +#include "addrlib/src/core/addrlib.h" +#include "image_runtime.h" +#include "resource.h" +#include "resource_gfx11.h" +#include "util.h" +#include "device_info.h" + +namespace rocr { +namespace image { + +//----------------------------------------------------------------------------- +// Workaround switch to combined format/type codes and missing gfx11 +// specific look up table. Only covers types used in image_lut_kv.cpp. +//----------------------------------------------------------------------------- +struct formatconverstion_t { + FMT fmt; + type type; + FORMAT format; +}; + +// Format/Type to combined format code table. +// Sorted and indexed to allow fast searches. +static const formatconverstion_t FormatLUT[] = { + {FMT_1_5_5_5, TYPE_UNORM, CFMT_1_5_5_5_UNORM}, + {FMT_10_10_10_2, TYPE_UNORM, CFMT_10_10_10_2_UNORM}, + {FMT_10_10_10_2, TYPE_SNORM, CFMT_10_10_10_2_SNORM}, + {FMT_10_10_10_2, TYPE_UINT, CFMT_10_10_10_2_UINT}, + {FMT_10_10_10_2, TYPE_SINT, CFMT_10_10_10_2_SINT}, + {FMT_16, TYPE_UNORM, CFMT_16_UNORM}, + {FMT_16, TYPE_SNORM, CFMT_16_SNORM}, + {FMT_16, TYPE_UINT, CFMT_16_UINT}, + {FMT_16, TYPE_SINT, CFMT_16_SINT}, + {FMT_16, TYPE_FLOAT, CFMT_16_FLOAT}, + {FMT_16_16, TYPE_UNORM, CFMT_16_16_UNORM}, + {FMT_16_16, TYPE_SNORM, CFMT_16_16_SNORM}, + {FMT_16_16, TYPE_UINT, CFMT_16_16_UINT}, + {FMT_16_16, TYPE_SINT, CFMT_16_16_SINT}, + {FMT_16_16, TYPE_FLOAT, CFMT_16_16_FLOAT}, + {FMT_16_16_16_16, TYPE_UNORM, CFMT_16_16_16_16_UNORM}, + {FMT_16_16_16_16, TYPE_SNORM, CFMT_16_16_16_16_SNORM}, + {FMT_16_16_16_16, TYPE_UINT, CFMT_16_16_16_16_UINT}, + {FMT_16_16_16_16, TYPE_SINT, CFMT_16_16_16_16_SINT}, + {FMT_16_16_16_16, TYPE_FLOAT, CFMT_16_16_16_16_FLOAT}, + {FMT_2_10_10_10, TYPE_UNORM, CFMT_2_10_10_10_UNORM}, + {FMT_2_10_10_10, TYPE_SNORM, CFMT_2_10_10_10_SNORM}, + {FMT_2_10_10_10, TYPE_UINT, CFMT_2_10_10_10_UINT}, + {FMT_2_10_10_10, TYPE_SINT, CFMT_2_10_10_10_SINT}, + {FMT_24_8, TYPE_UNORM, CFMT_24_8_UNORM}, + {FMT_24_8, TYPE_UINT, CFMT_24_8_UINT}, + {FMT_32, TYPE_UINT, CFMT_32_UINT}, + {FMT_32, TYPE_SINT, CFMT_32_SINT}, + {FMT_32, TYPE_FLOAT, CFMT_32_FLOAT}, + {FMT_32_32, TYPE_UINT, CFMT_32_32_UINT}, + {FMT_32_32, TYPE_SINT, CFMT_32_32_SINT}, + {FMT_32_32, TYPE_FLOAT, CFMT_32_32_FLOAT}, + {FMT_32_32_32, TYPE_UINT, CFMT_32_32_32_UINT}, + {FMT_32_32_32, TYPE_SINT, CFMT_32_32_32_SINT}, + {FMT_32_32_32, TYPE_FLOAT, CFMT_32_32_32_FLOAT}, + {FMT_32_32_32_32, TYPE_UINT, CFMT_32_32_32_32_UINT}, + {FMT_32_32_32_32, TYPE_SINT, CFMT_32_32_32_32_SINT}, + {FMT_32_32_32_32, TYPE_FLOAT, CFMT_32_32_32_32_FLOAT}, + {FMT_5_5_5_1, TYPE_UNORM, CFMT_5_5_5_1_UNORM}, + {FMT_5_6_5, TYPE_UNORM, CFMT_5_6_5_UNORM}, + {FMT_8, TYPE_UNORM, CFMT_8_UNORM}, + {FMT_8, TYPE_SNORM, CFMT_8_SNORM}, + {FMT_8, TYPE_UINT, CFMT_8_UINT}, + {FMT_8, TYPE_SINT, CFMT_8_SINT}, + {FMT_8, TYPE_SRGB, CFMT_8_SRGB}, + {FMT_8_24, TYPE_UNORM, CFMT_8_24_UNORM}, + {FMT_8_24, TYPE_UINT, CFMT_8_24_UINT}, + {FMT_8_8, TYPE_UNORM, CFMT_8_8_UNORM}, + {FMT_8_8, TYPE_SNORM, CFMT_8_8_SNORM}, + {FMT_8_8, TYPE_UINT, CFMT_8_8_UINT}, + {FMT_8_8, TYPE_SINT, CFMT_8_8_SINT}, + {FMT_8_8, TYPE_SRGB, CFMT_8_8_SRGB}, + {FMT_8_8_8_8, TYPE_UNORM, CFMT_8_8_8_8_UNORM}, + {FMT_8_8_8_8, TYPE_SNORM, CFMT_8_8_8_8_SNORM}, + {FMT_8_8_8_8, TYPE_UINT, CFMT_8_8_8_8_UINT}, + {FMT_8_8_8_8, TYPE_SINT, CFMT_8_8_8_8_SINT}, + {FMT_8_8_8_8, TYPE_SRGB, CFMT_8_8_8_8_SRGB} +}; +static const int FormatLUTSize = sizeof(FormatLUT)/sizeof(formatconverstion_t); + +//Index in FormatLUT to start search, indexed by FMT enum. +static const int FormatEntryPoint[] = { + 57, + 40, + 5, + 47, + 26, + 10, + 57, + 57, + 1, + 20, + 52, + 29, + 15, + 32, + 35, + 57, + 39, + 0, + 38, + 57, + 45, + 24 +}; + +static FORMAT GetCombinedFormat(uint8_t fmt, uint8_t type) { + assert(fmt < sizeof(FormatEntryPoint)/sizeof(int) && "FMT out of range."); + int start = FormatEntryPoint[fmt]; + int stop = std::min(start + 6, FormatLUTSize); // Only 6 types are used in image_kv_lut.cpp + + for(int i=start; i> 3) * out.pitch; + size_t slicePitch = rowPitch * out.height; + if (desc.geometry != HSA_EXT_IMAGE_GEOMETRY_1DB && + image_data_layout == HSA_EXT_IMAGE_DATA_LAYOUT_LINEAR && + ((image_data_row_pitch && (rowPitch != image_data_row_pitch)) || + (image_data_slice_pitch && (slicePitch != image_data_slice_pitch)))) { + return static_cast( + HSA_EXT_STATUS_ERROR_IMAGE_PITCH_UNSUPPORTED); + } + + image_info.size = out.surfSize; + assert(image_info.size != 0); + image_info.alignment = out.baseAlign; + assert(image_info.alignment != 0); + + return HSA_STATUS_SUCCESS; +} + +bool ImageManagerGfx11::IsLocalMemory(const void* address) const { + return true; +} + +hsa_status_t ImageManagerGfx11::PopulateImageSrd(Image& image, + const metadata_amd_t* descriptor) const { + const metadata_amd_nv_t* desc = + reinterpret_cast(descriptor); + bool atc_access = true; + const void* image_data_addr = image.data; + + ImageProperty image_prop = + image_lut_.MapFormat(image.desc.format, image.desc.geometry); + if ((image_prop.cap == HSA_EXT_IMAGE_CAPABILITY_NOT_SUPPORTED) || + (image_prop.element_size == 0)) + return (hsa_status_t)HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED; + + const Swizzle swizzle = + image_lut_.MapSwizzle(image.desc.format.channel_order); + + if (IsLocalMemory(image.data)) { + atc_access = false; + image_data_addr = reinterpret_cast( + reinterpret_cast(image.data) - local_memory_base_address_); + } + + image.srd[0] = desc->word0.u32All; + image.srd[1] = desc->word1.u32All; + image.srd[2] = desc->word2.u32All; + image.srd[3] = desc->word3.u32All; + image.srd[4] = desc->word4.u32All; + image.srd[5] = desc->word5.u32All; + image.srd[6] = desc->word6.u32All; + image.srd[7] = desc->word7.u32All; + + if (image.desc.geometry == HSA_EXT_IMAGE_GEOMETRY_1DB) { + SQ_BUF_RSRC_WORD0 word0; + SQ_BUF_RSRC_WORD1 word1; + SQ_BUF_RSRC_WORD2 word2; + SQ_BUF_RSRC_WORD3 word3; + + word0.val = 0; + word0.f.BASE_ADDRESS = PtrLow32(image_data_addr); + + word1.val = image.srd[1]; + word1.f.BASE_ADDRESS_HI = PtrHigh32(image_data_addr); + word1.f.STRIDE = image_prop.element_size; + + word3.val = image.srd[3]; + word3.f.DST_SEL_X = swizzle.x; + word3.f.DST_SEL_Y = swizzle.y; + word3.f.DST_SEL_Z = swizzle.z; + word3.f.DST_SEL_W = swizzle.w; + + word3.f.FORMAT = GetCombinedFormat(image_prop.data_format, image_prop.data_type); + word3.f.INDEX_STRIDE = image_prop.element_size; + + image.srd[0] = word0.val; + image.srd[1] = word1.val; + image.srd[3] = word3.val; + } else { + uint32_t hwPixelSize = image_lut_.GetPixelSize(image_prop.data_format, image_prop.data_type); + + if (image_prop.element_size != hwPixelSize) { + return (hsa_status_t)HSA_EXT_STATUS_ERROR_IMAGE_FORMAT_UNSUPPORTED; + } + reinterpret_cast(&image.srd[0])->bits.BASE_ADDRESS = + PtrLow40Shift8(image_data_addr); + reinterpret_cast(&image.srd[1])->bits.BASE_ADDRESS_HI = + PtrHigh64Shift40(image_data_addr); + reinterpret_cast(&image.srd[1])->bits.FORMAT = GetCombinedFormat(image_prop.data_format, image_prop.data_type); + reinterpret_cast(&image.srd[3])->bits.DST_SEL_X = + swizzle.x; + reinterpret_cast(&image.srd[3])->bits.DST_SEL_Y = + swizzle.y; + reinterpret_cast(&image.srd[3])->bits.DST_SEL_Z = + swizzle.z; + reinterpret_cast(&image.srd[3])->bits.DST_SEL_W = + swizzle.w; + if (image.desc.geometry == HSA_EXT_IMAGE_GEOMETRY_1DA || + image.desc.geometry == HSA_EXT_IMAGE_GEOMETRY_1D) { + reinterpret_cast(&image.srd[3])->bits.TYPE = + image_lut_.MapGeometry(image.desc.geometry); + } + + // Imported metadata holds the offset to metadata, add the image base address. + uintptr_t meta = uintptr_t(((SQ_IMG_RSRC_WORD7*)(&image.srd[7]))->bits.META_DATA_ADDRESS_HI) << 16; + meta |= uintptr_t(((SQ_IMG_RSRC_WORD6*)(&image.srd[6]))->bits.META_DATA_ADDRESS) << 8; + meta += reinterpret_cast(image_data_addr); + + ((SQ_IMG_RSRC_WORD6*)(&image.srd[6]))->bits.META_DATA_ADDRESS = PtrLow16Shift8((void*)meta); + ((SQ_IMG_RSRC_WORD7*)(&image.srd[7]))->bits.META_DATA_ADDRESS_HI = + PtrHigh64Shift16((void*)meta); + } + // Looks like this is only used for CPU copies. + image.row_pitch = 0; + image.slice_pitch = 0; + + // Used by HSAIL shader ABI + image.srd[8] = image.desc.format.channel_type; + image.srd[9] = image.desc.format.channel_order; + image.srd[10] = static_cast(image.desc.width); + + return HSA_STATUS_SUCCESS; +} + +static TEX_BC_SWIZZLE GetBcSwizzle(const Swizzle& swizzle) { + SEL r = (SEL)swizzle.x; + SEL g = (SEL)swizzle.y; + SEL b = (SEL)swizzle.z; + SEL a = (SEL)swizzle.w; + + TEX_BC_SWIZZLE bcSwizzle = TEX_BC_Swizzle_XYZW; + + if (a == SEL_X) { + // Have to use either TEX_BC_Swizzle_WZYX or TEX_BC_Swizzle_WXYZ + // + // For the pre-defined border color values (white, opaque black, + // transparent black), the only thing that matters is that the alpha + // channel winds up in the correct place (because the RGB channels are + // all the same) so either of these TEX_BC_Swizzle enumerations will + // work. Not sure what happens with border color palettes. + if (b == SEL_Y) { + // ABGR + bcSwizzle = TEX_BC_Swizzle_WZYX; + } else if ((r == SEL_X) && (g == SEL_X) && (b == SEL_X)) { + // RGBA + bcSwizzle = TEX_BC_Swizzle_XYZW; + } else { + // ARGB + bcSwizzle = TEX_BC_Swizzle_WXYZ; + } + } else if (r == SEL_X) { + // Have to use either TEX_BC_Swizzle_XYZW or TEX_BC_Swizzle_XWYZ + if (g == SEL_Y) { + // RGBA + bcSwizzle = TEX_BC_Swizzle_XYZW; + } else if ((g == SEL_X) && (b == SEL_X) && (a == SEL_W)) { + // RGBA + bcSwizzle = TEX_BC_Swizzle_XYZW; + } else { + // RAGB + bcSwizzle = TEX_BC_Swizzle_XWYZ; + } + } else if (g == SEL_X) { + // GRAB, have to use TEX_BC_Swizzle_YXWZ + bcSwizzle = TEX_BC_Swizzle_YXWZ; + } else if (b == SEL_X) { + // BGRA, have to use TEX_BC_Swizzle_ZYXW + bcSwizzle = TEX_BC_Swizzle_ZYXW; + } + + return bcSwizzle; +} + + +hsa_status_t ImageManagerGfx11::PopulateImageSrd(Image& image) const { + ImageProperty image_prop = + image_lut_.MapFormat(image.desc.format, image.desc.geometry); + assert(image_prop.cap != HSA_EXT_IMAGE_CAPABILITY_NOT_SUPPORTED); + assert(image_prop.element_size != 0); + + bool atc_access = true; + const void* image_data_addr = image.data; + + if (IsLocalMemory(image.data)) { + atc_access = false; + image_data_addr = reinterpret_cast( + reinterpret_cast(image.data) - local_memory_base_address_); + } + + if (image.desc.geometry == HSA_EXT_IMAGE_GEOMETRY_1DB) { + SQ_BUF_RSRC_WORD0 word0; + SQ_BUF_RSRC_WORD1 word1; + SQ_BUF_RSRC_WORD2 word2; + SQ_BUF_RSRC_WORD3 word3; + + word0.val = 0; + word0.f.BASE_ADDRESS = PtrLow32(image_data_addr); + + word1.val = 0; + word1.f.BASE_ADDRESS_HI = PtrHigh32(image_data_addr); + word1.f.STRIDE = image_prop.element_size; + word1.f.SWIZZLE_ENABLE = 0; + + word2.f.NUM_RECORDS = image.desc.width * image_prop.element_size; + + const Swizzle swizzle = + image_lut_.MapSwizzle(image.desc.format.channel_order); + word3.val = 0; + word3.f.RESOURCE_LEVEL = 1; + word3.f.DST_SEL_X = swizzle.x; + word3.f.DST_SEL_Y = swizzle.y; + word3.f.DST_SEL_Z = swizzle.z; + word3.f.DST_SEL_W = swizzle.w; + word3.f.FORMAT = GetCombinedFormat(image_prop.data_format, image_prop.data_type); + word3.f.INDEX_STRIDE = image_prop.element_size; + word3.f.TYPE = image_lut_.MapGeometry(image.desc.geometry); + + image.srd[0] = word0.val; + image.srd[1] = word1.val; + image.srd[2] = word2.val; + image.srd[3] = word3.val; + + image.row_pitch = image.desc.width * image_prop.element_size; + image.slice_pitch = image.row_pitch; + } else { + SQ_IMG_RSRC_WORD0 word0; + SQ_IMG_RSRC_WORD1 word1; + SQ_IMG_RSRC_WORD2 word2; + SQ_IMG_RSRC_WORD3 word3; + SQ_IMG_RSRC_WORD4 word4; + SQ_IMG_RSRC_WORD5 word5; + SQ_IMG_RSRC_WORD5 word6; + SQ_IMG_RSRC_WORD5 word7; + + ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0}; + + uint32_t swizzleMode = GetAddrlibSurfaceInfoNv( + image.component, image.desc, image.tile_mode, + image.row_pitch, image.slice_pitch, out); + if (swizzleMode == (uint32_t)(-1)) { + return HSA_STATUS_ERROR; + } + + assert((out.bpp / 8) == image_prop.element_size); + + const size_t row_pitch_size = out.pitch * image_prop.element_size; + + word0.f.BASE_ADDRESS = PtrLow40Shift8(image_data_addr); + + word1.val = 0; + word1.f.BASE_ADDRESS_HI = PtrHigh64Shift40(image_data_addr); + word1.f.FORMAT = GetCombinedFormat(image_prop.data_format, image_prop.data_type); + // Only take the lowest 2 bits of (image.desc.width - 1) + word1.f.WIDTH = BitSelect<0, 1>(image.desc.width - 1); + + word2.val = 0; + // Take the high 12 bits of (image.desc.width - 1) + word2.f.WIDTH_HI = BitSelect<2, 13>(image.desc.width - 1); + word2.f.HEIGHT = image.desc.height ? image.desc.height - 1 : 0; + + const Swizzle swizzle = + image_lut_.MapSwizzle(image.desc.format.channel_order); + word3.val = 0; + word3.f.DST_SEL_X = swizzle.x; + word3.f.DST_SEL_Y = swizzle.y; + word3.f.DST_SEL_Z = swizzle.z; + word3.f.DST_SEL_W = swizzle.w; + word3.f.SW_MODE = swizzleMode; + word3.f.BC_SWIZZLE = GetBcSwizzle(swizzle); + word3.f.TYPE = image_lut_.MapGeometry(image.desc.geometry); + + const bool image_array = + (image.desc.geometry == HSA_EXT_IMAGE_GEOMETRY_1DA || + image.desc.geometry == HSA_EXT_IMAGE_GEOMETRY_2DA || + image.desc.geometry == HSA_EXT_IMAGE_GEOMETRY_2DADEPTH); + const bool image_3d = (image.desc.geometry == HSA_EXT_IMAGE_GEOMETRY_3D); + + word4.val = 0; + word4.f.DEPTH = + (image_array) // Doesn't hurt but isn't array_size already >0? + ? std::max(image.desc.array_size, static_cast(1)) - 1 + : (image_3d) ? image.desc.depth - 1 : 0; + + // For 1d, 2d and 2d-msaa in gfx11 this is pitch-1 + if (!image_array && !image_3d) word4.f.PITCH = out.pitch - 1; + + word5.val = 0; + word6.val = 0; + word7.val = 0; + + image.srd[0] = word0.val; + image.srd[1] = word1.val; + image.srd[2] = word2.val; + image.srd[3] = word3.val; + image.srd[4] = word4.val; + image.srd[5] = word5.val; + image.srd[6] = word6.val; + image.srd[7] = word7.val; + + image.row_pitch = row_pitch_size; + image.slice_pitch = out.sliceSize; + } + + image.srd[8] = image.desc.format.channel_type; + image.srd[9] = image.desc.format.channel_order; + image.srd[10] = static_cast(image.desc.width); + + return HSA_STATUS_SUCCESS; +} + +hsa_status_t ImageManagerGfx11::ModifyImageSrd( + Image& image, hsa_ext_image_format_t& new_format) const { + image.desc.format = new_format; + + ImageProperty image_prop = + image_lut_.MapFormat(image.desc.format, image.desc.geometry); + assert(image_prop.cap != HSA_EXT_IMAGE_CAPABILITY_NOT_SUPPORTED); + assert(image_prop.element_size != 0); + + if (image.desc.geometry == HSA_EXT_IMAGE_GEOMETRY_1DB) { + const Swizzle swizzle = + image_lut_.MapSwizzle(image.desc.format.channel_order); + SQ_BUF_RSRC_WORD3* word3 = + reinterpret_cast(&image.srd[3]); + word3->bits.DST_SEL_X = swizzle.x; + word3->bits.DST_SEL_Y = swizzle.y; + word3->bits.DST_SEL_Z = swizzle.z; + word3->bits.DST_SEL_W = swizzle.w; + word3->bits.FORMAT = GetCombinedFormat(image_prop.data_format, image_prop.data_type); + } else { + SQ_IMG_RSRC_WORD1* word1 = + reinterpret_cast(&image.srd[1]); + word1->bits.FORMAT = GetCombinedFormat(image_prop.data_format, image_prop.data_type); + + const Swizzle swizzle = + image_lut_.MapSwizzle(image.desc.format.channel_order); + SQ_IMG_RSRC_WORD3* word3 = + reinterpret_cast(&image.srd[3]); + word3->bits.DST_SEL_X = swizzle.x; + word3->bits.DST_SEL_Y = swizzle.y; + word3->bits.DST_SEL_Z = swizzle.z; + word3->bits.DST_SEL_W = swizzle.w; + } + + image.srd[8] = image.desc.format.channel_type; + image.srd[9] = image.desc.format.channel_order; + image.srd[10] = static_cast(image.desc.width); + + return HSA_STATUS_SUCCESS; +} + +hsa_status_t ImageManagerGfx11::PopulateSamplerSrd(Sampler& sampler) const { + const hsa_ext_sampler_descriptor_t sampler_descriptor = sampler.desc; + + SQ_IMG_SAMP_WORD0 word0; + SQ_IMG_SAMP_WORD1 word1; + SQ_IMG_SAMP_WORD2 word2; + SQ_IMG_SAMP_WORD3 word3; + + word0.u32All = 0; + switch (sampler_descriptor.address_mode) { + case HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_EDGE: + word0.bits.CLAMP_X = static_cast(SQ_TEX_CLAMP_LAST_TEXEL); + break; + case HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_BORDER: + word0.bits.CLAMP_X = static_cast(SQ_TEX_CLAMP_BORDER); + break; + case HSA_EXT_SAMPLER_ADDRESSING_MODE_MIRRORED_REPEAT: + word0.bits.CLAMP_X = static_cast(SQ_TEX_MIRROR); + break; + case HSA_EXT_SAMPLER_ADDRESSING_MODE_UNDEFINED: + case HSA_EXT_SAMPLER_ADDRESSING_MODE_REPEAT: + word0.bits.CLAMP_X = static_cast(SQ_TEX_WRAP); + break; + default: + return HSA_STATUS_ERROR_INVALID_ARGUMENT; + } + word0.bits.CLAMP_Y = word0.bits.CLAMP_X; + word0.bits.CLAMP_Z = word0.bits.CLAMP_X; + word0.bits.FORCE_UNNORMALIZED = (sampler_descriptor.coordinate_mode == + HSA_EXT_SAMPLER_COORDINATE_MODE_UNNORMALIZED); + + word1.u32All = 0; + word1.bits.MAX_LOD = 4095; + + word2.u32All = 0; + switch (sampler_descriptor.filter_mode) { + case HSA_EXT_SAMPLER_FILTER_MODE_NEAREST: + word2.bits.XY_MAG_FILTER = static_cast(SQ_TEX_XY_FILTER_POINT); + break; + case HSA_EXT_SAMPLER_FILTER_MODE_LINEAR: + word2.bits.XY_MAG_FILTER = static_cast(SQ_TEX_XY_FILTER_BILINEAR); + break; + default: + return HSA_STATUS_ERROR_INVALID_ARGUMENT; + } + word2.bits.XY_MIN_FILTER = word2.bits.XY_MAG_FILTER; + word2.bits.Z_FILTER = SQ_TEX_Z_FILTER_NONE; + word2.bits.MIP_FILTER = SQ_TEX_MIP_FILTER_NONE; + + word3.u32All = 0; + + // TODO: check this bit with HSAIL spec. + word3.bits.BORDER_COLOR_TYPE = SQ_TEX_BORDER_COLOR_TRANS_BLACK; + + sampler.srd[0] = word0.u32All; + sampler.srd[1] = word1.u32All; + sampler.srd[2] = word2.u32All; + sampler.srd[3] = word3.u32All; + + return HSA_STATUS_SUCCESS; +} + +uint32_t ImageManagerGfx11::GetAddrlibSurfaceInfoNv( + hsa_agent_t component, const hsa_ext_image_descriptor_t& desc, + Image::TileMode tileMode, + size_t image_data_row_pitch, + size_t image_data_slice_pitch, + ADDR2_COMPUTE_SURFACE_INFO_OUTPUT& out) const { + const ImageProperty image_prop = + GetImageProperty(component, desc.format, desc.geometry); + + const AddrFormat addrlib_format = GetAddrlibFormat(image_prop); + + const uint32_t width = static_cast(desc.width); + const uint32_t height = static_cast(desc.height); + static const size_t kMinNumSlice = 1; + const uint32_t num_slice = static_cast( + std::max(kMinNumSlice, std::max(desc.array_size, desc.depth))); + + uint32_t minor_ver = MinorVerFromDevID(chip_id_); + ADDR2_COMPUTE_SURFACE_INFO_INPUT in = {0}; + in.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT); + in.format = addrlib_format; + in.bpp = static_cast(image_prop.element_size) * 8; + in.width = width; + in.height = height; + in.numSlices = num_slice; + in.pitchInElement = image_data_row_pitch / image_prop.element_size; + + switch (desc.geometry) { + case HSA_EXT_IMAGE_GEOMETRY_1D: + case HSA_EXT_IMAGE_GEOMETRY_1DB: + case HSA_EXT_IMAGE_GEOMETRY_1DA: + in.resourceType = ADDR_RSRC_TEX_1D; + break; + + case HSA_EXT_IMAGE_GEOMETRY_2D: + case HSA_EXT_IMAGE_GEOMETRY_2DDEPTH: + case HSA_EXT_IMAGE_GEOMETRY_2DA: + case HSA_EXT_IMAGE_GEOMETRY_2DADEPTH: + in.resourceType = ADDR_RSRC_TEX_2D; + break; + + case HSA_EXT_IMAGE_GEOMETRY_3D: + in.resourceType = ADDR_RSRC_TEX_3D; + break; + } + in.flags.texture = 1; + + ADDR2_GET_PREFERRED_SURF_SETTING_INPUT prefSettingsInput = { 0 }; + ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT prefSettingsOutput = { 0 }; + + prefSettingsInput.size = sizeof(prefSettingsInput); + prefSettingsInput.flags = in.flags; + prefSettingsInput.bpp = in.bpp; + prefSettingsInput.format = in.format; + prefSettingsInput.width = in.width; + prefSettingsInput.height = in.height; + prefSettingsInput.numFrags = in.numFrags; + prefSettingsInput.numSamples = in.numSamples; + prefSettingsInput.numMipLevels = in.numMipLevels; + prefSettingsInput.numSlices = in.numSlices; + prefSettingsInput.resourceLoction = ADDR_RSRC_LOC_UNDEF; + prefSettingsInput.resourceType = in.resourceType; + + // Disallow all swizzles but linear. + if (tileMode == Image::TileMode::LINEAR) { + prefSettingsInput.forbiddenBlock.macroThin4KB = 1; + prefSettingsInput.forbiddenBlock.macroThick4KB = 1; + prefSettingsInput.forbiddenBlock.macroThin64KB = 1; + prefSettingsInput.forbiddenBlock.macroThick64KB = 1; + prefSettingsInput.forbiddenBlock.micro = 1; + prefSettingsInput.forbiddenBlock.var = 1; + } else { + // Debug setting, simplifies buffer alignment until language runtimes have official gfx10 + // support. + prefSettingsInput.forbiddenBlock.macroThin64KB = 1; + prefSettingsInput.forbiddenBlock.macroThick64KB = 1; + } + + // but don't ever allow the 256b swizzle modes + //prefSettingsInput.forbiddenBlock.micro = 1; + // and don't allow variable-size block modes + //prefSettingsInput.forbiddenBlock.var = 1; + + if (ADDR_OK != Addr2GetPreferredSurfaceSetting(addr_lib_, + &prefSettingsInput, &prefSettingsOutput)) { + return (uint32_t)(-1); + } + + in.swizzleMode = prefSettingsOutput.swizzleMode; + + out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT); + if (ADDR_OK != Addr2ComputeSurfaceInfo(addr_lib_, &in, &out)) { + return (uint32_t)(-1); + } + if (out.surfSize == 0) { + return (uint32_t)(-1); + } + + return in.swizzleMode; +} + +hsa_status_t ImageManagerGfx11::FillImage(const Image& image, const void* pattern, + const hsa_ext_image_region_t& region) { + if (BlitQueueInit().queue_ == NULL) { + return HSA_STATUS_ERROR_OUT_OF_RESOURCES; + } + + Image* image_view = const_cast(&image); + + SQ_BUF_RSRC_WORD3* word3_buff = NULL; + SQ_IMG_RSRC_WORD3* word3_image = NULL; + uint32_t dst_sel_w_original = 0; + if (image_view->desc.format.channel_type == + HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_101010) { + // Force GPU to ignore the last two bits (alpha bits). + if (image_view->desc.geometry == HSA_EXT_IMAGE_GEOMETRY_1DB) { + word3_buff = reinterpret_cast(&image_view->srd[3]); + dst_sel_w_original = word3_buff->bits.DST_SEL_W; + word3_buff->bits.DST_SEL_W = SEL_0; + } else { + word3_image = reinterpret_cast(&image_view->srd[3]); + dst_sel_w_original = word3_image->bits.DST_SEL_W; + word3_image->bits.DST_SEL_W = SEL_0; + } + } + + SQ_IMG_RSRC_WORD1* word1 = NULL; + uint32_t num_format_original = 0; + const void* new_pattern = pattern; + float fill_value[4] = {0}; + switch (image_view->desc.format.channel_order) { + case HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBA: + case HSA_EXT_IMAGE_CHANNEL_ORDER_SRGB: + case HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBX: + case HSA_EXT_IMAGE_CHANNEL_ORDER_SBGRA: { + // KV and CZ don't have write support for SRGBA image, so convert pattern + // to standard form and treat the image as RGBA image. + const float* pattern_f = reinterpret_cast(pattern); + fill_value[0] = LinearToStandardRGB(pattern_f[0]); + fill_value[1] = LinearToStandardRGB(pattern_f[1]); + fill_value[2] = LinearToStandardRGB(pattern_f[2]); + fill_value[3] = pattern_f[3]; + new_pattern = fill_value; + + ImageProperty image_prop = image_lut_.MapFormat(image.desc.format, image.desc.geometry); + + word1 = reinterpret_cast(&image_view->srd[1]); + num_format_original = word1->bits.FORMAT; + word1->bits.FORMAT = GetCombinedFormat(image_prop.data_format, TYPE_UNORM); + } break; + default: + break; + } + + hsa_status_t status = ImageRuntime::instance()->blit_kernel().FillImage( + blit_queue_, blit_code_catalog_, *image_view, new_pattern, region); + + // Revert back original configuration. + if (word3_buff != NULL) { + word3_buff->bits.DST_SEL_W = dst_sel_w_original; + } + + if (word3_image != NULL) { + word3_image->bits.DST_SEL_W = dst_sel_w_original; + } + + if (word1 != NULL) { + word1->bits.FORMAT = num_format_original; + } + + return status; +} + +} // namespace image +} // namespace rocr diff --git a/projects/rocr-runtime/runtime/hsa-runtime/image/image_manager_gfx11.h b/projects/rocr-runtime/runtime/hsa-runtime/image/image_manager_gfx11.h new file mode 100755 index 0000000000..1b34bc751e --- /dev/null +++ b/projects/rocr-runtime/runtime/hsa-runtime/image/image_manager_gfx11.h @@ -0,0 +1,98 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// The University of Illinois/NCSA +// Open Source License (NCSA) +// +// Copyright (c) 2014-2021, Advanced Micro Devices, Inc. All rights reserved. +// +// Developed by: +// +// AMD Research and AMD HSA Software Development +// +// Advanced Micro Devices, Inc. +// +// www.amd.com +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to +// deal with the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimers. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimers in +// the documentation and/or other materials provided with the distribution. +// - Neither the names of Advanced Micro Devices, Inc, +// nor the names of its contributors may be used to endorse or promote +// products derived from this Software without specific prior written +// permission. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS WITH THE SOFTWARE. +// +//////////////////////////////////////////////////////////////////////////////// + +#ifndef EXT_IMAGE_IMAGE_MANAGER_GFX11_H_ +#define EXT_IMAGE_IMAGE_MANAGER_GFX11_H_ + +#include "addrlib/inc/addrinterface.h" //DYSDEBUG TODO: replace with new addrLib +#include "image_manager_kv.h" + +namespace rocr { +namespace image { + +class ImageManagerGfx11 : public ImageManagerKv { + public: + ImageManagerGfx11(); + virtual ~ImageManagerGfx11(); + + /// @brief Calculate the size and alignment of the backing storage of an + /// image. + virtual hsa_status_t CalculateImageSizeAndAlignment( + hsa_agent_t component, const hsa_ext_image_descriptor_t& desc, + hsa_ext_image_data_layout_t image_data_layout, + size_t image_data_row_pitch, size_t image_data_slice_pitch, + hsa_ext_image_data_info_t& image_info) const; + + /// @brief Fill image structure with device specific image object. + virtual hsa_status_t PopulateImageSrd(Image& image) const; + + /// @brief Fill image structure with device specific image object using the given format. + virtual hsa_status_t PopulateImageSrd(Image& image, const metadata_amd_t* desc) const; + + /// @brief Modify device specific image object according to the specified + /// new format. + virtual hsa_status_t ModifyImageSrd(Image& image, + hsa_ext_image_format_t& new_format) const; + + /// @brief Fill sampler structure with device specific sampler object. + virtual hsa_status_t PopulateSamplerSrd(Sampler& sampler) const; + + /// @brief Fill image backing storage using agent copy. + virtual hsa_status_t FillImage(const Image& image, const void* pattern, + const hsa_ext_image_region_t& region); + protected: + uint32_t GetAddrlibSurfaceInfoNv(hsa_agent_t component, + const hsa_ext_image_descriptor_t& desc, + Image::TileMode tileMode, + size_t image_data_row_pitch, + size_t image_data_slice_pitch, + ADDR2_COMPUTE_SURFACE_INFO_OUTPUT& out) const; + + bool IsLocalMemory(const void* address) const; + + private: + DISALLOW_COPY_AND_ASSIGN(ImageManagerGfx11); +}; + +} // namespace image +} // namespace rocr +#endif // EXT_IMAGE_IMAGE_MANAGER_GFX11_H_ diff --git a/projects/rocr-runtime/runtime/hsa-runtime/image/image_runtime.cpp b/projects/rocr-runtime/runtime/hsa-runtime/image/image_runtime.cpp index 5d2f136d62..770dd6e476 100755 --- a/projects/rocr-runtime/runtime/hsa-runtime/image/image_runtime.cpp +++ b/projects/rocr-runtime/runtime/hsa-runtime/image/image_runtime.cpp @@ -53,6 +53,7 @@ #include "image_manager_kv.h" #include "image_manager_ai.h" #include "image_manager_nv.h" +#include "image_manager_gfx11.h" #include "device_info.h" namespace rocr { @@ -108,7 +109,9 @@ hsa_status_t ImageRuntime::CreateImageManager(hsa_agent_t agent, void* data) { ImageManager* image_manager; - if (major_ver >= 10) { + if (major_ver >= 11) { + image_manager = new ImageManagerGfx11(); + } else if (major_ver >= 10) { image_manager = new ImageManagerNv(); } else if (major_ver >= 9) { image_manager = new ImageManagerAi(); diff --git a/projects/rocr-runtime/runtime/hsa-runtime/image/resource_gfx11.h b/projects/rocr-runtime/runtime/hsa-runtime/image/resource_gfx11.h new file mode 100755 index 0000000000..95efe26c57 --- /dev/null +++ b/projects/rocr-runtime/runtime/hsa-runtime/image/resource_gfx11.h @@ -0,0 +1,871 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// The University of Illinois/NCSA +// Open Source License (NCSA) +// +// Copyright (c) 2014-2020, Advanced Micro Devices, Inc. All rights reserved. +// +// Developed by: +// +// AMD Research and AMD HSA Software Development +// +// Advanced Micro Devices, Inc. +// +// www.amd.com +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to +// deal with the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimers. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimers in +// the documentation and/or other materials provided with the distribution. +// - Neither the names of Advanced Micro Devices, Inc, +// nor the names of its contributors may be used to endorse or promote +// products derived from this Software without specific prior written +// permission. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS WITH THE SOFTWARE. +// +//////////////////////////////////////////////////////////////////////////////// + +#ifndef EXT_IMAGE_RESOURCE_GFX11_H_ +#define EXT_IMAGE_RESOURCE_GFX11_H_ + +#if defined(LITTLEENDIAN_CPU) +#elif defined(BIGENDIAN_CPU) +#else +#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined" +#endif + +namespace rocr { +namespace image { + +/**********************************************************/ +/**********************************************************/ +#define SQ_BUF_RSC_WRD0_REG_SZ 32 +#define SQ_BUF_RSC_WRD0_BASE_ADDRESS_SZ 32 + +struct sq_buf_rsrc_word0_t { +#if defined(LITTLEENDIAN_CPU) + unsigned int BASE_ADDRESS : SQ_BUF_RSC_WRD0_BASE_ADDRESS_SZ; +#elif defined(BIGENDIAN_CPU) + unsigned int BASE_ADDRESS : SQ_BUF_RSC_WRD0_BASE_ADDRESS_SZ; +#endif +}; + +union SQ_BUF_RSRC_WORD0 { + sq_buf_rsrc_word0_t bitfields, bits, f; + uint32_t val : SQ_BUF_RSC_WRD0_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; + +/***********/ + +#define SQ_BUF_RSC_WRD1_REG_SZ 32 +#define SQ_BUF_RSC_WRD1_BASE_ADDRESS_HI_SZ 16 +#define SQ_BUF_RSC_WRD1_STRIDE_SZ 14 +#define SQ_BUF_RSC_WRD1_SWIZZLE_ENABLE_SZ 2 +struct sq_buf_rsrc_word1_t { +#if defined(LITTLEENDIAN_CPU) + unsigned int BASE_ADDRESS_HI : SQ_BUF_RSC_WRD1_BASE_ADDRESS_HI_SZ; + unsigned int STRIDE : SQ_BUF_RSC_WRD1_STRIDE_SZ; + unsigned int SWIZZLE_ENABLE : SQ_BUF_RSC_WRD1_SWIZZLE_ENABLE_SZ; +#elif defined(BIGENDIAN_CPU) + unsigned int SWIZZLE_ENABLE : SQ_BUF_RSC_WRD1_SWIZZLE_ENABLE_SZ; + unsigned int STRIDE : SQ_BUF_RSC_WRD1_STRIDE_SZ; + unsigned int BASE_ADDRESS_HI : SQ_BUF_RSC_WRD1_BASE_ADDRESS_HI_SZ; +#endif +}; + +union SQ_BUF_RSRC_WORD1 { + sq_buf_rsrc_word1_t bitfields, bits, f; + uint32_t val : SQ_BUF_RSC_WRD1_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; +/***********/ + +#define SQ_BUF_RSC_WRD2_REG_SZ 32 +#define SQ_BUF_RSC_WRD2_NUM_RECORDS_SZ 32 +struct sq_buf_rsrc_word2_t { +#if defined(LITTLEENDIAN_CPU) + unsigned int NUM_RECORDS : SQ_BUF_RSC_WRD2_NUM_RECORDS_SZ; +#elif defined(BIGENDIAN_CPU) + unsigned int NUM_RECORDS : SQ_BUF_RSC_WRD2_NUM_RECORDS_SZ; +#endif +}; +union SQ_BUF_RSRC_WORD2 { + sq_buf_rsrc_word2_t bitfields, bits, f; + uint32_t val : SQ_BUF_RSC_WRD2_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; +/***********/ + +#define SQ_BUF_RSC_WRD3_REG_SZ 32 +#define SQ_BUF_RSC_WRD3_DST_SEL_X_SZ 3 +#define SQ_BUF_RSC_WRD3_DST_SEL_Y_SZ 3 +#define SQ_BUF_RSC_WRD3_DST_SEL_Z_SZ 3 +#define SQ_BUF_RSC_WRD3_DST_SEL_W_SZ 3 +#define SQ_BUF_RSC_WRD3_FORMAT_SZ 6 +#define SQ_BUF_RSC_WRD3_INDEX_STRIDE_SZ 2 +#define SQ_BUF_RSC_WRD3_ADD_TID_ENABLE_SZ 1 +#define SQ_BUF_RSC_WRD3_RESOURCE_LEVEL 1 +#define SQ_BUF_RSC_WRD3_RESERVED_1 2 +#define SQ_BUF_RSC_WORD3_OOB_SELECT_SZ 2 +#define SQ_BUF_RSC_WRD3_TYPE_SZ 2 +struct sq_buf_rsrc_word3_t { +#if defined(LITTLEENDIAN_CPU) + unsigned int DST_SEL_X : SQ_BUF_RSC_WRD3_DST_SEL_X_SZ; + unsigned int DST_SEL_Y : SQ_BUF_RSC_WRD3_DST_SEL_Y_SZ; + unsigned int DST_SEL_Z : SQ_BUF_RSC_WRD3_DST_SEL_Z_SZ; + unsigned int DST_SEL_W : SQ_BUF_RSC_WRD3_DST_SEL_W_SZ; + unsigned int FORMAT : SQ_BUF_RSC_WRD3_FORMAT_SZ; + unsigned int : 3; + unsigned int INDEX_STRIDE : SQ_BUF_RSC_WRD3_INDEX_STRIDE_SZ; + unsigned int ADD_TID_ENABLE : SQ_BUF_RSC_WRD3_ADD_TID_ENABLE_SZ; + unsigned int RESOURCE_LEVEL : SQ_BUF_RSC_WRD3_RESOURCE_LEVEL; + unsigned int : 1; + unsigned int RESERVED_1 : SQ_BUF_RSC_WRD3_RESERVED_1; + unsigned int OOB_SELECT : SQ_BUF_RSC_WORD3_OOB_SELECT_SZ; + unsigned int TYPE : SQ_BUF_RSC_WRD3_TYPE_SZ; + +#elif defined(BIGENDIAN_CPU) + unsigned int TYPE : SQ_BUF_RSC_WRD3_TYPE_SZ; + unsigned int OOB_SELECT : SQ_BUF_RSC_WORD3_OOB_SELECT_SZ; + unsigned int RESERVED_1 : SQ_BUF_RSC_WRD3_RESERVED_1; + unsigned int : 1; + unsigned int RESOURCE_LEVEL : SQ_BUF_RSC_WRD3_RESOURCE_LEVEL; + unsigned int ADD_TID_ENABLE : SQ_BUF_RSC_WRD3_ADD_TID_ENABLE_SZ; + unsigned int INDEX_STRIDE : SQ_BUF_RSC_WRD3_INDEX_STRIDE_SZ; + unsigned int : 3; + unsigned int FORMAT : SQ_BUF_RSC_WRD3_FORMAT_SZ; + unsigned int DST_SEL_W : SQ_BUF_RSC_WRD3_DST_SEL_W_SZ; + unsigned int DST_SEL_Z : SQ_BUF_RSC_WRD3_DST_SEL_Z_SZ; + unsigned int DST_SEL_Y : SQ_BUF_RSC_WRD3_DST_SEL_Y_SZ; + unsigned int DST_SEL_X : SQ_BUF_RSC_WRD3_DST_SEL_X_SZ; + +#endif +}; +union SQ_BUF_RSRC_WORD3 { + sq_buf_rsrc_word3_t bitfields, bits, f; + uint32_t val : SQ_BUF_RSC_WRD3_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; +/***********/ + +/**********************************************************/ +/**********************************************************/ +#define SQ_IMG_RSC_WRD0_REG_SZ 32 +#define SQ_IMG_RSC_WRD0_BASE_ADDRESS_SZ 32 +struct sq_img_rsrc_word0_t { +#if defined(LITTLEENDIAN_CPU) + unsigned int BASE_ADDRESS : SQ_IMG_RSC_WRD0_BASE_ADDRESS_SZ; +#elif defined(BIGENDIAN_CPU) + unsigned int BASE_ADDRESS : SQ_IMG_RSC_WRD0_BASE_ADDRESS_SZ; +#endif +}; +union SQ_IMG_RSRC_WORD0 { + sq_img_rsrc_word0_t bitfields, bits, f; + uint32_t val : SQ_IMG_RSC_WRD0_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; +/***********/ + +#define SQ_IMG_RSC_WRD1_REG_SZ 32 +#define SQ_IMG_RSC_WRD1_BASE_ADDRESS_HI_SZ 8 +#define SQ_IMG_RSC_WRD1_RESERVED_2_SZ 2 +#define SQ_IMG_RSC_WRD1_BIG_PAGE_SZ 1 +#define SQ_IMG_RSC_WRD1_MAX_MIP_SZ 4 +#define SQ_IMG_RSC_WRD1_FORMAT_SZ 8 +#define SQ_IMG_RSC_WRD1_WIDTH_LO 2 + +struct sq_img_rsrc_word1_t{ +#if defined(LITTLEENDIAN_CPU) + unsigned int BASE_ADDRESS_HI : SQ_IMG_RSC_WRD1_BASE_ADDRESS_HI_SZ; + unsigned int : 5; + unsigned int RESERVED_2 : SQ_IMG_RSC_WRD1_RESERVED_2_SZ; + unsigned int BIG_PAGE : SQ_IMG_RSC_WRD1_BIG_PAGE_SZ; + unsigned int MAX_MIP : SQ_IMG_RSC_WRD1_MAX_MIP_SZ; + unsigned int FORMAT : SQ_IMG_RSC_WRD1_FORMAT_SZ; + unsigned int : 2; + unsigned int WIDTH : SQ_IMG_RSC_WRD1_WIDTH_LO; +#elif defined(BIGENDIAN_CPU) + unsigned int WIDTH : SQ_IMG_RSC_WRD1_WIDTH_LO; + unsigned int : 2; + unsigned int FORMAT : SQ_IMG_RSC_WRD1_FORMAT_SZ; + unsigned int MAX_MIP : SQ_IMG_RSC_WRD1_MAX_MIP_SZ; + unsigned int BIG_PAGE : SQ_IMG_RSC_WRD1_BIG_PAGE_SZ; + unsigned int RESERVED_2 : SQ_IMG_RSC_WRD1_RESERVED_2_SZ; + unsigned int : 5; + unsigned int BASE_ADDRESS_HI : SQ_IMG_RSC_WRD1_BASE_ADDRESS_HI_SZ; +#endif +}; +union SQ_IMG_RSRC_WORD1 { + sq_img_rsrc_word1_t bitfields, bits, f; + uint32_t val : SQ_IMG_RSC_WRD1_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; +/***********/ + +#define SQ_IMG_RSC_WRD2_REG_SZ 32 +#define SQ_IMG_RSC_WRD2_WIDTH_HI_SZ 12 +#define SQ_IMG_RSC_WRD2_HEIGHT_SZ 14 +#define SQ_IMG_RSC_WRD2_RESOURCE_LEVEL_SZ 1 +struct sq_img_rsrc_word2_t { +#if defined(LITTLEENDIAN_CPU) + unsigned int WIDTH_HI : SQ_IMG_RSC_WRD2_WIDTH_HI_SZ; + unsigned int : 2; + unsigned int HEIGHT : SQ_IMG_RSC_WRD2_HEIGHT_SZ; + unsigned int : 2; + unsigned int : 2; +#elif defined(BIGENDIAN_CPU) + unsigned int : 2; + unsigned int : 2; + unsigned int HEIGHT : SQ_IMG_RSC_WRD2_HEIGHT_SZ; + unsigned int : 2; + unsigned int WIDTH_HI : SQ_IMG_RSC_WRD2_WIDTH_SZ; +#endif +}; +union SQ_IMG_RSRC_WORD2 { + sq_img_rsrc_word2_t bitfields, bits, f; + uint32_t val : SQ_IMG_RSC_WRD2_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; +/***********/ + +#define SQ_IMG_RSC_WRD3_REG_SZ 32 +#define SQ_IMG_RSC_WRD3_DST_SEL_X_SZ 3 +#define SQ_IMG_RSC_WRD3_DST_SEL_Y_SZ 3 +#define SQ_IMG_RSC_WRD3_DST_SEL_Z_SZ 3 +#define SQ_IMG_RSC_WRD3_DST_SEL_W_SZ 3 +#define SQ_IMG_RSC_WRD3_BASE_LEVEL_SZ 4 +#define SQ_IMG_RSC_WRD3_LAST_LEVEL_SZ 4 +#define SQ_IMG_RSC_WRD3_SW_MODE_SZ 5 +#define SQ_IMG_RSC_WRD3_BC_SWIZZLE_SZ 3 +#define SQ_IMG_RSC_WRD3_TYPE_SZ 4 +struct sq_img_rsrc_word3_t { +#if defined(LITTLEENDIAN_CPU) + unsigned int DST_SEL_X : SQ_IMG_RSC_WRD3_DST_SEL_X_SZ; + unsigned int DST_SEL_Y : SQ_IMG_RSC_WRD3_DST_SEL_Y_SZ; + unsigned int DST_SEL_Z : SQ_IMG_RSC_WRD3_DST_SEL_Z_SZ; + unsigned int DST_SEL_W : SQ_IMG_RSC_WRD3_DST_SEL_W_SZ; + unsigned int BASE_LEVEL : SQ_IMG_RSC_WRD3_BASE_LEVEL_SZ; + unsigned int LAST_LEVEL : SQ_IMG_RSC_WRD3_LAST_LEVEL_SZ; + unsigned int SW_MODE : SQ_IMG_RSC_WRD3_SW_MODE_SZ; + unsigned int BC_SWIZZLE : SQ_IMG_RSC_WRD3_BC_SWIZZLE_SZ; + unsigned int TYPE : SQ_IMG_RSC_WRD3_TYPE_SZ; +#elif defined(BIGENDIAN_CPU) + unsigned int TYPE : SQ_IMG_RSC_WRD3_TYPE_SZ; + unsigned int BC_SWIZZLE : SQ_IMG_RSC_WRD3_BC_SWIZZLE_SZ; + unsigned int W_MODE : SQ_IMG_RSC_WRD3_SW_MODE_SZ; + unsigned int LAST_LEVEL : SQ_IMG_RSC_WRD3_LAST_LEVEL_SZ; + unsigned int BASE_LEVEL : SQ_IMG_RSC_WRD3_BASE_LEVEL_SZ; + unsigned int DST_SEL_W : SQ_IMG_RSC_WRD3_DST_SEL_W_SZ; + unsigned int DST_SEL_Z : SQ_IMG_RSC_WRD3_DST_SEL_Z_SZ; + unsigned int DST_SEL_Y : SQ_IMG_RSC_WRD3_DST_SEL_Y_SZ; + unsigned int DST_SEL_X : SQ_IMG_RSC_WRD3_DST_SEL_X_SZ; +#endif +}; +union SQ_IMG_RSRC_WORD3 { + sq_img_rsrc_word3_t bitfields, bits, f; + uint32_t val : SQ_IMG_RSC_WRD3_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; +/***********/ + +#define SQ_IMG_RSC_WRD4_REG_SZ 32 +#define SQ_IMG_RSC_WRD4_DEPTH_SZ 13 +#define SQ_IMG_RSC_WRD4_BASE_ARR_SZ 13 +#define SQ_IMG_RSC_WRD4_PITCH_SZ 14 +union sq_img_rsrc_word4_t { + struct { +#if defined(LITTLEENDIAN_CPU) + // For arrays this is last slice in view, for 3D this is depth-1, For remaining this is pitch-1 + unsigned int DEPTH : SQ_IMG_RSC_WRD4_DEPTH_SZ; + unsigned int : 1; //Pitch[13] in gfx1030 + unsigned int : 2; + unsigned int BASE_ARRAY : SQ_IMG_RSC_WRD4_BASE_ARR_SZ; + unsigned int : 3; +#elif defined(BIGENDIAN_CPU) + unsigned int : 3; + unsigned int BASE_ARRAY : SQ_IMG_RSC_WRD4_BASE_ARR_SZ; + unsigned int : 2; + unsigned int : 1; //Pitch[13] in gfx1030 + unsigned int DEPTH : SQ_IMG_RSC_WRD4_DEPTH_SZ; //Pitch[0:12] in gfx1030 +#endif + }; + struct { +#if defined(LITTLEENDIAN_CPU) + // For 1d, 2d and 2d-msaa in gfx1030 this is pitch-1 + unsigned int PITCH : SQ_IMG_RSC_WRD4_PITCH_SZ; + unsigned int : SQ_IMG_RSC_WRD4_REG_SZ-SQ_IMG_RSC_WRD4_PITCH_SZ; +#elif defined(BIGENDIAN_CPU) + unsigned int : SQ_IMG_RSC_WRD4_REG_SZ-SQ_IMG_RSC_WRD4_PITCH_SZ; + unsigned int PITCH : SQ_IMG_RSC_WRD4_PITCH_SZ; +#endif + }; +}; +union SQ_IMG_RSRC_WORD4 { + sq_img_rsrc_word4_t bitfields, bits, f; + uint32_t val : SQ_IMG_RSC_WRD4_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; +/***********/ + +#define SQ_IMG_RSC_WRD5_REG_SZ 32 +#define SQ_IMG_RSC_WRD5_ARRAY_PITCH_SZ 4 +#define SQ_IMG_RSC_WRD5_MID_LOD_WRN_SZ 12 +#define SQ_IMG_RSC_WRD5_PERF_MOD_SZ 3 +#define SQ_IMG_RSC_WRD5_CORNER_SAMPLES_SZ 1 +#define SQ_IMG_RSC_WRD5_LINKED_RESOURCE_SZ 1 +#define SQ_IMG_RSC_WRD5_PRT_DEFAULT_SZ 1 +#define SQ_IMG_RSC_WRD5_MIN_LOD_LO_SZ 5 + +struct sq_img_rsrc_word5_t { +#if defined(LITTLEENDIAN_CPU) + unsigned int ARRAY_PITCH : SQ_IMG_RSC_WRD5_ARRAY_PITCH_SZ; + unsigned int : 4; + unsigned int MID_LOD_WRN : SQ_IMG_RSC_WRD5_MID_LOD_WRN_SZ; + unsigned int PERF_MOD : SQ_IMG_RSC_WRD5_PERF_MOD_SZ; + unsigned int CORNER_SAMPLES : SQ_IMG_RSC_WRD5_CORNER_SAMPLES_SZ; + unsigned int LINKED_RESOURCE : SQ_IMG_RSC_WRD5_LINKED_RESOURCE_SZ; + unsigned int PRT_DEFAULT : SQ_IMG_RSC_WRD5_PRT_DEFAULT_SZ; + unsigned int MIN_LOD_LO : SQ_IMG_RSC_WRD5_MIN_LOD_LO_SZ; + unsigned int : 4; + +#elif defined(BIGENDIAN_CPU) + unsigned int : 4; + unsigned int MIN_LOD_LO : SQ_IMG_RSC_WRD5_MIN_LOD_LO_SZ; + unsigned int PRT_DEFAULT : SQ_IMG_RSC_WRD5_PRT_DEFAULT_SZ; + unsigned int LINKED_RESOURCE : SQ_IMG_RSC_WRD5_LINKED_RESOURCE_SZ; + unsigned int CORNER_SAMPLES : SQ_IMG_RSC_WRD5_CORNER_SAMPLES_SZ; + unsigned int PERF_MOD : SQ_IMG_RSC_WRD5_PERF_MOD_SZ; + unsigned int MID_LOD_WRN : SQ_IMG_RSC_WRD5_MID_LOD_WRN_SZ; + unsigned int : 4; + unsigned int ARRAY_PITCH : SQ_IMG_RSC_WRD5_ARRAY_PITCH_SZ; +#endif +}; + +union SQ_IMG_RSRC_WORD5 { + sq_img_rsrc_word5_t bitfields, bits, f; + uint32_t val : SQ_IMG_RSC_WRD5_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; +/***********/ + +#define SQ_IMG_RSC_WRD6_REG_SZ 32 +#define SQ_IMG_RSC_WRD6_MIN_LOD_HI_SZ 7 +#define SQ_IMG_RSC_WRD6_MAX_UNCOMP_BLK_SZ_SZ 2 +#define SQ_IMG_RSC_WRD6_MAX_COMP_BLK_SZ_SZ 2 +#define SQ_IMG_RSC_WRD6_META_PIPE_ALIGNED_SZ 1 +#define SQ_IMG_RSC_WRD6_WRITE_COMPRESS_EN_SZ 1 +#define SQ_IMG_RSC_WRD6_COMPRESSION_ENABLE_SZ 1 +#define SQ_IMG_RSC_WRD6_ALPHA_IS_ON_MSB_SZ 1 +#define SQ_IMG_RSC_WRD6_COLOR_TRANSFORM_SZ 1 +#define SQ_IMG_RSC_WRD6_META_DATA_ADDR_SZ 8 +struct sq_img_rsrc_word6_t { +#if defined(LITTLEENDIAN_CPU) + unsigned int MIN_LOD_HI : SQ_IMG_RSC_WRD6_MIN_LOD_HI_SZ; + unsigned int MAX_UNCOMP_BLK_SZ : SQ_IMG_RSC_WRD6_MAX_UNCOMP_BLK_SZ_SZ; + unsigned int MAX_COMP_BLK_SZ : SQ_IMG_RSC_WRD6_MAX_COMP_BLK_SZ_SZ; + unsigned int META_PIPE_ALIGNED : SQ_IMG_RSC_WRD6_META_PIPE_ALIGNED_SZ; + unsigned int WRITE_COMPRESS_ENABLE : SQ_IMG_RSC_WRD6_WRITE_COMPRESS_EN_SZ; + unsigned int COMPRESSION_ENABLE : SQ_IMG_RSC_WRD6_COMPRESSION_ENABLE_SZ; + unsigned int ALPHA_IS_ON_MSB : SQ_IMG_RSC_WRD6_ALPHA_IS_ON_MSB_SZ; + unsigned int COLOR_TRANSFORM : SQ_IMG_RSC_WRD6_COLOR_TRANSFORM_SZ; + unsigned int META_DATA_ADDRESS : SQ_IMG_RSC_WRD6_META_DATA_ADDR_SZ; +#elif defined(BIGENDIAN_CPU) + unsigned int META_DATA_ADDRESS : SQ_IMG_RSC_WRD6_META_DATA_ADDR_SZ; + unsigned int COLOR_TRANSFORM : SQ_IMG_RSC_WRD6_COLOR_TRANSFORM_SZ; + unsigned int ALPHA_IS_ON_MSB : SQ_IMG_RSC_WRD6_ALPHA_IS_ON_MSB_SZ; + unsigned int COMPRESSION_ENABLE : SQ_IMG_RSC_WRD6_COMPRESSION_ENABLE_SZ; + unsigned int WRITE_COMPRESS_ENABLE : SQ_IMG_RSC_WRD6_WRITE_COMPRESS_EN_SZ; + unsigned int META_PIPE_ALIGNED : SQ_IMG_RSC_WRD6_META_PIPE_ALIGNED_SZ; + unsigned int MAX_COMP_BLK_SZ : SQ_IMG_RSC_WRD6_MAX_COMP_BLK_SZ_SZ; + unsigned int MAX_UNCOMP_BLK_SZ : SQ_IMG_RSC_WRD6_MAX_UNCOMP_BLK_SZ_SZ; + unsigned int MIN_LOD_HI : SQ_IMG_RSC_WRD6_MIN_LOD_HI_SZ; +#endif +}; +union SQ_IMG_RSRC_WORD6 { + sq_img_rsrc_word6_t bitfields, bits, f; + uint32_t val : SQ_IMG_RSC_WRD6_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; +/***********/ + +#define SQ_IMG_RSC_WRD7_REG_SZ 32 +#define SQ_IMG_RSC_WRD7_META_DATA_ADDRESS_HI_SZ 32 +struct sq_img_rsrc_word7_t { +#if defined(LITTLEENDIAN_CPU) + unsigned int META_DATA_ADDRESS_HI : SQ_IMG_RSC_WRD7_META_DATA_ADDRESS_HI_SZ; +#elif defined(BIGENDIAN_CPU) + unsigned int META_DATA_ADDRESS_HI : SQ_IMG_RSC_WRD7_META_DATA_ADDRESS_HI_SZ; +#endif +}; +union SQ_IMG_RSRC_WORD7 { + sq_img_rsrc_word7_t bitfields, bits, f; + uint32_t val : SQ_IMG_RSC_WRD7_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; +/***********/ +/**********************************************************/ +/**********************************************************/ + +#define SQ_IMG_SAMP_WORD0_REG_SZ 32 +#define SQ_IMG_SAMP_WORD0_CLAMP_X_SZ 3 +#define SQ_IMG_SAMP_WORD0_CLAMP_Y_SZ 3 +#define SQ_IMG_SAMP_WORD0_CLAMP_Z_SZ 3 +#define SQ_IMG_SAMP_WORD0_MAX_ANISO_RATIO_SZ 3 +#define SQ_IMG_SAMP_WORD0_DEPTH_COMPARE_FUNC_SZ 3 +#define SQ_IMG_SAMP_WORD0_FORCE_UNNORMALIZED_SZ 1 +#define SQ_IMG_SAMP_WORD0_ANISO_THRESHOLD_SZ 3 +#define SQ_IMG_SAMP_WORD0_MC_COORD_TRUNC_SZ 1 +#define SQ_IMG_SAMP_WORD0_FORCE_DEGAMMA_SZ 1 +#define SQ_IMG_SAMP_WORD0_ANISO_BIAS_SZ 6 +#define SQ_IMG_SAMP_WORD0_TRUNC_COORD_SZ 1 +#define SQ_IMG_SAMP_WORD0_DISABLE_CUBE_WRAP_SZ 1 +#define SQ_IMG_SAMP_WORD0_FILTER_MODE_SZ 2 +#define SQ_IMG_SAMP_WORD0_SKIP_DEGAMMA_SZ 1 +struct sq_img_samp_word0_t { +#if defined(LITTLEENDIAN_CPU) + unsigned int CLAMP_X : SQ_IMG_SAMP_WORD0_CLAMP_X_SZ; + unsigned int CLAMP_Y : SQ_IMG_SAMP_WORD0_CLAMP_Y_SZ; + unsigned int CLAMP_Z : SQ_IMG_SAMP_WORD0_CLAMP_Z_SZ; + unsigned int MAX_ANISO_RATIO : SQ_IMG_SAMP_WORD0_MAX_ANISO_RATIO_SZ; + unsigned int DEPTH_COMPARE_FUNC : SQ_IMG_SAMP_WORD0_DEPTH_COMPARE_FUNC_SZ; + unsigned int FORCE_UNNORMALIZED : SQ_IMG_SAMP_WORD0_FORCE_UNNORMALIZED_SZ; + unsigned int ANISO_THRESHOLD : SQ_IMG_SAMP_WORD0_ANISO_THRESHOLD_SZ; + unsigned int MC_COORD_TRUNC : SQ_IMG_SAMP_WORD0_MC_COORD_TRUNC_SZ; + unsigned int FORCE_DEGAMMA : SQ_IMG_SAMP_WORD0_FORCE_DEGAMMA_SZ; + unsigned int ANISO_BIAS : SQ_IMG_SAMP_WORD0_ANISO_BIAS_SZ; + unsigned int TRUNC_COORD : SQ_IMG_SAMP_WORD0_TRUNC_COORD_SZ; + unsigned int DISABLE_CUBE_WRAP : SQ_IMG_SAMP_WORD0_DISABLE_CUBE_WRAP_SZ; + unsigned int FILTER_MODE : SQ_IMG_SAMP_WORD0_FILTER_MODE_SZ; + unsigned int SKIP_DEGAMMA : SQ_IMG_SAMP_WORD0_SKIP_DEGAMMA_SZ; +#elif defined(BIGENDIAN_CPU) + unsigned int SKIP_DEGAMMA : SQ_IMG_SAMP_WORD0_SKIP_DEGAMMA_SZ; + unsigned int FILTER_MODE : SQ_IMG_SAMP_WORD0_FILTER_MODE_SZ; + unsigned int DISABLE_CUBE_WRAP : SQ_IMG_SAMP_WORD0_DISABLE_CUBE_WRAP_SZ; + unsigned int TRUNC_COORD : SQ_IMG_SAMP_WORD0_TRUNC_COORD_SZ; + unsigned int ANISO_BIAS : SQ_IMG_SAMP_WORD0_ANISO_BIAS_SZ; + unsigned int FORCE_DEGAMMA : SQ_IMG_SAMP_WORD0_FORCE_DEGAMMA_SZ; + unsigned int MC_COORD_TRUNC : SQ_IMG_SAMP_WORD0_MC_COORD_TRUNC_SZ; + unsigned int ANISO_THRESHOLD : SQ_IMG_SAMP_WORD0_ANISO_THRESHOLD_SZ; + unsigned int FORCE_UNNORMALIZED : SQ_IMG_SAMP_WORD0_FORCE_UNNORMALIZED_SZ; + unsigned int DEPTH_COMPARE_FUNC : SQ_IMG_SAMP_WORD0_DEPTH_COMPARE_FUNC_SZ; + unsigned int MAX_ANISO_RATIO : SQ_IMG_SAMP_WORD0_MAX_ANISO_RATIO_SZ; + unsigned int CLAMP_Z : SQ_IMG_SAMP_WORD0_CLAMP_Z_SZ; + unsigned int CLAMP_Y : SQ_IMG_SAMP_WORD0_CLAMP_Y_SZ; + unsigned int CLAMP_X : SQ_IMG_SAMP_WORD0_CLAMP_X_SZ; +#endif +}; + +union SQ_IMG_SAMP_WORD0 { + sq_img_samp_word0_t bitfields, bits, f; + uint32_t val : SQ_IMG_SAMP_WORD0_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; +/***********/ + +#define SQ_IMG_SAMP_WORD1_REG_SZ 32 +#define SQ_IMG_SAMP_WORD1_MIN_LOD_SZ 12 +#define SQ_IMG_SAMP_WORD1_MAX_LOD_SZ 12 +#define SQ_IMG_SAMP_WORD1_PERF_MIP_SZ 4 +#define SQ_IMG_SAMP_WORD1_PERF_Z_SZ 4 +struct sq_img_samp_word1_t { +#if defined(LITTLEENDIAN_CPU) + unsigned int MIN_LOD : SQ_IMG_SAMP_WORD1_MIN_LOD_SZ; + unsigned int MAX_LOD : SQ_IMG_SAMP_WORD1_MAX_LOD_SZ; + unsigned int PERF_MIP : SQ_IMG_SAMP_WORD1_PERF_MIP_SZ; + unsigned int PERF_Z : SQ_IMG_SAMP_WORD1_PERF_Z_SZ; +#elif defined(BIGENDIAN_CPU) + unsigned int PERF_Z : SQ_IMG_SAMP_WORD1_PERF_Z_SZ; + unsigned int PERF_MIP : SQ_IMG_SAMP_WORD1_PERF_MIP_SZ; + unsigned int MAX_LOD : SQ_IMG_SAMP_WORD1_MAX_LOD_SZ; + unsigned int MIN_LOD : SQ_IMG_SAMP_WORD1_MIN_LOD_SZ; +#endif +}; + +union SQ_IMG_SAMP_WORD1 { + sq_img_samp_word1_t bitfields, bits, f; + uint32_t val : SQ_IMG_SAMP_WORD1_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; +/***********/ + +#define SQ_IMG_SAMP_WORD2_REG_SZ 32 +#define SQ_IMG_SAMP_WORD2_BC_LRS_LB_SZ 12 +#define SQ_IMG_SAMP_WORD2_BC_OR_BCT_SZ 2 +#define SQ_IMG_SAMP_WORD2_LOD_BIAS_SEC_SZ 6 +#define SQ_IMG_SAMP_WORD2_XY_MAG_FILTER_SZ 2 +#define SQ_IMG_SAMP_WORD2_XY_MIN_FILTER_SZ 2 +#define SQ_IMG_SAMP_WORD2_Z_FILTER_SZ 2 +#define SQ_IMG_SAMP_WORD2_MIP_FILTER_SZ 2 +#define SQ_IMG_SAMP_WORD2_MIP_POINT_PRECLAMP_SZ 1 +#define SQ_IMG_SAMP_WORD2_ANISO_OVERRIDE_SZ 1 +#define SQ_IMG_SAMP_WORD2_BLEND_ZERO_PRT_SZ 1 +struct sq_img_samp_word2_t { +#if defined(LITTLEENDIAN_CPU) + unsigned int BC_LRS_LB : SQ_IMG_SAMP_WORD2_BC_LRS_LB_SZ; + unsigned int BC_OR_BCT : SQ_IMG_SAMP_WORD2_BC_OR_BCT_SZ; + unsigned int LOD_BIAS_SEC : SQ_IMG_SAMP_WORD2_LOD_BIAS_SEC_SZ; + unsigned int XY_MAG_FILTER : SQ_IMG_SAMP_WORD2_XY_MAG_FILTER_SZ; + unsigned int XY_MIN_FILTER : SQ_IMG_SAMP_WORD2_XY_MIN_FILTER_SZ; + unsigned int Z_FILTER : SQ_IMG_SAMP_WORD2_Z_FILTER_SZ; + unsigned int MIP_FILTER : SQ_IMG_SAMP_WORD2_MIP_FILTER_SZ; + unsigned int MIP_POINT_PRECLAMP : SQ_IMG_SAMP_WORD2_MIP_POINT_PRECLAMP_SZ; + unsigned int ANISO_OVERRIDE : SQ_IMG_SAMP_WORD2_ANISO_OVERRIDE_SZ; + unsigned int BLEND_ZERO_PRT : SQ_IMG_SAMP_WORD2_BLEND_ZERO_PRT_SZ; +#elif defined(BIGENDIAN_CPU) + unsigned int BLEND_ZERO_PRT : SQ_IMG_SAMP_WORD2_BLEND_ZERO_PRT_SZ; + unsigned int ANISO_OVERRIDE : SQ_IMG_SAMP_WORD2_ANISO_OVERRIDE_SZ; + unsigned int MIP_POINT_PRECLAMP : SQ_IMG_SAMP_WORD2_MIP_POINT_PRECLAMP_SZ; + unsigned int MIP_FILTER : SQ_IMG_SAMP_WORD2_MIP_FILTER_SZ; + unsigned int Z_FILTER : SQ_IMG_SAMP_WORD2_Z_FILTER_SZ; + unsigned int XY_MIN_FILTER : SQ_IMG_SAMP_WORD2_XY_MIN_FILTER_SZ; + unsigned int XY_MAG_FILTER : SQ_IMG_SAMP_WORD2_XY_MAG_FILTER_SZ; + unsigned int LOD_BIAS_SEC : SQ_IMG_SAMP_WORD2_LOD_BIAS_SEC_SZ; + unsigned int BC_OR_BCT : SQ_IMG_SAMP_WORD2_BC_OR_BCT_SZ; + unsigned int LOD_BIAS : SQ_IMG_SAMP_WORD2_BC_LRS_LB_SZ; +#endif +}; + +union SQ_IMG_SAMP_WORD2 { + sq_img_samp_word2_t bitfields, bits, f; + uint32_t val : SQ_IMG_SAMP_WORD2_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; +/***********/ + +#define SQ_IMG_SAMP_WORD3_REG_SZ 32 +#define SQ_IMG_SAMP_WORD3_GRAD_ADJ_OR_DAV_SZ 16 +#define SQ_IMG_SAMP_WORD3_RES_OR_DAV_SZ 2 +#define SQ_IMG_SAMP_WORD3_BCP_LRS_DAV_SZ 12 +#define SQ_IMG_SAMP_WORD3_BORD_COLOR_TYPE_SZ 2 + +struct sq_img_samp_word3_t { +#if defined(LITTLEENDIAN_CPU) + unsigned int GRAD_ADJ_OR_DAV : SQ_IMG_SAMP_WORD3_GRAD_ADJ_OR_DAV_SZ; + unsigned int RES_OR_DAV : SQ_IMG_SAMP_WORD3_RES_OR_DAV_SZ; + unsigned int BCP_LRS_DAV : SQ_IMG_SAMP_WORD3_BCP_LRS_DAV_SZ; + unsigned int BORDER_COLOR_TYPE : SQ_IMG_SAMP_WORD3_BORD_COLOR_TYPE_SZ; +#elif defined(BIGENDIAN_CPU) + unsigned int BORDER_COLOR_TYPE : SQ_IMG_SAMP_WORD3_BORD_COLOR_TYPE_SZ; + unsigned int BCP_LRS_DAV : SQ_IMG_SAMP_WORD3_BCP_LRS_DAV_SZ; + unsigned int RES_OR_DAV : SQ_IMG_SAMP_WORD3_RES_OR_DAV_SZ; + unsigned int GRAD_ADJ_OR_DAV : SQ_IMG_SAMP_WORD3_GRAD_ADJ_OR_DAV_SZ; +#endif +}; + +union SQ_IMG_SAMP_WORD3 { + sq_img_samp_word3_t bitfields, bits, f; + uint32_t val : SQ_IMG_SAMP_WORD3_REG_SZ; + uint32_t u32All; + int32_t i32All; + float f32All; +}; +/***********/ + +/**************************************************************/ +/**************************************************************/ +/**************************************************************/ + +typedef enum FMT { +FMT_INVALID = 0x00000000, +FMT_8 = 0x00000001, +FMT_16 = 0x00000002, +FMT_8_8 = 0x00000003, +FMT_32 = 0x00000004, +FMT_16_16 = 0x00000005, +FMT_10_11_11 = 0x00000006, +FMT_11_11_10 = 0x00000007, +FMT_10_10_10_2 = 0x00000008, +FMT_2_10_10_10 = 0x00000009, +FMT_8_8_8_8 = 0x0000000a, +FMT_32_32 = 0x0000000b, +FMT_16_16_16_16 = 0x0000000c, +FMT_32_32_32 = 0x0000000d, +FMT_32_32_32_32 = 0x0000000e, +FMT_RESERVED_78 = 0x0000000f, +FMT_5_6_5 = 0x00000010, +FMT_1_5_5_5 = 0x00000011, +FMT_5_5_5_1 = 0x00000012, +FMT_4_4_4_4 = 0x00000013, +FMT_8_24 = 0x00000014, +FMT_24_8 = 0x00000015, +FMT_X24_8_32 = 0x00000016, +FMT_RESERVED_155 = 0x00000017, +FMT_1 = 0x00000018, +FMT_1_REVERSED = 0x00000019, +FMT_GB_GR = 0x0000001a, +FMT_BG_RG = 0x0000001b, +FMT_4_4 = 0x0000001c, +FMT_BC1 = 0x0000001d, +FMT_BC2 = 0x0000001e, +FMT_BC3 = 0x0000001f, +FMT_BC4 = 0x00000020, +FMT_BC5 = 0x00000021, +FMT_BC6 = 0x00000022, +FMT_BC7 = 0x00000023, +FMT_6E4 = 0x00000024, +FMT_5_9_9_9 = 0x00000025, +FMT_FMASK8_S2 = 0x00000026, +FMT_FMASK8_S4 = 0x00000027, +FMT_FMASK8_S8 = 0x00000028, +FMT_FMASK16_S16 = 0x00000029, +FMT_FMASK16_S8 = 0x0000002a, +FMT_FMASK32_S16 = 0x0000002b, +FMT_FMASK32_S8 = 0x0000002c, +FMT_FMASK64_S16 = 0x0000002d, +FMT_ETC2_RGB = 0x0000002e, +FMT_ETC2_RGBA = 0x0000002f, +FMT_ETC2_R = 0x00000030, +FMT_ETC2_RG = 0x00000031, +FMT_ETC2_RGBA1 = 0x00000032, +FMT_ASTC_2D_LDR = 0x00000033, +FMT_ASTC_2D_HDR = 0x00000034, +FMT_ASTC_2D_LDR_SRGB = 0x00000035, +FMT_ASTC_3D_LDR = 0x00000036, +FMT_ASTC_3D_HDR = 0x00000037, +FMT_ASTC_3D_LDR_SRGB = 0x00000038, +FMT_MM_8 = 0x00000039, +FMT_MM_8_8 = 0x0000003a, +FMT_MM_8_8_8_8 = 0x0000003b, +FMT_MM_VYUY8 = 0x0000003c, +FMT_MM_10_11_11 = 0x0000003d, +FMT_MM_2_10_10_10 = 0x0000003e, +FMT_MM_16_16_16_16 = 0x0000003f, +FMT_10_IN_16 = 0x00000040, +FMT_10_IN_16_16 = 0x00000041, +FMT_10_IN_16_16_16_16 = 0x00000042, +FMT_7E3 = 0x00000043, +FMT_YCBCR = 0x00000044, +} FMT; + +typedef enum type { +TYPE_UNORM = 0x00000000, +TYPE_SNORM = 0x00000001, +TYPE_USCALED = 0x00000002, +TYPE_SSCALED = 0x00000003, +TYPE_UINT = 0x00000004, +TYPE_SINT = 0x00000005, +TYPE_RESERVED_6 = 0x00000006, +TYPE_FLOAT = 0x00000007, +TYPE_RESERVED_8 = 0x00000008, +TYPE_SRGB = 0x00000009, +TYPE_UNORM_UINT = 0x0000000a, +TYPE_REVERSED_UNORM = 0x0000000b, +TYPE_FLOAT_CLAMP = 0x0000000c, +TYPE_F1 = 0x0000000d, +TYPE_F2 = 0x0000000e, +TYPE_F4 = 0x0000000f, +TYPE_F8 = 0x00000010, +TYPE_4X4 = 0x00000011, +TYPE_5X4 = 0x00000012, +TYPE_5X5 = 0x00000013, +TYPE_6X5 = 0x00000014, +TYPE_6X6 = 0x00000015, +TYPE_8X5 = 0x00000016, +TYPE_8X6 = 0x00000017, +TYPE_8X8 = 0x00000018, +TYPE_10X5 = 0x00000019, +TYPE_10X6 = 0x0000001a, +TYPE_10X8 = 0x0000001b, +TYPE_10X10 = 0x0000001c, +TYPE_12X10 = 0x0000001d, +TYPE_12X12 = 0x0000001e, +TYPE_3X3X3 = 0x0000001f, +TYPE_4X4X3 = 0x00000020, +TYPE_4X4X4 = 0x00000021, +TYPE_5X4X4 = 0x00000022, +TYPE_5X5X4 = 0x00000023, +TYPE_6X5X5 = 0x00000024, +TYPE_6X6X6 = 0x00000025 +} type; + +enum FORMAT { +CFMT_INVALID = 0, +CFMT_8_UNORM = 1, +CFMT_8_SNORM = 2, +CFMT_8_UINT = 5, +CFMT_8_SINT = 6, +CFMT_16_UNORM = 7, +CFMT_16_SNORM = 8, +CFMT_16_UINT = 11, +CFMT_16_SINT = 12, +CFMT_16_FLOAT = 13, +CFMT_8_8_UNORM = 14, +CFMT_8_8_SNORM = 15, +CFMT_8_8_UINT = 18, +CFMT_8_8_SINT = 19, +CFMT_32_UINT = 20, +CFMT_32_SINT = 21, +CFMT_32_FLOAT = 22, +CFMT_16_16_UNORM = 23, +CFMT_16_16_SNORM = 24, +CFMT_16_16_UINT = 27, +CFMT_16_16_SINT = 28, +CFMT_16_16_FLOAT = 29, +CFMT_10_10_10_2_UNORM = 44, +CFMT_10_10_10_2_SNORM = 45, +CFMT_10_10_10_2_UINT = 48, +CFMT_10_10_10_2_SINT = 49, +CFMT_2_10_10_10_UNORM = 50, +CFMT_2_10_10_10_SNORM = 51, +CFMT_2_10_10_10_UINT = 54, +CFMT_2_10_10_10_SINT = 55, +CFMT_8_8_8_8_UNORM = 56, +CFMT_8_8_8_8_SNORM = 57, +CFMT_8_8_8_8_UINT = 60, +CFMT_8_8_8_8_SINT = 61, +CFMT_32_32_UINT = 62, +CFMT_32_32_SINT = 63, +CFMT_32_32_FLOAT = 64, +CFMT_16_16_16_16_UNORM = 65, +CFMT_16_16_16_16_SNORM = 66, +CFMT_16_16_16_16_UINT = 69, +CFMT_16_16_16_16_SINT = 70, +CFMT_16_16_16_16_FLOAT = 71, +CFMT_32_32_32_UINT = 72, +CFMT_32_32_32_SINT = 73, +CFMT_32_32_32_FLOAT = 74, +CFMT_32_32_32_32_UINT = 75, +CFMT_32_32_32_32_SINT = 76, +CFMT_32_32_32_32_FLOAT = 77, +CFMT_8_SRGB = 128, +CFMT_8_8_SRGB = 129, +CFMT_8_8_8_8_SRGB = 130, +CFMT_5_6_5_UNORM = 133, +CFMT_1_5_5_5_UNORM = 134, +CFMT_5_5_5_1_UNORM = 135, +CFMT_8_24_UNORM = 141, +CFMT_8_24_UINT = 142, +CFMT_24_8_UNORM = 143, +CFMT_24_8_UINT = 144 +}; + +typedef enum SEL { + SEL_0 = 0x00000000, + SEL_1 = 0x00000001, + SEL_X = 0x00000004, + SEL_Y = 0x00000005, + SEL_Z = 0x00000006, + SEL_W = 0x00000007, +} SEL; + +typedef enum SQ_RSRC_IMG_TYPE { + SQ_RSRC_IMG_1D = 0x00000008, + SQ_RSRC_IMG_2D = 0x00000009, + SQ_RSRC_IMG_3D = 0x0000000a, + SQ_RSRC_IMG_CUBE_ARRAY = 0x0000000b, + SQ_RSRC_IMG_1D_ARRAY = 0x0000000c, + SQ_RSRC_IMG_2D_ARRAY = 0x0000000d, + SQ_RSRC_IMG_2D_MSAA = 0x0000000e, + SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f, +} SQ_RSRC_IMG_TYPE; + +typedef enum SQ_TEX_XY_FILTER { + SQ_TEX_XY_FILTER_POINT = 0x00000000, + SQ_TEX_XY_FILTER_BILINEAR = 0x00000001, + SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002, + SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003, +} SQ_TEX_XY_FILTER; + +typedef enum SQ_TEX_Z_FILTER { + SQ_TEX_Z_FILTER_NONE = 0x00000000, + SQ_TEX_Z_FILTER_POINT = 0x00000001, + SQ_TEX_Z_FILTER_LINEAR = 0x00000002, +} SQ_TEX_Z_FILTER; + +typedef enum SQ_TEX_MIP_FILTER { + SQ_TEX_MIP_FILTER_NONE = 0x00000000, + SQ_TEX_MIP_FILTER_POINT = 0x00000001, + SQ_TEX_MIP_FILTER_LINEAR = 0x00000002, + SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ__VI = 0x00000003, +} SQ_TEX_MIP_FILTER; + +typedef enum SQ_TEX_CLAMP { + SQ_TEX_WRAP = 0x00000000, + SQ_TEX_MIRROR = 0x00000001, + SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002, + SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003, + SQ_TEX_CLAMP_HALF_BORDER = 0x00000004, + SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005, + SQ_TEX_CLAMP_BORDER = 0x00000006, + SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007, +} SQ_TEX_CLAMP; + +typedef enum SQ_TEX_BORDER_COLOR { + SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000, + SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001, + SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002, + SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003, +} SQ_TEX_BORDER_COLOR; + +typedef enum TEX_BC_SWIZZLE { +TEX_BC_Swizzle_XYZW = 0x00000000, +TEX_BC_Swizzle_XWYZ = 0x00000001, +TEX_BC_Swizzle_WZYX = 0x00000002, +TEX_BC_Swizzle_WXYZ = 0x00000003, +TEX_BC_Swizzle_ZYXW = 0x00000004, +TEX_BC_Swizzle_YXWZ = 0x00000005, +} TEX_BC_SWIZZLE; + +typedef struct metadata_amd_nv_s { + uint32_t version; // Must be 1 + uint32_t vendorID; // AMD + SQ_IMG_RSRC_WORD0 word0; + SQ_IMG_RSRC_WORD1 word1; + SQ_IMG_RSRC_WORD2 word2; + SQ_IMG_RSRC_WORD3 word3; + SQ_IMG_RSRC_WORD4 word4; + SQ_IMG_RSRC_WORD5 word5; + SQ_IMG_RSRC_WORD6 word6; + SQ_IMG_RSRC_WORD7 word7; + uint32_t mip_offsets[0]; +} metadata_amd_nv_t; + +} // namespace image +} // namespace rocr +#endif // EXT_IMAGE_RESOURCE_GFX11_H_