From 65d554f5e4495d52f1f68debff68af681db22d6e Mon Sep 17 00:00:00 2001
From: Oak Zeng <Oak.Zeng@amd.com>
Date: Fri, 10 May 2019 12:38:12 -0500
Subject: [PATCH] Thunk API to allocate queue GWS

Change-Id: I6c5b109e2567cb71aed9245923cfcbeee6295ab2
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
---
 include/hsakmt.h  | 12 ++++++++++++
 src/libhsakmt.ver |  1 +
 src/queues.c      | 42 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 55 insertions(+)

diff --git a/include/hsakmt.h b/include/hsakmt.h
index 6d4b1f3a26..6d666a931c 100644
--- a/include/hsakmt.h
+++ b/include/hsakmt.h
@@ -571,6 +571,18 @@ hsaKmtUnmapGraphicHandle(
                 HSAuint64              SizeInBytes              //IN
                 );
 
+/**
+  Allocate GWS resource for a queue
+ */
+
+HSAKMT_STATUS
+HSAKMTAPI
+hsaKmtAllocQueueGWS(
+                HSAuint32          NodeId,                      //IN
+                HSA_QUEUEID        QueueId,                     //IN
+                HSAuint32          nGWS,                        //IN
+                HSAuint32          *firstGWS                    //OUT
+                );
 
 /**
   Notifies the kernel driver that a process wants to use GPU debugging facilities
diff --git a/src/libhsakmt.ver b/src/libhsakmt.ver
index 8e9b745042..54d79b440d 100644
--- a/src/libhsakmt.ver
+++ b/src/libhsakmt.ver
@@ -64,6 +64,7 @@ hsaKmtSetWaveLaunchTrapOverride;
 hsaKmtSetWaveLaunchMode;
 hsaKmtQueueSuspend;
 hsaKmtQueueResume;
+hsaKmtAllocQueueGWS;
 
 local: *;
 };
diff --git a/src/queues.c b/src/queues.c
index 69b96ba6e8..f967805c22 100644
--- a/src/queues.c
+++ b/src/queues.c
@@ -34,6 +34,7 @@
 #include <sys/types.h>
 #include <sys/mman.h>
 #include <fcntl.h>
+#include <errno.h>
 
 /* 1024 doorbells, 4 or 8 bytes each doorbell depending on ASIC generation */
 #define DOORBELL_SIZE_GFX7 4
@@ -817,3 +818,44 @@ uint32_t *convert_queue_ids(HSAuint32 NumQueues, HSA_QUEUEID *Queues)
 	return queue_ids_ptr;
 }
 
+HSAKMT_STATUS
+HSAKMTAPI
+hsaKmtAllocQueueGWS(
+                HSAuint32          NodeId,
+                HSA_QUEUEID        QueueId,
+                HSAuint32          nGWS,
+                HSAuint32          *firstGWS)
+{
+	struct kfd_ioctl_alloc_queue_gws_args args = {0};
+	struct queue *q = PORT_UINT64_TO_VPTR(QueueId);
+	HSAKMT_STATUS result;
+	uint32_t gpu_id;
+
+	CHECK_KFD_OPEN();
+
+	result = validate_nodeid(NodeId, &gpu_id);
+	if (result != HSAKMT_STATUS_SUCCESS) {
+		pr_err("[%s] invalid node ID: %d\n", __func__, NodeId);
+		return result;
+	}
+
+	args.gpu_id = gpu_id;
+	args.queue_id = (HSAuint32)q->queue_id;
+	args.num_gws = nGWS;
+
+	int err = kmtIoctl(kfd_fd, AMDKFD_IOC_ALLOC_QUEUE_GWS, &args);
+
+	if (!err && firstGWS)
+		*firstGWS = args.first_gws;
+
+	if (!err)
+		return HSAKMT_STATUS_SUCCESS;
+	else if (err == -EINVAL)
+		return HSAKMT_STATUS_INVALID_PARAMETER;
+	else if (err == -EBUSY)
+		return HSAKMT_STATUS_OUT_OF_RESOURCES;
+	else if (err == -ENODEV)
+		return HSAKMT_STATUS_NOT_SUPPORTED;
+	else
+		return HSAKMT_STATUS_ERROR;
+}