diff --git a/projects/clr/rocclr/compiler/lib/backends/common/linker.cpp b/projects/clr/rocclr/compiler/lib/backends/common/linker.cpp index e82117a9c3..adb5493500 100644 --- a/projects/clr/rocclr/compiler/lib/backends/common/linker.cpp +++ b/projects/clr/rocclr/compiler/lib/backends/common/linker.cpp @@ -585,7 +585,13 @@ amdcl::OCLLinker::link(llvm::Module* input, std::vectorgetContext().setAMDLLVMContextHook(&hookup_); diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp b/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp index 21f6efce5a..7baac90aa2 100644 --- a/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp +++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp @@ -26,6 +26,12 @@ static const std::string sgfx900 = "AMD:AMDGPU:9:0:0"; static const std::string sgfx901 = "AMD:AMDGPU:9:0:1"; static const std::string sgfx902 = "AMD:AMDGPU:9:0:2"; static const std::string sgfx903 = "AMD:AMDGPU:9:0:3"; +static const std::string sgfx904 = "AMD:AMDGPU:9:0:4"; +static const std::string sgfx905 = "AMD:AMDGPU:9:0:5"; +static const std::string sgfx906 = "AMD:AMDGPU:9:0:6"; +static const std::string sgfx907 = "AMD:AMDGPU:9:0:7"; +static const std::string sgfx1000 = "AMD:AMDGPU:10:0:0"; +static const std::string sgfx1001 = "AMD:AMDGPU:10:0:1"; // Utility function to set a flag in option structure // of the aclDevCaps. @@ -530,6 +536,12 @@ const std::string &getIsaTypeName(const aclTargetInfo *target) case 901: return sgfx901; case 902: return sgfx902; case 903: return sgfx903; + case 904: return sgfx904; + case 905: return sgfx905; + case 906: return sgfx906; + case 907: return sgfx907; + case 1000: return sgfx1000; + case 1001: return sgfx1001; } } @@ -591,13 +603,20 @@ int getIsaType(const aclTargetInfo *target) case FAMILY_AI: switch (Mapping.chip_enum) { default: return 900; - case AI_GREENLAND_P_A0: return Mapping.xnack_supported ? 901 : 900; + case AI_GREENLAND_P_A0: + case AI_GREENLAND_P_A1: return Mapping.xnack_supported ? 901 : 900; + case AI_VEGA20_P_A0: return Mapping.xnack_supported ? 907 : 906; } case FAMILY_RV: switch (Mapping.chip_enum) { default: return 902; case RAVEN_A0: return Mapping.xnack_supported ? 903 : 902; } + case FAMILY_NV: + switch (Mapping.chip_enum) { + default: return 1000; + case NV_NAVI10_P_A0: return Mapping.xnack_supported ? 1001 : 1000; + } } } diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings.h b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings.h index 1a005bf3c8..d86e24508d 100644 --- a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings.h +++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings.h @@ -213,6 +213,12 @@ static const char* calTargetMapping[] = { IF(IS_BRAHMA,"","gfx901"), IF(IS_BRAHMA,"","gfx902"), IF(IS_BRAHMA,"","gfx903"), + IF(IS_BRAHMA,"","gfx904"), + IF(IS_BRAHMA,"","gfx905"), + IF(IS_BRAHMA,"","gfx906"), + IF(IS_BRAHMA,"","gfx907"), + IF(IS_BRAHMA,"","gfx1000"), + IF(IS_BRAHMA,"","gfx1001"), }; #include "utils/v0_8/target_mappings_amdil.h" diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h index 54ce3d8929..cfc1ca9d42 100644 --- a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h +++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h @@ -10,6 +10,7 @@ #include "cz_id.h" #include "ai_id.h" #include "rv_id.h" +#include "nv_id.h" #include "atiid.h" static const TargetMapping HSAILTargetMapping_0_8[] = { @@ -34,17 +35,29 @@ static const TargetMapping HSAILTargetMapping_0_8[] = { { "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, false, FAMILY_VI, false }, { "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A1, F_VI_BASE, true, true, FAMILY_VI, false }, #ifndef BRAHMA - { "AI", "gfx900", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, true, FAMILY_AI }, + { "AI", "gfx900", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, false, FAMILY_AI }, + { "AI", "gfx900", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A1, F_AI_BASE, true, true, FAMILY_AI }, { "VI", "gfx804", "GFX8", amd::GPU_Library_HSAIL, VI_LEXA_V_A0, F_VI_BASE, true, true, FAMILY_VI }, - { "AI", "gfx901", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, true, FAMILY_AI ,true }, + { "AI", "gfx901", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, false, FAMILY_AI ,true }, + { "AI", "gfx901", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A1, F_AI_BASE, true, true, FAMILY_AI ,true }, { "RV", "gfx902", "GFX9", amd::GPU_Library_HSAIL, RAVEN_A0, F_AI_BASE, true, true, FAMILY_RV, false }, { "RV", "gfx903", "GFX9", amd::GPU_Library_HSAIL, RAVEN_A0, F_AI_BASE, true, true, FAMILY_RV, true }, + { "AI", "gfx906", "GFX9", amd::GPU_Library_HSAIL, AI_VEGA20_P_A0, F_AI_BASE, true, true, FAMILY_AI, false }, + { "AI", "gfx907", "GFX9", amd::GPU_Library_HSAIL, AI_VEGA20_P_A0, F_AI_BASE, true, true, FAMILY_AI, true }, + { "NV", "gfx1000", "GFX10", amd::GPU_Library_HSAIL, NV_NAVI10_P_A0, F_AI_BASE, true, true, FAMILY_NV, false }, + { "NV", "gfx1001", "GFX10", amd::GPU_Library_HSAIL, NV_NAVI10_P_A0, F_AI_BASE, true, true, FAMILY_NV, true }, #else UnknownTarget, UnknownTarget, UnknownTarget, UnknownTarget, UnknownTarget, + UnknownTarget, + UnknownTarget, + UnknownTarget, + UnknownTarget, + UnknownTarget, + UnknownTarget, #endif InvalidTarget }; diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h index efa0c06d27..061ec95211 100644 --- a/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h +++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h @@ -9,6 +9,7 @@ #include "ci_id.h" #include "ai_id.h" #include "rv_id.h" +#include "nv_id.h" #include "atiid.h" static const TargetMapping HSAIL64TargetMapping_0_8[] = { @@ -33,17 +34,29 @@ static const TargetMapping HSAIL64TargetMapping_0_8[] = { { "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, false, FAMILY_VI, false }, { "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A1, F_VI_BASE, true, true, FAMILY_VI, false }, #ifndef BRAHMA - { "AI", "gfx900", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, true, FAMILY_AI, false }, + { "AI", "gfx900", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, false, FAMILY_AI, false }, + { "AI", "gfx900", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A1, F_AI_BASE, true, true, FAMILY_AI, false }, { "VI", "gfx804", "GFX8", amd::GPU_Library_HSAIL, VI_LEXA_V_A0, F_VI_BASE, true, true, FAMILY_VI, false }, - { "AI", "gfx901", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, true, FAMILY_AI, true }, + { "AI", "gfx901", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, false, FAMILY_AI, true }, + { "AI", "gfx901", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A1, F_AI_BASE, true, true, FAMILY_AI, true }, { "RV", "gfx902", "GFX9", amd::GPU_Library_HSAIL, RAVEN_A0, F_AI_BASE, true, true, FAMILY_RV, false }, { "RV", "gfx903", "GFX9", amd::GPU_Library_HSAIL, RAVEN_A0, F_AI_BASE, true, true, FAMILY_RV, true }, + { "AI", "gfx906", "GFX9", amd::GPU_Library_HSAIL, AI_VEGA20_P_A0, F_AI_BASE, true, true, FAMILY_AI, false }, + { "AI", "gfx907", "GFX9", amd::GPU_Library_HSAIL, AI_VEGA20_P_A0, F_AI_BASE, true, true, FAMILY_AI, true }, + { "NV", "gfx1000", "GFX10", amd::GPU_Library_HSAIL, NV_NAVI10_P_A0, F_AI_BASE, true, true, FAMILY_NV, false }, + { "NV", "gfx1001", "GFX10", amd::GPU_Library_HSAIL, NV_NAVI10_P_A0, F_AI_BASE, true, true, FAMILY_NV, true }, #else UnknownTarget, UnknownTarget, UnknownTarget, UnknownTarget, UnknownTarget, + UnknownTarget, + UnknownTarget, + UnknownTarget, + UnknownTarget, + UnknownTarget, + UnknownTarget, #endif InvalidTarget }; diff --git a/projects/clr/rocclr/runtime/device/gpu/gpudefs.hpp b/projects/clr/rocclr/runtime/device/gpu/gpudefs.hpp index d6c08bf992..3393f16bcf 100644 --- a/projects/clr/rocclr/runtime/device/gpu/gpudefs.hpp +++ b/projects/clr/rocclr/runtime/device/gpu/gpudefs.hpp @@ -157,6 +157,13 @@ static const AMDDeviceInfo DeviceInfo[] = { IF(IS_BRAHMA, "", "gfx901"), 4, 16, 1, 256, 64 * Ki, 32, 900}, /* CAL_TARGET_POLARIS22 */ {ED_ATI_CAL_MACHINE_POLARIS22_ISA, IF(IS_BRAHMA, "", "gfx804"), IF(IS_BRAHMA, "", "gfx804"), 4, 16, 1, 256, 64 * Ki, 32, 800}, + /* CAL_TARGET_VEGA12 */{ ED_ATI_CAL_MACHINE_VEGA12_ISA, IF(IS_BRAHMA, "", "gfx904"), + IF(IS_BRAHMA, "", "gfx904"), 4, 16, 1, 256, 64 * Ki, 32, 900 }, + /* CAL_TARGET_VEGA20 */{ ED_ATI_CAL_MACHINE_VEGA20_ISA, IF(IS_BRAHMA, "", "gfx906"), + IF(IS_BRAHMA, "", "gfx906"), 4, 16, 1, 256, 64 * Ki, 32, 900 }, + /* CAL_TARGET_NAVI10 */{ ED_ATI_CAL_MACHINE_NAVI10_ISA, IF(IS_BRAHMA, "", "gfx1000"), + IF(IS_BRAHMA, "", "gfx1000"), 4, 16, 1, 256, 64 * Ki, 32, 1000 }, + }; enum gfx_handle { @@ -168,7 +175,15 @@ enum gfx_handle { gfx804 = 804, gfx810 = 810, gfx900 = 900, - gfx901 = 901 + gfx901 = 901, + gfx902 = 902, + gfx903 = 903, + gfx904 = 904, + gfx905 = 905, + gfx906 = 906, + gfx907 = 907, + gfx1000 = 1000, + gfx1001 = 1001 }; static const char* Gfx700 = "AMD:AMDGPU:7:0:0"; @@ -179,6 +194,14 @@ static const char* Gfx804 = "AMD:AMDGPU:8:0:4"; static const char* Gfx810 = "AMD:AMDGPU:8:1:0"; static const char* Gfx900 = "AMD:AMDGPU:9:0:0"; static const char* Gfx901 = "AMD:AMDGPU:9:0:1"; +static const char* Gfx902 = "AMD:AMDGPU:9:0:2"; +static const char* Gfx903 = "AMD:AMDGPU:9:0:3"; +static const char* Gfx904 = "AMD:AMDGPU:9:0:4"; +static const char* Gfx905 = "AMD:AMDGPU:9:0:5"; +static const char* Gfx906 = "AMD:AMDGPU:9:0:6"; +static const char* Gfx907 = "AMD:AMDGPU:9:0:7"; +static const char* Gfx1000 = "AMD:AMDGPU:10:0:0"; +static const char* Gfx1001 = "AMD:AMDGPU:10:0:1"; // Supported OpenCL versions enum OclVersion { OpenCL10, OpenCL11, OpenCL12, OpenCL20 }; diff --git a/projects/clr/rocclr/runtime/device/gpu/gpudevice.cpp b/projects/clr/rocclr/runtime/device/gpu/gpudevice.cpp index 1460bd1d78..fa95eda983 100644 --- a/projects/clr/rocclr/runtime/device/gpu/gpudevice.cpp +++ b/projects/clr/rocclr/runtime/device/gpu/gpudevice.cpp @@ -142,6 +142,9 @@ bool NullDevice::create(CALtarget target) { case CAL_TARGET_LEXA: case CAL_TARGET_RAVEN: case CAL_TARGET_POLARIS22: + case CAL_TARGET_VEGA12: + case CAL_TARGET_VEGA20: + case CAL_TARGET_NAVI10: calAttr.doublePrecision = CAL_TRUE; calAttr.isOpenCL200Device = CAL_TRUE; break; @@ -812,7 +815,8 @@ bool Device::create(CALuint ordinal, CALuint numOfDevices) { hwInfo_ = &DeviceInfo[calTarget_]; if ((GPU_ENABLE_PAL == 2) && - (calTarget_ == CAL_TARGET_GREENLAND || calTarget_ == CAL_TARGET_RAVEN)) { + (calTarget_ == CAL_TARGET_GREENLAND || calTarget_ == CAL_TARGET_RAVEN || + calTarget_ >= CAL_TARGET_VEGA12)) { return false; } diff --git a/projects/clr/rocclr/runtime/device/gpu/gpuprogram.cpp b/projects/clr/rocclr/runtime/device/gpu/gpuprogram.cpp index 2afff29701..f29ab699ae 100644 --- a/projects/clr/rocclr/runtime/device/gpu/gpuprogram.cpp +++ b/projects/clr/rocclr/runtime/device/gpu/gpuprogram.cpp @@ -2227,6 +2227,39 @@ hsa_isa_t ORCAHSALoaderContext::IsaFromName(const char* name) { isa.handle = gfx901; return isa; } + if (!strcmp(Gfx902, name)) { + isa.handle = gfx902; + return isa; + } + if (!strcmp(Gfx903, name)) { + isa.handle = gfx903; + return isa; + } + if (!strcmp(Gfx904, name)) { + isa.handle = gfx904; + return isa; + } + if (!strcmp(Gfx905, name)) { + isa.handle = gfx905; + return isa; + } + if (!strcmp(Gfx906, name)) { + isa.handle = gfx906; + return isa; + } + if (!strcmp(Gfx907, name)) { + isa.handle = gfx907; + return isa; + } + if (!strcmp(Gfx1000, name)) { + isa.handle = gfx1000; + return isa; + } + if (!strcmp(Gfx1001, name)) { + isa.handle = gfx1001; + return isa; + } + return isa; } @@ -2262,13 +2295,35 @@ bool ORCAHSALoaderContext::IsaSupportedByAgent(hsa_agent_t agent, hsa_isa_t isa) return false; } case gfx900: + case gfx901: + case gfx902: + case gfx903: + case gfx904: + case gfx905: + case gfx906: + case gfx907: switch (program_->dev().hwInfo()->machine_) { case ED_ATI_CAL_MACHINE_GREENLAND_ISA: return isa.handle == gfx900 || isa.handle == gfx901; + case ED_ATI_CAL_MACHINE_RAVEN_ISA: + return isa.handle == gfx902 || isa.handle == gfx903; + case ED_ATI_CAL_MACHINE_VEGA12_ISA: + return isa.handle == gfx904 || isa.handle == gfx905; + case ED_ATI_CAL_MACHINE_VEGA20_ISA: + return isa.handle == gfx906 || isa.handle == gfx907; default: assert(0); return false; } + case gfx1000: + case gfx1001: + switch (program_->dev().hwInfo()->machine_) { + case ED_ATI_CAL_MACHINE_NAVI10_ISA: + return isa.handle == gfx1000 || isa.handle == gfx1001; + default: + assert(0); + return false; + } } } diff --git a/projects/clr/rocclr/runtime/device/gpu/gpusettings.cpp b/projects/clr/rocclr/runtime/device/gpu/gpusettings.cpp index 57395bbc7c..c186a307aa 100644 --- a/projects/clr/rocclr/runtime/device/gpu/gpusettings.cpp +++ b/projects/clr/rocclr/runtime/device/gpu/gpusettings.cpp @@ -164,6 +164,9 @@ bool Settings::create(const CALdeviceattribs& calAttr, bool reportAsOCL12Device, // APU systems for AI apuSystem_ = true; case CAL_TARGET_GREENLAND: + case CAL_TARGET_VEGA12: + case CAL_TARGET_VEGA20: + case CAL_TARGET_NAVI10: // TODO: specific codes for AI aiPlus_ = true; // Fall through to VI ... diff --git a/projects/clr/rocclr/runtime/device/gpu/gslbe/src/rt/GSLDevice.cpp b/projects/clr/rocclr/runtime/device/gpu/gslbe/src/rt/GSLDevice.cpp index 01db5f1729..52f2f59f47 100644 --- a/projects/clr/rocclr/runtime/device/gpu/gslbe/src/rt/GSLDevice.cpp +++ b/projects/clr/rocclr/runtime/device/gpu/gslbe/src/rt/GSLDevice.cpp @@ -513,6 +513,19 @@ CALGSLDevice::SetupContext(int32 &asic_id) m_target = CAL_TARGET_POLARIS22; m_elfmachine = ED_ATI_CAL_MACHINE_POLARIS22_ISA; break; + case GSL_ATIASIC_ID_VEGA12: + m_target = CAL_TARGET_VEGA12; + m_elfmachine = ED_ATI_CAL_MACHINE_VEGA12_ISA; + break; + case GSL_ATIASIC_ID_VEGA20: + m_target = CAL_TARGET_VEGA20; + m_elfmachine = ED_ATI_CAL_MACHINE_VEGA20_ISA; + break; + case GSL_ATIASIC_ID_NAVI10: + m_target = CAL_TARGET_NAVI10; + m_elfmachine = ED_ATI_CAL_MACHINE_NAVI10_ISA; + break; + default: // 6XX is not supported m_adp->deleteContext(temp_cs); diff --git a/projects/clr/rocclr/runtime/device/gpu/gslbe/src/rt/caltarget.h b/projects/clr/rocclr/runtime/device/gpu/gslbe/src/rt/caltarget.h index ca3bb2c7cf..7f127fc18a 100644 --- a/projects/clr/rocclr/runtime/device/gpu/gslbe/src/rt/caltarget.h +++ b/projects/clr/rocclr/runtime/device/gpu/gslbe/src/rt/caltarget.h @@ -48,7 +48,10 @@ typedef enum CALtargetEnum { CAL_TARGET_LEXA, /**< LEXA GPU ISA*/ CAL_TARGET_RAVEN, /**< RAVEN GPU ISA*/ CAL_TARGET_POLARIS22, /**< POLARIS22 GPU ISA*/ - CAL_TARGET_LAST = CAL_TARGET_POLARIS22, /**< last */ + CAL_TARGET_VEGA12, /**< VEGA12 GPU ISA*/ + CAL_TARGET_VEGA20, /**< VEGA20 GPU ISA*/ + CAL_TARGET_NAVI10, /**< NAVI10 GPU ISA*/ + CAL_TARGET_LAST = CAL_TARGET_NAVI10, /**< last */ //##END_PRIVATE## } CALtarget; diff --git a/projects/clr/rocclr/runtime/device/pal/paldefs.hpp b/projects/clr/rocclr/runtime/device/pal/paldefs.hpp index c94c5b19d7..cccc22eee6 100644 --- a/projects/clr/rocclr/runtime/device/pal/paldefs.hpp +++ b/projects/clr/rocclr/runtime/device/pal/paldefs.hpp @@ -153,6 +153,7 @@ static const AMDDeviceInfo GfxIpDeviceInfo[] = { /* GFX800 */ {"gfx800", "gfx800", 4, 16, 1, 256, 64 * Ki, 32, 800}, /* GFX801 */ {"gfx801", "gfx801", 4, 16, 1, 256, 64 * Ki, 32, 801}, /* GFX900 */ {"gfx900", "gfx900", 4, 16, 1, 256, 64 * Ki, 32, 900}, + /* GFX1000 */ {"gfx1000", "gfx1000", 4, 16, 1, 256, 64 * Ki, 32, 1000 }, }; // Ordering as per AsicRevision# in //depot/stg/pal/inc/core/palDevice.h and @@ -160,16 +161,16 @@ static const AMDDeviceInfo GfxIpDeviceInfo[] = { static const AMDDeviceInfo Gfx9PlusSubDeviceInfo[] = { /* Vega10 */{"gfx900", "gfx900", 4, 16, 1, 256, 64 * Ki, 32, 900}, /* Vega10 XNACK */{"gfx901", "gfx901", 4, 16, 1, 256, 64 * Ki, 32, 901}, - /* Vega12 */{0}, - /* Vega12 XNACK */{0}, - /* Vega20 */{0}, - /* Vega20 XNACK */{0}, + /* Vega12 */{"gfx904", "gfx904", 4, 16, 1, 256, 64 * Ki, 32, 904}, + /* Vega12 XNACK */{"gfx905", "gfx905", 4, 16, 1, 256, 64 * Ki, 32, 905}, + /* Vega20 */{"gfx906", "gfx906", 4, 16, 1, 256, 64 * Ki, 32, 906}, + /* Vega20 XNACK */{"gfx907", "gfx907", 4, 16, 1, 256, 64 * Ki, 32, 907}, /* Raven */{"gfx902", "gfx902", 4, 16, 1, 256, 64 * Ki, 32, 902}, /* Raven XNACK */{"gfx903", "gfx903", 4, 16, 1, 256, 64 * Ki, 32, 903}, /* Raven2 */{0}, /* Raven2 XNACK */{0}, - /* Navi10 */{0}, - /* Navi10 XNACK */{0}, + /* Navi10 */{"gfx1000", "gfx1000", 4, 16, 1, 256, 64 * Ki, 32, 1000}, + /* Navi10 XNACK */{"gfx1001", "gfx1001", 4, 16, 1, 256, 64 * Ki, 32, 1001}, }; enum gfx_handle { @@ -183,7 +184,13 @@ enum gfx_handle { gfx900 = 900, gfx901 = 901, gfx902 = 902, - gfx903 = 903 + gfx903 = 903, + gfx904 = 904, + gfx905 = 905, + gfx906 = 906, + gfx907 = 907, + gfx1000 = 1000, + gfx1001 = 1001 }; static const char* Gfx700 = "AMD:AMDGPU:7:0:0"; @@ -196,6 +203,12 @@ static const char* Gfx900 = "AMD:AMDGPU:9:0:0"; static const char* Gfx901 = "AMD:AMDGPU:9:0:1"; static const char* Gfx902 = "AMD:AMDGPU:9:0:2"; static const char* Gfx903 = "AMD:AMDGPU:9:0:3"; +static const char* Gfx904 = "AMD:AMDGPU:9:0:4"; +static const char* Gfx905 = "AMD:AMDGPU:9:0:5"; +static const char* Gfx906 = "AMD:AMDGPU:9:0:6"; +static const char* Gfx907 = "AMD:AMDGPU:9:0:7"; +static const char* Gfx1000 = "AMD:AMDGPU:10:0:0"; +static const char* Gfx1001 = "AMD:AMDGPU:10:0:1"; // Supported OpenCL versions enum OclVersion { OpenCL10, OpenCL11, OpenCL12, OpenCL20 }; diff --git a/projects/clr/rocclr/runtime/device/pal/palprogram.cpp b/projects/clr/rocclr/runtime/device/pal/palprogram.cpp index 61176cb00c..c252af2e74 100644 --- a/projects/clr/rocclr/runtime/device/pal/palprogram.cpp +++ b/projects/clr/rocclr/runtime/device/pal/palprogram.cpp @@ -899,6 +899,31 @@ hsa_isa_t PALHSALoaderContext::IsaFromName(const char* name) { isa.handle = gfx903; return isa; } + if (!strcmp(Gfx904, name)) { + isa.handle = gfx904; + return isa; + } + if (!strcmp(Gfx905, name)) { + isa.handle = gfx905; + return isa; + } + if (!strcmp(Gfx906, name)) { + isa.handle = gfx906; + return isa; + } + if (!strcmp(Gfx907, name)) { + isa.handle = gfx907; + return isa; + } + if (!strcmp(Gfx1000, name)) { + isa.handle = gfx1000; + return isa; + } + if (!strcmp(Gfx1001, name)) { + isa.handle = gfx1001; + return isa; + } + return isa; } @@ -928,6 +953,15 @@ bool PALHSALoaderContext::IsaSupportedByAgent(hsa_agent_t agent, hsa_isa_t isa) case gfx902: case gfx903: return isa.handle == gfx902 || isa.handle == gfx903; + case gfx904: + case gfx905: + return isa.handle == gfx904 || isa.handle == gfx905; + case gfx906: + case gfx907: + return isa.handle == gfx906 || isa.handle == gfx907; + case gfx1000: + case gfx1001: + return isa.handle == gfx1000 || isa.handle == gfx1001; } } diff --git a/projects/clr/rocclr/runtime/device/pal/palsettings.cpp b/projects/clr/rocclr/runtime/device/pal/palsettings.cpp index 9835ecbef1..b8b15115fc 100644 --- a/projects/clr/rocclr/runtime/device/pal/palsettings.cpp +++ b/projects/clr/rocclr/runtime/device/pal/palsettings.cpp @@ -171,6 +171,8 @@ bool Settings::create(const Pal::DeviceProperties& palProp, assert(0 && "Unknown GfxIP type!"); return false; } + case Pal::AsicRevision::Navi10: + case Pal::AsicRevision::Vega20: case Pal::AsicRevision::Vega10: case Pal::AsicRevision::Raven: aiPlus_ = true;