diff --git a/rocclr/runtime/device/rocm/roccounters.cpp b/rocclr/runtime/device/rocm/roccounters.cpp
index 9c2c746f29..7dab57e569 100644
--- a/rocclr/runtime/device/rocm/roccounters.cpp
+++ b/rocclr/runtime/device/rocm/roccounters.cpp
@@ -259,6 +259,147 @@ static const std::array<std::pair<hsa_ven_amd_aqlprofile_block_name_t, int>, 125
     {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 7},     // RMI - 124
 }};
 
+static const std::array<std::pair<hsa_ven_amd_aqlprofile_block_name_t, int>, 139> gfx10BlockIdOrcaToRocr = {{
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // CB0      - 0
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 1},      // CB1      - 1
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 2},      // CB2      - 2
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 3},      // CB3      - 3
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPF, 0},     // CPF      - 4
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // DB0      - 5
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 1},      // DB1      - 6
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 2},      // DB2      - 7
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 3},      // DB3      - 8
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBM, 0},    // GRBM     - 9
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GRBMSE, 0},  // GRBMSE   - 10
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // PA_SU    - 11
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // PA_SC0   - 12
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // PA_SC1   - 13
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SPI, 0},     // SPI      - 14
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ, 0},      // SQ       - 15
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // SQ_ES    - 16
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // SQ_GS    - 17
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // SQ_VS    - 18
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // SQ_PS    - 19
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // SQ_LS    - 20
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // SQ_HS    - 21
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQCS, 0},    // SQ_CS    - 22
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SX, 0},      // SX       - 23
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 0},      // TA0      - 24
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 1},      // TA1      - 25
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 2},      // TA2      - 26
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 3},      // TA3      - 27
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 4},      // TA4      - 28
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 5},      // TA5      - 29
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 6},      // TA6      - 30
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 7},      // TA7      - 31
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 8},      // TA8      - 32
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 9},      // TA9      - 33
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 0x0a},   // TA10     - 34
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 0x0b},   // TA11     - 35
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 0x0c},   // TA12     - 36
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 0x0d},   // TA13     - 37
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 0x0e},   // TA14     - 38
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 0x0f},   // TA15     - 39
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 0},      // TD0      - 40
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 1},      // TD1      - 41
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 2},      // TD2      - 42
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 3},      // TD3      - 43
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 4},      // TD4      - 44
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 5},      // TD5      - 45
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 6},      // TD6      - 46
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 7},      // TD7      - 47
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 8},      // TD8      - 48
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 9},      // TD9      - 49
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 0x0a},   // TD10     - 50
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 0x0b},   // TD11     - 51
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 0x0c},   // TD12     - 52
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 0x0d},   // TD13     - 53
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 0x0e},   // TD14     - 54
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 0x0f},   // TD15     - 55
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 0},     // TCP0     - 56
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 1},     // TCP1     - 57
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 2},     // TCP2     - 58
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 3},     // TCP3     - 59
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 4},     // TCP4     - 60
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 5},     // TCP5     - 61
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 6},     // TCP6     - 62
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 7},     // TCP7     - 63
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 8},     // TCP8     - 64
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 9},     // TCP9     - 65
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 0x0a},  // TCP10    - 66
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 0x0b},  // TCP11    - 67
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 0x0c},  // TCP12    - 68
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 0x0d},  // TCP13    - 69
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 0x0e},  // TCP14    - 70
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 0x0f},  // TCP15    - 71
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GDS, 0},     // GDS      - 72
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // CPG      - 73
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPC, 0},     // CPC      - 74
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATC, 0},     // ATC      - 75
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_ATCL2, 0},   // ATCL2    - 76
+    {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_MCVML2, 0},  // MCVML2   - 77
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // EA       - 78
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 1},      // EA       - 79
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 2},      // EA       - 80
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 3},      // EA       - 81
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 4},      // EA       - 82
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 5},      // EA       - 83
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 6},      // EA       - 84
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 7},      // EA       - 85
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 8},      // EA       - 86
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 9},      // EA       - 87
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x0a},   // EA       - 88
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x0b},   // EA       - 89
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x0c},   // EA       - 90
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x0d},   // EA       - 91
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x0e},   // EA       - 92
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x0f},   // EA       - 93
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // RPB      - 94
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // RMI0     - 95
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 1},      // RMI1     - 96
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // GE       - 97
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // GL1A     - 98
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // GL1C     - 99
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // GL1CG0   - 100
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 1},      // GL1CG1   - 101
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 2},      // GL1CG2   - 102
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 3},      // GL1CG3   - 103
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // GL2A0    - 104
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 1},      // GL2A1    - 105
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 2},      // GL2A2    - 106
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 3},      // GL2A3    - 107
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // GL2C0    - 108
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 1},      // GL2C1    - 109
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 2},      // GL2C2    - 110
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 3},      // GL2C3    - 111
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 4},      // GL2C4    - 112
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 5},      // GL2C5    - 113
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 6},      // GL2C6    - 114
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 7},      // GL2C7    - 115
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 8},      // GL2C8    - 116
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 9},      // GL2C9    - 117
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x0a},   // GL2C10   - 118
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x0b},   // GL2C11   - 119
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x0c},   // GL2C12   - 120
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x0d},   // GL2C13   - 121
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x0e},   // GL2C14   - 122
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x0f},   // GL2C15   - 123
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x10},   // GL2C16   - 124
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x11},   // GL2C17   - 125
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x12},   // GL2C18   - 126
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x13},   // GL2C19   - 127
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x14},   // GL2C20   - 128
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x15},   // GL2C21   - 129
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x16},   // GL2C22   - 130
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0x17},   // GL2C23   - 131
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // CHA      - 132
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // CHC      - 133
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // CHCG     - 134
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // GUS      - 135
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // GCR      - 136
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // PH       - 137
+    {HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER, 0},      // UTCL1    - 138
+}};
 
   //! Constructor for the ROC PerfCounter object
 PerfCounter::PerfCounter(const Device& device,   //!< A ROC device object
@@ -290,6 +431,14 @@ PerfCounter::PerfCounter(const Device& device,   //!< A ROC device object
         event_.block_index = std::get<1>(p);
       }
       break;
+    case (10):
+      gfxVersion_ = ROC_GFX10;
+      if (blockIndex < gfx10BlockIdOrcaToRocr.size()) {
+        auto p = gfx10BlockIdOrcaToRocr[blockIndex];
+        event_.block_name = std::get<0>(p);
+        event_.block_index = std::get<1>(p);
+      }
+      break;
     default:
       gfxVersion_ = ROC_UNSUPPORTED;
       event_.block_name = HSA_VEN_AMD_AQLPROFILE_BLOCKS_NUMBER;
diff --git a/rocclr/runtime/device/rocm/roccounters.hpp b/rocclr/runtime/device/rocm/roccounters.hpp
index 3fb3818fa1..291ccaa1b3 100644
--- a/rocclr/runtime/device/rocm/roccounters.hpp
+++ b/rocclr/runtime/device/rocm/roccounters.hpp
@@ -20,7 +20,8 @@ class PerfCounter : public device::PerfCounter {
   enum {
     ROC_UNSUPPORTED = 0,
     ROC_GFX8,
-    ROC_GFX9
+    ROC_GFX9,
+    ROC_GFX10
   };
 
   //! The performance counter info
diff --git a/rocclr/runtime/device/rocm/rocvirtual.cpp b/rocclr/runtime/device/rocm/rocvirtual.cpp
index a22ebd189d..a288693ba1 100644
--- a/rocclr/runtime/device/rocm/rocvirtual.cpp
+++ b/rocclr/runtime/device/rocm/rocvirtual.cpp
@@ -480,6 +480,7 @@ bool VirtualGPU::dispatchCounterAqlPacket(hsa_ext_amd_aql_pm4_packet_t* packet,
       }
       break;
     case PerfCounter::ROC_GFX9:
+    case PerfCounter::ROC_GFX10:
       {
         packet->header = HSA_PACKET_TYPE_VENDOR_SPECIFIC << HSA_PACKET_HEADER_TYPE;
         return dispatchGenericAqlPacket(packet, 0, 0, blocking);