From 6a30645259d20794a146e64fed13ca587244f423 Mon Sep 17 00:00:00 2001 From: foreman Date: Mon, 23 Jul 2018 15:41:16 -0400 Subject: [PATCH] P4 to Git Change 1584092 by zukhan@zukhan-lc-win10 on 2018/07/23 15:24:19 SWDEV-155860 - [OCL][LC] 62 Failures running on OCL/LC Windows drivers - Conformance test basic->vload_private was failing due to alignment assert check on akc->workitem_private_segment_byte_size. - Determined needed to add alignment, so added alignment into the header file, and removed assert check (as alignment was done afterwards). ReviewBoardURL = http://ocltc.amd.com/reviews/r/15451/diff/ Affected files ... ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palkernel.cpp#57 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palkernel.hpp#18 edit [ROCm/clr commit: 12a063779d9ffb2be6a6dbac8783dcf374021821] --- projects/clr/rocclr/runtime/device/pal/palkernel.cpp | 1 - projects/clr/rocclr/runtime/device/pal/palkernel.hpp | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/projects/clr/rocclr/runtime/device/pal/palkernel.cpp b/projects/clr/rocclr/runtime/device/pal/palkernel.cpp index 6abfd86ba6..f35ac18b7a 100644 --- a/projects/clr/rocclr/runtime/device/pal/palkernel.cpp +++ b/projects/clr/rocclr/runtime/device/pal/palkernel.cpp @@ -420,7 +420,6 @@ bool HSAILKernel::aqlCreateHWInfo(amd::hsa::loader::Symbol* sym) { return false; } - assert((akc->workitem_private_segment_byte_size & 3) == 0 && "Scratch must be DWORD aligned"); workGroupInfo_.scratchRegs_ = amd::alignUp(akc->workitem_private_segment_byte_size, 16) / sizeof(uint); workGroupInfo_.privateMemSize_ = akc->workitem_private_segment_byte_size; diff --git a/projects/clr/rocclr/runtime/device/pal/palkernel.hpp b/projects/clr/rocclr/runtime/device/pal/palkernel.hpp index 7ffc144c8b..d62cabb436 100644 --- a/projects/clr/rocclr/runtime/device/pal/palkernel.hpp +++ b/projects/clr/rocclr/runtime/device/pal/palkernel.hpp @@ -161,7 +161,7 @@ class HSAILKernel : public device::Kernel { size_t argsBufferSize() const { return cpuAqlCode_->kernarg_segment_byte_size; } //! Returns spill reg size per workitem - int spillSegSize() const { return cpuAqlCode_->workitem_private_segment_byte_size; } + int spillSegSize() const { return amd::alignUp(cpuAqlCode_->workitem_private_segment_byte_size, sizeof(uint32_t)); } //! Returns TRUE if kernel uses dynamic parallelism bool dynamicParallelism() const { return (flags_.dynamicParallelism_) ? true : false; }