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SWDEV-451594 - Change device kernel args to use HDP flush by default

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The Readback and Avoid HDP Flush memory ordering workaround is
used as a fallback solution only when HDP flush register is invalid

Change-Id: Ic284eba1f95ed22b0270d3abeb904fb902015b1a
This commit is contained in:
Ioannis Assiouras
2024-05-02 01:18:47 +01:00
committed by Saleel Kudchadker
parent e53df57ffe
commit 6cb7b6ec6b
3 changed files with 33 additions and 49 deletions
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hipamd/src/hip_graph_internal.cpp
+11 -18
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@@ -395,28 +395,21 @@ hipError_t GraphExec::CaptureAQLPackets() {
}
}
auto kernArgImpl = device->settings().kernel_arg_impl_;
if (device_kernarg_pool_) {
auto kernArgImpl = device->settings().kernel_arg_impl_;
const auto applyMemOrderingWA =
((kernArgImpl == KernelArgImpl::DeviceKernelArgsReadback) ||
(kernArgImpl == KernelArgImpl::DeviceKernelArgsHDP)) &&
kernarg_pool_size_graph_ > 0;
if (device_kernarg_pool_ && applyMemOrderingWA) {
address dev_ptr = kernarg_pool_graph_ + kernarg_pool_size_graph_;
volatile char kSentinel = *(dev_ptr - 1);
// Memory ordering workaround for pcie: execute sfence followed by
// write the last byte of kernarg.
_mm_sfence();
*(dev_ptr - 1) = kSentinel;
// HDP flush is required to guarantee ordering in Navi and MI100
if (kernArgImpl == KernelArgImpl::DeviceKernelArgsHDP) {
*device->info().hdpMemFlushCntl = 1u;
volatile auto kSentinel = *device->info().hdpMemFlushCntl;
} else if (kernArgImpl == KernelArgImpl::DeviceKernelArgsReadback &&
kernarg_pool_size_graph_ != 0) {
address dev_ptr = kernarg_pool_graph_ + kernarg_pool_size_graph_;
volatile auto kSentinel = *(dev_ptr - 1);
_mm_sfence();
*(dev_ptr - 1) = kSentinel;
_mm_mfence();
kSentinel = *(dev_ptr - 1);
}
// Memory ordering workaround for pcie: execute mfence followed by
// read of the last byte of kernarg.
_mm_mfence();
kSentinel = *(dev_ptr - 1);
}
ResetQueueIndex();