SWDEV-451594 - Change device kernel args to use HDP flush by default
The Readback and Avoid HDP Flush memory ordering workaround is used as a fallback solution only when HDP flush register is invalid Change-Id: Ic284eba1f95ed22b0270d3abeb904fb902015b1a
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@@ -250,8 +250,6 @@ void Settings::setKernelArgImpl(const amd::Isa& isa, bool isXgmi, bool hasValidH
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const bool isMI300 = gfxipMajor == 9 && gfxipMinor == 4 &&
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(gfxStepping == 0 || gfxStepping == 1 || gfxStepping == 2);
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const bool isMI200 = (gfxipMajor == 9 && gfxipMinor == 0 && gfxStepping == 10);
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const bool isMI100 = (gfxipMajor == 9 && gfxipMinor == 0 && gfxStepping == 8);
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const bool isNavi = (gfxipMajor >= 10);
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auto kernelArgImpl = KernelArgImpl::HostKernelArgs;
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@@ -259,15 +257,15 @@ void Settings::setKernelArgImpl(const amd::Isa& isa, bool isXgmi, bool hasValidH
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// The XGMI-connected path does not require the manual memory ordering
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// workarounds that the PCIe connected path requires
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kernelArgImpl = KernelArgImpl::DeviceKernelArgs;
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} else if (isMI300 || isMI200) {
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// Implement the kernel argument readback workaround. It works only on
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// MI200, MI300 because of the strict guarantee on ordering of
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// stores in those ASICS
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kernelArgImpl = KernelArgImpl::DeviceKernelArgsReadback;
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} else if (hasValidHDPFlush && (isNavi || isMI100)) {
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// For dev >= gfx10 and MI100 ASICS implement the HDP flush to MMIO if the
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// HDP flush register is valid
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} else if (hasValidHDPFlush) {
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// If the HDP flush register is valid implement the HDP flush to MMIO
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kernelArgImpl = KernelArgImpl::DeviceKernelArgsHDP;
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} else if (isMI300 || isMI200) {
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// Implement the kernel argument readback workaround
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// (write all args -> sfence -> write last byte -> mfence -> read last byte)
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// It works only on MI200 and MI300 because of the strict guarantee on
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// ordering of stores in those ASICS
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kernelArgImpl = KernelArgImpl::DeviceKernelArgsReadback;
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}
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// Enable device kernel args for MI300* for now
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