From 6da9d181406d4adce41ab6ee3ebe5683cb643216 Mon Sep 17 00:00:00 2001 From: German Andryeyev Date: Mon, 20 Sep 2021 16:13:36 -0400 Subject: [PATCH] SWDEV-292408 - Disable cache coherency tracking for HIP Cache coherency layer is OCL feature to support multiple devices in single OCL context. Change-Id: Ic66df9551fad5b0c4df95ab3e1db1da259919f25 --- rocclr/platform/memory.cpp | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/rocclr/platform/memory.cpp b/rocclr/platform/memory.cpp index 0ebe458f83..5a42a435ed 100644 --- a/rocclr/platform/memory.cpp +++ b/rocclr/platform/memory.cpp @@ -457,13 +457,16 @@ bool Memory::setDestructorCallback(DestructorCallBackFunction callback, void* da } void Memory::signalWrite(const Device* writer) { - // (the potential race condition below doesn't matter, no critical - // section needed) - ++version_; - lastWriter_ = writer; - // Update all subbuffers for this object - for (auto buf : subBuffers_) { - buf->signalWrite(writer); + // Disable cache coherency layer for HIP + if (!amd::IS_HIP) { + // (the potential race condition below doesn't matter, no critical + // section needed) + ++version_; + lastWriter_ = writer; + // Update all subbuffers for this object + for (auto buf : subBuffers_) { + buf->signalWrite(writer); + } } }