kfdtest: Add kfdtest source code
The code is a snapshot up to this commit around July 31 2018. commit b00fadff36a3 Author: xinhui pan <xinhui.pan@amd.com> Date: Mon Jul 30 09:53:03 2018 +0800 kfdtest: skip MMapLarge test on apu Change-Id: I40e9a5a18e5c8f075e5290bb80532f1a3f689058 Signed-off-by: Yong Zhao <yong.zhao@amd.com>
Bu işleme şunda yer alıyor:
Yong Zhao
@@ -0,0 +1,76 @@
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/*
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* Copyright (C) 2015-2018 Advanced Micro Devices, Inc. All Rights Reserved.
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||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
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||||
*/
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#ifndef AMDP2PTEST_H_
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#define AMDP2PTEST_H_
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#include <linux/ioctl.h>
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#define AMDP2PTEST_IOCTL_MAGIC 'A'
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#define AMDP2PTEST_DEVICE_NAME "amdp2ptest"
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#define AMDP2PTEST_DEVICE_PATH "/dev/amdp2ptest"
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struct AMDRDMA_IOCTL_GET_PAGE_SIZE_PARAM {
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/* Input parameters */
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uint64_t addr;
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uint64_t length;
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/* Output parameters */
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uint64_t page_size;
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};
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struct AMDRDMA_IOCTL_GET_PAGES_PARAM {
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/* Input parameters */
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uint64_t addr;
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uint64_t length;
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};
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struct AMDRDMA_IOCTL_PUT_PAGES_PARAM {
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/* Input parameters */
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uint64_t addr;
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uint64_t length;
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};
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struct AMDRDMA_IOCTL_IS_GPU_ADDRESS_PARAM {
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/* Input parameters */
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uint64_t addr;
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uint64_t ret_value;
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};
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#define AMD2P2PTEST_IOCTL_GET_PAGE_SIZE \
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_IOWR(AMDP2PTEST_IOCTL_MAGIC, 1, struct AMDRDMA_IOCTL_GET_PAGE_SIZE_PARAM *)
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#define AMD2P2PTEST_IOCTL_GET_PAGES \
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_IOWR(AMDP2PTEST_IOCTL_MAGIC, 2, struct AMDRDMA_IOCTL_GET_PAGES_PARAM *)
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#define AMD2P2PTEST_IOCTL_PUT_PAGES \
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_IOW(AMDP2PTEST_IOCTL_MAGIC, 3, struct AMDRDMA_IOCTL_PUT_PAGES_PARAM *)
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#define AMD2P2PTEST_IOCTL_IS_GPU_ADDRESS \
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_IOW(AMDP2PTEST_IOCTL_MAGIC, 4, struct AMDRDMA_IOCTL_IS_GPU_ADDRESS *)
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#endif /* AMDP2PTEST_H */
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@@ -0,0 +1,107 @@
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/*
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||||
* Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
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#ifndef KFD_PM4_OPCODES_H
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#define KFD_PM4_OPCODES_H
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enum it_opcode_type {
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IT_NOP = 0x10,
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IT_SET_BASE = 0x11,
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IT_CLEAR_STATE = 0x12,
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IT_INDEX_BUFFER_SIZE = 0x13,
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IT_DISPATCH_DIRECT = 0x15,
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IT_DISPATCH_INDIRECT = 0x16,
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IT_ATOMIC_GDS = 0x1D,
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IT_OCCLUSION_QUERY = 0x1F,
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IT_SET_PREDICATION = 0x20,
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IT_REG_RMW = 0x21,
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IT_COND_EXEC = 0x22,
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IT_PRED_EXEC = 0x23,
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IT_DRAW_INDIRECT = 0x24,
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IT_DRAW_INDEX_INDIRECT = 0x25,
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IT_INDEX_BASE = 0x26,
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IT_DRAW_INDEX_2 = 0x27,
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IT_CONTEXT_CONTROL = 0x28,
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IT_INDEX_TYPE = 0x2A,
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IT_DRAW_INDIRECT_MULTI = 0x2C,
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IT_DRAW_INDEX_AUTO = 0x2D,
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IT_NUM_INSTANCES = 0x2F,
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IT_DRAW_INDEX_MULTI_AUTO = 0x30,
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IT_INDIRECT_BUFFER_CNST = 0x33,
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IT_STRMOUT_BUFFER_UPDATE = 0x34,
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IT_DRAW_INDEX_OFFSET_2 = 0x35,
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IT_DRAW_PREAMBLE = 0x36,
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IT_WRITE_DATA = 0x37,
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IT_DRAW_INDEX_INDIRECT_MULTI = 0x38,
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IT_MEM_SEMAPHORE = 0x39,
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IT_COPY_DW = 0x3B,
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IT_WAIT_REG_MEM = 0x3C,
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IT_INDIRECT_BUFFER = 0x3F,
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IT_COPY_DATA = 0x40,
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IT_PFP_SYNC_ME = 0x42,
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IT_SURFACE_SYNC = 0x43,
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IT_COND_WRITE = 0x45,
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IT_EVENT_WRITE = 0x46,
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IT_EVENT_WRITE_EOP = 0x47,
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IT_EVENT_WRITE_EOS = 0x48,
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IT_RELEASE_MEM = 0x49,
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IT_PREAMBLE_CNTL = 0x4A,
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IT_DMA_DATA = 0x50,
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IT_ACQUIRE_MEM = 0x58,
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IT_REWIND = 0x59,
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IT_LOAD_UCONFIG_REG = 0x5E,
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IT_LOAD_SH_REG = 0x5F,
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IT_LOAD_CONFIG_REG = 0x60,
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IT_LOAD_CONTEXT_REG = 0x61,
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IT_SET_CONFIG_REG = 0x68,
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IT_SET_CONTEXT_REG = 0x69,
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IT_SET_CONTEXT_REG_INDIRECT = 0x73,
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IT_SET_SH_REG = 0x76,
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IT_SET_SH_REG_OFFSET = 0x77,
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IT_SET_QUEUE_REG = 0x78,
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IT_SET_UCONFIG_REG = 0x79,
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IT_SCRATCH_RAM_WRITE = 0x7D,
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IT_SCRATCH_RAM_READ = 0x7E,
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IT_LOAD_CONST_RAM = 0x80,
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IT_WRITE_CONST_RAM = 0x81,
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IT_DUMP_CONST_RAM = 0x83,
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IT_INCREMENT_CE_COUNTER = 0x84,
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IT_INCREMENT_DE_COUNTER = 0x85,
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IT_WAIT_ON_CE_COUNTER = 0x86,
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IT_WAIT_ON_DE_COUNTER_DIFF = 0x88,
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IT_SWITCH_BUFFER = 0x8B,
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IT_SET_RESOURCES = 0xA0,
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IT_MAP_PROCESS = 0xA1,
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IT_MAP_QUEUES = 0xA2,
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IT_UNMAP_QUEUES = 0xA3,
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IT_QUERY_STATUS = 0xA4,
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IT_RUN_LIST = 0xA5,
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};
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#define PM4_TYPE_0 0
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#define PM4_TYPE_2 2
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#define PM4_TYPE_3 3
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#endif /* KFD_PM4_OPCODES_H */
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@@ -0,0 +1,160 @@
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/*
|
||||
* Copyright (C) 2016-2018 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __PM4_PKT_STRUCT_AI_H__
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#define __PM4_PKT_STRUCT_AI_H__
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||||
#ifndef PM4_MEC_RELEASE_MEM_AI_DEFINED
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||||
#define PM4_MEC_RELEASE_MEM_AI_DEFINED
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enum AI_MEC_RELEASE_MEM_event_index_enum {
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||||
event_index__mec_release_mem__end_of_pipe = 5,
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event_index__mec_release_mem__shader_done = 6 };
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enum AI_MEC_RELEASE_MEM_cache_policy_enum {
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cache_policy__mec_release_mem__lru = 0,
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cache_policy__mec_release_mem__stream = 1 };
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enum AI_MEC_RELEASE_MEM_pq_exe_status_enum {
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pq_exe_status__mec_release_mem__default = 0,
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pq_exe_status__mec_release_mem__phase_update = 1 };
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enum AI_MEC_RELEASE_MEM_dst_sel_enum {
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dst_sel__mec_release_mem__memory_controller = 0,
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dst_sel__mec_release_mem__tc_l2 = 1,
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dst_sel__mec_release_mem__queue_write_pointer_register = 2,
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dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3 };
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enum AI_MEC_RELEASE_MEM_int_sel_enum {
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int_sel__mec_release_mem__none = 0,
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int_sel__mec_release_mem__send_interrupt_only = 1,
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int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2,
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int_sel__mec_release_mem__send_data_after_write_confirm = 3,
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int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4,
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int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5,
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int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6 };
|
||||
|
||||
enum AI_MEC_RELEASE_MEM_data_sel_enum {
|
||||
data_sel__mec_release_mem__none = 0,
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||||
data_sel__mec_release_mem__send_32_bit_low = 1,
|
||||
data_sel__mec_release_mem__send_64_bit_data = 2,
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data_sel__mec_release_mem__send_gpu_clock_counter = 3,
|
||||
data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4,
|
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data_sel__mec_release_mem__store_gds_data_to_memory = 5 };
|
||||
|
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|
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typedef struct PM4_MEC_RELEASE_MEM_AI {
|
||||
union {
|
||||
PM4_TYPE_3_HEADER header;
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unsigned int ordinal1;
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||||
};
|
||||
|
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union {
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||||
struct {
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||||
unsigned int event_type:6;
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||||
unsigned int reserved1:2;
|
||||
AI_MEC_RELEASE_MEM_event_index_enum event_index:4;
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unsigned int tcl1_vol_action_ena:1;
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unsigned int tc_vol_action_ena:1;
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unsigned int reserved2:1;
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||||
unsigned int tc_wb_action_ena:1;
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||||
unsigned int tcl1_action_ena:1;
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||||
unsigned int tc_action_ena:1;
|
||||
unsigned int reserved3:1;
|
||||
unsigned int tc_nc_action_ena:1;
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unsigned int tc_wc_action_ena:1;
|
||||
unsigned int tc_md_action_ena:1;
|
||||
unsigned int reserved4:3;
|
||||
AI_MEC_RELEASE_MEM_cache_policy_enum cache_policy:2;
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||||
unsigned int reserved5:2;
|
||||
AI_MEC_RELEASE_MEM_pq_exe_status_enum pq_exe_status:1;
|
||||
unsigned int reserved6:2;
|
||||
} bitfields2;
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||||
unsigned int ordinal2;
|
||||
};
|
||||
|
||||
union {
|
||||
struct {
|
||||
unsigned int reserved7:16;
|
||||
AI_MEC_RELEASE_MEM_dst_sel_enum dst_sel:2;
|
||||
unsigned int reserved8:6;
|
||||
AI_MEC_RELEASE_MEM_int_sel_enum int_sel:3;
|
||||
unsigned int reserved9:2;
|
||||
AI_MEC_RELEASE_MEM_data_sel_enum data_sel:3;
|
||||
} bitfields3;
|
||||
unsigned int ordinal3;
|
||||
};
|
||||
|
||||
union {
|
||||
struct {
|
||||
unsigned int reserved10:2;
|
||||
unsigned int address_lo_32b:30;
|
||||
} bitfields4a;
|
||||
struct {
|
||||
unsigned int reserved11:3;
|
||||
unsigned int address_lo_64b:29;
|
||||
} bitfields4b;
|
||||
unsigned int reserved12;
|
||||
|
||||
unsigned int ordinal4;
|
||||
};
|
||||
|
||||
union {
|
||||
unsigned int address_hi;
|
||||
|
||||
unsigned int reserved13;
|
||||
|
||||
unsigned int ordinal5;
|
||||
};
|
||||
|
||||
union {
|
||||
unsigned int data_lo;
|
||||
|
||||
unsigned int cmp_data_lo;
|
||||
|
||||
struct {
|
||||
unsigned int dw_offset:16;
|
||||
unsigned int num_dwords:16;
|
||||
} bitfields6c;
|
||||
unsigned int reserved14;
|
||||
|
||||
unsigned int ordinal6;
|
||||
};
|
||||
|
||||
union {
|
||||
unsigned int data_hi;
|
||||
|
||||
unsigned int cmp_data_hi;
|
||||
|
||||
unsigned int reserved15;
|
||||
|
||||
unsigned int reserved16;
|
||||
|
||||
unsigned int ordinal7;
|
||||
};
|
||||
|
||||
unsigned int int_ctxid;
|
||||
} PM4MEC_RELEASE_MEM_AI, *PPM4MEC_RELEASE_MEM_AI;
|
||||
|
||||
#endif // PM4_MEC_RELEASE_MEM_AI_DEFINED
|
||||
#endif // __PM4_PKT_STRUCT_AI_H__
|
||||
@@ -0,0 +1,129 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2018 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __PM4_PKT_STRUCT_CI_H__
|
||||
#define __PM4_PKT_STRUCT_CI_H__
|
||||
|
||||
|
||||
enum WRITE_DATA_CI_atc_enum { atc_write_data_NOT_USE_ATC_0 = 0, atc_write_data_USE_ATC_1 = 1 };
|
||||
enum WRITE_DATA_CI_engine_sel { engine_sel_write_data_ci_MICRO_ENGINE_0 = 0, engine_sel_write_data_ci_PREFETCH_PARSER_1 = 1, engine_sel_write_data_ci_CONST_ENG_2 = 2 };
|
||||
|
||||
typedef struct _PM4WRITE_DATA_CI {
|
||||
union {
|
||||
PM4_TYPE_3_HEADER header;
|
||||
unsigned int ordinal1;
|
||||
};
|
||||
|
||||
union {
|
||||
struct {
|
||||
unsigned int reserved1:8;
|
||||
MEC_WRITE_DATA_dst_sel_enum dst_sel:4;
|
||||
unsigned int reserved2:4;
|
||||
MEC_WRITE_DATA_addr_incr_enum addr_incr:1;
|
||||
unsigned int reserved3:3;
|
||||
MEC_WRITE_DATA_wr_confirm_enum wr_confirm:1;
|
||||
unsigned int reserved4:3;
|
||||
WRITE_DATA_CI_atc_enum atc:1;
|
||||
MEC_WRITE_DATA_cache_policy_enum cache_policy:2;
|
||||
unsigned int volatile_setting:1;
|
||||
unsigned int reserved5:2;
|
||||
WRITE_DATA_CI_engine_sel engine_sel:2;
|
||||
} bitfields2;
|
||||
unsigned int ordinal2;
|
||||
};
|
||||
|
||||
unsigned int dst_addr_lo;
|
||||
|
||||
unsigned int dst_address_hi;
|
||||
|
||||
unsigned int data[1]; // 1..N of these fields
|
||||
} PM4WRITE_DATA_CI, *PPM4WRITE_DATA_CI;
|
||||
|
||||
|
||||
enum MEC_RELEASE_MEM_CI_atc_enum { atc_mec_release_mem_ci_NOT_USE_ATC_0 = 0, atc_mec_release_mem_ci_USE_ATC_1 = 1 };
|
||||
|
||||
typedef struct _PM4_RELEASE_MEM_CI {
|
||||
union {
|
||||
PM4_TYPE_3_HEADER header;
|
||||
unsigned int ordinal1;
|
||||
};
|
||||
|
||||
union {
|
||||
struct {
|
||||
unsigned int event_type:6;
|
||||
unsigned int reserved1:2;
|
||||
MEC_RELEASE_MEM_event_index_enum event_index:4;
|
||||
unsigned int l1_vol:1;
|
||||
unsigned int l2_vol:1;
|
||||
unsigned int reserved:1;
|
||||
unsigned int l2_wb:1;
|
||||
unsigned int l1_inv:1;
|
||||
unsigned int l2_inv:1;
|
||||
unsigned int reserved2:6;
|
||||
MEC_RELEASE_MEM_CI_atc_enum atc:1;
|
||||
MEC_RELEASE_MEM_cache_policy_enum cache_policy:2;
|
||||
unsigned int volatile_setting:1;
|
||||
unsigned int reserved3:4;
|
||||
} bitfields2;
|
||||
unsigned int ordinal2;
|
||||
};
|
||||
|
||||
union {
|
||||
struct {
|
||||
unsigned int reserved4:16;
|
||||
MEC_RELEASE_MEM_dst_sel_enum dst_sel:2;
|
||||
unsigned int reserved5:6;
|
||||
MEC_RELEASE_MEM_int_sel_enum int_sel:3;
|
||||
unsigned int reserved6:2;
|
||||
MEC_RELEASE_MEM_data_sel_enum data_sel:3;
|
||||
} bitfields3;
|
||||
unsigned int ordinal3;
|
||||
};
|
||||
|
||||
union {
|
||||
struct {
|
||||
unsigned int reserved7:2;
|
||||
unsigned int address_lo_dword_aligned:30;
|
||||
} bitfields4a;
|
||||
struct {
|
||||
unsigned int reserved8:3;
|
||||
unsigned int address_lo_qword_aligned:29;
|
||||
} bitfields4b;
|
||||
unsigned int ordinal4;
|
||||
};
|
||||
|
||||
unsigned int addr_hi;
|
||||
|
||||
union {
|
||||
unsigned int data_lo;
|
||||
struct {
|
||||
unsigned int offset:16;
|
||||
unsigned int num_dwords:16;
|
||||
} bitfields5b;
|
||||
unsigned int ordinal6;
|
||||
};
|
||||
|
||||
unsigned int data_hi;
|
||||
} PM4_RELEASE_MEM_CI, *PPM4_RELEASE_MEM_CI;
|
||||
|
||||
#endif // __PM4_PKT_STRUCT_CI_H__
|
||||
@@ -0,0 +1,275 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __PM4_PKT_STRUCT_COMMON_H__
|
||||
#define __PM4_PKT_STRUCT_COMMON_H__
|
||||
|
||||
#ifndef PM4_HEADER_DEFINED
|
||||
#define PM4_HEADER_DEFINED
|
||||
typedef union PM4_TYPE_3_HEADER
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int predicate : 1; ///< predicated version of packet when set
|
||||
unsigned int shaderType: 1; ///< 0: Graphics, 1: Compute Shader
|
||||
unsigned int reserved1 : 6; ///< reserved
|
||||
unsigned int opcode : 8; ///< IT opcode
|
||||
unsigned int count : 14;///< number of DWORDs - 1 in the information body.
|
||||
unsigned int type : 2; ///< packet identifier. It should be 3 for type 3 packets
|
||||
};
|
||||
unsigned int u32All;
|
||||
} PM4_TYPE_3_HEADER;
|
||||
#endif // PM4_HEADER_DEFINED
|
||||
|
||||
//--------------------DISPATCH_DIRECT--------------------
|
||||
|
||||
|
||||
typedef struct _PM4_DISPATCH_DIRECT
|
||||
{
|
||||
union
|
||||
{
|
||||
PM4_TYPE_3_HEADER header; ///header
|
||||
unsigned int ordinal1;
|
||||
};
|
||||
|
||||
unsigned int dim_x;
|
||||
|
||||
|
||||
unsigned int dim_y;
|
||||
|
||||
|
||||
unsigned int dim_z;
|
||||
|
||||
|
||||
unsigned int dispatch_initiator;
|
||||
|
||||
|
||||
} PM4DISPATCH_DIRECT, *PPM4DISPATCH_DIRECT;
|
||||
|
||||
//--------------------INDIRECT_BUFFER--------------------
|
||||
|
||||
enum INDIRECT_BUFFER_cache_policy_enum { cache_policy_indirect_buffer_LRU_0 = 0, cache_policy_indirect_buffer_STREAM_1 = 1, cache_policy_indirect_buffer_BYPASS_2 = 2 };
|
||||
|
||||
|
||||
//--------------------EVENT_WRITE--------------------
|
||||
|
||||
enum EVENT_WRITE_event_index_enum { event_index_event_write_OTHER_0 = 0, event_index_event_write_ZPASS_DONE_1 = 1, event_index_event_write_SAMPLE_PIPELINESTAT_2 = 2, event_index_event_write_SAMPLE_STREAMOUTSTAT_3 = 3, event_index_event_write_CS_VS_PS_PARTIAL_FLUSH_4 = 4, event_index_event_write_RESERVED_EOP_5 = 5, event_index_event_write_RESERVED_EOS_6 = 6, event_index_event_write_CACHE_FLUSH_7 = 7 };
|
||||
|
||||
typedef struct _PM4_EVENT_WRITE
|
||||
{
|
||||
union
|
||||
{
|
||||
PM4_TYPE_3_HEADER header; ///header
|
||||
unsigned int ordinal1;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int event_type:6;
|
||||
unsigned int reserved1:2;
|
||||
EVENT_WRITE_event_index_enum event_index:4;
|
||||
unsigned int reserved2:20;
|
||||
} bitfields2;
|
||||
unsigned int ordinal2;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int reserved3:3;
|
||||
unsigned int address_lo:29;
|
||||
} bitfields3;
|
||||
unsigned int ordinal3;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int address_hi:16;
|
||||
unsigned int reserved4:16;
|
||||
} bitfields4;
|
||||
unsigned int ordinal4;
|
||||
};
|
||||
|
||||
} PM4EVENT_WRITE, *PPM4EVENT_WRITE;
|
||||
|
||||
|
||||
//--------------------SET_SH_REG--------------------
|
||||
|
||||
|
||||
typedef struct _PM4_SET_SH_REG
|
||||
{
|
||||
union
|
||||
{
|
||||
PM4_TYPE_3_HEADER header; ///header
|
||||
unsigned int ordinal1;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int reg_offset:16;
|
||||
unsigned int reserved1:16;
|
||||
} bitfields2;
|
||||
unsigned int ordinal2;
|
||||
};
|
||||
|
||||
unsigned int reg_data[1]; //1..N of these fields
|
||||
|
||||
|
||||
} PM4SET_SH_REG, *PPM4SET_SH_REG;
|
||||
|
||||
|
||||
//--------------------ACQUIRE_MEM--------------------
|
||||
|
||||
enum ACQUIRE_MEM_engine_enum { engine_acquire_mem_PFP_0 = 0, engine_acquire_mem_ME_1 = 1 };
|
||||
|
||||
|
||||
typedef struct _PM4_ACQUIRE_MEM
|
||||
{
|
||||
union
|
||||
{
|
||||
PM4_TYPE_3_HEADER header; ///header
|
||||
unsigned int ordinal1;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int coher_cntl:31;
|
||||
ACQUIRE_MEM_engine_enum engine:1;
|
||||
} bitfields2;
|
||||
unsigned int ordinal2;
|
||||
};
|
||||
|
||||
unsigned int coher_size;
|
||||
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int coher_size_hi:8;
|
||||
unsigned int reserved1:24;
|
||||
} bitfields3;
|
||||
unsigned int ordinal4;
|
||||
};
|
||||
|
||||
unsigned int coher_base_lo;
|
||||
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int coher_base_hi:25;
|
||||
unsigned int reserved2:7;
|
||||
} bitfields4;
|
||||
unsigned int ordinal6;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int poll_interval:16;
|
||||
unsigned int reserved3:16;
|
||||
} bitfields5;
|
||||
unsigned int ordinal7;
|
||||
};
|
||||
|
||||
} PM4ACQUIRE_MEM, *PPM4ACQUIRE_MEM;
|
||||
|
||||
|
||||
//--------------------MEC_INDIRECT_BUFFER--------------------
|
||||
|
||||
typedef struct _PM4_MEC_INDIRECT_BUFFER
|
||||
{
|
||||
union
|
||||
{
|
||||
PM4_TYPE_3_HEADER header; ///header
|
||||
unsigned int ordinal1;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int swap_function:2;
|
||||
unsigned int ib_base_lo:30;
|
||||
} bitfields2;
|
||||
unsigned int ordinal2;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int ib_base_hi:16;
|
||||
unsigned int reserved1:16;
|
||||
} bitfields3;
|
||||
unsigned int ordinal3;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int ib_size:20;
|
||||
unsigned int chain:1;
|
||||
unsigned int offload_polling:1;
|
||||
unsigned int volatile_setting:1;
|
||||
unsigned int valid:1;
|
||||
unsigned int vmid:4;
|
||||
INDIRECT_BUFFER_cache_policy_enum cache_policy:2;
|
||||
unsigned int reserved4:2;
|
||||
} bitfields4;
|
||||
unsigned int ordinal4;
|
||||
};
|
||||
|
||||
} PM4MEC_INDIRECT_BUFFER, *PPM4MEC_INDIRECT_BUFFER;
|
||||
|
||||
//--------------------MEC_WRITE_DATA--------------------
|
||||
|
||||
enum MEC_WRITE_DATA_dst_sel_enum { dst_sel_mec_write_data_MEM_MAPPED_REGISTER_0 = 0, dst_sel_mec_write_data_TC_L2_2 = 2, dst_sel_mec_write_data_GDS_3 = 3, dst_sel_mec_write_data_MEMORY_5 = 5 };
|
||||
enum MEC_WRITE_DATA_addr_incr_enum { addr_incr_mec_write_data_INCREMENT_ADDR_0 = 0, addr_incr_mec_write_data_DO_NOT_INCREMENT_ADDR_1 = 1 };
|
||||
enum MEC_WRITE_DATA_wr_confirm_enum { wr_confirm_mec_write_data_DO_NOT_WAIT_FOR_CONFIRMATION_0 = 0, wr_confirm_mec_write_data_WAIT_FOR_CONFIRMATION_1 = 1 };
|
||||
enum MEC_WRITE_DATA_cache_policy_enum { cache_policy_mec_write_data_LRU_0 = 0, cache_policy_mec_write_data_STREAM_1 = 1, cache_policy_mec_write_data_BYPASS_2 = 2 };
|
||||
|
||||
//--------------------MEC_RELEASE_MEM--------------------
|
||||
|
||||
enum MEC_RELEASE_MEM_event_index_enum { event_index_mec_release_mem_EVENT_WRITE_EOP_5 = 5, event_index_mec_release_mem_CS_Done_6 = 6 };
|
||||
enum MEC_RELEASE_MEM_cache_policy_enum { cache_policy_mec_release_mem_LRU_0 = 0, cache_policy_mec_release_mem_STREAM_1 = 1, cache_policy_mec_release_mem_BYPASS_2 = 2 };
|
||||
enum MEC_RELEASE_MEM_dst_sel_enum { dst_sel_mec_release_mem_MEMORY_CONTROLLER_0 = 0, dst_sel_mec_release_mem_TC_L2_1 = 1 };
|
||||
enum MEC_RELEASE_MEM_int_sel_enum { int_sel_mec_release_mem_NONE_0 = 0, int_sel_mec_release_mem_SEND_INTERRUPT_ONLY_1 = 1, int_sel_mec_release_mem_SEND_INTERRUPT_AFTER_WRITE_CONFIRM_2 = 2, int_sel_mec_release_mem_SEND_DATA_AFTER_WRITE_CONFIRM_3 = 3 };
|
||||
enum MEC_RELEASE_MEM_data_sel_enum { data_sel_mec_release_mem_NONE_0 = 0, data_sel_mec_release_mem_SEND_32_BIT_LOW_1 = 1, data_sel_mec_release_mem_SEND_64_BIT_DATA_2 = 2, data_sel_mec_release_mem_SEND_GPU_CLOCK_COUNTER_3 = 3, data_sel_mec_release_mem_SEND_CP_PERFCOUNTER_HI_LO_4 = 4, data_sel_mec_release_mem_STORE_GDS_DATA_TO_MEMORY_5 = 5 };
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,316 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __SDMA_PKT_STRUCT_H__
|
||||
#define __SDMA_PKT_STRUCT_H__
|
||||
|
||||
|
||||
const unsigned int SDMA_OP_COPY = 1;
|
||||
const unsigned int SDMA_OP_WRITE = 2;
|
||||
|
||||
const unsigned int SDMA_OP_FENCE = 5;
|
||||
const unsigned int SDMA_OP_TRAP = 6;
|
||||
|
||||
const unsigned int SDMA_OP_CONST_FILL = 11;
|
||||
|
||||
const unsigned int SDMA_SUBOP_COPY_LINEAR = 0;
|
||||
|
||||
const unsigned int SDMA_SUBOP_WRITE_LINEAR = 0;
|
||||
|
||||
/*
|
||||
** Definitions for SDMA_PKT_COPY_LINEAR packet
|
||||
*/
|
||||
|
||||
typedef struct SDMA_PKT_COPY_LINEAR_TAG
|
||||
{
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int op:8;
|
||||
unsigned int sub_op:8;
|
||||
unsigned int reserved_0:11;
|
||||
unsigned int broadcast:1;
|
||||
unsigned int reserved_1:4;
|
||||
};
|
||||
unsigned int DW_0_DATA;
|
||||
} HEADER_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int count:22;
|
||||
unsigned int reserved_0:10;
|
||||
};
|
||||
unsigned int DW_1_DATA;
|
||||
} COUNT_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int reserved_0:16;
|
||||
unsigned int dst_sw:2;
|
||||
unsigned int reserved_1:4;
|
||||
unsigned int dst_ha:1;
|
||||
unsigned int reserved_2:1;
|
||||
unsigned int src_sw:2;
|
||||
unsigned int reserved_3:4;
|
||||
unsigned int src_ha:1;
|
||||
unsigned int reserved_4:1;
|
||||
};
|
||||
unsigned int DW_2_DATA;
|
||||
} PARAMETER_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int src_addr_31_0:32;
|
||||
};
|
||||
unsigned int DW_3_DATA;
|
||||
} SRC_ADDR_LO_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int src_addr_63_32:32;
|
||||
};
|
||||
unsigned int DW_4_DATA;
|
||||
} SRC_ADDR_HI_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int dst_addr_31_0:32;
|
||||
};
|
||||
unsigned int DW_5_DATA;
|
||||
} DST_ADDR_LO_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int dst_addr_63_32:32;
|
||||
};
|
||||
unsigned int DW_6_DATA;
|
||||
} DST_ADDR_HI_UNION;
|
||||
} SDMA_PKT_COPY_LINEAR, *PSDMA_PKT_COPY_LINEAR;
|
||||
|
||||
/*
|
||||
** Definitions for SDMA_PKT_WRITE_UNTILED packet
|
||||
*/
|
||||
|
||||
typedef struct SDMA_PKT_WRITE_UNTILED_TAG
|
||||
{
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int op:8;
|
||||
unsigned int sub_op:8;
|
||||
unsigned int reserved_0:16;
|
||||
};
|
||||
unsigned int DW_0_DATA;
|
||||
} HEADER_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int dst_addr_31_0:32;
|
||||
};
|
||||
unsigned int DW_1_DATA;
|
||||
} DST_ADDR_LO_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int dst_addr_63_32:32;
|
||||
};
|
||||
unsigned int DW_2_DATA;
|
||||
} DST_ADDR_HI_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int count:22;
|
||||
unsigned int reserved_0:2;
|
||||
unsigned int sw:2;
|
||||
unsigned int reserved_1:6;
|
||||
};
|
||||
unsigned int DW_3_DATA;
|
||||
} DW_3_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int data0:32;
|
||||
};
|
||||
unsigned int DW_4_DATA;
|
||||
} DATA0_UNION;
|
||||
} SDMA_PKT_WRITE_UNTILED, *PSDMA_PKT_WRITE_UNTILED;
|
||||
|
||||
/*
|
||||
** Definitions for SDMA_PKT_FENCE packet
|
||||
*/
|
||||
|
||||
typedef struct SDMA_PKT_FENCE_TAG
|
||||
{
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int op:8;
|
||||
unsigned int sub_op:8;
|
||||
unsigned int reserved_0:16;
|
||||
};
|
||||
unsigned int DW_0_DATA;
|
||||
} HEADER_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int addr_31_0:32;
|
||||
};
|
||||
unsigned int DW_1_DATA;
|
||||
} ADDR_LO_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int addr_63_32:32;
|
||||
};
|
||||
unsigned int DW_2_DATA;
|
||||
} ADDR_HI_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int data:32;
|
||||
};
|
||||
unsigned int DW_3_DATA;
|
||||
} DATA_UNION;
|
||||
} SDMA_PKT_FENCE, *PSDMA_PKT_FENCE;
|
||||
|
||||
/*
|
||||
** Definitions for SDMA_PKT_CONSTANT_FILL packet
|
||||
*/
|
||||
|
||||
typedef struct SDMA_PKT_CONSTANT_FILL_TAG
|
||||
{
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int op:8;
|
||||
unsigned int sub_op:8;
|
||||
unsigned int sw:2;
|
||||
unsigned int reserved_0:12;
|
||||
unsigned int fillsize:2;
|
||||
};
|
||||
unsigned int DW_0_DATA;
|
||||
} HEADER_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int dst_addr_31_0:32;
|
||||
};
|
||||
unsigned int DW_1_DATA;
|
||||
} DST_ADDR_LO_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int dst_addr_63_32:32;
|
||||
};
|
||||
unsigned int DW_2_DATA;
|
||||
} DST_ADDR_HI_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int src_data_31_0:32;
|
||||
};
|
||||
unsigned int DW_3_DATA;
|
||||
} DATA_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int count:22;
|
||||
unsigned int reserved_0:10;
|
||||
};
|
||||
unsigned int DW_4_DATA;
|
||||
} COUNT_UNION;
|
||||
} SDMA_PKT_CONSTANT_FILL, *PSDMA_PKT_CONSTANT_FILL;
|
||||
|
||||
/*
|
||||
** Definitions for SDMA_PKT_TRAP packet
|
||||
*/
|
||||
|
||||
typedef struct SDMA_PKT_TRAP_TAG
|
||||
{
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int op:8;
|
||||
unsigned int sub_op:8;
|
||||
unsigned int reserved_0:16;
|
||||
};
|
||||
unsigned int DW_0_DATA;
|
||||
} HEADER_UNION;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
unsigned int int_context:28;
|
||||
unsigned int reserved_0:4;
|
||||
};
|
||||
unsigned int DW_1_DATA;
|
||||
} INT_CONTEXT_UNION;
|
||||
} SDMA_PKT_TRAP, *PSDMA_PKT_TRAP;
|
||||
|
||||
|
||||
#endif // __SDMA_PKT_STRUCT_H__
|
||||
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