Pull from Github
Squashed commit of the following: commit f029195705a15700380c6f832ba5d15d46fd6de7 Author: Jonathan R. Madsen <jrmadsen@users.noreply.github.com> Date: Thu Jul 13 14:38:56 2023 -0500 Formatting workflows for source (clang-format) and cmake (cmake-format) (#4) * Add .cmake-format.yaml file * Add formatting workflow * provide base input for creating PR * Update scheme for extracting branch name - disable running formatting on push to amd-staging branch * patch .cmake-format.yaml for find_package signature - apparently cmake-format doesn't format the full signature of find_package * run formatting (clang-format v11) (#7) Co-authored-by: jrmadsen <jrmadsen@users.noreply.github.com> * run cmake formatting (cmake-format) (#6) Co-authored-by: jrmadsen <jrmadsen@users.noreply.github.com> --------- Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> commit bc4d135fdd8a1a9e51235f18a5d575fd2b3735e6 Author: Ammar ELWazir <aelwazir@amd.com> Date: Thu Jul 13 12:55:17 2023 -0500 Removing Build cache for potential issues with auto-generated header files (#5) Change-Id: I9e2319f4335e2f88585ffa6fac2bd88a1c952e6e commit ce86dea6a311d44d880fa684eb78f3329295e2a4 Author: Jonathan R. Madsen <jrmadsen@users.noreply.github.com> Date: Thu Jul 13 11:08:58 2023 -0500 Fix decltype(<hsa-function>) function pointer usage (#3) - the following is done in several places: decltype(hsa_memory_allocate)* hsa_memory_allocate - above can cause compiler errors - replace decltype(<hsa-function>) with decltype(::<hsa-function>) - this ensures that the type within the decltype is recognized as the global scope HSA function, not the variable - in many places, the variable has a "_fn" suffix to prevent this issue but added '::' anyway for consistency commit ac49fdd92a72e9c99394253a02da413a6c2e3b3a Merge: a07946a 03a0855 Author: Ammar ELWazir <aelwazir@amd.com> Date: Wed Jul 12 11:36:24 2023 -0500 Merge pull request #2 from ROCm-Developer-Tools/gerrit-amd-staging Pull from gerrit commit 03a085588cffe863e8f466de67be1cfb205b675a Merge:c26b32ba07946a Author: Ammar ELWazir <aelwazir@amd.com> Date: Wed Jul 12 10:57:30 2023 -0500 Merge branch 'amd-staging' into gerrit-amd-staging commit a07946a5cd4c670c83c27ad1a076a9d4567ce6d7 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 15:46:04 2023 +0000 Enabling Cached Builds commit 525e494a7f13941077a8fd4ad6840904db4d27d4 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 04:53:54 2023 +0000 Updating missed GPU Targets commit 42c75862f628c9bee7cfb7dc04dff2619430efbc Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 04:43:02 2023 +0000 Adding V1 Testing commit 9d72fd4aee85e4b0c12e717060d2730fa5b73be1 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 03:34:31 2023 +0000 Fixing Artifacts directory path commit f4000cc558b3b2e4676f7994f7ce8c8e6f94518e Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 03:27:26 2023 +0000 Fixing CMake for test build job commit 2ce8115d4c33948c3c8f957f545a95a04e1d6cd2 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 03:16:18 2023 +0000 Fixing Ubuntu CMake for ubuntu test build commit 6d0ed439191be900748d0c025157f9d689a73ec7 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 01:28:41 2023 +0000 Removing Navi21 commit e349a7642e5ae5eb03ab9fcd0a0f74f09f78cab5 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 01:14:14 2023 +0000 Removing Navi21 commit fefd02fe68d2a4bca7ec2e381960ad004ee9fc5b Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 00:42:48 2023 +0000 Fixing CMake Job commit 2ea46abf7bf92643efa8c549fa70346ffbd79d65 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 00:35:13 2023 +0000 Fixing CMake Job commit d99d681ed1999c5fcf291dc678b11a77205fb0f3 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 00:32:13 2023 +0000 Fixing Pull Latest Dockers and CMake Jobs commit dfc4498072d13b4a1df3a63047d34c682c3d9a29 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Tue Jul 11 23:54:21 2023 +0000 Fixing CMake job commit 919efe04de707f7c702031be15c3e2c5f8442cbb Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Tue Jul 11 23:52:13 2023 +0000 Adding Pull Last dockers job commit be1b1256e8b0e05308e8f7e7e69bee3acca55281 Author: Ammar ELWazir <aelwazir@amd.com> Date: Tue Jul 11 18:25:40 2023 -0500 Update cmake.yml commit 212299fa4355ae6ec18f9aaacbb79c51ea6c6f97 Author: Ammar ELWazir <aelwazir@amd.com> Date: Tue Jul 11 18:23:35 2023 -0500 Update cmake.yml commit 7c2c1327086a61466cc6cac39f70865c051a8bc7 Author: Ammar ELWazir <aelwazir@amd.com> Date: Tue Jul 11 18:18:53 2023 -0500 Update cmake.yml commit 191b5ce007e612e814c1d7a3afb4ad398f3852e1 Author: Ammar ELWazir <aelwazir@amd.com> Date: Tue Jul 11 16:03:22 2023 -0500 Update cmake.yml commit 8824113d95f3e13c7ce4d0af8e0d9d8f522a6c4a Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Tue Jul 11 16:28:09 2023 +0000 Fixing Pull from Gerrit job name Change-Id: I9e7ed9a27a13ca49d62c93bdadb30f0057e4d385 commit cc3d5e4b02ffb439e8cc2b3efa53527c376f9982 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Tue Jul 11 16:21:43 2023 +0000 Adding Staging sync job Change-Id: I0551f43878b0678ce4b3e74e27d62357cf95ad95 commit b9be2eee71380a2e6dd34d520e92d0c4209277a0 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Tue Jul 11 15:57:11 2023 +0000 Fixing build.sh Change-Id: Ia987b0244f0875370d5fe69907b3f5e9cea914de commit 9eee33a95a1abd656a7ac5ca10a9f245e9825431 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 21:39:46 2023 -0500 Update cmake.yml commit 7093b85a78497140e8b52632ca2a002bdaeacd62 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 21:33:29 2023 -0500 Update cmake.yml commit f54697172c72a67740f9fdfa0c217b6ea6931576 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 21:01:26 2023 -0500 Update cmake.yml commit 1b6620e16f8940386b0f4f04e69e2410d21c0e26 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 20:21:02 2023 -0500 Update cmake.yml commit a94bec740c6b42c4b79c87bca20fa87b99bf060d Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 19:46:35 2023 -0500 Update cmake.yml commit 85d6b29d4375a69d575c18ece8542c50f2ddfcc3 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 19:34:39 2023 -0500 Update cmake.yml commit 8c004887cf1435f1a6214c3d2455299a8a27bd4c Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 19:31:17 2023 -0500 Update cmake.yml commit a14a9168e17d9348a53c6e9c9a47ba1edb4c4509 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 19:25:46 2023 -0500 Update cmake.yml commit 000f2f40b84e6a2f7d4becdbf5aed01436ca4c83 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 19:08:18 2023 -0500 Update cmake.yml commit a28a53d56731cad848fa9133d1c4dbaa8fc7afa7 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 19:03:39 2023 -0500 Update cmake.yml commit a6a2db01027f0b01fdfbb5997ddb772c7f51b649 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 18:21:53 2023 -0500 Update cmake.yml commit 118ef2a88b2d44e3207c31c343da3e5e5ec6f176 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 17:55:57 2023 -0500 Update cmake.yml commit 03c4c232396440cd0be6d2dd7baf4ceea1c2589d Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 17:48:49 2023 -0500 Create cmake.yml Change-Id: I77992f15694e77cbae49c56f9ff02f4f9079235d [ROCm/rocprofiler commit:d4a33cf33a]
This commit is contained in:
Ammar ELWazir
committed by
Ammar Elwazir
Ammar Elwazir
parent
e599708211
commit
6eb06cf201
@@ -27,8 +27,7 @@ namespace Counter {
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static std::atomic<uint64_t> COUNTER_COUNTER{0};
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DerivedCounter::DerivedCounter(std::string name, std::string description,
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std::string gpu_name)
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DerivedCounter::DerivedCounter(std::string name, std::string description, std::string gpu_name)
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: Counter(name, description, gpu_name) {
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metric_id_ = COUNTER_COUNTER.fetch_add(1, std::memory_order_release);
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addCounterToCounterMap();
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@@ -41,20 +40,17 @@ DerivedCounter::~DerivedCounter() {
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uint64_t DerivedCounter::getMetricId() { return metric_id_; }
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std::map<uint64_t, BasicCounter*> *DerivedCounter::getAllCounters() {
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return &counters_;
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}
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std::map<uint64_t, BasicCounter*>* DerivedCounter::getAllCounters() { return &counters_; }
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BasicCounter *DerivedCounter::getBasicCounterFromDerived(uint64_t counter_id) {
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BasicCounter* DerivedCounter::getBasicCounterFromDerived(uint64_t counter_id) {
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return counters_[counter_id];
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}
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void DerivedCounter::addBasicCounter(uint64_t counter_id,
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BasicCounter *counter) {
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void DerivedCounter::addBasicCounter(uint64_t counter_id, BasicCounter* counter) {
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counters_.emplace(counter_id, counter);
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}
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@DERIVED_XML_PARSE_RESULT@
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@DERIVED_XML_PARSE_RESULT @
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} // namespace Counter
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@@ -39,8 +39,7 @@ namespace Counter {
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class DerivedCounter : Counter {
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public:
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std::function<uint64_t()> evaluate_metric;
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DerivedCounter(std::string name, std::string description,
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std::string gpu_name);
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DerivedCounter(std::string name, std::string description, std::string gpu_name);
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~DerivedCounter();
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uint64_t getMetricId();
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@@ -108,7 +108,7 @@ bool metrics::ExtractMetricEvents(
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// adding result object for derived metric
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std::lock_guard<std::mutex> lock(extract_metric_events_lock);
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if(metric_names[i].compare("KERNEL_DURATION")==0) {
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if (metric_names[i].compare("KERNEL_DURATION") == 0) {
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if (results_map.find(metric_names[i]) == results_map.end()) {
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results_map[metric_names[i]] = new results_t(metric_names[i], {}, xcc_count);
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}
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@@ -192,7 +192,7 @@ bool metrics::GetMetricsData(std::map<std::string, results_t*>& results_map,
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auto it = results_map.find(metric->GetName());
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if (it == results_map.end()) rocprofiler::fatal("metric results not found ");
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results_t* res = it->second;
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if(metric->GetName().compare("KERNEL_DURATION") == 0) {
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if (metric->GetName().compare("KERNEL_DURATION") == 0) {
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res->val_double = kernel_duration;
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continue;
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}
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@@ -206,7 +206,8 @@ bool metrics::GetMetricsData(std::map<std::string, results_t*>& results_map,
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void metrics::GetCountersAndMetricResultsByXcc(uint32_t xcc_index,
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std::vector<results_t*>& results_list,
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std::map<std::string, results_t*>& results_map,
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std::vector<const Metric*>& metrics_list, uint64_t kernel_duration) {
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std::vector<const Metric*>& metrics_list,
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uint64_t kernel_duration) {
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for (auto it = results_list.begin(); it != results_list.end(); it++) {
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(*it)->val_double =
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(*it)->xcc_vals[xcc_index]; // set val_double to hold value for specific xcc
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@@ -35,10 +35,10 @@ namespace rocprofiler {
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typedef std::vector<double> xcc_results_t;
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class results_t{
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public:
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results_t(std::string in_name, event_t in_event, uint32_t xcc_count):
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name(in_name), val_double(0), event(in_event) {
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class results_t {
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public:
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results_t(std::string in_name, event_t in_event, uint32_t xcc_count)
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: name(in_name), val_double(0), event(in_event) {
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xcc_vals.resize(xcc_count);
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std::fill(xcc_vals.begin(), xcc_vals.end(), 0);
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}
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@@ -78,8 +78,9 @@ bool GetMetricsData(std::map<std::string, results_t*>& results_map,
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std::vector<const Metric*>& metrics_list, uint64_t kernel_duration = 0);
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void GetCountersAndMetricResultsByXcc(uint32_t xcc_index, std::vector<results_t*>& results_list,
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std::map<std::string, results_t*>& results_map,
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std::vector<const Metric*>& metrics_list, uint64_t kernel_duration = 0);
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std::map<std::string, results_t*>& results_map,
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std::vector<const Metric*>& metrics_list,
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uint64_t kernel_duration = 0);
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} // namespace metrics
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} // namespace rocprofiler
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@@ -45,7 +45,7 @@ THE SOFTWARE.
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do { \
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std::ostringstream oss; \
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oss << __FUNCTION__ << "(), " << stream; \
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throw rocprofiler::util::exception(error, oss.str()); \
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throw rocprofiler::util::exception(error, oss.str()); \
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} while (0)
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#define AQL_EXC_RAISING(error, stream) \
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Executable → Regular
+3
-6
@@ -221,14 +221,11 @@ class MetricsDict {
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agent_name_ = agent_name_.substr(0, agent_name_.find(':'));
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std::unordered_set<std::string> supported_agent_names = {
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"gfx906",
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"gfx908",
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"gfx906", "gfx908",
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"gfx90a", // Vega
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"gfx940",
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"gfx941",
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"gfx940", "gfx941",
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"gfx942", // Mi300
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"gfx1030",
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"gfx1031",
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"gfx1030", "gfx1031",
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"gfx1032", // Navi2x
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"gfx1100",
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"gfx1101" // Navi3x
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@@ -17,8 +17,8 @@ class DFPerfMonMI200 : public PerfMon {
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DFPerfMonMI200(const Agent::AgentInfo& info);
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~DFPerfMonMI200();
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void Start() override;
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void Stop() {};
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void Read(std::vector<rocprofiler_counters_sampler_counter_output_t>& values) {};
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void Stop(){};
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void Read(std::vector<rocprofiler_counters_sampler_counter_output_t>& values){};
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void SetCounterNames(std::vector<std::string>& counter_names);
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mmio::mmap_type_t Type() override { return mmio::mmap_type_t::DF_PERFMON; }
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@@ -31,7 +31,6 @@ class DFPerfMonMI200 : public PerfMon {
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uint64_t GetFicaNodeOutboundBw(uint32_t ficaa_val);
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private:
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mmio::DFPerfmonMMIO* mmio_;
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static std::mutex mutex_; // should be an MMIO member
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@@ -13,12 +13,12 @@ PciePerfMonMI200::~PciePerfMonMI200() {
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mmio::MMIOManager::DestroyMMIOInstance(dynamic_cast<mmio::MMIO*>(mmio_));
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}
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void PciePerfMonMI200::writeRegister(uint32_t reg_offset, uint32_t value){
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void PciePerfMonMI200::writeRegister(uint32_t reg_offset, uint32_t value) {
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// mmio or ioctl approaches
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mmio_->RegisterWriteAPI(reg_offset, value);
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mmio_->RegisterWriteAPI(reg_offset, value);
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}
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void PciePerfMonMI200::readRegister(uint32_t reg_offset, uint32_t& value){
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void PciePerfMonMI200::readRegister(uint32_t reg_offset, uint32_t& value) {
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// mmio or ioctl approaches
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mmio_->RegisterReadAPI(reg_offset, value);
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}
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@@ -35,44 +35,40 @@ void PciePerfMonMI200::SetCounterNames(std::vector<std::string>& counter_names)
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}
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}
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void PciePerfMonMI200::Start(){
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void PciePerfMonMI200::Start() {
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// TODO: make sure values stored in table
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// in registers header are dec and not hex
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Start_RX_TILE_SCLK(event_id_);
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}
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void PciePerfMonMI200::Stop(){
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void PciePerfMonMI200::Stop() {
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// TODO: revisit correct value to stop
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writeRegister(PCIE_MI200::PCIE_PERF_COUNT_CNTL, 0x2); // stop
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writeRegister(PCIE_MI200::PCIE_PERF_COUNT_CNTL, 0x2); // stop
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}
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void PciePerfMonMI200::Read(std::vector<rocprofiler_counters_sampler_counter_output_t>& values){
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uint64_t val=0;
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void PciePerfMonMI200::Read(std::vector<rocprofiler_counters_sampler_counter_output_t>& values) {
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uint64_t val = 0;
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Read_RX_TILE_SCLK(val);
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rocprofiler_counters_sampler_counter_output_t value = {
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ROCPROFILER_COUNTERS_SAMPLER_PCIE_COUNTERS,
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static_cast<double>(val)
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};
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rocprofiler_counters_sampler_counter_output_t value = {ROCPROFILER_COUNTERS_SAMPLER_PCIE_COUNTERS,
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static_cast<double>(val)};
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values.push_back(value);
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}
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void PciePerfMonMI200::Start_RX_TILE_TXCLK(uint32_t event){
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void PciePerfMonMI200::Start_RX_TILE_TXCLK(uint32_t event) {
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// Step 1: PORT SEL update
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writeRegister(PCIE_MI200::PCIE_PERF_CNTL_EVENT_CI_PORT_SEL, 0x0);
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// Step 2: EVENT SEL update
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uint32_t value = event; // last 8 bits for event
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uint32_t value = event; // last 8 bits for event
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writeRegister(PCIE_MI200::PCIE_PERF_CNTL_TXCLK3, value);
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// Steps 3 & 4: Performance counters initialization, enable:
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// TODO: revisit. Just a single write with 0x3 might be enough (check with pcie team)
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writeRegister(PCIE_MI200::PCIE_PERF_COUNT_CNTL, 0x5);
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}
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void PciePerfMonMI200::Read_RX_TILE_TXCLK(uint64_t& result){
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void PciePerfMonMI200::Read_RX_TILE_TXCLK(uint64_t& result) {
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// Step 5: Performance counters read:
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uint32_t lo_val, hi_val;
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readRegister(PCIE_MI200::PCIE_PERF_COUNT0_TXCLK3, lo_val);
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@@ -84,22 +80,20 @@ void PciePerfMonMI200::Read_RX_TILE_TXCLK(uint64_t& result){
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result = val | lo_val;
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}
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void PciePerfMonMI200::Start_RX_TILE_SCLK(uint32_t event){
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void PciePerfMonMI200::Start_RX_TILE_SCLK(uint32_t event) {
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// Step 1: PORT SEL update
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writeRegister(PCIE_MI200::PCIE_PERF_CNTL_EVENT_CI_PORT_SEL, 0x0);
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// Step 2: EVENT SEL update
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uint32_t value = event; // last 8 bits for event
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uint32_t value = event; // last 8 bits for event
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writeRegister(PCIE_MI200::PCIE_PERF_CNTL_LCLK1, value);
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// Steps 3 & 4: Performance counters initialization, enable:
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// TODO: revisit. Just a single write with 0x3 might be enough (check with pcie team)
|
||||
writeRegister(PCIE_MI200::PCIE_PERF_COUNT_CNTL, 0x5);
|
||||
|
||||
}
|
||||
|
||||
void PciePerfMonMI200::Read_RX_TILE_SCLK(uint64_t& result){
|
||||
void PciePerfMonMI200::Read_RX_TILE_SCLK(uint64_t& result) {
|
||||
// Step 5: Performance counters read:
|
||||
uint32_t lo_val, hi_val;
|
||||
readRegister(PCIE_MI200::PCIE_PERF_COUNT0_LCLK1, lo_val);
|
||||
@@ -111,6 +105,4 @@ void PciePerfMonMI200::Read_RX_TILE_SCLK(uint64_t& result){
|
||||
result = val | lo_val;
|
||||
}
|
||||
|
||||
} // namespace rocprofiler
|
||||
|
||||
|
||||
} // namespace rocprofiler
|
||||
|
||||
@@ -22,7 +22,7 @@ class PciePerfMonMI200 : public PerfMon {
|
||||
mmio::mmap_type_t Type() override { return mmio::mmap_type_t::PCIE_PERFMON; }
|
||||
|
||||
private:
|
||||
// TODO : check google coding std
|
||||
// TODO : check google coding std
|
||||
void writeRegister(uint32_t reg_offset, uint32_t value);
|
||||
void readRegister(uint32_t reg_offset, uint32_t& value);
|
||||
|
||||
|
||||
@@ -4,70 +4,70 @@
|
||||
#include <stdint.h>
|
||||
|
||||
namespace PCIE_MI200 {
|
||||
|
||||
|
||||
// -------- RX Tile TXCLK Start --------
|
||||
|
||||
// Step 1: PORT SEL update
|
||||
const static uint32_t PCIE_PERF_CNTL_EVENT_CI_PORT_SEL = 0x11180250;
|
||||
|
||||
// Step 2: EVENT SEL update
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK1 = 0x11180204;
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK2 = 0x11180210;
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK3 = 0x1118021C; //#
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK4 = 0x11180228; //#
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK5 = 0x11180258;
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK6 = 0x11180264;
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK7 = 0x11180888;
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK8 = 0x11180894;
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK9 = 0x111808A0;
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK10 = 0x111808AC;
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK1 = 0x11180204;
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK2 = 0x11180210;
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK3 = 0x1118021C; //#
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK4 = 0x11180228; //#
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK5 = 0x11180258;
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK6 = 0x11180264;
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK7 = 0x11180888;
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK8 = 0x11180894;
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK9 = 0x111808A0;
|
||||
const static uint32_t PCIE_PERF_CNTL_TXCLK10 = 0x111808AC;
|
||||
|
||||
// Steps 3 & 4: Performance counters initialization, enable:
|
||||
const static uint32_t PCIE_PERF_COUNT_CNTL = 0x11180200;
|
||||
|
||||
// Step 5: Performance counters read:
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK1 = 0x11180208;
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK2 = 0x11180214;
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK3 = 0x11180220; //#
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK4 = 0x1118022C; //#
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK5 = 0x1118025C;
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK6 = 0x11180268;
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK7 = 0x1118088C;
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK8 = 0x11180898;
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK9 = 0x111808A4;
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK10 = 0x111808B0;
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK1 = 0x11180208;
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK2 = 0x11180214;
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK3 = 0x11180220; //#
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK4 = 0x1118022C; //#
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK5 = 0x1118025C;
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK6 = 0x11180268;
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK7 = 0x1118088C;
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK8 = 0x11180898;
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK9 = 0x111808A4;
|
||||
const static uint32_t PCIE_PERF_COUNT0_TXCLK10 = 0x111808B0;
|
||||
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK1 = 0x111808E8;
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK2 = 0x111808F0;
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK3 = 0x111808F8; //#
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK4 = 0x11180900; //#
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK5 = 0x11180908;
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK6 = 0x11180910;
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK7 = 0x11180918;
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK8 = 0x11180920;
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK9 = 0x11180928;
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK1 = 0x111808E8;
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK2 = 0x111808F0;
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK3 = 0x111808F8; //#
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK4 = 0x11180900; //#
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK5 = 0x11180908;
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK6 = 0x11180910;
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK7 = 0x11180918;
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK8 = 0x11180920;
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK9 = 0x11180928;
|
||||
const static uint32_t PCIE_PERF_COUNT0_UPVAL_TXCLK10 = 0x11180930;
|
||||
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK1 = 0x1118020C;
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK2 = 0x11180218;
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK3 = 0x11180224; //#
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK4 = 0x11180230; //#
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK5 = 0x11180260;
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK6 = 0x1118026C;
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK7 = 0x11180890;
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK8 = 0x1118089C;
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK9 = 0x111808A8;
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK1 = 0x1118020C;
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK2 = 0x11180218;
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK3 = 0x11180224; //#
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK4 = 0x11180230; //#
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK5 = 0x11180260;
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK6 = 0x1118026C;
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK7 = 0x11180890;
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK8 = 0x1118089C;
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK9 = 0x111808A8;
|
||||
const static uint32_t PCIE_PERF_COUNT1_TXCLK10 = 0x111808B4;
|
||||
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK1 = 0x111808EC;
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK2 = 0x111808F4;
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK3 = 0x111808FC; //#
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK4 = 0x11180904; //#
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK5 = 0x1118090C;
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK6 = 0x11180914;
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK7 = 0x1118091C;
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK8 = 0x11180924;
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK9 = 0x1118092C;
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK1 = 0x111808EC;
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK2 = 0x111808F4;
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK3 = 0x111808FC; //#
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK4 = 0x11180904; //#
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK5 = 0x1118090C;
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK6 = 0x11180914;
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK7 = 0x1118091C;
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK8 = 0x11180924;
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK9 = 0x1118092C;
|
||||
const static uint32_t PCIE_PERF_COUNT1_UPVAL_TXCLK10 = 0x11180934;
|
||||
|
||||
|
||||
@@ -127,201 +127,200 @@ const static uint32_t PCIE_PERF_COUNT1_UPVAL_LCLK8 = 0x11180974;
|
||||
|
||||
// -------- RX Tile SCLK End ----------
|
||||
|
||||
typedef enum{
|
||||
TX_TILE_TXCLK = 0,
|
||||
TX_TILE_SCLK = 1,
|
||||
RX_TILE_TXCLK = 2,
|
||||
RX_TILE_SCLK = 3,
|
||||
LC_TILE_TXCLK = 4
|
||||
}pcie_event_category_t;
|
||||
typedef enum {
|
||||
TX_TILE_TXCLK = 0,
|
||||
TX_TILE_SCLK = 1,
|
||||
RX_TILE_TXCLK = 2,
|
||||
RX_TILE_SCLK = 3,
|
||||
LC_TILE_TXCLK = 4
|
||||
} pcie_event_category_t;
|
||||
|
||||
struct pcie_event_t{
|
||||
pcie_event_t(int id, pcie_event_category_t cat): event_id(id), event_category(cat){}
|
||||
int event_id;
|
||||
pcie_event_category_t event_category;
|
||||
struct pcie_event_t {
|
||||
pcie_event_t(int id, pcie_event_category_t cat) : event_id(id), event_category(cat) {}
|
||||
int event_id;
|
||||
pcie_event_category_t event_category;
|
||||
};
|
||||
|
||||
const static std::map<std::string, pcie_event_t> pcie_events_table = {
|
||||
{"RX_PERF_RXP_RX_TailEdb_A[0]", {2, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_TailEdb_A[1]", {3, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_TailEdb_A[2]", {4, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_TailEdb_A[3]", {5, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_TailEnd_A[0]", {6, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_TailEnd_A[1]", {7, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_TailEnd_A[2]", {8, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_TailEnd_A[3]", {9, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadSdp_A[0]", {10, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadSdp_A[1]", {11, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadSdp_A[2]", {12, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadSdp_A[3]", {13, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadStp_A[0]", {14, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadStp_A[1]", {15, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadStp_A[2]", {16, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadStp_A[3]", {17, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXCRC_nullified_tlp_A", {18, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXCRC_valid_crc_A", {19, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXCRC_invalid_crc_A", {20, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_vendor_type1_A", {21, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_vendor_type0_A", {22, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_set_slot_power_limit_A", {23, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_unlock_A", {24, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_err_fatal_A", {25, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_err_nonfatal_A", {26, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_err_corr_A", {27, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_pme_to_ack_A", {28, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_pme_turn_off_A", {29, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_pm_pme_A", {30, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_pm_active_state_nak_A", {31, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_deassert_intd_A", {32, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_deassert_intc_A", {33, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_deassert_intb_A", {34, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_deassert_inta_A", {35, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_assert_intd_A", {36, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_assert_intc_A", {37, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_assert_intb_A", {38, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_assert_inta_A", {39, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_valid_A", {40, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_unsupported_A", {41, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RCB_unexpected_cpl_A", {42, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RCB_timeout_cpl_A", {43, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_HDS_tlphdrvalid_A", {44, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_HDS_tlpdatavalid_A", {45, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_GAN_bad_tlp_A", {46, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_GAN_nak_A", {47, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_GAN_ack_A", {48, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_unsupported_req_A", {49, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_unsupported_cpl_A", {50, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_unexpected_cpl_A", {51, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_poisoned_tlp_A", {52, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_poisoned_cpl_A", {53, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_malformed_tlp_A", {54, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_cpl_abort_A", {55, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_request_MSG_A", {56, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_request_CFG_WR_A", {57, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_request_CFG_RD_A", {58, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_request_IO_WR_A", {59, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_request_IO_RD_A", {60, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_request_MEM_WR_A", {61, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_request_MEM_RD_A", {62, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_MST_gt16_A", {63, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_MST_9to16_A", {64, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_MST_5to8_A", {65, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_MST_2to4_A", {66, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_MST_1_A", {67, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_SLV_gt32_A", {68, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_SLV_17to32_A", {69, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_SLV_9to16_A", {70, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_SLV_5to8_A", {71, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_SLV_2to4_A", {72, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_SLV_1_A", {73, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_cpl_status_CA_A", {74, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_cpl_status_CRS_A", {75, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_cpl_status_UR_A", {76, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_cpl_status_SC_A", {77, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_pm_active_state_request_l1_A", {78, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_pm_request_ack_A", {79, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_pm_enter_l23_A", {80, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_pm_enter_l1_A", {81, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_error_A", {82, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_crc_err_A", {83, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_FCC_npd_0", {84, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_FCC_pd_0", {85, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_FCC_nph_0", {86, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_FCC_ph_0", {87, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_fail_crc_rd_hdr_0", {88, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_pass_crc_rd_hdr_0", {89, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_fail_crc_wr_hdr_0", {90, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_pass_crc_wr_hdr_0", {91, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_fail_crc_data_0", {92, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_pass_crc_data_0", {93, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_invalid_crc_0", {94, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_valid_crc_0", {95, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_rd_hdr_WEN_0", {96, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_wr_hdr_WEN_0", {97, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_data_WEN_0", {98, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_non_post_rd_from_FE", {99, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_non_post_wr_from_FE", {100, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_post_req_from_FE", {101, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_non_post_rd_from_FE_0", {102, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_non_post_wr_from_FE_0", {103, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_post_req_from_FE_0", {104, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_nak_A", {111, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_ack_A", {112, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_allErrors_A", {113, RX_TILE_TXCLK}},
|
||||
{"perf_PG_COUNT", {175, RX_TILE_TXCLK}},
|
||||
{"perf_NOT_POWER_GATED", {176, RX_TILE_TXCLK}},
|
||||
{"perf_POWER_GATED", {177, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_TailEdb_A[0]", {2, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_TailEdb_A[1]", {3, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_TailEdb_A[2]", {4, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_TailEdb_A[3]", {5, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_TailEnd_A[0]", {6, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_TailEnd_A[1]", {7, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_TailEnd_A[2]", {8, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_TailEnd_A[3]", {9, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadSdp_A[0]", {10, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadSdp_A[1]", {11, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadSdp_A[2]", {12, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadSdp_A[3]", {13, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadStp_A[0]", {14, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadStp_A[1]", {15, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadStp_A[2]", {16, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXP_RX_HeadStp_A[3]", {17, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXCRC_nullified_tlp_A", {18, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXCRC_valid_crc_A", {19, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RXCRC_invalid_crc_A", {20, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_vendor_type1_A", {21, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_vendor_type0_A", {22, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_set_slot_power_limit_A", {23, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_unlock_A", {24, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_err_fatal_A", {25, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_err_nonfatal_A", {26, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_err_corr_A", {27, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_pme_to_ack_A", {28, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_pme_turn_off_A", {29, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_pm_pme_A", {30, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_pm_active_state_nak_A", {31, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_deassert_intd_A", {32, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_deassert_intc_A", {33, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_deassert_intb_A", {34, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_deassert_inta_A", {35, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_assert_intd_A", {36, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_assert_intc_A", {37, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_assert_intb_A", {38, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_assert_inta_A", {39, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_valid_A", {40, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RMSG_unsupported_A", {41, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RCB_unexpected_cpl_A", {42, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_RCB_timeout_cpl_A", {43, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_HDS_tlphdrvalid_A", {44, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_HDS_tlpdatavalid_A", {45, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_GAN_bad_tlp_A", {46, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_GAN_nak_A", {47, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_GAN_ack_A", {48, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_unsupported_req_A", {49, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_unsupported_cpl_A", {50, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_unexpected_cpl_A", {51, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_poisoned_tlp_A", {52, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_poisoned_cpl_A", {53, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_malformed_tlp_A", {54, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_cpl_abort_A", {55, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_request_MSG_A", {56, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_request_CFG_WR_A", {57, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_request_CFG_RD_A", {58, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_request_IO_WR_A", {59, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_request_IO_RD_A", {60, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_request_MEM_WR_A", {61, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_request_MEM_RD_A", {62, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_MST_gt16_A", {63, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_MST_9to16_A", {64, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_MST_5to8_A", {65, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_MST_2to4_A", {66, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_MST_1_A", {67, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_SLV_gt32_A", {68, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_SLV_17to32_A", {69, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_SLV_9to16_A", {70, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_SLV_5to8_A", {71, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_SLV_2to4_A", {72, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_length_SLV_1_A", {73, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_cpl_status_CA_A", {74, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_cpl_status_CRS_A", {75, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_cpl_status_UR_A", {76, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_FE_cpl_status_SC_A", {77, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_pm_active_state_request_l1_A", {78, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_pm_request_ack_A", {79, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_pm_enter_l23_A", {80, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_pm_enter_l1_A", {81, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_error_A", {82, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_crc_err_A", {83, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_FCC_npd_0", {84, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_FCC_pd_0", {85, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_FCC_nph_0", {86, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_FCC_ph_0", {87, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_fail_crc_rd_hdr_0", {88, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_pass_crc_rd_hdr_0", {89, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_fail_crc_wr_hdr_0", {90, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_pass_crc_wr_hdr_0", {91, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_fail_crc_data_0", {92, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_pass_crc_data_0", {93, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_invalid_crc_0", {94, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_valid_crc_0", {95, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_rd_hdr_WEN_0", {96, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_wr_hdr_WEN_0", {97, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_data_WEN_0", {98, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_non_post_rd_from_FE", {99, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_non_post_wr_from_FE", {100, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_post_req_from_FE", {101, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_non_post_rd_from_FE_0", {102, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_non_post_wr_from_FE_0", {103, RX_TILE_TXCLK}},
|
||||
{"SB_PERF_post_req_from_FE_0", {104, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_nak_A", {111, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_DLLP_ack_A", {112, RX_TILE_TXCLK}},
|
||||
{"RX_PERF_allErrors_A", {113, RX_TILE_TXCLK}},
|
||||
{"perf_PG_COUNT", {175, RX_TILE_TXCLK}},
|
||||
{"perf_NOT_POWER_GATED", {176, RX_TILE_TXCLK}},
|
||||
{"perf_POWER_GATED", {177, RX_TILE_TXCLK}},
|
||||
|
||||
{"SB_PERF_non_post_rd_to_HI", {2, RX_TILE_SCLK}},
|
||||
{"SB_PERF_non_post_wr_to_HI", {3, RX_TILE_SCLK}},
|
||||
{"SB_PERF_post_req_to_HI", {4, RX_TILE_SCLK}},
|
||||
{"SB_PERF_non_post_rd_to_HI_0", {5, RX_TILE_SCLK}},
|
||||
{"SB_PERF_non_post_wr_to_HI_0", {6, RX_TILE_SCLK}},
|
||||
{"SB_PERF_post_req_to_HI_0", {7, RX_TILE_SCLK}},
|
||||
{"SB_PERF_rd_hdr_REN_0", {8, RX_TILE_SCLK}},
|
||||
{"SB_PERF_wr_hdr_REN_0", {9, RX_TILE_SCLK}},
|
||||
{"SB_PERF_data_REN_0", {10, RX_TILE_SCLK}},
|
||||
{"SB_PERF_rd_hdr_empty_0", {11, RX_TILE_SCLK}},
|
||||
{"SB_PERF_wr_hdr_empty_0", {12, RX_TILE_SCLK}},
|
||||
{"SB_PERF_data_empty_0", {13, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_total128BRdCpl", {29, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_total32BMemRdTx", {30, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_total64BMemRdTx", {31, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_total16BMemWrTx", {32, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_total32BMemWrTx", {33, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_total64BMemWrTx", {34, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_totalTx", {35, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_stallGrantGen", {36, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_totalGrant", {37, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_txPending", {38, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_numMemRdLT32B", {39, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_numMemRdLT16B", {40, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_totalMemTx", {41, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_totalMemRdTx", {42, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_totalMemWrTx", {43, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_numGrant0", {44, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_portCntOverFlow_ns0", {45, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_portCntUnderFlow_ns0", {46, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_portCntOverFlow_s0", {47, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_portCntUnderFlow_s0", {48, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_portCntOverFlow0", {49, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_portCntUnderFlow0", {50, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_npNotAccepted_ns0", {51, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_npNotAccepted_s0", {52, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_num128BRdCpl0", {53, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_num32BMemRdTx0", {54, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_num64BMemRdTx0", {55, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_num16BMemWrTx0", {56, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_num32BMemWrTx0", {57, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_num64BMemWrTx0", {58, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemRd_Bandwidth0", {59, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemWr_Bandwidth0", {60, RX_TILE_SCLK}},
|
||||
{"TX_PERF_S_RCLK_s_tag_buf_empty", {61, RX_TILE_SCLK}},
|
||||
{"P_request_latency_500ns_or_more", {62, RX_TILE_SCLK}},
|
||||
{"P_request_latency_250_to_500ns", {63, RX_TILE_SCLK}},
|
||||
{"P_request_latency_100_to_250ns", {64, RX_TILE_SCLK}},
|
||||
{"P_request_latency_100ns_or_less", {65, RX_TILE_SCLK}},
|
||||
{"NP_request_latency_500ns_or_more", {66, RX_TILE_SCLK}},
|
||||
{"NP_request_latency_250_to_500ns", {67, RX_TILE_SCLK}},
|
||||
{"NP_request_latency_100_to_250ns", {68, RX_TILE_SCLK}},
|
||||
{"NP_request_latency_100ns_or_less", {69, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemRd_wait_for_cpl_slot[0]", {70, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemRd_wait_for_tag[0]", {71, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemRd_wait_for_d_credit[0]", {72, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemRd_wait_for_h_credit[0]", {73, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemWr_wait_for_tag[0]", {74, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemWr_wait_for_d_credit[0]", {75, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemWr_wait_for_h_credit[0]", {76, RX_TILE_SCLK}},
|
||||
{"CISLV_PERF_no_VC1_no_tags_q", {77, RX_TILE_SCLK}},
|
||||
{"CISLV_PERF_no_VC1_data_credits_q", {78, RX_TILE_SCLK}},
|
||||
{"CISLV_PERF_no_VC1_req_credits_q", {79, RX_TILE_SCLK}},
|
||||
{"CISLV_PERF_no_cpl_slots_q[0]", {80, RX_TILE_SCLK}},
|
||||
{"CISLV_PERF_no_VC0_no_tags_q", {81, RX_TILE_SCLK}},
|
||||
{"CISLV_PERF_no_VC0_data_credits_q", {82, RX_TILE_SCLK}},
|
||||
{"CISLV_PERF_no_VC0_req_credits_q", {83, RX_TILE_SCLK}}
|
||||
};
|
||||
{"SB_PERF_non_post_rd_to_HI", {2, RX_TILE_SCLK}},
|
||||
{"SB_PERF_non_post_wr_to_HI", {3, RX_TILE_SCLK}},
|
||||
{"SB_PERF_post_req_to_HI", {4, RX_TILE_SCLK}},
|
||||
{"SB_PERF_non_post_rd_to_HI_0", {5, RX_TILE_SCLK}},
|
||||
{"SB_PERF_non_post_wr_to_HI_0", {6, RX_TILE_SCLK}},
|
||||
{"SB_PERF_post_req_to_HI_0", {7, RX_TILE_SCLK}},
|
||||
{"SB_PERF_rd_hdr_REN_0", {8, RX_TILE_SCLK}},
|
||||
{"SB_PERF_wr_hdr_REN_0", {9, RX_TILE_SCLK}},
|
||||
{"SB_PERF_data_REN_0", {10, RX_TILE_SCLK}},
|
||||
{"SB_PERF_rd_hdr_empty_0", {11, RX_TILE_SCLK}},
|
||||
{"SB_PERF_wr_hdr_empty_0", {12, RX_TILE_SCLK}},
|
||||
{"SB_PERF_data_empty_0", {13, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_total128BRdCpl", {29, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_total32BMemRdTx", {30, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_total64BMemRdTx", {31, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_total16BMemWrTx", {32, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_total32BMemWrTx", {33, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_total64BMemWrTx", {34, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_totalTx", {35, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_stallGrantGen", {36, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_totalGrant", {37, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_txPending", {38, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_numMemRdLT32B", {39, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_numMemRdLT16B", {40, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_totalMemTx", {41, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_totalMemRdTx", {42, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_totalMemWrTx", {43, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_numGrant0", {44, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_portCntOverFlow_ns0", {45, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_portCntUnderFlow_ns0", {46, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_portCntOverFlow_s0", {47, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_portCntUnderFlow_s0", {48, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_portCntOverFlow0", {49, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_portCntUnderFlow0", {50, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_npNotAccepted_ns0", {51, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_npNotAccepted_s0", {52, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_num128BRdCpl0", {53, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_num32BMemRdTx0", {54, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_num64BMemRdTx0", {55, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_num16BMemWrTx0", {56, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_num32BMemWrTx0", {57, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_num64BMemWrTx0", {58, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemRd_Bandwidth0", {59, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemWr_Bandwidth0", {60, RX_TILE_SCLK}},
|
||||
{"TX_PERF_S_RCLK_s_tag_buf_empty", {61, RX_TILE_SCLK}},
|
||||
{"P_request_latency_500ns_or_more", {62, RX_TILE_SCLK}},
|
||||
{"P_request_latency_250_to_500ns", {63, RX_TILE_SCLK}},
|
||||
{"P_request_latency_100_to_250ns", {64, RX_TILE_SCLK}},
|
||||
{"P_request_latency_100ns_or_less", {65, RX_TILE_SCLK}},
|
||||
{"NP_request_latency_500ns_or_more", {66, RX_TILE_SCLK}},
|
||||
{"NP_request_latency_250_to_500ns", {67, RX_TILE_SCLK}},
|
||||
{"NP_request_latency_100_to_250ns", {68, RX_TILE_SCLK}},
|
||||
{"NP_request_latency_100ns_or_less", {69, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemRd_wait_for_cpl_slot[0]", {70, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemRd_wait_for_tag[0]", {71, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemRd_wait_for_d_credit[0]", {72, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemRd_wait_for_h_credit[0]", {73, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemWr_wait_for_tag[0]", {74, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemWr_wait_for_d_credit[0]", {75, RX_TILE_SCLK}},
|
||||
{"CI_PERF_slv_MemWr_wait_for_h_credit[0]", {76, RX_TILE_SCLK}},
|
||||
{"CISLV_PERF_no_VC1_no_tags_q", {77, RX_TILE_SCLK}},
|
||||
{"CISLV_PERF_no_VC1_data_credits_q", {78, RX_TILE_SCLK}},
|
||||
{"CISLV_PERF_no_VC1_req_credits_q", {79, RX_TILE_SCLK}},
|
||||
{"CISLV_PERF_no_cpl_slots_q[0]", {80, RX_TILE_SCLK}},
|
||||
{"CISLV_PERF_no_VC0_no_tags_q", {81, RX_TILE_SCLK}},
|
||||
{"CISLV_PERF_no_VC0_data_credits_q", {82, RX_TILE_SCLK}},
|
||||
{"CISLV_PERF_no_VC0_req_credits_q", {83, RX_TILE_SCLK}}};
|
||||
|
||||
}
|
||||
} // namespace PCIE_MI200
|
||||
|
||||
|
||||
#endif
|
||||
@@ -42,6 +42,6 @@ class PerfMon {
|
||||
std::vector<std::string> counter_names_;
|
||||
};
|
||||
|
||||
} // namespace rocprofiler
|
||||
} // namespace rocprofiler
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user