From 7078aab43601b5c2fd82e5da018a8ddb4f49fb69 Mon Sep 17 00:00:00 2001
From: Vladana Stojiljkovic <vladana.stojiljkovic@amd.com>
Date: Mon, 20 Jan 2025 12:27:08 +0200
Subject: [PATCH] SWDEV-510059 - Format CU mask properly

Change-Id: I80e94b4f3ea25f6988fc06d83aeb398e81ccddd1


[ROCm/clr commit: 061c5d877fb5751eb56658574d898a192aa86415]
---
 projects/clr/rocclr/device/rocm/rocdevice.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/projects/clr/rocclr/device/rocm/rocdevice.cpp b/projects/clr/rocclr/device/rocm/rocdevice.cpp
index ad427706f5..9ddf8441f4 100644
--- a/projects/clr/rocclr/device/rocm/rocdevice.cpp
+++ b/projects/clr/rocclr/device/rocm/rocdevice.cpp
@@ -53,6 +53,7 @@
 #include <cstring>
 #include <fstream>
 #include <iostream>
+#include <iomanip>
 #include <memory>
 #ifdef ROCCLR_SUPPORT_NUMA_POLICY
 #include <numa.h>
@@ -3088,7 +3089,7 @@ hsa_queue_t* Device::acquireQueue(uint32_t queue_size_hint, bool coop_queue,
 
 
     for (int i = mask.size() - 1; i >= 0; i--) {
-      ss << mask[i];
+      ss << std::setfill('0') << std::setw(4) << mask[i];
     }
     ClPrint(amd::LOG_INFO, amd::LOG_QUEUE, "Setting CU mask 0x%s for hardware queue %p",
             ss.str().c_str(), queue->base_address);