From 71ac51b9650d1ed1c89fac6f36c78ea4f54d0e02 Mon Sep 17 00:00:00 2001
From: Aditya Atluri <Aditya.Atluri@amd.com>
Date: Tue, 25 Oct 2016 09:33:45 -0500
Subject: [PATCH] correct cachesize to output correct value

Change-Id: I5db031591eb718b0c12e78a35e4b19349de9526d


[ROCm/clr commit: e28f65604b40fbfe236be8807ead696bf36e0153]
---
 projects/clr/hipamd/src/hip_hcc.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/clr/hipamd/src/hip_hcc.cpp b/projects/clr/hipamd/src/hip_hcc.cpp
index 7fa25334bc..0ef9a45ca6 100644
--- a/projects/clr/hipamd/src/hip_hcc.cpp
+++ b/projects/clr/hipamd/src/hip_hcc.cpp
@@ -769,7 +769,7 @@ hipError_t ihipDevice_t::initProperties(hipDeviceProp_t* prop)
     uint32_t cache_size[4];
     err = hsa_agent_get_info(_hsaAgent, HSA_AGENT_INFO_CACHE_SIZE, cache_size);
     DeviceErrorCheck(err);
-    prop->l2CacheSize = cache_size[1];
+    prop->l2CacheSize = cache_size[0];
 
     /* Computemode for HSA Devices is always : cudaComputeModeDefault */
     prop->computeMode = 0;